siopvar_common.h revision 1.36
1 /* $NetBSD: siopvar_common.h,v 1.36 2008/06/11 02:09:16 kiyohara Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include "opt_siop.h" 34 35 /* common struct and routines used by siop and esiop */ 36 37 #ifndef SIOP_DEFAULT_TARGET 38 #define SIOP_DEFAULT_TARGET 7 39 #endif 40 41 /* tables used by SCRIPT */ 42 typedef struct scr_table { 43 u_int32_t count; 44 u_int32_t addr; 45 } __packed scr_table_t; 46 47 /* Number of scatter/gather entries */ 48 #define SIOP_NSG (MAXPHYS/PAGE_SIZE + 1) /* XXX PAGE_SIZE */ 49 50 /* 51 * This structure interfaces the SCRIPT with the driver; it describes a full 52 * transfer. 53 * If you change something here, don't forget to update offsets in {s,es}iop.ss 54 */ 55 struct siop_common_xfer { 56 u_int8_t msg_out[16]; /* 0 */ 57 u_int8_t msg_in[16]; /* 16 */ 58 u_int32_t status; /* 32 */ 59 u_int32_t pad1; /* 36 */ 60 u_int32_t id; /* 40 */ 61 u_int32_t pad2; /* 44 */ 62 scr_table_t t_msgin; /* 48 */ 63 scr_table_t t_extmsgin; /* 56 */ 64 scr_table_t t_extmsgdata; /* 64 */ 65 scr_table_t t_msgout; /* 72 */ 66 scr_table_t cmd; /* 80 */ 67 scr_table_t t_status; /* 88 */ 68 scr_table_t data[SIOP_NSG]; /* 96 */ 69 } __packed; 70 71 /* status can hold the SCSI_* status values, and 2 additional values: */ 72 #define SCSI_SIOP_NOCHECK 0xfe /* don't check the scsi status */ 73 #define SCSI_SIOP_NOSTATUS 0xff /* device didn't report status */ 74 75 /* offset is initialised to SIOP_NOOFFSET, used to check if it was updated */ 76 #define SIOP_NOOFFSET 0xffffffff 77 78 /* 79 * This describes a command handled by the SCSI controller 80 */ 81 struct siop_common_cmd { 82 struct siop_common_softc *siop_sc; /* points back to our adapter */ 83 struct siop_common_target *siop_target; /* pointer to our target def */ 84 struct scsipi_xfer *xs; /* xfer from the upper level */ 85 struct siop_common_xfer *siop_tables; /* tables for this cmd */ 86 bus_addr_t dsa; /* DSA value to load */ 87 bus_dmamap_t dmamap_cmd; 88 bus_dmamap_t dmamap_data; 89 int status; 90 int flags; 91 int tag; /* tag used for tagged command queuing */ 92 int resid; /* valid when CMDFL_RESID is set */ 93 }; 94 95 /* status defs */ 96 #define CMDST_FREE 0 /* cmd slot is free */ 97 #define CMDST_READY 1 /* cmd slot is waiting for processing */ 98 #define CMDST_ACTIVE 2 /* cmd slot is being processed */ 99 #define CMDST_DONE 3 /* cmd slot has been processed */ 100 /* flags defs */ 101 #define CMDFL_TIMEOUT 0x0001 /* cmd timed out */ 102 #define CMDFL_TAG 0x0002 /* tagged cmd */ 103 #define CMDFL_RESID 0x0004 /* current offset in table is partial */ 104 105 /* per-target struct */ 106 struct siop_common_target { 107 int status; /* target status, see below */ 108 int flags; /* target flags, see below */ 109 u_int32_t id; /* for SELECT FROM */ 110 int period; 111 int offset; 112 }; 113 114 /* target status */ 115 #define TARST_PROBING 0 /* target is being probed */ 116 #define TARST_ASYNC 1 /* target needs sync/wide negotiation */ 117 #define TARST_WIDE_NEG 2 /* target is doing wide negotiation */ 118 #define TARST_SYNC_NEG 3 /* target is doing sync negotiation */ 119 #define TARST_PPR_NEG 4 /* target is doing sync negotiation */ 120 #define TARST_OK 5 /* sync/wide agreement is valid */ 121 122 /* target flags */ 123 #define TARF_SYNC 0x01 /* target can do sync */ 124 #define TARF_WIDE 0x02 /* target can do wide */ 125 #define TARF_TAG 0x04 /* target can do tags */ 126 #define TARF_DT 0x08 /* target can do DT clocking */ 127 #define TARF_ISWIDE 0x10 /* target is wide */ 128 #define TARF_ISDT 0x20 /* target is doing DT clocking */ 129 130 /* Driver internal state */ 131 struct siop_common_softc { 132 struct device sc_dev; 133 struct scsipi_channel sc_chan; 134 struct scsipi_adapter sc_adapt; 135 int features; /* chip's features */ 136 int ram_size; 137 int maxburst; 138 int maxoff; 139 int clock_div; /* async. clock divider (scntl3) */ 140 int clock_period; /* clock period (ns * 10) */ 141 int st_minsync; /* min and max sync period, */ 142 int dt_minsync; 143 int st_maxsync; /* as sent in or PPR messages */ 144 int dt_maxsync; 145 int mode; /* current SE/LVD/HVD mode */ 146 bus_space_tag_t sc_rt; /* bus_space registers tag */ 147 bus_space_handle_t sc_rh; /* bus_space registers handle */ 148 bus_addr_t sc_raddr; /* register addresses */ 149 bus_space_tag_t sc_ramt; /* bus_space ram tag */ 150 bus_space_handle_t sc_ramh; /* bus_space ram handle */ 151 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 152 void (*sc_reset)(struct siop_common_softc*); /* reset callback */ 153 bus_dmamap_t sc_scriptdma; /* DMA map for script */ 154 bus_addr_t sc_scriptaddr; /* on-board ram or physical address */ 155 u_int32_t *sc_script; /* script location in memory */ 156 struct siop_common_target *targets[16]; /* per-target states */ 157 }; 158 159 /* features */ 160 #define SF_BUS_WIDE 0x00000001 /* wide bus */ 161 #define SF_BUS_ULTRA 0x00000002 /* Ultra (20MHz) bus */ 162 #define SF_BUS_ULTRA2 0x00000004 /* Ultra2 (40MHz) bus */ 163 #define SF_BUS_ULTRA3 0x00000008 /* Ultra3 (80MHz) bus */ 164 #define SF_BUS_DIFF 0x00000010 /* differential bus */ 165 166 #define SF_CHIP_LED0 0x00000100 /* led on GPIO0 */ 167 #define SF_CHIP_LEDC 0x00000200 /* led on GPIO0 with hardware control */ 168 #define SF_CHIP_DBLR 0x00000400 /* clock doubler or quadrupler */ 169 #define SF_CHIP_QUAD 0x00000800 /* clock quadrupler, with PPL */ 170 #define SF_CHIP_FIFO 0x00001000 /* large fifo */ 171 #define SF_CHIP_PF 0x00002000 /* Instructions prefetch */ 172 #define SF_CHIP_RAM 0x00004000 /* on-board RAM */ 173 #define SF_CHIP_LS 0x00008000 /* load/store instruction */ 174 #define SF_CHIP_10REGS 0x00010000 /* 10 scratch registers */ 175 #define SF_CHIP_DFBC 0x00020000 /* Use DFBC register */ 176 #define SF_CHIP_DT 0x00040000 /* DT clocking */ 177 #define SF_CHIP_GEBUG 0x00080000 /* SCSI gross error bug */ 178 #define SF_CHIP_AAIP 0x00100000 /* Always generate AIP regardless of SNCTL4*/ 179 #define SF_CHIP_BE 0x00200000 /* big-endian */ 180 #define SF_CHIP_USEPCIC 0x00400000 /* use PCI clock */ 181 182 #define SF_PCI_RL 0x01000000 /* PCI read line */ 183 #define SF_PCI_RM 0x02000000 /* PCI read multiple */ 184 #define SF_PCI_BOF 0x04000000 /* PCI burst opcode fetch */ 185 #define SF_PCI_CLS 0x08000000 /* PCI cache line size */ 186 #define SF_PCI_WRI 0x10000000 /* PCI write and invalidate */ 187 188 int siop_common_attach(struct siop_common_softc *); 189 void siop_common_reset(struct siop_common_softc *); 190 void siop_setuptables(struct siop_common_cmd *); 191 int siop_modechange(struct siop_common_softc *); 192 193 int siop_wdtr_neg(struct siop_common_cmd *); 194 int siop_sdtr_neg(struct siop_common_cmd *); 195 int siop_ppr_neg(struct siop_common_cmd *); 196 void siop_sdtr_msg(struct siop_common_cmd *, int, int, int); 197 void siop_wdtr_msg(struct siop_common_cmd *, int, int); 198 void siop_ppr_msg(struct siop_common_cmd *, int, int, int); 199 void siop_update_xfer_mode(struct siop_common_softc *, int); 200 int siop_iwr(struct siop_common_cmd *); 201 /* actions to take at return of siop_wdtr_neg(), siop_sdtr_neg() and siop_iwr */ 202 #define SIOP_NEG_NOP 0x0 203 #define SIOP_NEG_MSGOUT 0x1 204 #define SIOP_NEG_ACK 0x2 205 206 void siop_minphys(struct buf *); 207 int siop_ioctl(struct scsipi_channel *, u_long, 208 void *, int, struct proc *); 209 void siop_ma (struct siop_common_cmd *); 210 void siop_sdp(struct siop_common_cmd *, int); 211 void siop_update_resid(struct siop_common_cmd *, int); 212 void siop_clearfifo(struct siop_common_softc *); 213 void siop_resetbus(struct siop_common_softc *); 214 215 #define siop_htoc32(sc, x) \ 216 (((sc)->features & SF_CHIP_BE) ? htobe32((x)) : htole32((x))) 217 218 #define siop_ctoh32(sc, x) \ 219 (((sc)->features & SF_CHIP_BE) ? be32toh((x)) : le32toh((x))) 220
Indexes created Sat Sep 27 14:09:57 GMT 2025