smc83c170.c revision 1.14
1 /* $NetBSD: smc83c170.c,v 1.14 1999/02/18 02:24:30 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Device driver for the Standard Microsystems Corp. 83C170 42 * Ethernet PCI Integrated Controller (EPIC/100). 43 */ 44 45 #include "opt_inet.h" 46 #include "opt_ns.h" 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #endif 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 73 #ifdef NS 74 #include <netns/ns.h> 75 #include <netns/ns_if.h> 76 #endif 77 78 #include <machine/bus.h> 79 #include <machine/intr.h> 80 81 #include <dev/mii/miivar.h> 82 83 #include <dev/ic/smc83c170reg.h> 84 #include <dev/ic/smc83c170var.h> 85 86 void epic_start __P((struct ifnet *)); 87 void epic_watchdog __P((struct ifnet *)); 88 int epic_ioctl __P((struct ifnet *, u_long, caddr_t)); 89 90 void epic_shutdown __P((void *)); 91 92 void epic_reset __P((struct epic_softc *)); 93 void epic_init __P((struct epic_softc *)); 94 void epic_stop __P((struct epic_softc *)); 95 int epic_add_rxbuf __P((struct epic_softc *, int)); 96 void epic_read_eeprom __P((struct epic_softc *, int, int, u_int16_t *)); 97 void epic_set_mchash __P((struct epic_softc *)); 98 void epic_fixup_clock_source __P((struct epic_softc *)); 99 int epic_mii_read __P((struct device *, int, int)); 100 void epic_mii_write __P((struct device *, int, int, int)); 101 int epic_mii_wait __P((struct epic_softc *, u_int32_t)); 102 void epic_tick __P((void *)); 103 104 void epic_statchg __P((struct device *)); 105 int epic_mediachange __P((struct ifnet *)); 106 void epic_mediastatus __P((struct ifnet *, struct ifmediareq *)); 107 108 /* XXX Should be somewhere else. */ 109 #define ETHER_MIN_LEN 60 110 111 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 112 INTSTAT_TXC | INTSTAT_RQE | INTSTAT_RCC) 113 114 /* 115 * Attach an EPIC interface to the system. 116 */ 117 void 118 epic_attach(sc) 119 struct epic_softc *sc; 120 { 121 bus_space_tag_t st = sc->sc_st; 122 bus_space_handle_t sh = sc->sc_sh; 123 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 124 int i, rseg, error; 125 bus_dma_segment_t seg; 126 u_int8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 127 u_int16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 128 129 /* 130 * Allocate the control data structures, and create and load the 131 * DMA map for it. 132 */ 133 if ((error = bus_dmamem_alloc(sc->sc_dmat, 134 sizeof(struct epic_control_data), NBPG, 0, &seg, 1, &rseg, 135 BUS_DMA_NOWAIT)) != 0) { 136 printf("%s: unable to allocate control data, error = %d\n", 137 sc->sc_dev.dv_xname, error); 138 goto fail_0; 139 } 140 141 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 142 sizeof(struct epic_control_data), (caddr_t *)&sc->sc_control_data, 143 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 144 printf("%s: unable to map control data, error = %d\n", 145 sc->sc_dev.dv_xname, error); 146 goto fail_1; 147 } 148 149 if ((error = bus_dmamap_create(sc->sc_dmat, 150 sizeof(struct epic_control_data), 1, 151 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 152 &sc->sc_cddmamap)) != 0) { 153 printf("%s: unable to create control data DMA map, " 154 "error = %d\n", sc->sc_dev.dv_xname, error); 155 goto fail_2; 156 } 157 158 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 159 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 160 BUS_DMA_NOWAIT)) != 0) { 161 printf("%s: unable to load control data DMA map, error = %d\n", 162 sc->sc_dev.dv_xname, error); 163 goto fail_3; 164 } 165 166 /* 167 * Create the transmit buffer DMA maps. 168 */ 169 for (i = 0; i < EPIC_NTXDESC; i++) { 170 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 171 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 172 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 173 printf("%s: unable to create tx DMA map %d, " 174 "error = %d\n", sc->sc_dev.dv_xname, i, error); 175 goto fail_4; 176 } 177 } 178 179 /* 180 * Create the recieve buffer DMA maps. 181 */ 182 for (i = 0; i < EPIC_NRXDESC; i++) { 183 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 184 MCLBYTES, 0, BUS_DMA_NOWAIT, 185 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 186 printf("%s: unable to create rx DMA map %d, " 187 "error = %d\n", sc->sc_dev.dv_xname, i, error); 188 goto fail_5; 189 } 190 } 191 192 /* 193 * Pre-allocate the receive buffers. 194 */ 195 for (i = 0; i < EPIC_NRXDESC; i++) { 196 if ((error = epic_add_rxbuf(sc, i)) != 0) { 197 printf("%s: unable to allocate or map rx buffer %d\n," 198 " error = %d\n", sc->sc_dev.dv_xname, i, error); 199 goto fail_6; 200 } 201 } 202 203 /* 204 * Bring the chip out of low-power mode and reset it to a known state. 205 */ 206 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 207 epic_reset(sc); 208 209 /* 210 * Read the Ethernet address from the EEPROM. 211 */ 212 epic_read_eeprom(sc, 0, (sizeof(myea) / sizeof(myea[0])), myea); 213 bcopy(myea, enaddr, sizeof(myea)); 214 215 /* 216 * ...and the device name. 217 */ 218 epic_read_eeprom(sc, 0x2c, (sizeof(mydevname) / sizeof(mydevname[0])), 219 mydevname); 220 bcopy(mydevname, devname, sizeof(mydevname)); 221 devname[sizeof(mydevname)] = '\0'; 222 for (i = sizeof(mydevname) - 1; i >= 0; i--) { 223 if (devname[i] == ' ') 224 devname[i] = '\0'; 225 else 226 break; 227 } 228 229 printf("%s: %s, Ethernet address %s\n", sc->sc_dev.dv_xname, 230 devname, ether_sprintf(enaddr)); 231 232 /* 233 * Initialize our media structures and probe the MII. 234 */ 235 sc->sc_mii.mii_ifp = ifp; 236 sc->sc_mii.mii_readreg = epic_mii_read; 237 sc->sc_mii.mii_writereg = epic_mii_write; 238 sc->sc_mii.mii_statchg = epic_statchg; 239 ifmedia_init(&sc->sc_mii.mii_media, 0, epic_mediachange, 240 epic_mediastatus); 241 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 242 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 243 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 244 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 245 } else 246 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 247 248 ifp = &sc->sc_ethercom.ec_if; 249 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 250 ifp->if_softc = sc; 251 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 252 ifp->if_ioctl = epic_ioctl; 253 ifp->if_start = epic_start; 254 ifp->if_watchdog = epic_watchdog; 255 256 /* 257 * Attach the interface. 258 */ 259 if_attach(ifp); 260 ether_ifattach(ifp, enaddr); 261 #if NBPFILTER > 0 262 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 263 sizeof(struct ether_header)); 264 #endif 265 266 /* 267 * Make sure the interface is shutdown during reboot. 268 */ 269 sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc); 270 if (sc->sc_sdhook == NULL) 271 printf("%s: WARNING: unable to establish shutdown hook\n", 272 sc->sc_dev.dv_xname); 273 return; 274 275 /* 276 * Free any resources we've allocated during the failed attach 277 * attempt. Do this in reverse order and fall through. 278 */ 279 fail_6: 280 for (i = 0; i < EPIC_NRXDESC; i++) { 281 if (EPIC_DSRX(sc, i)->ds_mbuf != NULL) { 282 bus_dmamap_unload(sc->sc_dmat, 283 EPIC_DSRX(sc, i)->ds_dmamap); 284 m_freem(EPIC_DSRX(sc, i)->ds_mbuf); 285 } 286 } 287 fail_5: 288 for (i = 0; i < EPIC_NRXDESC; i++) { 289 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 290 bus_dmamap_destroy(sc->sc_dmat, 291 EPIC_DSRX(sc, i)->ds_dmamap); 292 } 293 fail_4: 294 for (i = 0; i < EPIC_NTXDESC; i++) { 295 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 296 bus_dmamap_destroy(sc->sc_dmat, 297 EPIC_DSTX(sc, i)->ds_dmamap); 298 } 299 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 300 fail_3: 301 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 302 fail_2: 303 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 304 sizeof(struct epic_control_data)); 305 fail_1: 306 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 307 fail_0: 308 return; 309 } 310 311 /* 312 * Shutdown hook. Make sure the interface is stopped at reboot. 313 */ 314 void 315 epic_shutdown(arg) 316 void *arg; 317 { 318 struct epic_softc *sc = arg; 319 320 epic_stop(sc); 321 } 322 323 /* 324 * Start packet transmission on the interface. 325 * [ifnet interface function] 326 */ 327 void 328 epic_start(ifp) 329 struct ifnet *ifp; 330 { 331 struct epic_softc *sc = ifp->if_softc; 332 struct mbuf *m0, *m; 333 struct epic_txdesc *txd; 334 struct epic_descsoft *ds; 335 struct epic_fraglist *fr; 336 bus_dmamap_t dmamap; 337 int error, firsttx, nexttx, opending, seg; 338 339 /* 340 * Remember the previous txpending and the first transmit 341 * descriptor we use. 342 */ 343 opending = sc->sc_txpending; 344 firsttx = EPIC_NEXTTX(sc->sc_txlast); 345 346 /* 347 * Loop through the send queue, setting up transmit descriptors 348 * until we drain the queue, or use up all available transmit 349 * descriptors. 350 */ 351 while (sc->sc_txpending < EPIC_NTXDESC) { 352 /* 353 * Grab a packet off the queue. 354 */ 355 IF_DEQUEUE(&ifp->if_snd, m0); 356 if (m0 == NULL) 357 break; 358 359 /* 360 * Get the last and next available transmit descriptor. 361 */ 362 nexttx = EPIC_NEXTTX(sc->sc_txlast); 363 txd = EPIC_CDTX(sc, nexttx); 364 fr = EPIC_CDFL(sc, nexttx); 365 ds = EPIC_DSTX(sc, nexttx); 366 dmamap = ds->ds_dmamap; 367 368 /* 369 * Load the DMA map. If this fails, the packet either 370 * didn't fit in the alloted number of frags, or we were 371 * short on resources. In this case, we'll copy and try 372 * again. 373 */ 374 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 375 BUS_DMA_NOWAIT) != 0) { 376 MGETHDR(m, M_DONTWAIT, MT_DATA); 377 if (m == NULL) { 378 printf("%s: unable to allocate Tx mbuf\n", 379 sc->sc_dev.dv_xname); 380 IF_PREPEND(&ifp->if_snd, m0); 381 break; 382 } 383 if (m0->m_pkthdr.len > MHLEN) { 384 MCLGET(m, M_DONTWAIT); 385 if ((m->m_flags & M_EXT) == 0) { 386 printf("%s: unable to allocate Tx " 387 "cluster\n", sc->sc_dev.dv_xname); 388 m_freem(m); 389 IF_PREPEND(&ifp->if_snd, m0); 390 break; 391 } 392 } 393 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 394 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 395 m_freem(m0); 396 m0 = m; 397 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 398 m0, BUS_DMA_NOWAIT); 399 if (error) { 400 printf("%s: unable to load Tx buffer, " 401 "error = %d\n", sc->sc_dev.dv_xname, error); 402 IF_PREPEND(&ifp->if_snd, m0); 403 break; 404 } 405 } 406 407 /* Initialize the fraglist. */ 408 fr->ef_nfrags = dmamap->dm_nsegs; 409 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 410 fr->ef_frags[seg].ef_addr = 411 dmamap->dm_segs[seg].ds_addr; 412 fr->ef_frags[seg].ef_length = 413 dmamap->dm_segs[seg].ds_len; 414 } 415 416 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 417 418 /* Sync the DMA map. */ 419 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 420 BUS_DMASYNC_PREWRITE); 421 422 /* 423 * Store a pointer to the packet so we can free it later. 424 */ 425 ds->ds_mbuf = m0; 426 427 /* 428 * Fill in the transmit descriptor. The EPIC doesn't 429 * auto-pad, so we have to do this ourselves. 430 */ 431 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 432 txd->et_txlength = max(m0->m_pkthdr.len, ETHER_MIN_LEN); 433 434 /* 435 * If this is the first descriptor we're enqueueing, 436 * don't give it to the EPIC yet. That could cause 437 * a race condition. We'll do it below. 438 */ 439 if (nexttx == firsttx) 440 txd->et_txstatus = 0; 441 else 442 txd->et_txstatus = ET_TXSTAT_OWNER; 443 444 EPIC_CDTXSYNC(sc, nexttx, 445 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 446 447 /* Advance the tx pointer. */ 448 sc->sc_txpending++; 449 sc->sc_txlast = nexttx; 450 451 #if NBPFILTER > 0 452 /* 453 * Pass the packet to any BPF listeners. 454 */ 455 if (ifp->if_bpf) 456 bpf_mtap(ifp->if_bpf, m0); 457 #endif 458 } 459 460 if (sc->sc_txpending == EPIC_NTXDESC) { 461 /* No more slots left; notify upper layer. */ 462 ifp->if_flags |= IFF_OACTIVE; 463 } 464 465 if (sc->sc_txpending != opending) { 466 /* 467 * We enqueued packets. If the transmitter was idle, 468 * reset the txdirty pointer. 469 */ 470 if (opending == 0) 471 sc->sc_txdirty = firsttx; 472 473 /* 474 * Cause a transmit interrupt to happen on the 475 * last packet we enqueued. 476 */ 477 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 478 EPIC_CDTXSYNC(sc, sc->sc_txlast, 479 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 480 481 /* 482 * The entire packet chain is set up. Give the 483 * first descriptor to the EPIC now. 484 */ 485 EPIC_CDTX(sc, firsttx)->et_txstatus = ET_TXSTAT_OWNER; 486 EPIC_CDTXSYNC(sc, firsttx, 487 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 488 489 /* Start the transmitter. */ 490 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 491 COMMAND_TXQUEUED); 492 493 /* Set a watchdog timer in case the chip flakes out. */ 494 ifp->if_timer = 5; 495 } 496 } 497 498 /* 499 * Watchdog timer handler. 500 * [ifnet interface function] 501 */ 502 void 503 epic_watchdog(ifp) 504 struct ifnet *ifp; 505 { 506 struct epic_softc *sc = ifp->if_softc; 507 508 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 509 ifp->if_oerrors++; 510 511 epic_init(sc); 512 } 513 514 /* 515 * Handle control requests from the operator. 516 * [ifnet interface function] 517 */ 518 int 519 epic_ioctl(ifp, cmd, data) 520 struct ifnet *ifp; 521 u_long cmd; 522 caddr_t data; 523 { 524 struct epic_softc *sc = ifp->if_softc; 525 struct ifreq *ifr = (struct ifreq *)data; 526 struct ifaddr *ifa = (struct ifaddr *)data; 527 int s, error = 0; 528 529 s = splnet(); 530 531 switch (cmd) { 532 case SIOCSIFADDR: 533 ifp->if_flags |= IFF_UP; 534 535 switch (ifa->ifa_addr->sa_family) { 536 #ifdef INET 537 case AF_INET: 538 epic_init(sc); 539 arp_ifinit(ifp, ifa); 540 break; 541 #endif /* INET */ 542 #ifdef NS 543 case AF_NS: 544 { 545 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 546 547 if (ns_nullhost(*ina)) 548 ina->x_host = *(union ns_host *) 549 LLADDR(ifp->if_sadl); 550 else 551 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 552 ifp->if_addrlen); 553 /* Set new address. */ 554 epic_init(sc); 555 break; 556 } 557 #endif /* NS */ 558 default: 559 epic_init(sc); 560 break; 561 } 562 break; 563 564 case SIOCSIFMTU: 565 if (ifr->ifr_mtu > ETHERMTU) 566 error = EINVAL; 567 else 568 ifp->if_mtu = ifr->ifr_mtu; 569 break; 570 571 case SIOCSIFFLAGS: 572 if ((ifp->if_flags & IFF_UP) == 0 && 573 (ifp->if_flags & IFF_RUNNING) != 0) { 574 /* 575 * If interface is marked down and it is running, then 576 * stop it. 577 */ 578 epic_stop(sc); 579 } else if ((ifp->if_flags & IFF_UP) != 0 && 580 (ifp->if_flags & IFF_RUNNING) == 0) { 581 /* 582 * If interfase it marked up and it is stopped, then 583 * start it. 584 */ 585 epic_init(sc); 586 } else if ((ifp->if_flags & IFF_UP) != 0) { 587 /* 588 * Reset the interface to pick up changes in any other 589 * flags that affect the hardware state. 590 */ 591 epic_init(sc); 592 } 593 break; 594 595 case SIOCADDMULTI: 596 case SIOCDELMULTI: 597 error = (cmd == SIOCADDMULTI) ? 598 ether_addmulti(ifr, &sc->sc_ethercom) : 599 ether_delmulti(ifr, &sc->sc_ethercom); 600 601 if (error == ENETRESET) { 602 /* 603 * Multicast list has changed; set the hardware filter 604 * accordingly. Update our idea of the current media; 605 * epic_set_mchash() needs to know what it is. 606 */ 607 mii_pollstat(&sc->sc_mii); 608 epic_set_mchash(sc); 609 error = 0; 610 } 611 break; 612 613 case SIOCSIFMEDIA: 614 case SIOCGIFMEDIA: 615 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 616 break; 617 618 default: 619 error = EINVAL; 620 break; 621 } 622 623 splx(s); 624 return (error); 625 } 626 627 /* 628 * Interrupt handler. 629 */ 630 int 631 epic_intr(arg) 632 void *arg; 633 { 634 struct epic_softc *sc = arg; 635 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 636 struct ether_header *eh; 637 struct epic_rxdesc *rxd; 638 struct epic_txdesc *txd; 639 struct epic_descsoft *ds; 640 struct mbuf *m; 641 u_int32_t intstat; 642 int i, len, claimed = 0; 643 644 top: 645 /* 646 * Get the interrupt status from the EPIC. 647 */ 648 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 649 if ((intstat & INTSTAT_INT_ACTV) == 0) 650 return (claimed); 651 652 claimed = 1; 653 654 /* 655 * Acknowledge the interrupt. 656 */ 657 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 658 intstat & INTMASK); 659 660 /* 661 * Check for receive interrupts. 662 */ 663 if (intstat & (INTSTAT_RCC | INTSTAT_RQE)) { 664 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 665 rxd = EPIC_CDRX(sc, i); 666 ds = EPIC_DSRX(sc, i); 667 668 EPIC_CDRXSYNC(sc, i, 669 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 670 671 if (rxd->er_rxstatus & ER_RXSTAT_OWNER) { 672 /* 673 * We have processed all of the 674 * receive buffers. 675 */ 676 break; 677 } 678 679 /* 680 * Make sure the packet arrived intact. If an error 681 * occurred, update stats and reset the descriptor. 682 * The buffer will be reused the next time the 683 * descriptor comes up in the ring. 684 */ 685 if ((rxd->er_rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 686 if (rxd->er_rxstatus & ER_RXSTAT_CRCERROR) 687 printf("%s: CRC error\n", 688 sc->sc_dev.dv_xname); 689 if (rxd->er_rxstatus & ER_RXSTAT_ALIGNERROR) 690 printf("%s: alignment error\n", 691 sc->sc_dev.dv_xname); 692 ifp->if_ierrors++; 693 EPIC_INIT_RXDESC(sc, i); 694 continue; 695 } 696 697 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 698 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 699 700 /* 701 * Add a new buffer to the receive chain. If this 702 * fails, the old buffer is recycled. 703 */ 704 m = ds->ds_mbuf; 705 if (epic_add_rxbuf(sc, i) != 0) { 706 ifp->if_ierrors++; 707 EPIC_INIT_RXDESC(sc, i); 708 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 709 ds->ds_dmamap->dm_mapsize, 710 BUS_DMASYNC_PREREAD); 711 continue; 712 } 713 714 len = rxd->er_buflength; 715 if (len < sizeof(struct ether_header)) { 716 m_freem(m); 717 continue; 718 } 719 720 m->m_pkthdr.rcvif = ifp; 721 m->m_pkthdr.len = m->m_len = len; 722 eh = mtod(m, struct ether_header *); 723 724 #if NBPFILTER > 0 725 /* 726 * Pass this up to any BPF listeners, but only 727 * pass it up the stack if its for us. 728 */ 729 if (ifp->if_bpf) { 730 bpf_mtap(ifp->if_bpf, m); 731 if ((ifp->if_flags & IFF_PROMISC) != 0 && 732 bcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 733 ETHER_ADDR_LEN) != 0 && 734 (rxd->er_rxstatus & 735 (ER_RXSTAT_BCAST|ER_RXSTAT_MCAST)) == 0) { 736 m_freem(m); 737 continue; 738 } 739 } 740 #endif /* NPBFILTER > 0 */ 741 742 /* Remove the Ethernet header and pass it on. */ 743 m_adj(m, sizeof(struct ether_header)); 744 ether_input(ifp, eh, m); 745 } 746 747 /* Update the recieve pointer. */ 748 sc->sc_rxptr = i; 749 750 /* 751 * Check for receive queue underflow. 752 */ 753 if (intstat & INTSTAT_RQE) { 754 printf("%s: receiver queue empty\n", 755 sc->sc_dev.dv_xname); 756 /* 757 * Ring is already built; just restart the 758 * receiver. 759 */ 760 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 761 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 762 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 763 COMMAND_RXQUEUED | COMMAND_START_RX); 764 } 765 } 766 767 /* 768 * Check for transmission complete interrupts. 769 */ 770 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 771 ifp->if_flags &= ~IFF_OACTIVE; 772 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 773 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 774 txd = EPIC_CDTX(sc, i); 775 ds = EPIC_DSTX(sc, i); 776 777 EPIC_CDTXSYNC(sc, i, 778 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 779 780 if (txd->et_txstatus & ET_TXSTAT_OWNER) 781 break; 782 783 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 784 785 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 786 0, ds->ds_dmamap->dm_mapsize, 787 BUS_DMASYNC_POSTWRITE); 788 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 789 m_freem(ds->ds_mbuf); 790 ds->ds_mbuf = NULL; 791 792 /* 793 * Check for errors and collisions. 794 */ 795 if ((txd->et_txstatus & ET_TXSTAT_PACKETTX) == 0) 796 ifp->if_oerrors++; 797 else 798 ifp->if_opackets++; 799 ifp->if_collisions += 800 TXSTAT_COLLISIONS(txd->et_txstatus); 801 if (txd->et_txstatus & ET_TXSTAT_CARSENSELOST) 802 printf("%s: lost carrier\n", 803 sc->sc_dev.dv_xname); 804 } 805 806 /* Update the dirty transmit buffer pointer. */ 807 sc->sc_txdirty = i; 808 809 /* 810 * Cancel the watchdog timer if there are no pending 811 * transmissions. 812 */ 813 if (sc->sc_txpending == 0) 814 ifp->if_timer = 0; 815 816 /* 817 * Kick the transmitter after a DMA underrun. 818 */ 819 if (intstat & INTSTAT_TXU) { 820 printf("%s: transmit underrun\n", sc->sc_dev.dv_xname); 821 bus_space_write_4(sc->sc_st, sc->sc_sh, 822 EPIC_COMMAND, COMMAND_TXUGO); 823 if (sc->sc_txpending) 824 bus_space_write_4(sc->sc_st, sc->sc_sh, 825 EPIC_COMMAND, COMMAND_TXQUEUED); 826 } 827 828 /* 829 * Try to get more packets going. 830 */ 831 epic_start(ifp); 832 } 833 834 /* 835 * Check for fatal interrupts. 836 */ 837 if (intstat & INTSTAT_FATAL_INT) { 838 printf("%s: fatal error, resetting\n", sc->sc_dev.dv_xname); 839 epic_init(sc); 840 } 841 842 /* 843 * Check for more interrupts. 844 */ 845 goto top; 846 } 847 848 /* 849 * One second timer, used to tick the MII. 850 */ 851 void 852 epic_tick(arg) 853 void *arg; 854 { 855 struct epic_softc *sc = arg; 856 int s; 857 858 s = splnet(); 859 mii_tick(&sc->sc_mii); 860 splx(s); 861 862 timeout(epic_tick, sc, hz); 863 } 864 865 /* 866 * Fixup the clock source on the EPIC. 867 */ 868 void 869 epic_fixup_clock_source(sc) 870 struct epic_softc *sc; 871 { 872 int i; 873 874 /* 875 * According to SMC Application Note 7-15, the EPIC's clock 876 * source is incorrect following a reset. This manifests itself 877 * as failure to recognize when host software has written to 878 * a register on the EPIC. The appnote recommends issuing at 879 * least 16 consecutive writes to the CLOCK TEST bit to correctly 880 * configure the clock source. 881 */ 882 for (i = 0; i < 16; i++) 883 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 884 TEST_CLOCKTEST); 885 } 886 887 /* 888 * Perform a soft reset on the EPIC. 889 */ 890 void 891 epic_reset(sc) 892 struct epic_softc *sc; 893 { 894 895 epic_fixup_clock_source(sc); 896 897 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 898 delay(100); 899 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 900 delay(100); 901 902 epic_fixup_clock_source(sc); 903 } 904 905 /* 906 * Initialize the interface. Must be called at splnet(). 907 */ 908 void 909 epic_init(sc) 910 struct epic_softc *sc; 911 { 912 bus_space_tag_t st = sc->sc_st; 913 bus_space_handle_t sh = sc->sc_sh; 914 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 915 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 916 struct epic_txdesc *txd; 917 u_int32_t genctl, reg0; 918 int i; 919 920 /* 921 * Cancel any pending I/O. 922 */ 923 epic_stop(sc); 924 925 /* 926 * Reset the EPIC to a known state. 927 */ 928 epic_reset(sc); 929 930 /* 931 * Magical mystery initialization. 932 */ 933 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 934 935 /* 936 * Initialize the EPIC genctl register: 937 * 938 * - 64 byte receive FIFO threshold 939 * - automatic advance to next receive frame 940 */ 941 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 942 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 943 944 /* 945 * Reset the MII bus and PHY. 946 */ 947 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 948 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 949 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 950 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 951 delay(100); 952 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 953 delay(100); 954 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 955 956 /* 957 * Initialize Ethernet address. 958 */ 959 reg0 = enaddr[1] << 8 | enaddr[0]; 960 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 961 reg0 = enaddr[3] << 8 | enaddr[2]; 962 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 963 reg0 = enaddr[5] << 8 | enaddr[4]; 964 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 965 966 /* 967 * Initialize receive control. Remember the external buffer 968 * size setting. 969 */ 970 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 971 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 972 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 973 if (ifp->if_flags & IFF_PROMISC) 974 reg0 |= RXCON_PROMISCMODE; 975 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 976 977 /* Set the current media. */ 978 mii_mediachg(&sc->sc_mii); 979 980 /* Set up the multicast hash table. */ 981 epic_set_mchash(sc); 982 983 /* 984 * Initialize the transmit descriptor ring. txlast is initialized 985 * to the end of the list so that it will wrap around to the first 986 * descriptor when the first packet is transmitted. 987 */ 988 for (i = 0; i < EPIC_NTXDESC; i++) { 989 txd = EPIC_CDTX(sc, i); 990 memset(txd, 0, sizeof(struct epic_txdesc)); 991 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 992 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 993 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 994 } 995 sc->sc_txpending = 0; 996 sc->sc_txdirty = 0; 997 sc->sc_txlast = EPIC_NTXDESC - 1; 998 999 /* 1000 * Initialize the receive descriptor ring. The buffers are 1001 * already allocated. 1002 */ 1003 for (i = 0; i < EPIC_NRXDESC; i++) 1004 EPIC_INIT_RXDESC(sc, i); 1005 sc->sc_rxptr = 0; 1006 1007 /* 1008 * Initialize the interrupt mask and enable interrupts. 1009 */ 1010 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1011 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1012 1013 /* 1014 * Give the transmit and receive rings to the EPIC. 1015 */ 1016 bus_space_write_4(st, sh, EPIC_PTCDAR, 1017 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1018 bus_space_write_4(st, sh, EPIC_PRCDAR, 1019 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1020 1021 /* 1022 * Set the EPIC in motion. 1023 */ 1024 bus_space_write_4(st, sh, EPIC_COMMAND, 1025 COMMAND_RXQUEUED | COMMAND_START_RX); 1026 1027 /* 1028 * ...all done! 1029 */ 1030 ifp->if_flags |= IFF_RUNNING; 1031 ifp->if_flags &= ~IFF_OACTIVE; 1032 1033 /* 1034 * Start the one second clock. 1035 */ 1036 timeout(epic_tick, sc, hz); 1037 1038 /* 1039 * Attempt to start output on the interface. 1040 */ 1041 epic_start(ifp); 1042 } 1043 1044 /* 1045 * Stop transmission on the interface. 1046 */ 1047 void 1048 epic_stop(sc) 1049 struct epic_softc *sc; 1050 { 1051 bus_space_tag_t st = sc->sc_st; 1052 bus_space_handle_t sh = sc->sc_sh; 1053 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1054 struct epic_descsoft *ds; 1055 u_int32_t reg; 1056 int i; 1057 1058 /* 1059 * Stop the one second clock. 1060 */ 1061 untimeout(epic_tick, sc); 1062 1063 /* Paranoia... */ 1064 epic_fixup_clock_source(sc); 1065 1066 /* 1067 * Disable interrupts. 1068 */ 1069 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1070 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1071 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1072 1073 /* 1074 * Stop the DMA engine and take the receiver off-line. 1075 */ 1076 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1077 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1078 1079 /* 1080 * Release any queued transmit buffers. 1081 */ 1082 for (i = 0; i < EPIC_NTXDESC; i++) { 1083 ds = EPIC_DSTX(sc, i); 1084 if (ds->ds_mbuf != NULL) { 1085 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1086 m_freem(ds->ds_mbuf); 1087 ds->ds_mbuf = NULL; 1088 } 1089 } 1090 1091 /* 1092 * Mark the interface down and cancel the watchdog timer. 1093 */ 1094 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1095 ifp->if_timer = 0; 1096 } 1097 1098 /* 1099 * Read the EPIC Serial EEPROM. 1100 */ 1101 void 1102 epic_read_eeprom(sc, word, wordcnt, data) 1103 struct epic_softc *sc; 1104 int word, wordcnt; 1105 u_int16_t *data; 1106 { 1107 bus_space_tag_t st = sc->sc_st; 1108 bus_space_handle_t sh = sc->sc_sh; 1109 u_int16_t reg; 1110 int i, x; 1111 1112 #define EEPROM_WAIT_READY(st, sh) \ 1113 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1114 /* nothing */ 1115 1116 /* 1117 * Enable the EEPROM. 1118 */ 1119 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1120 EEPROM_WAIT_READY(st, sh); 1121 1122 for (i = 0; i < wordcnt; i++) { 1123 /* Send CHIP SELECT for one clock tick. */ 1124 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1125 EEPROM_WAIT_READY(st, sh); 1126 1127 /* Shift in the READ opcode. */ 1128 for (x = 3; x > 0; x--) { 1129 reg = EECTL_ENABLE|EECTL_EECS; 1130 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1131 reg |= EECTL_EEDI; 1132 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1133 EEPROM_WAIT_READY(st, sh); 1134 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1135 EEPROM_WAIT_READY(st, sh); 1136 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1137 EEPROM_WAIT_READY(st, sh); 1138 } 1139 1140 /* Shift in address. */ 1141 for (x = 6; x > 0; x--) { 1142 reg = EECTL_ENABLE|EECTL_EECS; 1143 if ((word + i) & (1 << (x - 1))) 1144 reg |= EECTL_EEDI; 1145 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1146 EEPROM_WAIT_READY(st, sh); 1147 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1148 EEPROM_WAIT_READY(st, sh); 1149 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1150 EEPROM_WAIT_READY(st, sh); 1151 } 1152 1153 /* Shift out data. */ 1154 reg = EECTL_ENABLE|EECTL_EECS; 1155 data[i] = 0; 1156 for (x = 16; x > 0; x--) { 1157 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1158 EEPROM_WAIT_READY(st, sh); 1159 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1160 data[i] |= (1 << (x - 1)); 1161 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1162 EEPROM_WAIT_READY(st, sh); 1163 } 1164 1165 /* Clear CHIP SELECT. */ 1166 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1167 EEPROM_WAIT_READY(st, sh); 1168 } 1169 1170 /* 1171 * Disable the EEPROM. 1172 */ 1173 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1174 1175 #undef EEPROM_WAIT_READY 1176 } 1177 1178 /* 1179 * Add a receive buffer to the indicated descriptor. 1180 */ 1181 int 1182 epic_add_rxbuf(sc, idx) 1183 struct epic_softc *sc; 1184 int idx; 1185 { 1186 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1187 struct mbuf *m; 1188 int error; 1189 1190 MGETHDR(m, M_DONTWAIT, MT_DATA); 1191 if (m == NULL) 1192 return (ENOBUFS); 1193 1194 MCLGET(m, M_DONTWAIT); 1195 if ((m->m_flags & M_EXT) == 0) { 1196 m_freem(m); 1197 return (ENOBUFS); 1198 } 1199 1200 if (ds->ds_mbuf != NULL) 1201 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1202 1203 ds->ds_mbuf = m; 1204 1205 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1206 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1207 if (error) { 1208 printf("%s: can't load rx DMA map %d, error = %d\n", 1209 sc->sc_dev.dv_xname, idx, error); 1210 panic("epic_add_rxbuf"); /* XXX */ 1211 } 1212 1213 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1214 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1215 1216 EPIC_INIT_RXDESC(sc, idx); 1217 1218 return (0); 1219 } 1220 1221 /* 1222 * Set the EPIC multicast hash table. 1223 * 1224 * NOTE: We rely on a recently-updated mii_media_active here! 1225 */ 1226 void 1227 epic_set_mchash(sc) 1228 struct epic_softc *sc; 1229 { 1230 struct ethercom *ec = &sc->sc_ethercom; 1231 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1232 struct ether_multi *enm; 1233 struct ether_multistep step; 1234 u_int8_t *cp; 1235 u_int32_t crc, mchash[4]; 1236 int len; 1237 static const u_int32_t crctab[] = { 1238 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, 1239 0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c, 1240 0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c, 1241 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c 1242 }; 1243 1244 /* 1245 * Set up the multicast address filter by passing all multicast 1246 * addresses through a CRC generator, and then using the high-order 1247 * 6 bits as an index into the 64 bit multicast hash table (only 1248 * the lower 16 bits of each 32 bit multicast hash register are 1249 * valid). The high order bit selects the register, while the 1250 * rest of the bits select the bit within the register. 1251 */ 1252 1253 if (ifp->if_flags & IFF_PROMISC) 1254 goto allmulti; 1255 1256 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1257 /* XXX hardware bug in 10Mbps mode. */ 1258 goto allmulti; 1259 } 1260 1261 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1262 1263 ETHER_FIRST_MULTI(step, ec, enm); 1264 while (enm != NULL) { 1265 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1266 /* 1267 * We must listen to a range of multicast addresses. 1268 * For now, just accept all multicasts, rather than 1269 * trying to set only those filter bits needed to match 1270 * the range. (At this time, the only use of address 1271 * ranges is for IP multicast routing, for which the 1272 * range is big enough to require all bits set.) 1273 */ 1274 goto allmulti; 1275 } 1276 1277 cp = enm->enm_addrlo; 1278 crc = 0xffffffff; 1279 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1280 crc ^= *cp++; 1281 crc = (crc >> 4) ^ crctab[crc & 0xf]; 1282 crc = (crc >> 4) ^ crctab[crc & 0xf]; 1283 } 1284 /* Just want the 6 most significant bits. */ 1285 crc >>= 26; 1286 1287 /* Set the corresponding bit in the hash table. */ 1288 mchash[crc >> 4] |= 1 << (crc & 0xf); 1289 1290 ETHER_NEXT_MULTI(step, enm); 1291 } 1292 1293 ifp->if_flags &= ~IFF_ALLMULTI; 1294 goto sethash; 1295 1296 allmulti: 1297 ifp->if_flags |= IFF_ALLMULTI; 1298 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1299 1300 sethash: 1301 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1302 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1303 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1304 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1305 } 1306 1307 /* 1308 * Wait for the MII to become ready. 1309 */ 1310 int 1311 epic_mii_wait(sc, rw) 1312 struct epic_softc *sc; 1313 u_int32_t rw; 1314 { 1315 int i; 1316 1317 for (i = 0; i < 50; i++) { 1318 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1319 == 0) 1320 break; 1321 delay(2); 1322 } 1323 if (i == 50) { 1324 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1325 return (1); 1326 } 1327 1328 return (0); 1329 } 1330 1331 /* 1332 * Read from the MII. 1333 */ 1334 int 1335 epic_mii_read(self, phy, reg) 1336 struct device *self; 1337 int phy, reg; 1338 { 1339 struct epic_softc *sc = (struct epic_softc *)self; 1340 1341 if (epic_mii_wait(sc, MMCTL_WRITE)) 1342 return (0); 1343 1344 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1345 MMCTL_ARG(phy, reg, MMCTL_READ)); 1346 1347 if (epic_mii_wait(sc, MMCTL_READ)) 1348 return (0); 1349 1350 return (bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) & 1351 MMDATA_MASK); 1352 } 1353 1354 /* 1355 * Write to the MII. 1356 */ 1357 void 1358 epic_mii_write(self, phy, reg, val) 1359 struct device *self; 1360 int phy, reg, val; 1361 { 1362 struct epic_softc *sc = (struct epic_softc *)self; 1363 1364 if (epic_mii_wait(sc, MMCTL_WRITE)) 1365 return; 1366 1367 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1368 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1369 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1370 } 1371 1372 /* 1373 * Callback from PHY when media changes. 1374 */ 1375 void 1376 epic_statchg(self) 1377 struct device *self; 1378 { 1379 struct epic_softc *sc = (struct epic_softc *)self; 1380 u_int32_t txcon; 1381 1382 /* 1383 * Update loopback bits in TXCON to reflect duplex mode. 1384 */ 1385 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1386 if (sc->sc_mii.mii_media_active & IFM_FDX) 1387 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1388 else 1389 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1390 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1391 1392 /* 1393 * There is a multicast filter bug in 10Mbps mode. Kick the 1394 * multicast filter in case the speed changed. 1395 */ 1396 epic_set_mchash(sc); 1397 1398 /* XXX Update ifp->if_baudrate */ 1399 } 1400 1401 /* 1402 * Callback from ifmedia to request current media status. 1403 */ 1404 void 1405 epic_mediastatus(ifp, ifmr) 1406 struct ifnet *ifp; 1407 struct ifmediareq *ifmr; 1408 { 1409 struct epic_softc *sc = ifp->if_softc; 1410 1411 mii_pollstat(&sc->sc_mii); 1412 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1413 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1414 } 1415 1416 /* 1417 * Callback from ifmedia to request new media setting. 1418 */ 1419 int 1420 epic_mediachange(ifp) 1421 struct ifnet *ifp; 1422 { 1423 struct epic_softc *sc = ifp->if_softc; 1424 1425 if (ifp->if_flags & IFF_UP) 1426 mii_mediachg(&sc->sc_mii); 1427 return (0); 1428 } 1429
Indexes created Wed Sep 24 02:09:48 GMT 2025