smc83c170.c revision 1.18
1 /* $NetBSD: smc83c170.c,v 1.18 1999/07/27 00:55:34 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Device driver for the Standard Microsystems Corp. 83C170 42 * Ethernet PCI Integrated Controller (EPIC/100). 43 */ 44 45 #include "opt_inet.h" 46 #include "opt_ns.h" 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #endif 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 73 #ifdef NS 74 #include <netns/ns.h> 75 #include <netns/ns_if.h> 76 #endif 77 78 #include <machine/bus.h> 79 #include <machine/intr.h> 80 81 #include <dev/mii/miivar.h> 82 83 #include <dev/ic/smc83c170reg.h> 84 #include <dev/ic/smc83c170var.h> 85 86 void epic_start __P((struct ifnet *)); 87 void epic_watchdog __P((struct ifnet *)); 88 int epic_ioctl __P((struct ifnet *, u_long, caddr_t)); 89 90 void epic_shutdown __P((void *)); 91 92 void epic_reset __P((struct epic_softc *)); 93 void epic_init __P((struct epic_softc *)); 94 void epic_stop __P((struct epic_softc *)); 95 int epic_add_rxbuf __P((struct epic_softc *, int)); 96 void epic_read_eeprom __P((struct epic_softc *, int, int, u_int16_t *)); 97 void epic_set_mchash __P((struct epic_softc *)); 98 void epic_fixup_clock_source __P((struct epic_softc *)); 99 int epic_mii_read __P((struct device *, int, int)); 100 void epic_mii_write __P((struct device *, int, int, int)); 101 int epic_mii_wait __P((struct epic_softc *, u_int32_t)); 102 void epic_tick __P((void *)); 103 104 void epic_statchg __P((struct device *)); 105 int epic_mediachange __P((struct ifnet *)); 106 void epic_mediastatus __P((struct ifnet *, struct ifmediareq *)); 107 108 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 109 INTSTAT_TXC | INTSTAT_RQE | INTSTAT_RCC) 110 111 /* 112 * Attach an EPIC interface to the system. 113 */ 114 void 115 epic_attach(sc) 116 struct epic_softc *sc; 117 { 118 bus_space_tag_t st = sc->sc_st; 119 bus_space_handle_t sh = sc->sc_sh; 120 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 121 int i, rseg, error; 122 bus_dma_segment_t seg; 123 u_int8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 124 u_int16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 125 126 /* 127 * Allocate the control data structures, and create and load the 128 * DMA map for it. 129 */ 130 if ((error = bus_dmamem_alloc(sc->sc_dmat, 131 sizeof(struct epic_control_data), NBPG, 0, &seg, 1, &rseg, 132 BUS_DMA_NOWAIT)) != 0) { 133 printf("%s: unable to allocate control data, error = %d\n", 134 sc->sc_dev.dv_xname, error); 135 goto fail_0; 136 } 137 138 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 139 sizeof(struct epic_control_data), (caddr_t *)&sc->sc_control_data, 140 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 141 printf("%s: unable to map control data, error = %d\n", 142 sc->sc_dev.dv_xname, error); 143 goto fail_1; 144 } 145 146 if ((error = bus_dmamap_create(sc->sc_dmat, 147 sizeof(struct epic_control_data), 1, 148 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 149 &sc->sc_cddmamap)) != 0) { 150 printf("%s: unable to create control data DMA map, " 151 "error = %d\n", sc->sc_dev.dv_xname, error); 152 goto fail_2; 153 } 154 155 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 156 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 157 BUS_DMA_NOWAIT)) != 0) { 158 printf("%s: unable to load control data DMA map, error = %d\n", 159 sc->sc_dev.dv_xname, error); 160 goto fail_3; 161 } 162 163 /* 164 * Create the transmit buffer DMA maps. 165 */ 166 for (i = 0; i < EPIC_NTXDESC; i++) { 167 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 168 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 169 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 170 printf("%s: unable to create tx DMA map %d, " 171 "error = %d\n", sc->sc_dev.dv_xname, i, error); 172 goto fail_4; 173 } 174 } 175 176 /* 177 * Create the recieve buffer DMA maps. 178 */ 179 for (i = 0; i < EPIC_NRXDESC; i++) { 180 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 181 MCLBYTES, 0, BUS_DMA_NOWAIT, 182 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 183 printf("%s: unable to create rx DMA map %d, " 184 "error = %d\n", sc->sc_dev.dv_xname, i, error); 185 goto fail_5; 186 } 187 } 188 189 /* 190 * Pre-allocate the receive buffers. 191 */ 192 for (i = 0; i < EPIC_NRXDESC; i++) { 193 if ((error = epic_add_rxbuf(sc, i)) != 0) { 194 printf("%s: unable to allocate or map rx buffer %d\n," 195 " error = %d\n", sc->sc_dev.dv_xname, i, error); 196 goto fail_6; 197 } 198 } 199 200 /* 201 * Bring the chip out of low-power mode and reset it to a known state. 202 */ 203 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 204 epic_reset(sc); 205 206 /* 207 * Read the Ethernet address from the EEPROM. 208 */ 209 epic_read_eeprom(sc, 0, (sizeof(myea) / sizeof(myea[0])), myea); 210 bcopy(myea, enaddr, sizeof(myea)); 211 212 /* 213 * ...and the device name. 214 */ 215 epic_read_eeprom(sc, 0x2c, (sizeof(mydevname) / sizeof(mydevname[0])), 216 mydevname); 217 bcopy(mydevname, devname, sizeof(mydevname)); 218 devname[sizeof(mydevname)] = '\0'; 219 for (i = sizeof(mydevname) - 1; i >= 0; i--) { 220 if (devname[i] == ' ') 221 devname[i] = '\0'; 222 else 223 break; 224 } 225 226 printf("%s: %s, Ethernet address %s\n", sc->sc_dev.dv_xname, 227 devname, ether_sprintf(enaddr)); 228 229 /* 230 * Initialize our media structures and probe the MII. 231 */ 232 sc->sc_mii.mii_ifp = ifp; 233 sc->sc_mii.mii_readreg = epic_mii_read; 234 sc->sc_mii.mii_writereg = epic_mii_write; 235 sc->sc_mii.mii_statchg = epic_statchg; 236 ifmedia_init(&sc->sc_mii.mii_media, 0, epic_mediachange, 237 epic_mediastatus); 238 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 239 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 240 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 241 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 242 } else 243 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 244 245 ifp = &sc->sc_ethercom.ec_if; 246 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 247 ifp->if_softc = sc; 248 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 249 ifp->if_ioctl = epic_ioctl; 250 ifp->if_start = epic_start; 251 ifp->if_watchdog = epic_watchdog; 252 253 /* 254 * Attach the interface. 255 */ 256 if_attach(ifp); 257 ether_ifattach(ifp, enaddr); 258 #if NBPFILTER > 0 259 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 260 sizeof(struct ether_header)); 261 #endif 262 263 /* 264 * Make sure the interface is shutdown during reboot. 265 */ 266 sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc); 267 if (sc->sc_sdhook == NULL) 268 printf("%s: WARNING: unable to establish shutdown hook\n", 269 sc->sc_dev.dv_xname); 270 return; 271 272 /* 273 * Free any resources we've allocated during the failed attach 274 * attempt. Do this in reverse order and fall through. 275 */ 276 fail_6: 277 for (i = 0; i < EPIC_NRXDESC; i++) { 278 if (EPIC_DSRX(sc, i)->ds_mbuf != NULL) { 279 bus_dmamap_unload(sc->sc_dmat, 280 EPIC_DSRX(sc, i)->ds_dmamap); 281 m_freem(EPIC_DSRX(sc, i)->ds_mbuf); 282 } 283 } 284 fail_5: 285 for (i = 0; i < EPIC_NRXDESC; i++) { 286 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 287 bus_dmamap_destroy(sc->sc_dmat, 288 EPIC_DSRX(sc, i)->ds_dmamap); 289 } 290 fail_4: 291 for (i = 0; i < EPIC_NTXDESC; i++) { 292 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 293 bus_dmamap_destroy(sc->sc_dmat, 294 EPIC_DSTX(sc, i)->ds_dmamap); 295 } 296 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 297 fail_3: 298 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 299 fail_2: 300 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 301 sizeof(struct epic_control_data)); 302 fail_1: 303 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 304 fail_0: 305 return; 306 } 307 308 /* 309 * Shutdown hook. Make sure the interface is stopped at reboot. 310 */ 311 void 312 epic_shutdown(arg) 313 void *arg; 314 { 315 struct epic_softc *sc = arg; 316 317 epic_stop(sc); 318 } 319 320 /* 321 * Start packet transmission on the interface. 322 * [ifnet interface function] 323 */ 324 void 325 epic_start(ifp) 326 struct ifnet *ifp; 327 { 328 struct epic_softc *sc = ifp->if_softc; 329 struct mbuf *m0, *m; 330 struct epic_txdesc *txd; 331 struct epic_descsoft *ds; 332 struct epic_fraglist *fr; 333 bus_dmamap_t dmamap; 334 int error, firsttx, nexttx, opending, seg; 335 336 /* 337 * Remember the previous txpending and the first transmit 338 * descriptor we use. 339 */ 340 opending = sc->sc_txpending; 341 firsttx = EPIC_NEXTTX(sc->sc_txlast); 342 343 /* 344 * Loop through the send queue, setting up transmit descriptors 345 * until we drain the queue, or use up all available transmit 346 * descriptors. 347 */ 348 while (sc->sc_txpending < EPIC_NTXDESC) { 349 /* 350 * Grab a packet off the queue. 351 */ 352 IF_DEQUEUE(&ifp->if_snd, m0); 353 if (m0 == NULL) 354 break; 355 356 /* 357 * Get the last and next available transmit descriptor. 358 */ 359 nexttx = EPIC_NEXTTX(sc->sc_txlast); 360 txd = EPIC_CDTX(sc, nexttx); 361 fr = EPIC_CDFL(sc, nexttx); 362 ds = EPIC_DSTX(sc, nexttx); 363 dmamap = ds->ds_dmamap; 364 365 /* 366 * Load the DMA map. If this fails, the packet either 367 * didn't fit in the alloted number of frags, or we were 368 * short on resources. In this case, we'll copy and try 369 * again. 370 */ 371 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 372 BUS_DMA_NOWAIT) != 0) { 373 MGETHDR(m, M_DONTWAIT, MT_DATA); 374 if (m == NULL) { 375 printf("%s: unable to allocate Tx mbuf\n", 376 sc->sc_dev.dv_xname); 377 IF_PREPEND(&ifp->if_snd, m0); 378 break; 379 } 380 if (m0->m_pkthdr.len > MHLEN) { 381 MCLGET(m, M_DONTWAIT); 382 if ((m->m_flags & M_EXT) == 0) { 383 printf("%s: unable to allocate Tx " 384 "cluster\n", sc->sc_dev.dv_xname); 385 m_freem(m); 386 IF_PREPEND(&ifp->if_snd, m0); 387 break; 388 } 389 } 390 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 391 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 392 m_freem(m0); 393 m0 = m; 394 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 395 m0, BUS_DMA_NOWAIT); 396 if (error) { 397 printf("%s: unable to load Tx buffer, " 398 "error = %d\n", sc->sc_dev.dv_xname, error); 399 IF_PREPEND(&ifp->if_snd, m0); 400 break; 401 } 402 } 403 404 /* Initialize the fraglist. */ 405 fr->ef_nfrags = dmamap->dm_nsegs; 406 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 407 fr->ef_frags[seg].ef_addr = 408 dmamap->dm_segs[seg].ds_addr; 409 fr->ef_frags[seg].ef_length = 410 dmamap->dm_segs[seg].ds_len; 411 } 412 413 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 414 415 /* Sync the DMA map. */ 416 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 417 BUS_DMASYNC_PREWRITE); 418 419 /* 420 * Store a pointer to the packet so we can free it later. 421 */ 422 ds->ds_mbuf = m0; 423 424 /* 425 * Fill in the transmit descriptor. The EPIC doesn't 426 * auto-pad, so we have to do this ourselves. 427 */ 428 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 429 txd->et_txlength = max(m0->m_pkthdr.len, ETHER_MIN_LEN); 430 431 /* 432 * If this is the first descriptor we're enqueueing, 433 * don't give it to the EPIC yet. That could cause 434 * a race condition. We'll do it below. 435 */ 436 if (nexttx == firsttx) 437 txd->et_txstatus = 0; 438 else 439 txd->et_txstatus = ET_TXSTAT_OWNER; 440 441 EPIC_CDTXSYNC(sc, nexttx, 442 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 443 444 /* Advance the tx pointer. */ 445 sc->sc_txpending++; 446 sc->sc_txlast = nexttx; 447 448 #if NBPFILTER > 0 449 /* 450 * Pass the packet to any BPF listeners. 451 */ 452 if (ifp->if_bpf) 453 bpf_mtap(ifp->if_bpf, m0); 454 #endif 455 } 456 457 if (sc->sc_txpending == EPIC_NTXDESC) { 458 /* No more slots left; notify upper layer. */ 459 ifp->if_flags |= IFF_OACTIVE; 460 } 461 462 if (sc->sc_txpending != opending) { 463 /* 464 * We enqueued packets. If the transmitter was idle, 465 * reset the txdirty pointer. 466 */ 467 if (opending == 0) 468 sc->sc_txdirty = firsttx; 469 470 /* 471 * Cause a transmit interrupt to happen on the 472 * last packet we enqueued. 473 */ 474 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 475 EPIC_CDTXSYNC(sc, sc->sc_txlast, 476 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 477 478 /* 479 * The entire packet chain is set up. Give the 480 * first descriptor to the EPIC now. 481 */ 482 EPIC_CDTX(sc, firsttx)->et_txstatus = ET_TXSTAT_OWNER; 483 EPIC_CDTXSYNC(sc, firsttx, 484 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 485 486 /* Start the transmitter. */ 487 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 488 COMMAND_TXQUEUED); 489 490 /* Set a watchdog timer in case the chip flakes out. */ 491 ifp->if_timer = 5; 492 } 493 } 494 495 /* 496 * Watchdog timer handler. 497 * [ifnet interface function] 498 */ 499 void 500 epic_watchdog(ifp) 501 struct ifnet *ifp; 502 { 503 struct epic_softc *sc = ifp->if_softc; 504 505 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 506 ifp->if_oerrors++; 507 508 epic_init(sc); 509 } 510 511 /* 512 * Handle control requests from the operator. 513 * [ifnet interface function] 514 */ 515 int 516 epic_ioctl(ifp, cmd, data) 517 struct ifnet *ifp; 518 u_long cmd; 519 caddr_t data; 520 { 521 struct epic_softc *sc = ifp->if_softc; 522 struct ifreq *ifr = (struct ifreq *)data; 523 struct ifaddr *ifa = (struct ifaddr *)data; 524 int s, error = 0; 525 526 s = splnet(); 527 528 switch (cmd) { 529 case SIOCSIFADDR: 530 ifp->if_flags |= IFF_UP; 531 532 switch (ifa->ifa_addr->sa_family) { 533 #ifdef INET 534 case AF_INET: 535 epic_init(sc); 536 arp_ifinit(ifp, ifa); 537 break; 538 #endif /* INET */ 539 #ifdef NS 540 case AF_NS: 541 { 542 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 543 544 if (ns_nullhost(*ina)) 545 ina->x_host = *(union ns_host *) 546 LLADDR(ifp->if_sadl); 547 else 548 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 549 ifp->if_addrlen); 550 /* Set new address. */ 551 epic_init(sc); 552 break; 553 } 554 #endif /* NS */ 555 default: 556 epic_init(sc); 557 break; 558 } 559 break; 560 561 case SIOCSIFMTU: 562 if (ifr->ifr_mtu > ETHERMTU) 563 error = EINVAL; 564 else 565 ifp->if_mtu = ifr->ifr_mtu; 566 break; 567 568 case SIOCSIFFLAGS: 569 if ((ifp->if_flags & IFF_UP) == 0 && 570 (ifp->if_flags & IFF_RUNNING) != 0) { 571 /* 572 * If interface is marked down and it is running, then 573 * stop it. 574 */ 575 epic_stop(sc); 576 } else if ((ifp->if_flags & IFF_UP) != 0 && 577 (ifp->if_flags & IFF_RUNNING) == 0) { 578 /* 579 * If interfase it marked up and it is stopped, then 580 * start it. 581 */ 582 epic_init(sc); 583 } else if ((ifp->if_flags & IFF_UP) != 0) { 584 /* 585 * Reset the interface to pick up changes in any other 586 * flags that affect the hardware state. 587 */ 588 epic_init(sc); 589 } 590 break; 591 592 case SIOCADDMULTI: 593 case SIOCDELMULTI: 594 error = (cmd == SIOCADDMULTI) ? 595 ether_addmulti(ifr, &sc->sc_ethercom) : 596 ether_delmulti(ifr, &sc->sc_ethercom); 597 598 if (error == ENETRESET) { 599 /* 600 * Multicast list has changed; set the hardware filter 601 * accordingly. Update our idea of the current media; 602 * epic_set_mchash() needs to know what it is. 603 */ 604 mii_pollstat(&sc->sc_mii); 605 epic_set_mchash(sc); 606 error = 0; 607 } 608 break; 609 610 case SIOCSIFMEDIA: 611 case SIOCGIFMEDIA: 612 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 613 break; 614 615 default: 616 error = EINVAL; 617 break; 618 } 619 620 splx(s); 621 return (error); 622 } 623 624 /* 625 * Interrupt handler. 626 */ 627 int 628 epic_intr(arg) 629 void *arg; 630 { 631 struct epic_softc *sc = arg; 632 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 633 struct ether_header *eh; 634 struct epic_rxdesc *rxd; 635 struct epic_txdesc *txd; 636 struct epic_descsoft *ds; 637 struct mbuf *m; 638 u_int32_t intstat; 639 int i, len, claimed = 0; 640 641 top: 642 /* 643 * Get the interrupt status from the EPIC. 644 */ 645 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 646 if ((intstat & INTSTAT_INT_ACTV) == 0) 647 return (claimed); 648 649 claimed = 1; 650 651 /* 652 * Acknowledge the interrupt. 653 */ 654 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 655 intstat & INTMASK); 656 657 /* 658 * Check for receive interrupts. 659 */ 660 if (intstat & (INTSTAT_RCC | INTSTAT_RQE)) { 661 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 662 rxd = EPIC_CDRX(sc, i); 663 ds = EPIC_DSRX(sc, i); 664 665 EPIC_CDRXSYNC(sc, i, 666 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 667 668 if (rxd->er_rxstatus & ER_RXSTAT_OWNER) { 669 /* 670 * We have processed all of the 671 * receive buffers. 672 */ 673 break; 674 } 675 676 /* 677 * Make sure the packet arrived intact. If an error 678 * occurred, update stats and reset the descriptor. 679 * The buffer will be reused the next time the 680 * descriptor comes up in the ring. 681 */ 682 if ((rxd->er_rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 683 if (rxd->er_rxstatus & ER_RXSTAT_CRCERROR) 684 printf("%s: CRC error\n", 685 sc->sc_dev.dv_xname); 686 if (rxd->er_rxstatus & ER_RXSTAT_ALIGNERROR) 687 printf("%s: alignment error\n", 688 sc->sc_dev.dv_xname); 689 ifp->if_ierrors++; 690 EPIC_INIT_RXDESC(sc, i); 691 continue; 692 } 693 694 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 695 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 696 697 /* 698 * Add a new buffer to the receive chain. If this 699 * fails, the old buffer is recycled. 700 */ 701 m = ds->ds_mbuf; 702 if (epic_add_rxbuf(sc, i) != 0) { 703 ifp->if_ierrors++; 704 EPIC_INIT_RXDESC(sc, i); 705 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 706 ds->ds_dmamap->dm_mapsize, 707 BUS_DMASYNC_PREREAD); 708 continue; 709 } 710 711 len = rxd->er_rxlength; 712 if (len < sizeof(struct ether_header)) { 713 m_freem(m); 714 continue; 715 } 716 717 m->m_pkthdr.rcvif = ifp; 718 m->m_pkthdr.len = m->m_len = len; 719 eh = mtod(m, struct ether_header *); 720 721 #if NBPFILTER > 0 722 /* 723 * Pass this up to any BPF listeners, but only 724 * pass it up the stack if its for us. 725 */ 726 if (ifp->if_bpf) { 727 bpf_mtap(ifp->if_bpf, m); 728 if ((ifp->if_flags & IFF_PROMISC) != 0 && 729 bcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 730 ETHER_ADDR_LEN) != 0 && 731 (rxd->er_rxstatus & 732 (ER_RXSTAT_BCAST|ER_RXSTAT_MCAST)) == 0) { 733 m_freem(m); 734 continue; 735 } 736 } 737 #endif /* NPBFILTER > 0 */ 738 739 /* Pass it on. */ 740 (*ifp->if_input)(ifp, m); 741 ifp->if_ipackets++; 742 } 743 744 /* Update the recieve pointer. */ 745 sc->sc_rxptr = i; 746 747 /* 748 * Check for receive queue underflow. 749 */ 750 if (intstat & INTSTAT_RQE) { 751 printf("%s: receiver queue empty\n", 752 sc->sc_dev.dv_xname); 753 /* 754 * Ring is already built; just restart the 755 * receiver. 756 */ 757 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 758 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 759 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 760 COMMAND_RXQUEUED | COMMAND_START_RX); 761 } 762 } 763 764 /* 765 * Check for transmission complete interrupts. 766 */ 767 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 768 ifp->if_flags &= ~IFF_OACTIVE; 769 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 770 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 771 txd = EPIC_CDTX(sc, i); 772 ds = EPIC_DSTX(sc, i); 773 774 EPIC_CDTXSYNC(sc, i, 775 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 776 777 if (txd->et_txstatus & ET_TXSTAT_OWNER) 778 break; 779 780 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 781 782 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 783 0, ds->ds_dmamap->dm_mapsize, 784 BUS_DMASYNC_POSTWRITE); 785 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 786 m_freem(ds->ds_mbuf); 787 ds->ds_mbuf = NULL; 788 789 /* 790 * Check for errors and collisions. 791 */ 792 if ((txd->et_txstatus & ET_TXSTAT_PACKETTX) == 0) 793 ifp->if_oerrors++; 794 else 795 ifp->if_opackets++; 796 ifp->if_collisions += 797 TXSTAT_COLLISIONS(txd->et_txstatus); 798 if (txd->et_txstatus & ET_TXSTAT_CARSENSELOST) 799 printf("%s: lost carrier\n", 800 sc->sc_dev.dv_xname); 801 } 802 803 /* Update the dirty transmit buffer pointer. */ 804 sc->sc_txdirty = i; 805 806 /* 807 * Cancel the watchdog timer if there are no pending 808 * transmissions. 809 */ 810 if (sc->sc_txpending == 0) 811 ifp->if_timer = 0; 812 813 /* 814 * Kick the transmitter after a DMA underrun. 815 */ 816 if (intstat & INTSTAT_TXU) { 817 printf("%s: transmit underrun\n", sc->sc_dev.dv_xname); 818 bus_space_write_4(sc->sc_st, sc->sc_sh, 819 EPIC_COMMAND, COMMAND_TXUGO); 820 if (sc->sc_txpending) 821 bus_space_write_4(sc->sc_st, sc->sc_sh, 822 EPIC_COMMAND, COMMAND_TXQUEUED); 823 } 824 825 /* 826 * Try to get more packets going. 827 */ 828 epic_start(ifp); 829 } 830 831 /* 832 * Check for fatal interrupts. 833 */ 834 if (intstat & INTSTAT_FATAL_INT) { 835 printf("%s: fatal error, resetting\n", sc->sc_dev.dv_xname); 836 epic_init(sc); 837 } 838 839 /* 840 * Check for more interrupts. 841 */ 842 goto top; 843 } 844 845 /* 846 * One second timer, used to tick the MII. 847 */ 848 void 849 epic_tick(arg) 850 void *arg; 851 { 852 struct epic_softc *sc = arg; 853 int s; 854 855 s = splnet(); 856 mii_tick(&sc->sc_mii); 857 splx(s); 858 859 timeout(epic_tick, sc, hz); 860 } 861 862 /* 863 * Fixup the clock source on the EPIC. 864 */ 865 void 866 epic_fixup_clock_source(sc) 867 struct epic_softc *sc; 868 { 869 int i; 870 871 /* 872 * According to SMC Application Note 7-15, the EPIC's clock 873 * source is incorrect following a reset. This manifests itself 874 * as failure to recognize when host software has written to 875 * a register on the EPIC. The appnote recommends issuing at 876 * least 16 consecutive writes to the CLOCK TEST bit to correctly 877 * configure the clock source. 878 */ 879 for (i = 0; i < 16; i++) 880 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 881 TEST_CLOCKTEST); 882 } 883 884 /* 885 * Perform a soft reset on the EPIC. 886 */ 887 void 888 epic_reset(sc) 889 struct epic_softc *sc; 890 { 891 892 epic_fixup_clock_source(sc); 893 894 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 895 delay(100); 896 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 897 delay(100); 898 899 epic_fixup_clock_source(sc); 900 } 901 902 /* 903 * Initialize the interface. Must be called at splnet(). 904 */ 905 void 906 epic_init(sc) 907 struct epic_softc *sc; 908 { 909 bus_space_tag_t st = sc->sc_st; 910 bus_space_handle_t sh = sc->sc_sh; 911 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 912 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 913 struct epic_txdesc *txd; 914 u_int32_t genctl, reg0; 915 int i; 916 917 /* 918 * Cancel any pending I/O. 919 */ 920 epic_stop(sc); 921 922 /* 923 * Reset the EPIC to a known state. 924 */ 925 epic_reset(sc); 926 927 /* 928 * Magical mystery initialization. 929 */ 930 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 931 932 /* 933 * Initialize the EPIC genctl register: 934 * 935 * - 64 byte receive FIFO threshold 936 * - automatic advance to next receive frame 937 */ 938 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 939 #if BYTE_ORDER == BIG_ENDIAN 940 genctl |= GENCTL_BIG_ENDIAN; 941 #endif 942 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 943 944 /* 945 * Reset the MII bus and PHY. 946 */ 947 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 948 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 949 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 950 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 951 delay(100); 952 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 953 delay(100); 954 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 955 956 /* 957 * Initialize Ethernet address. 958 */ 959 reg0 = enaddr[1] << 8 | enaddr[0]; 960 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 961 reg0 = enaddr[3] << 8 | enaddr[2]; 962 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 963 reg0 = enaddr[5] << 8 | enaddr[4]; 964 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 965 966 /* 967 * Initialize receive control. Remember the external buffer 968 * size setting. 969 */ 970 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 971 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 972 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 973 if (ifp->if_flags & IFF_PROMISC) 974 reg0 |= RXCON_PROMISCMODE; 975 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 976 977 /* Set the current media. */ 978 mii_mediachg(&sc->sc_mii); 979 980 /* Set up the multicast hash table. */ 981 epic_set_mchash(sc); 982 983 /* 984 * Initialize the transmit descriptor ring. txlast is initialized 985 * to the end of the list so that it will wrap around to the first 986 * descriptor when the first packet is transmitted. 987 */ 988 for (i = 0; i < EPIC_NTXDESC; i++) { 989 txd = EPIC_CDTX(sc, i); 990 memset(txd, 0, sizeof(struct epic_txdesc)); 991 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 992 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 993 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 994 } 995 sc->sc_txpending = 0; 996 sc->sc_txdirty = 0; 997 sc->sc_txlast = EPIC_NTXDESC - 1; 998 999 /* 1000 * Initialize the receive descriptor ring. The buffers are 1001 * already allocated. 1002 */ 1003 for (i = 0; i < EPIC_NRXDESC; i++) 1004 EPIC_INIT_RXDESC(sc, i); 1005 sc->sc_rxptr = 0; 1006 1007 /* 1008 * Initialize the interrupt mask and enable interrupts. 1009 */ 1010 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1011 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1012 1013 /* 1014 * Give the transmit and receive rings to the EPIC. 1015 */ 1016 bus_space_write_4(st, sh, EPIC_PTCDAR, 1017 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1018 bus_space_write_4(st, sh, EPIC_PRCDAR, 1019 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1020 1021 /* 1022 * Set the EPIC in motion. 1023 */ 1024 bus_space_write_4(st, sh, EPIC_COMMAND, 1025 COMMAND_RXQUEUED | COMMAND_START_RX); 1026 1027 /* 1028 * ...all done! 1029 */ 1030 ifp->if_flags |= IFF_RUNNING; 1031 ifp->if_flags &= ~IFF_OACTIVE; 1032 1033 /* 1034 * Start the one second clock. 1035 */ 1036 timeout(epic_tick, sc, hz); 1037 1038 /* 1039 * Attempt to start output on the interface. 1040 */ 1041 epic_start(ifp); 1042 } 1043 1044 /* 1045 * Stop transmission on the interface. 1046 */ 1047 void 1048 epic_stop(sc) 1049 struct epic_softc *sc; 1050 { 1051 bus_space_tag_t st = sc->sc_st; 1052 bus_space_handle_t sh = sc->sc_sh; 1053 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1054 struct epic_descsoft *ds; 1055 u_int32_t reg; 1056 int i; 1057 1058 /* 1059 * Stop the one second clock. 1060 */ 1061 untimeout(epic_tick, sc); 1062 1063 /* Paranoia... */ 1064 epic_fixup_clock_source(sc); 1065 1066 /* 1067 * Disable interrupts. 1068 */ 1069 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1070 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1071 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1072 1073 /* 1074 * Stop the DMA engine and take the receiver off-line. 1075 */ 1076 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1077 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1078 1079 /* 1080 * Release any queued transmit buffers. 1081 */ 1082 for (i = 0; i < EPIC_NTXDESC; i++) { 1083 ds = EPIC_DSTX(sc, i); 1084 if (ds->ds_mbuf != NULL) { 1085 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1086 m_freem(ds->ds_mbuf); 1087 ds->ds_mbuf = NULL; 1088 } 1089 } 1090 1091 /* 1092 * Mark the interface down and cancel the watchdog timer. 1093 */ 1094 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1095 ifp->if_timer = 0; 1096 } 1097 1098 /* 1099 * Read the EPIC Serial EEPROM. 1100 */ 1101 void 1102 epic_read_eeprom(sc, word, wordcnt, data) 1103 struct epic_softc *sc; 1104 int word, wordcnt; 1105 u_int16_t *data; 1106 { 1107 bus_space_tag_t st = sc->sc_st; 1108 bus_space_handle_t sh = sc->sc_sh; 1109 u_int16_t reg; 1110 int i, x; 1111 1112 #define EEPROM_WAIT_READY(st, sh) \ 1113 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1114 /* nothing */ 1115 1116 /* 1117 * Enable the EEPROM. 1118 */ 1119 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1120 EEPROM_WAIT_READY(st, sh); 1121 1122 for (i = 0; i < wordcnt; i++) { 1123 /* Send CHIP SELECT for one clock tick. */ 1124 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1125 EEPROM_WAIT_READY(st, sh); 1126 1127 /* Shift in the READ opcode. */ 1128 for (x = 3; x > 0; x--) { 1129 reg = EECTL_ENABLE|EECTL_EECS; 1130 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1131 reg |= EECTL_EEDI; 1132 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1133 EEPROM_WAIT_READY(st, sh); 1134 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1135 EEPROM_WAIT_READY(st, sh); 1136 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1137 EEPROM_WAIT_READY(st, sh); 1138 } 1139 1140 /* Shift in address. */ 1141 for (x = 6; x > 0; x--) { 1142 reg = EECTL_ENABLE|EECTL_EECS; 1143 if ((word + i) & (1 << (x - 1))) 1144 reg |= EECTL_EEDI; 1145 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1146 EEPROM_WAIT_READY(st, sh); 1147 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1148 EEPROM_WAIT_READY(st, sh); 1149 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1150 EEPROM_WAIT_READY(st, sh); 1151 } 1152 1153 /* Shift out data. */ 1154 reg = EECTL_ENABLE|EECTL_EECS; 1155 data[i] = 0; 1156 for (x = 16; x > 0; x--) { 1157 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1158 EEPROM_WAIT_READY(st, sh); 1159 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1160 data[i] |= (1 << (x - 1)); 1161 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1162 EEPROM_WAIT_READY(st, sh); 1163 } 1164 1165 /* Clear CHIP SELECT. */ 1166 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1167 EEPROM_WAIT_READY(st, sh); 1168 } 1169 1170 /* 1171 * Disable the EEPROM. 1172 */ 1173 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1174 1175 #undef EEPROM_WAIT_READY 1176 } 1177 1178 /* 1179 * Add a receive buffer to the indicated descriptor. 1180 */ 1181 int 1182 epic_add_rxbuf(sc, idx) 1183 struct epic_softc *sc; 1184 int idx; 1185 { 1186 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1187 struct mbuf *m; 1188 int error; 1189 1190 MGETHDR(m, M_DONTWAIT, MT_DATA); 1191 if (m == NULL) 1192 return (ENOBUFS); 1193 1194 MCLGET(m, M_DONTWAIT); 1195 if ((m->m_flags & M_EXT) == 0) { 1196 m_freem(m); 1197 return (ENOBUFS); 1198 } 1199 1200 if (ds->ds_mbuf != NULL) 1201 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1202 1203 ds->ds_mbuf = m; 1204 1205 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1206 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1207 if (error) { 1208 printf("%s: can't load rx DMA map %d, error = %d\n", 1209 sc->sc_dev.dv_xname, idx, error); 1210 panic("epic_add_rxbuf"); /* XXX */ 1211 } 1212 1213 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1214 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1215 1216 EPIC_INIT_RXDESC(sc, idx); 1217 1218 return (0); 1219 } 1220 1221 /* 1222 * Set the EPIC multicast hash table. 1223 * 1224 * NOTE: We rely on a recently-updated mii_media_active here! 1225 */ 1226 void 1227 epic_set_mchash(sc) 1228 struct epic_softc *sc; 1229 { 1230 struct ethercom *ec = &sc->sc_ethercom; 1231 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1232 struct ether_multi *enm; 1233 struct ether_multistep step; 1234 u_int8_t *cp; 1235 u_int32_t crc, mchash[4]; 1236 int len; 1237 static const u_int32_t crctab[] = { 1238 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, 1239 0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c, 1240 0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c, 1241 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c 1242 }; 1243 1244 /* 1245 * Set up the multicast address filter by passing all multicast 1246 * addresses through a CRC generator, and then using the high-order 1247 * 6 bits as an index into the 64 bit multicast hash table (only 1248 * the lower 16 bits of each 32 bit multicast hash register are 1249 * valid). The high order bit selects the register, while the 1250 * rest of the bits select the bit within the register. 1251 */ 1252 1253 if (ifp->if_flags & IFF_PROMISC) 1254 goto allmulti; 1255 1256 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1257 /* XXX hardware bug in 10Mbps mode. */ 1258 goto allmulti; 1259 } 1260 1261 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1262 1263 ETHER_FIRST_MULTI(step, ec, enm); 1264 while (enm != NULL) { 1265 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1266 /* 1267 * We must listen to a range of multicast addresses. 1268 * For now, just accept all multicasts, rather than 1269 * trying to set only those filter bits needed to match 1270 * the range. (At this time, the only use of address 1271 * ranges is for IP multicast routing, for which the 1272 * range is big enough to require all bits set.) 1273 */ 1274 goto allmulti; 1275 } 1276 1277 cp = enm->enm_addrlo; 1278 crc = 0xffffffff; 1279 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1280 crc ^= *cp++; 1281 crc = (crc >> 4) ^ crctab[crc & 0xf]; 1282 crc = (crc >> 4) ^ crctab[crc & 0xf]; 1283 } 1284 /* Just want the 6 most significant bits. */ 1285 crc >>= 26; 1286 1287 /* Set the corresponding bit in the hash table. */ 1288 mchash[crc >> 4] |= 1 << (crc & 0xf); 1289 1290 ETHER_NEXT_MULTI(step, enm); 1291 } 1292 1293 ifp->if_flags &= ~IFF_ALLMULTI; 1294 goto sethash; 1295 1296 allmulti: 1297 ifp->if_flags |= IFF_ALLMULTI; 1298 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1299 1300 sethash: 1301 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1302 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1303 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1304 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1305 } 1306 1307 /* 1308 * Wait for the MII to become ready. 1309 */ 1310 int 1311 epic_mii_wait(sc, rw) 1312 struct epic_softc *sc; 1313 u_int32_t rw; 1314 { 1315 int i; 1316 1317 for (i = 0; i < 50; i++) { 1318 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1319 == 0) 1320 break; 1321 delay(2); 1322 } 1323 if (i == 50) { 1324 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1325 return (1); 1326 } 1327 1328 return (0); 1329 } 1330 1331 /* 1332 * Read from the MII. 1333 */ 1334 int 1335 epic_mii_read(self, phy, reg) 1336 struct device *self; 1337 int phy, reg; 1338 { 1339 struct epic_softc *sc = (struct epic_softc *)self; 1340 1341 if (epic_mii_wait(sc, MMCTL_WRITE)) 1342 return (0); 1343 1344 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1345 MMCTL_ARG(phy, reg, MMCTL_READ)); 1346 1347 if (epic_mii_wait(sc, MMCTL_READ)) 1348 return (0); 1349 1350 return (bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) & 1351 MMDATA_MASK); 1352 } 1353 1354 /* 1355 * Write to the MII. 1356 */ 1357 void 1358 epic_mii_write(self, phy, reg, val) 1359 struct device *self; 1360 int phy, reg, val; 1361 { 1362 struct epic_softc *sc = (struct epic_softc *)self; 1363 1364 if (epic_mii_wait(sc, MMCTL_WRITE)) 1365 return; 1366 1367 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1368 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1369 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1370 } 1371 1372 /* 1373 * Callback from PHY when media changes. 1374 */ 1375 void 1376 epic_statchg(self) 1377 struct device *self; 1378 { 1379 struct epic_softc *sc = (struct epic_softc *)self; 1380 u_int32_t txcon; 1381 1382 /* 1383 * Update loopback bits in TXCON to reflect duplex mode. 1384 */ 1385 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1386 if (sc->sc_mii.mii_media_active & IFM_FDX) 1387 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1388 else 1389 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1390 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1391 1392 /* 1393 * There is a multicast filter bug in 10Mbps mode. Kick the 1394 * multicast filter in case the speed changed. 1395 */ 1396 epic_set_mchash(sc); 1397 1398 /* XXX Update ifp->if_baudrate */ 1399 } 1400 1401 /* 1402 * Callback from ifmedia to request current media status. 1403 */ 1404 void 1405 epic_mediastatus(ifp, ifmr) 1406 struct ifnet *ifp; 1407 struct ifmediareq *ifmr; 1408 { 1409 struct epic_softc *sc = ifp->if_softc; 1410 1411 mii_pollstat(&sc->sc_mii); 1412 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1413 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1414 } 1415 1416 /* 1417 * Callback from ifmedia to request new media setting. 1418 */ 1419 int 1420 epic_mediachange(ifp) 1421 struct ifnet *ifp; 1422 { 1423 struct epic_softc *sc = ifp->if_softc; 1424 1425 if (ifp->if_flags & IFF_UP) 1426 mii_mediachg(&sc->sc_mii); 1427 return (0); 1428 } 1429
Indexes created Wed Sep 24 15:09:51 GMT 2025