smc83c170.c revision 1.38
1 /* $NetBSD: smc83c170.c,v 1.38 2000/11/14 18:21:02 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Device driver for the Standard Microsystems Corp. 83C170 42 * Ethernet PCI Integrated Controller (EPIC/100). 43 */ 44 45 #include "opt_inet.h" 46 #include "opt_ns.h" 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #include <net/if.h> 63 #include <net/if_dl.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/if_inarp.h> 74 #endif 75 76 #ifdef NS 77 #include <netns/ns.h> 78 #include <netns/ns_if.h> 79 #endif 80 81 #include <machine/bus.h> 82 #include <machine/intr.h> 83 84 #include <dev/mii/miivar.h> 85 86 #include <dev/ic/smc83c170reg.h> 87 #include <dev/ic/smc83c170var.h> 88 89 void epic_start __P((struct ifnet *)); 90 void epic_watchdog __P((struct ifnet *)); 91 int epic_ioctl __P((struct ifnet *, u_long, caddr_t)); 92 int epic_init __P((struct ifnet *)); 93 void epic_stop __P((struct ifnet *, int)); 94 95 void epic_shutdown __P((void *)); 96 97 void epic_reset __P((struct epic_softc *)); 98 void epic_rxdrain __P((struct epic_softc *)); 99 int epic_add_rxbuf __P((struct epic_softc *, int)); 100 void epic_read_eeprom __P((struct epic_softc *, int, int, u_int16_t *)); 101 void epic_set_mchash __P((struct epic_softc *)); 102 void epic_fixup_clock_source __P((struct epic_softc *)); 103 int epic_mii_read __P((struct device *, int, int)); 104 void epic_mii_write __P((struct device *, int, int, int)); 105 int epic_mii_wait __P((struct epic_softc *, u_int32_t)); 106 void epic_tick __P((void *)); 107 108 void epic_statchg __P((struct device *)); 109 int epic_mediachange __P((struct ifnet *)); 110 void epic_mediastatus __P((struct ifnet *, struct ifmediareq *)); 111 112 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 113 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 114 115 int epic_copy_small = 0; 116 117 /* 118 * Attach an EPIC interface to the system. 119 */ 120 void 121 epic_attach(sc) 122 struct epic_softc *sc; 123 { 124 bus_space_tag_t st = sc->sc_st; 125 bus_space_handle_t sh = sc->sc_sh; 126 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 127 int i, rseg, error; 128 bus_dma_segment_t seg; 129 u_int8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 130 u_int16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 131 132 callout_init(&sc->sc_mii_callout); 133 134 /* 135 * Allocate the control data structures, and create and load the 136 * DMA map for it. 137 */ 138 if ((error = bus_dmamem_alloc(sc->sc_dmat, 139 sizeof(struct epic_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 140 BUS_DMA_NOWAIT)) != 0) { 141 printf("%s: unable to allocate control data, error = %d\n", 142 sc->sc_dev.dv_xname, error); 143 goto fail_0; 144 } 145 146 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 147 sizeof(struct epic_control_data), (caddr_t *)&sc->sc_control_data, 148 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 149 printf("%s: unable to map control data, error = %d\n", 150 sc->sc_dev.dv_xname, error); 151 goto fail_1; 152 } 153 154 if ((error = bus_dmamap_create(sc->sc_dmat, 155 sizeof(struct epic_control_data), 1, 156 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 157 &sc->sc_cddmamap)) != 0) { 158 printf("%s: unable to create control data DMA map, " 159 "error = %d\n", sc->sc_dev.dv_xname, error); 160 goto fail_2; 161 } 162 163 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 164 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 165 BUS_DMA_NOWAIT)) != 0) { 166 printf("%s: unable to load control data DMA map, error = %d\n", 167 sc->sc_dev.dv_xname, error); 168 goto fail_3; 169 } 170 171 /* 172 * Create the transmit buffer DMA maps. 173 */ 174 for (i = 0; i < EPIC_NTXDESC; i++) { 175 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 176 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 177 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 178 printf("%s: unable to create tx DMA map %d, " 179 "error = %d\n", sc->sc_dev.dv_xname, i, error); 180 goto fail_4; 181 } 182 } 183 184 /* 185 * Create the recieve buffer DMA maps. 186 */ 187 for (i = 0; i < EPIC_NRXDESC; i++) { 188 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 189 MCLBYTES, 0, BUS_DMA_NOWAIT, 190 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 191 printf("%s: unable to create rx DMA map %d, " 192 "error = %d\n", sc->sc_dev.dv_xname, i, error); 193 goto fail_5; 194 } 195 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 196 } 197 198 199 /* 200 * Bring the chip out of low-power mode and reset it to a known state. 201 */ 202 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 203 epic_reset(sc); 204 205 /* 206 * Read the Ethernet address from the EEPROM. 207 */ 208 epic_read_eeprom(sc, 0, (sizeof(myea) / sizeof(myea[0])), myea); 209 for (i = 0; i < sizeof(myea)/ sizeof(myea[0]); i++) { 210 enaddr[i * 2] = myea[i] & 0xff; 211 enaddr[i * 2 + 1] = myea[i] >> 8; 212 } 213 214 /* 215 * ...and the device name. 216 */ 217 epic_read_eeprom(sc, 0x2c, (sizeof(mydevname) / sizeof(mydevname[0])), 218 mydevname); 219 for (i = 0; i < sizeof(mydevname) / sizeof(mydevname[0]); i++) { 220 devname[i * 2] = mydevname[i] & 0xff; 221 devname[i * 2 + 1] = mydevname[i] >> 8; 222 } 223 224 devname[sizeof(mydevname)] = '\0'; 225 for (i = sizeof(mydevname) - 1; i >= 0; i--) { 226 if (devname[i] == ' ') 227 devname[i] = '\0'; 228 else 229 break; 230 } 231 232 printf("%s: %s, Ethernet address %s\n", sc->sc_dev.dv_xname, 233 devname, ether_sprintf(enaddr)); 234 235 /* 236 * Initialize our media structures and probe the MII. 237 */ 238 sc->sc_mii.mii_ifp = ifp; 239 sc->sc_mii.mii_readreg = epic_mii_read; 240 sc->sc_mii.mii_writereg = epic_mii_write; 241 sc->sc_mii.mii_statchg = epic_statchg; 242 ifmedia_init(&sc->sc_mii.mii_media, 0, epic_mediachange, 243 epic_mediastatus); 244 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 245 MII_OFFSET_ANY, 0); 246 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 247 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 248 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 249 } else 250 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 251 252 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 253 ifp->if_softc = sc; 254 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 255 ifp->if_ioctl = epic_ioctl; 256 ifp->if_start = epic_start; 257 ifp->if_watchdog = epic_watchdog; 258 ifp->if_init = epic_init; 259 ifp->if_stop = epic_stop; 260 261 /* 262 * We can support 802.1Q VLAN-sized frames. 263 */ 264 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 265 266 /* 267 * Attach the interface. 268 */ 269 if_attach(ifp); 270 ether_ifattach(ifp, enaddr); 271 #if NBPFILTER > 0 272 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 273 sizeof(struct ether_header)); 274 #endif 275 276 /* 277 * Make sure the interface is shutdown during reboot. 278 */ 279 sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc); 280 if (sc->sc_sdhook == NULL) 281 printf("%s: WARNING: unable to establish shutdown hook\n", 282 sc->sc_dev.dv_xname); 283 return; 284 285 /* 286 * Free any resources we've allocated during the failed attach 287 * attempt. Do this in reverse order and fall through. 288 */ 289 fail_5: 290 for (i = 0; i < EPIC_NRXDESC; i++) { 291 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 292 bus_dmamap_destroy(sc->sc_dmat, 293 EPIC_DSRX(sc, i)->ds_dmamap); 294 } 295 fail_4: 296 for (i = 0; i < EPIC_NTXDESC; i++) { 297 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 298 bus_dmamap_destroy(sc->sc_dmat, 299 EPIC_DSTX(sc, i)->ds_dmamap); 300 } 301 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 302 fail_3: 303 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 304 fail_2: 305 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 306 sizeof(struct epic_control_data)); 307 fail_1: 308 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 309 fail_0: 310 return; 311 } 312 313 /* 314 * Shutdown hook. Make sure the interface is stopped at reboot. 315 */ 316 void 317 epic_shutdown(arg) 318 void *arg; 319 { 320 struct epic_softc *sc = arg; 321 322 epic_stop(&sc->sc_ethercom.ec_if, 1); 323 } 324 325 /* 326 * Start packet transmission on the interface. 327 * [ifnet interface function] 328 */ 329 void 330 epic_start(ifp) 331 struct ifnet *ifp; 332 { 333 struct epic_softc *sc = ifp->if_softc; 334 struct mbuf *m0, *m; 335 struct epic_txdesc *txd; 336 struct epic_descsoft *ds; 337 struct epic_fraglist *fr; 338 bus_dmamap_t dmamap; 339 int error, firsttx, nexttx, opending, seg; 340 341 /* 342 * Remember the previous txpending and the first transmit 343 * descriptor we use. 344 */ 345 opending = sc->sc_txpending; 346 firsttx = EPIC_NEXTTX(sc->sc_txlast); 347 348 /* 349 * Loop through the send queue, setting up transmit descriptors 350 * until we drain the queue, or use up all available transmit 351 * descriptors. 352 */ 353 while (sc->sc_txpending < EPIC_NTXDESC) { 354 /* 355 * Grab a packet off the queue. 356 */ 357 IF_DEQUEUE(&ifp->if_snd, m0); 358 if (m0 == NULL) 359 break; 360 361 /* 362 * Get the last and next available transmit descriptor. 363 */ 364 nexttx = EPIC_NEXTTX(sc->sc_txlast); 365 txd = EPIC_CDTX(sc, nexttx); 366 fr = EPIC_CDFL(sc, nexttx); 367 ds = EPIC_DSTX(sc, nexttx); 368 dmamap = ds->ds_dmamap; 369 370 /* 371 * Load the DMA map. If this fails, the packet either 372 * didn't fit in the alloted number of frags, or we were 373 * short on resources. In this case, we'll copy and try 374 * again. 375 */ 376 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 377 BUS_DMA_NOWAIT) != 0) { 378 MGETHDR(m, M_DONTWAIT, MT_DATA); 379 if (m == NULL) { 380 printf("%s: unable to allocate Tx mbuf\n", 381 sc->sc_dev.dv_xname); 382 IF_PREPEND(&ifp->if_snd, m0); 383 break; 384 } 385 if (m0->m_pkthdr.len > MHLEN) { 386 MCLGET(m, M_DONTWAIT); 387 if ((m->m_flags & M_EXT) == 0) { 388 printf("%s: unable to allocate Tx " 389 "cluster\n", sc->sc_dev.dv_xname); 390 m_freem(m); 391 IF_PREPEND(&ifp->if_snd, m0); 392 break; 393 } 394 } 395 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 396 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 397 m_freem(m0); 398 m0 = m; 399 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 400 m0, BUS_DMA_NOWAIT); 401 if (error) { 402 printf("%s: unable to load Tx buffer, " 403 "error = %d\n", sc->sc_dev.dv_xname, error); 404 IF_PREPEND(&ifp->if_snd, m0); 405 break; 406 } 407 } 408 409 /* Initialize the fraglist. */ 410 fr->ef_nfrags = dmamap->dm_nsegs; 411 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 412 fr->ef_frags[seg].ef_addr = 413 dmamap->dm_segs[seg].ds_addr; 414 fr->ef_frags[seg].ef_length = 415 dmamap->dm_segs[seg].ds_len; 416 } 417 418 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 419 420 /* Sync the DMA map. */ 421 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 422 BUS_DMASYNC_PREWRITE); 423 424 /* 425 * Store a pointer to the packet so we can free it later. 426 */ 427 ds->ds_mbuf = m0; 428 429 /* 430 * Fill in the transmit descriptor. The EPIC doesn't 431 * auto-pad, so we have to do this ourselves. 432 */ 433 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 434 txd->et_txlength = max(m0->m_pkthdr.len, 435 ETHER_MIN_LEN - ETHER_CRC_LEN); 436 437 /* 438 * If this is the first descriptor we're enqueueing, 439 * don't give it to the EPIC yet. That could cause 440 * a race condition. We'll do it below. 441 */ 442 if (nexttx == firsttx) 443 txd->et_txstatus = 0; 444 else 445 txd->et_txstatus = ET_TXSTAT_OWNER; 446 447 EPIC_CDTXSYNC(sc, nexttx, 448 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 449 450 /* Advance the tx pointer. */ 451 sc->sc_txpending++; 452 sc->sc_txlast = nexttx; 453 454 #if NBPFILTER > 0 455 /* 456 * Pass the packet to any BPF listeners. 457 */ 458 if (ifp->if_bpf) 459 bpf_mtap(ifp->if_bpf, m0); 460 #endif 461 } 462 463 if (sc->sc_txpending == EPIC_NTXDESC) { 464 /* No more slots left; notify upper layer. */ 465 ifp->if_flags |= IFF_OACTIVE; 466 } 467 468 if (sc->sc_txpending != opending) { 469 /* 470 * We enqueued packets. If the transmitter was idle, 471 * reset the txdirty pointer. 472 */ 473 if (opending == 0) 474 sc->sc_txdirty = firsttx; 475 476 /* 477 * Cause a transmit interrupt to happen on the 478 * last packet we enqueued. 479 */ 480 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 481 EPIC_CDTXSYNC(sc, sc->sc_txlast, 482 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 483 484 /* 485 * The entire packet chain is set up. Give the 486 * first descriptor to the EPIC now. 487 */ 488 EPIC_CDTX(sc, firsttx)->et_txstatus = ET_TXSTAT_OWNER; 489 EPIC_CDTXSYNC(sc, firsttx, 490 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 491 492 /* Start the transmitter. */ 493 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 494 COMMAND_TXQUEUED); 495 496 /* Set a watchdog timer in case the chip flakes out. */ 497 ifp->if_timer = 5; 498 } 499 } 500 501 /* 502 * Watchdog timer handler. 503 * [ifnet interface function] 504 */ 505 void 506 epic_watchdog(ifp) 507 struct ifnet *ifp; 508 { 509 struct epic_softc *sc = ifp->if_softc; 510 511 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 512 ifp->if_oerrors++; 513 514 (void) epic_init(ifp); 515 } 516 517 /* 518 * Handle control requests from the operator. 519 * [ifnet interface function] 520 */ 521 int 522 epic_ioctl(ifp, cmd, data) 523 struct ifnet *ifp; 524 u_long cmd; 525 caddr_t data; 526 { 527 struct epic_softc *sc = ifp->if_softc; 528 struct ifreq *ifr = (struct ifreq *)data; 529 int s, error; 530 531 s = splnet(); 532 533 switch (cmd) { 534 case SIOCSIFMEDIA: 535 case SIOCGIFMEDIA: 536 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 537 break; 538 539 default: 540 error = ether_ioctl(ifp, cmd, data); 541 if (error == ENETRESET) { 542 /* 543 * Multicast list has changed; set the hardware filter 544 * accordingly. Update our idea of the current media; 545 * epic_set_mchash() needs to know what it is. 546 */ 547 mii_pollstat(&sc->sc_mii); 548 epic_set_mchash(sc); 549 error = 0; 550 } 551 break; 552 } 553 554 splx(s); 555 return (error); 556 } 557 558 /* 559 * Interrupt handler. 560 */ 561 int 562 epic_intr(arg) 563 void *arg; 564 { 565 struct epic_softc *sc = arg; 566 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 567 struct epic_rxdesc *rxd; 568 struct epic_txdesc *txd; 569 struct epic_descsoft *ds; 570 struct mbuf *m; 571 u_int32_t intstat; 572 int i, len, claimed = 0; 573 574 top: 575 /* 576 * Get the interrupt status from the EPIC. 577 */ 578 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 579 if ((intstat & INTSTAT_INT_ACTV) == 0) 580 return (claimed); 581 582 claimed = 1; 583 584 /* 585 * Acknowledge the interrupt. 586 */ 587 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 588 intstat & INTMASK); 589 590 /* 591 * Check for receive interrupts. 592 */ 593 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 594 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 595 rxd = EPIC_CDRX(sc, i); 596 ds = EPIC_DSRX(sc, i); 597 598 EPIC_CDRXSYNC(sc, i, 599 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 600 601 if (rxd->er_rxstatus & ER_RXSTAT_OWNER) { 602 /* 603 * We have processed all of the 604 * receive buffers. 605 */ 606 break; 607 } 608 609 /* 610 * Make sure the packet arrived intact. If an error 611 * occurred, update stats and reset the descriptor. 612 * The buffer will be reused the next time the 613 * descriptor comes up in the ring. 614 */ 615 if ((rxd->er_rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 616 if (rxd->er_rxstatus & ER_RXSTAT_CRCERROR) 617 printf("%s: CRC error\n", 618 sc->sc_dev.dv_xname); 619 if (rxd->er_rxstatus & ER_RXSTAT_ALIGNERROR) 620 printf("%s: alignment error\n", 621 sc->sc_dev.dv_xname); 622 ifp->if_ierrors++; 623 EPIC_INIT_RXDESC(sc, i); 624 continue; 625 } 626 627 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 628 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 629 630 /* 631 * The EPIC includes the CRC with every packet. 632 */ 633 len = rxd->er_rxlength; 634 635 if (len < sizeof(struct ether_header)) { 636 /* 637 * Runt packet; drop it now. 638 */ 639 ifp->if_ierrors++; 640 EPIC_INIT_RXDESC(sc, i); 641 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 642 ds->ds_dmamap->dm_mapsize, 643 BUS_DMASYNC_PREREAD); 644 continue; 645 } 646 647 /* 648 * If the packet is small enough to fit in a 649 * single header mbuf, allocate one and copy 650 * the data into it. This greatly reduces 651 * memory consumption when we receive lots 652 * of small packets. 653 * 654 * Otherwise, we add a new buffer to the receive 655 * chain. If this fails, we drop the packet and 656 * recycle the old buffer. 657 */ 658 if (epic_copy_small != 0 && len <= MHLEN) { 659 MGETHDR(m, M_DONTWAIT, MT_DATA); 660 if (m == NULL) 661 goto dropit; 662 memcpy(mtod(m, caddr_t), 663 mtod(ds->ds_mbuf, caddr_t), len); 664 EPIC_INIT_RXDESC(sc, i); 665 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 666 ds->ds_dmamap->dm_mapsize, 667 BUS_DMASYNC_PREREAD); 668 } else { 669 m = ds->ds_mbuf; 670 if (epic_add_rxbuf(sc, i) != 0) { 671 dropit: 672 ifp->if_ierrors++; 673 EPIC_INIT_RXDESC(sc, i); 674 bus_dmamap_sync(sc->sc_dmat, 675 ds->ds_dmamap, 0, 676 ds->ds_dmamap->dm_mapsize, 677 BUS_DMASYNC_PREREAD); 678 continue; 679 } 680 } 681 682 m->m_flags |= M_HASFCS; 683 m->m_pkthdr.rcvif = ifp; 684 m->m_pkthdr.len = m->m_len = len; 685 686 #if NBPFILTER > 0 687 /* 688 * Pass this up to any BPF listeners, but only 689 * pass it up the stack if its for us. 690 */ 691 if (ifp->if_bpf) 692 bpf_mtap(ifp->if_bpf, m); 693 #endif 694 695 /* Pass it on. */ 696 (*ifp->if_input)(ifp, m); 697 ifp->if_ipackets++; 698 } 699 700 /* Update the recieve pointer. */ 701 sc->sc_rxptr = i; 702 703 /* 704 * Check for receive queue underflow. 705 */ 706 if (intstat & INTSTAT_RQE) { 707 printf("%s: receiver queue empty\n", 708 sc->sc_dev.dv_xname); 709 /* 710 * Ring is already built; just restart the 711 * receiver. 712 */ 713 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 714 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 715 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 716 COMMAND_RXQUEUED | COMMAND_START_RX); 717 } 718 } 719 720 /* 721 * Check for transmission complete interrupts. 722 */ 723 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 724 ifp->if_flags &= ~IFF_OACTIVE; 725 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 726 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 727 txd = EPIC_CDTX(sc, i); 728 ds = EPIC_DSTX(sc, i); 729 730 EPIC_CDTXSYNC(sc, i, 731 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 732 733 if (txd->et_txstatus & ET_TXSTAT_OWNER) 734 break; 735 736 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 737 738 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 739 0, ds->ds_dmamap->dm_mapsize, 740 BUS_DMASYNC_POSTWRITE); 741 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 742 m_freem(ds->ds_mbuf); 743 ds->ds_mbuf = NULL; 744 745 /* 746 * Check for errors and collisions. 747 */ 748 if ((txd->et_txstatus & ET_TXSTAT_PACKETTX) == 0) 749 ifp->if_oerrors++; 750 else 751 ifp->if_opackets++; 752 ifp->if_collisions += 753 TXSTAT_COLLISIONS(txd->et_txstatus); 754 if (txd->et_txstatus & ET_TXSTAT_CARSENSELOST) 755 printf("%s: lost carrier\n", 756 sc->sc_dev.dv_xname); 757 } 758 759 /* Update the dirty transmit buffer pointer. */ 760 sc->sc_txdirty = i; 761 762 /* 763 * Cancel the watchdog timer if there are no pending 764 * transmissions. 765 */ 766 if (sc->sc_txpending == 0) 767 ifp->if_timer = 0; 768 769 /* 770 * Kick the transmitter after a DMA underrun. 771 */ 772 if (intstat & INTSTAT_TXU) { 773 printf("%s: transmit underrun\n", sc->sc_dev.dv_xname); 774 bus_space_write_4(sc->sc_st, sc->sc_sh, 775 EPIC_COMMAND, COMMAND_TXUGO); 776 if (sc->sc_txpending) 777 bus_space_write_4(sc->sc_st, sc->sc_sh, 778 EPIC_COMMAND, COMMAND_TXQUEUED); 779 } 780 781 /* 782 * Try to get more packets going. 783 */ 784 epic_start(ifp); 785 } 786 787 /* 788 * Check for fatal interrupts. 789 */ 790 if (intstat & INTSTAT_FATAL_INT) { 791 if (intstat & INTSTAT_PTA) 792 printf("%s: PCI target abort error\n", 793 sc->sc_dev.dv_xname); 794 else if (intstat & INTSTAT_PMA) 795 printf("%s: PCI master abort error\n", 796 sc->sc_dev.dv_xname); 797 else if (intstat & INTSTAT_APE) 798 printf("%s: PCI address parity error\n", 799 sc->sc_dev.dv_xname); 800 else if (intstat & INTSTAT_DPE) 801 printf("%s: PCI data parity error\n", 802 sc->sc_dev.dv_xname); 803 else 804 printf("%s: unknown fatal error\n", 805 sc->sc_dev.dv_xname); 806 (void) epic_init(ifp); 807 } 808 809 /* 810 * Check for more interrupts. 811 */ 812 goto top; 813 } 814 815 /* 816 * One second timer, used to tick the MII. 817 */ 818 void 819 epic_tick(arg) 820 void *arg; 821 { 822 struct epic_softc *sc = arg; 823 int s; 824 825 s = splnet(); 826 mii_tick(&sc->sc_mii); 827 splx(s); 828 829 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 830 } 831 832 /* 833 * Fixup the clock source on the EPIC. 834 */ 835 void 836 epic_fixup_clock_source(sc) 837 struct epic_softc *sc; 838 { 839 int i; 840 841 /* 842 * According to SMC Application Note 7-15, the EPIC's clock 843 * source is incorrect following a reset. This manifests itself 844 * as failure to recognize when host software has written to 845 * a register on the EPIC. The appnote recommends issuing at 846 * least 16 consecutive writes to the CLOCK TEST bit to correctly 847 * configure the clock source. 848 */ 849 for (i = 0; i < 16; i++) 850 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 851 TEST_CLOCKTEST); 852 } 853 854 /* 855 * Perform a soft reset on the EPIC. 856 */ 857 void 858 epic_reset(sc) 859 struct epic_softc *sc; 860 { 861 862 epic_fixup_clock_source(sc); 863 864 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 865 delay(100); 866 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 867 delay(100); 868 869 epic_fixup_clock_source(sc); 870 } 871 872 /* 873 * Initialize the interface. Must be called at splnet(). 874 */ 875 int 876 epic_init(ifp) 877 struct ifnet *ifp; 878 { 879 struct epic_softc *sc = ifp->if_softc; 880 bus_space_tag_t st = sc->sc_st; 881 bus_space_handle_t sh = sc->sc_sh; 882 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 883 struct epic_txdesc *txd; 884 struct epic_descsoft *ds; 885 u_int32_t genctl, reg0; 886 int i, error = 0; 887 888 /* 889 * Cancel any pending I/O. 890 */ 891 epic_stop(ifp, 0); 892 893 /* 894 * Reset the EPIC to a known state. 895 */ 896 epic_reset(sc); 897 898 /* 899 * Magical mystery initialization. 900 */ 901 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 902 903 /* 904 * Initialize the EPIC genctl register: 905 * 906 * - 64 byte receive FIFO threshold 907 * - automatic advance to next receive frame 908 */ 909 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 910 #if BYTE_ORDER == BIG_ENDIAN 911 genctl |= GENCTL_BIG_ENDIAN; 912 #endif 913 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 914 915 /* 916 * Reset the MII bus and PHY. 917 */ 918 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 919 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 920 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 921 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 922 delay(100); 923 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 924 delay(100); 925 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 926 927 /* 928 * Initialize Ethernet address. 929 */ 930 reg0 = enaddr[1] << 8 | enaddr[0]; 931 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 932 reg0 = enaddr[3] << 8 | enaddr[2]; 933 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 934 reg0 = enaddr[5] << 8 | enaddr[4]; 935 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 936 937 /* 938 * Initialize receive control. Remember the external buffer 939 * size setting. 940 */ 941 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 942 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 943 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 944 if (ifp->if_flags & IFF_PROMISC) 945 reg0 |= RXCON_PROMISCMODE; 946 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 947 948 /* Set the current media. */ 949 mii_mediachg(&sc->sc_mii); 950 951 /* Set up the multicast hash table. */ 952 epic_set_mchash(sc); 953 954 /* 955 * Initialize the transmit descriptor ring. txlast is initialized 956 * to the end of the list so that it will wrap around to the first 957 * descriptor when the first packet is transmitted. 958 */ 959 for (i = 0; i < EPIC_NTXDESC; i++) { 960 txd = EPIC_CDTX(sc, i); 961 memset(txd, 0, sizeof(struct epic_txdesc)); 962 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 963 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 964 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 965 } 966 sc->sc_txpending = 0; 967 sc->sc_txdirty = 0; 968 sc->sc_txlast = EPIC_NTXDESC - 1; 969 970 /* 971 * Initialize the receive descriptor ring. 972 */ 973 for (i = 0; i < EPIC_NRXDESC; i++) { 974 ds = EPIC_DSRX(sc, i); 975 if (ds->ds_mbuf == NULL) { 976 if ((error = epic_add_rxbuf(sc, i)) != 0) { 977 printf("%s: unable to allocate or map rx " 978 "buffer %d error = %d\n", 979 sc->sc_dev.dv_xname, i, error); 980 /* 981 * XXX Should attempt to run with fewer receive 982 * XXX buffers instead of just failing. 983 */ 984 epic_rxdrain(sc); 985 goto out; 986 } 987 } 988 } 989 sc->sc_rxptr = 0; 990 991 /* 992 * Initialize the interrupt mask and enable interrupts. 993 */ 994 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 995 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 996 997 /* 998 * Give the transmit and receive rings to the EPIC. 999 */ 1000 bus_space_write_4(st, sh, EPIC_PTCDAR, 1001 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1002 bus_space_write_4(st, sh, EPIC_PRCDAR, 1003 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1004 1005 /* 1006 * Set the EPIC in motion. 1007 */ 1008 bus_space_write_4(st, sh, EPIC_COMMAND, 1009 COMMAND_RXQUEUED | COMMAND_START_RX); 1010 1011 /* 1012 * ...all done! 1013 */ 1014 ifp->if_flags |= IFF_RUNNING; 1015 ifp->if_flags &= ~IFF_OACTIVE; 1016 1017 /* 1018 * Start the one second clock. 1019 */ 1020 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 1021 1022 /* 1023 * Attempt to start output on the interface. 1024 */ 1025 epic_start(ifp); 1026 1027 out: 1028 if (error) 1029 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1030 return (error); 1031 } 1032 1033 /* 1034 * Drain the receive queue. 1035 */ 1036 void 1037 epic_rxdrain(sc) 1038 struct epic_softc *sc; 1039 { 1040 struct epic_descsoft *ds; 1041 int i; 1042 1043 for (i = 0; i < EPIC_NRXDESC; i++) { 1044 ds = EPIC_DSRX(sc, i); 1045 if (ds->ds_mbuf != NULL) { 1046 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1047 m_freem(ds->ds_mbuf); 1048 ds->ds_mbuf = NULL; 1049 } 1050 } 1051 } 1052 1053 /* 1054 * Stop transmission on the interface. 1055 */ 1056 void 1057 epic_stop(ifp, disable) 1058 struct ifnet *ifp; 1059 int disable; 1060 { 1061 struct epic_softc *sc = ifp->if_softc; 1062 bus_space_tag_t st = sc->sc_st; 1063 bus_space_handle_t sh = sc->sc_sh; 1064 struct epic_descsoft *ds; 1065 u_int32_t reg; 1066 int i; 1067 1068 /* 1069 * Stop the one second clock. 1070 */ 1071 callout_stop(&sc->sc_mii_callout); 1072 1073 /* Down the MII. */ 1074 mii_down(&sc->sc_mii); 1075 1076 /* Paranoia... */ 1077 epic_fixup_clock_source(sc); 1078 1079 /* 1080 * Disable interrupts. 1081 */ 1082 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1083 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1084 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1085 1086 /* 1087 * Stop the DMA engine and take the receiver off-line. 1088 */ 1089 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1090 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1091 1092 /* 1093 * Release any queued transmit buffers. 1094 */ 1095 for (i = 0; i < EPIC_NTXDESC; i++) { 1096 ds = EPIC_DSTX(sc, i); 1097 if (ds->ds_mbuf != NULL) { 1098 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1099 m_freem(ds->ds_mbuf); 1100 ds->ds_mbuf = NULL; 1101 } 1102 } 1103 1104 if (disable) 1105 epic_rxdrain(sc); 1106 1107 /* 1108 * Mark the interface down and cancel the watchdog timer. 1109 */ 1110 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1111 ifp->if_timer = 0; 1112 } 1113 1114 /* 1115 * Read the EPIC Serial EEPROM. 1116 */ 1117 void 1118 epic_read_eeprom(sc, word, wordcnt, data) 1119 struct epic_softc *sc; 1120 int word, wordcnt; 1121 u_int16_t *data; 1122 { 1123 bus_space_tag_t st = sc->sc_st; 1124 bus_space_handle_t sh = sc->sc_sh; 1125 u_int16_t reg; 1126 int i, x; 1127 1128 #define EEPROM_WAIT_READY(st, sh) \ 1129 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1130 /* nothing */ 1131 1132 /* 1133 * Enable the EEPROM. 1134 */ 1135 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1136 EEPROM_WAIT_READY(st, sh); 1137 1138 for (i = 0; i < wordcnt; i++) { 1139 /* Send CHIP SELECT for one clock tick. */ 1140 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1141 EEPROM_WAIT_READY(st, sh); 1142 1143 /* Shift in the READ opcode. */ 1144 for (x = 3; x > 0; x--) { 1145 reg = EECTL_ENABLE|EECTL_EECS; 1146 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1147 reg |= EECTL_EEDI; 1148 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1149 EEPROM_WAIT_READY(st, sh); 1150 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1151 EEPROM_WAIT_READY(st, sh); 1152 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1153 EEPROM_WAIT_READY(st, sh); 1154 } 1155 1156 /* Shift in address. */ 1157 for (x = 6; x > 0; x--) { 1158 reg = EECTL_ENABLE|EECTL_EECS; 1159 if ((word + i) & (1 << (x - 1))) 1160 reg |= EECTL_EEDI; 1161 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1162 EEPROM_WAIT_READY(st, sh); 1163 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1164 EEPROM_WAIT_READY(st, sh); 1165 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1166 EEPROM_WAIT_READY(st, sh); 1167 } 1168 1169 /* Shift out data. */ 1170 reg = EECTL_ENABLE|EECTL_EECS; 1171 data[i] = 0; 1172 for (x = 16; x > 0; x--) { 1173 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1174 EEPROM_WAIT_READY(st, sh); 1175 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1176 data[i] |= (1 << (x - 1)); 1177 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1178 EEPROM_WAIT_READY(st, sh); 1179 } 1180 1181 /* Clear CHIP SELECT. */ 1182 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1183 EEPROM_WAIT_READY(st, sh); 1184 } 1185 1186 /* 1187 * Disable the EEPROM. 1188 */ 1189 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1190 1191 #undef EEPROM_WAIT_READY 1192 } 1193 1194 /* 1195 * Add a receive buffer to the indicated descriptor. 1196 */ 1197 int 1198 epic_add_rxbuf(sc, idx) 1199 struct epic_softc *sc; 1200 int idx; 1201 { 1202 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1203 struct mbuf *m; 1204 int error; 1205 1206 MGETHDR(m, M_DONTWAIT, MT_DATA); 1207 if (m == NULL) 1208 return (ENOBUFS); 1209 1210 MCLGET(m, M_DONTWAIT); 1211 if ((m->m_flags & M_EXT) == 0) { 1212 m_freem(m); 1213 return (ENOBUFS); 1214 } 1215 1216 if (ds->ds_mbuf != NULL) 1217 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1218 1219 ds->ds_mbuf = m; 1220 1221 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1222 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1223 if (error) { 1224 printf("%s: can't load rx DMA map %d, error = %d\n", 1225 sc->sc_dev.dv_xname, idx, error); 1226 panic("epic_add_rxbuf"); /* XXX */ 1227 } 1228 1229 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1230 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1231 1232 EPIC_INIT_RXDESC(sc, idx); 1233 1234 return (0); 1235 } 1236 1237 /* 1238 * Set the EPIC multicast hash table. 1239 * 1240 * NOTE: We rely on a recently-updated mii_media_active here! 1241 */ 1242 void 1243 epic_set_mchash(sc) 1244 struct epic_softc *sc; 1245 { 1246 struct ethercom *ec = &sc->sc_ethercom; 1247 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1248 struct ether_multi *enm; 1249 struct ether_multistep step; 1250 u_int32_t hash, mchash[4]; 1251 1252 /* 1253 * Set up the multicast address filter by passing all multicast 1254 * addresses through a CRC generator, and then using the low-order 1255 * 6 bits as an index into the 64 bit multicast hash table (only 1256 * the lower 16 bits of each 32 bit multicast hash register are 1257 * valid). The high order bits select the register, while the 1258 * rest of the bits select the bit within the register. 1259 */ 1260 1261 if (ifp->if_flags & IFF_PROMISC) 1262 goto allmulti; 1263 1264 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1265 /* XXX hardware bug in 10Mbps mode. */ 1266 goto allmulti; 1267 } 1268 1269 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1270 1271 ETHER_FIRST_MULTI(step, ec, enm); 1272 while (enm != NULL) { 1273 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1274 /* 1275 * We must listen to a range of multicast addresses. 1276 * For now, just accept all multicasts, rather than 1277 * trying to set only those filter bits needed to match 1278 * the range. (At this time, the only use of address 1279 * ranges is for IP multicast routing, for which the 1280 * range is big enough to require all bits set.) 1281 */ 1282 goto allmulti; 1283 } 1284 1285 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1286 hash >>= 26; 1287 1288 /* Set the corresponding bit in the hash table. */ 1289 mchash[hash >> 4] |= 1 << (hash & 0xf); 1290 1291 ETHER_NEXT_MULTI(step, enm); 1292 } 1293 1294 ifp->if_flags &= ~IFF_ALLMULTI; 1295 goto sethash; 1296 1297 allmulti: 1298 ifp->if_flags |= IFF_ALLMULTI; 1299 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1300 1301 sethash: 1302 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1303 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1304 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1305 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1306 } 1307 1308 /* 1309 * Wait for the MII to become ready. 1310 */ 1311 int 1312 epic_mii_wait(sc, rw) 1313 struct epic_softc *sc; 1314 u_int32_t rw; 1315 { 1316 int i; 1317 1318 for (i = 0; i < 50; i++) { 1319 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1320 == 0) 1321 break; 1322 delay(2); 1323 } 1324 if (i == 50) { 1325 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1326 return (1); 1327 } 1328 1329 return (0); 1330 } 1331 1332 /* 1333 * Read from the MII. 1334 */ 1335 int 1336 epic_mii_read(self, phy, reg) 1337 struct device *self; 1338 int phy, reg; 1339 { 1340 struct epic_softc *sc = (struct epic_softc *)self; 1341 1342 if (epic_mii_wait(sc, MMCTL_WRITE)) 1343 return (0); 1344 1345 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1346 MMCTL_ARG(phy, reg, MMCTL_READ)); 1347 1348 if (epic_mii_wait(sc, MMCTL_READ)) 1349 return (0); 1350 1351 return (bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) & 1352 MMDATA_MASK); 1353 } 1354 1355 /* 1356 * Write to the MII. 1357 */ 1358 void 1359 epic_mii_write(self, phy, reg, val) 1360 struct device *self; 1361 int phy, reg, val; 1362 { 1363 struct epic_softc *sc = (struct epic_softc *)self; 1364 1365 if (epic_mii_wait(sc, MMCTL_WRITE)) 1366 return; 1367 1368 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1369 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1370 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1371 } 1372 1373 /* 1374 * Callback from PHY when media changes. 1375 */ 1376 void 1377 epic_statchg(self) 1378 struct device *self; 1379 { 1380 struct epic_softc *sc = (struct epic_softc *)self; 1381 u_int32_t txcon; 1382 1383 /* 1384 * Update loopback bits in TXCON to reflect duplex mode. 1385 */ 1386 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1387 if (sc->sc_mii.mii_media_active & IFM_FDX) 1388 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1389 else 1390 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1391 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1392 1393 /* 1394 * There is a multicast filter bug in 10Mbps mode. Kick the 1395 * multicast filter in case the speed changed. 1396 */ 1397 epic_set_mchash(sc); 1398 } 1399 1400 /* 1401 * Callback from ifmedia to request current media status. 1402 */ 1403 void 1404 epic_mediastatus(ifp, ifmr) 1405 struct ifnet *ifp; 1406 struct ifmediareq *ifmr; 1407 { 1408 struct epic_softc *sc = ifp->if_softc; 1409 1410 mii_pollstat(&sc->sc_mii); 1411 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1412 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1413 } 1414 1415 /* 1416 * Callback from ifmedia to request new media setting. 1417 */ 1418 int 1419 epic_mediachange(ifp) 1420 struct ifnet *ifp; 1421 { 1422 struct epic_softc *sc = ifp->if_softc; 1423 1424 if (ifp->if_flags & IFF_UP) 1425 mii_mediachg(&sc->sc_mii); 1426 return (0); 1427 } 1428
Indexes created Sun Sep 28 16:09:52 GMT 2025