smc83c170.c revision 1.51
1 /* $NetBSD: smc83c170.c,v 1.51 2002/11/07 07:48:35 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Device driver for the Standard Microsystems Corp. 83C170 42 * Ethernet PCI Integrated Controller (EPIC/100). 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.51 2002/11/07 07:48:35 thorpej Exp $"); 47 48 #include "bpfilter.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/callout.h> 53 #include <sys/mbuf.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/socket.h> 57 #include <sys/ioctl.h> 58 #include <sys/errno.h> 59 #include <sys/device.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/mii/miivar.h> 76 #include <dev/mii/lxtphyreg.h> 77 78 #include <dev/ic/smc83c170reg.h> 79 #include <dev/ic/smc83c170var.h> 80 81 void epic_start __P((struct ifnet *)); 82 void epic_watchdog __P((struct ifnet *)); 83 int epic_ioctl __P((struct ifnet *, u_long, caddr_t)); 84 int epic_init __P((struct ifnet *)); 85 void epic_stop __P((struct ifnet *, int)); 86 87 void epic_shutdown __P((void *)); 88 89 void epic_reset __P((struct epic_softc *)); 90 void epic_rxdrain __P((struct epic_softc *)); 91 int epic_add_rxbuf __P((struct epic_softc *, int)); 92 void epic_read_eeprom __P((struct epic_softc *, int, int, u_int16_t *)); 93 void epic_set_mchash __P((struct epic_softc *)); 94 void epic_fixup_clock_source __P((struct epic_softc *)); 95 int epic_mii_read __P((struct device *, int, int)); 96 void epic_mii_write __P((struct device *, int, int, int)); 97 int epic_mii_wait __P((struct epic_softc *, u_int32_t)); 98 void epic_tick __P((void *)); 99 100 void epic_statchg __P((struct device *)); 101 int epic_mediachange __P((struct ifnet *)); 102 void epic_mediastatus __P((struct ifnet *, struct ifmediareq *)); 103 104 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 105 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 106 107 int epic_copy_small = 0; 108 109 /* 110 * Attach an EPIC interface to the system. 111 */ 112 void 113 epic_attach(sc) 114 struct epic_softc *sc; 115 { 116 bus_space_tag_t st = sc->sc_st; 117 bus_space_handle_t sh = sc->sc_sh; 118 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 119 int rseg, error, miiflags; 120 u_int i; 121 bus_dma_segment_t seg; 122 u_int8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 123 u_int16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 124 125 callout_init(&sc->sc_mii_callout); 126 127 /* 128 * Allocate the control data structures, and create and load the 129 * DMA map for it. 130 */ 131 if ((error = bus_dmamem_alloc(sc->sc_dmat, 132 sizeof(struct epic_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 133 BUS_DMA_NOWAIT)) != 0) { 134 printf("%s: unable to allocate control data, error = %d\n", 135 sc->sc_dev.dv_xname, error); 136 goto fail_0; 137 } 138 139 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 140 sizeof(struct epic_control_data), (caddr_t *)&sc->sc_control_data, 141 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 142 printf("%s: unable to map control data, error = %d\n", 143 sc->sc_dev.dv_xname, error); 144 goto fail_1; 145 } 146 147 if ((error = bus_dmamap_create(sc->sc_dmat, 148 sizeof(struct epic_control_data), 1, 149 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 150 &sc->sc_cddmamap)) != 0) { 151 printf("%s: unable to create control data DMA map, " 152 "error = %d\n", sc->sc_dev.dv_xname, error); 153 goto fail_2; 154 } 155 156 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 157 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 158 BUS_DMA_NOWAIT)) != 0) { 159 printf("%s: unable to load control data DMA map, error = %d\n", 160 sc->sc_dev.dv_xname, error); 161 goto fail_3; 162 } 163 164 /* 165 * Create the transmit buffer DMA maps. 166 */ 167 for (i = 0; i < EPIC_NTXDESC; i++) { 168 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 169 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 170 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 171 printf("%s: unable to create tx DMA map %d, " 172 "error = %d\n", sc->sc_dev.dv_xname, i, error); 173 goto fail_4; 174 } 175 } 176 177 /* 178 * Create the receive buffer DMA maps. 179 */ 180 for (i = 0; i < EPIC_NRXDESC; i++) { 181 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 182 MCLBYTES, 0, BUS_DMA_NOWAIT, 183 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 184 printf("%s: unable to create rx DMA map %d, " 185 "error = %d\n", sc->sc_dev.dv_xname, i, error); 186 goto fail_5; 187 } 188 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 189 } 190 191 192 /* 193 * Bring the chip out of low-power mode and reset it to a known state. 194 */ 195 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 196 epic_reset(sc); 197 198 /* 199 * Read the Ethernet address from the EEPROM. 200 */ 201 epic_read_eeprom(sc, 0, (sizeof(myea) / sizeof(myea[0])), myea); 202 for (i = 0; i < sizeof(myea)/ sizeof(myea[0]); i++) { 203 enaddr[i * 2] = myea[i] & 0xff; 204 enaddr[i * 2 + 1] = myea[i] >> 8; 205 } 206 207 /* 208 * ...and the device name. 209 */ 210 epic_read_eeprom(sc, 0x2c, (sizeof(mydevname) / sizeof(mydevname[0])), 211 mydevname); 212 for (i = 0; i < sizeof(mydevname) / sizeof(mydevname[0]); i++) { 213 devname[i * 2] = mydevname[i] & 0xff; 214 devname[i * 2 + 1] = mydevname[i] >> 8; 215 } 216 217 devname[sizeof(mydevname)] = '\0'; 218 for (i = sizeof(mydevname) - 1; i >= 0; i--) { 219 if (devname[i] == ' ') 220 devname[i] = '\0'; 221 else 222 break; 223 } 224 225 printf("%s: %s, Ethernet address %s\n", sc->sc_dev.dv_xname, 226 devname, ether_sprintf(enaddr)); 227 228 miiflags = 0; 229 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 230 miiflags |= MIIF_HAVEFIBER; 231 232 /* 233 * Initialize our media structures and probe the MII. 234 */ 235 sc->sc_mii.mii_ifp = ifp; 236 sc->sc_mii.mii_readreg = epic_mii_read; 237 sc->sc_mii.mii_writereg = epic_mii_write; 238 sc->sc_mii.mii_statchg = epic_statchg; 239 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epic_mediachange, 240 epic_mediastatus); 241 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 242 MII_OFFSET_ANY, miiflags); 243 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 244 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 245 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 246 } else 247 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 248 249 if (sc->sc_hwflags & EPIC_HAS_BNC) { 250 /* use the next free media instance */ 251 sc->sc_serinst = sc->sc_mii.mii_instance++; 252 ifmedia_add(&sc->sc_mii.mii_media, 253 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, 254 sc->sc_serinst), 255 0, NULL); 256 printf("%s: 10base2/BNC\n", sc->sc_dev.dv_xname); 257 } else 258 sc->sc_serinst = -1; 259 260 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 261 ifp->if_softc = sc; 262 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 263 ifp->if_ioctl = epic_ioctl; 264 ifp->if_start = epic_start; 265 ifp->if_watchdog = epic_watchdog; 266 ifp->if_init = epic_init; 267 ifp->if_stop = epic_stop; 268 IFQ_SET_READY(&ifp->if_snd); 269 270 /* 271 * We can support 802.1Q VLAN-sized frames. 272 */ 273 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 274 275 /* 276 * Attach the interface. 277 */ 278 if_attach(ifp); 279 ether_ifattach(ifp, enaddr); 280 281 /* 282 * Make sure the interface is shutdown during reboot. 283 */ 284 sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc); 285 if (sc->sc_sdhook == NULL) 286 printf("%s: WARNING: unable to establish shutdown hook\n", 287 sc->sc_dev.dv_xname); 288 return; 289 290 /* 291 * Free any resources we've allocated during the failed attach 292 * attempt. Do this in reverse order and fall through. 293 */ 294 fail_5: 295 for (i = 0; i < EPIC_NRXDESC; i++) { 296 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 297 bus_dmamap_destroy(sc->sc_dmat, 298 EPIC_DSRX(sc, i)->ds_dmamap); 299 } 300 fail_4: 301 for (i = 0; i < EPIC_NTXDESC; i++) { 302 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 303 bus_dmamap_destroy(sc->sc_dmat, 304 EPIC_DSTX(sc, i)->ds_dmamap); 305 } 306 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 307 fail_3: 308 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 309 fail_2: 310 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 311 sizeof(struct epic_control_data)); 312 fail_1: 313 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 314 fail_0: 315 return; 316 } 317 318 /* 319 * Shutdown hook. Make sure the interface is stopped at reboot. 320 */ 321 void 322 epic_shutdown(arg) 323 void *arg; 324 { 325 struct epic_softc *sc = arg; 326 327 epic_stop(&sc->sc_ethercom.ec_if, 1); 328 } 329 330 /* 331 * Start packet transmission on the interface. 332 * [ifnet interface function] 333 */ 334 void 335 epic_start(ifp) 336 struct ifnet *ifp; 337 { 338 struct epic_softc *sc = ifp->if_softc; 339 struct mbuf *m0, *m; 340 struct epic_txdesc *txd; 341 struct epic_descsoft *ds; 342 struct epic_fraglist *fr; 343 bus_dmamap_t dmamap; 344 int error, firsttx, nexttx, opending, seg; 345 346 /* 347 * Remember the previous txpending and the first transmit 348 * descriptor we use. 349 */ 350 opending = sc->sc_txpending; 351 firsttx = EPIC_NEXTTX(sc->sc_txlast); 352 353 /* 354 * Loop through the send queue, setting up transmit descriptors 355 * until we drain the queue, or use up all available transmit 356 * descriptors. 357 */ 358 while (sc->sc_txpending < EPIC_NTXDESC) { 359 /* 360 * Grab a packet off the queue. 361 */ 362 IFQ_POLL(&ifp->if_snd, m0); 363 if (m0 == NULL) 364 break; 365 m = NULL; 366 367 /* 368 * Get the last and next available transmit descriptor. 369 */ 370 nexttx = EPIC_NEXTTX(sc->sc_txlast); 371 txd = EPIC_CDTX(sc, nexttx); 372 fr = EPIC_CDFL(sc, nexttx); 373 ds = EPIC_DSTX(sc, nexttx); 374 dmamap = ds->ds_dmamap; 375 376 /* 377 * Load the DMA map. If this fails, the packet either 378 * didn't fit in the alloted number of frags, or we were 379 * short on resources. In this case, we'll copy and try 380 * again. 381 */ 382 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 383 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 384 MGETHDR(m, M_DONTWAIT, MT_DATA); 385 if (m == NULL) { 386 printf("%s: unable to allocate Tx mbuf\n", 387 sc->sc_dev.dv_xname); 388 break; 389 } 390 if (m0->m_pkthdr.len > MHLEN) { 391 MCLGET(m, M_DONTWAIT); 392 if ((m->m_flags & M_EXT) == 0) { 393 printf("%s: unable to allocate Tx " 394 "cluster\n", sc->sc_dev.dv_xname); 395 m_freem(m); 396 break; 397 } 398 } 399 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 400 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 401 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 402 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 403 if (error) { 404 printf("%s: unable to load Tx buffer, " 405 "error = %d\n", sc->sc_dev.dv_xname, error); 406 break; 407 } 408 } 409 IFQ_DEQUEUE(&ifp->if_snd, m0); 410 if (m != NULL) { 411 m_freem(m0); 412 m0 = m; 413 } 414 415 /* Initialize the fraglist. */ 416 fr->ef_nfrags = dmamap->dm_nsegs; 417 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 418 fr->ef_frags[seg].ef_addr = 419 dmamap->dm_segs[seg].ds_addr; 420 fr->ef_frags[seg].ef_length = 421 dmamap->dm_segs[seg].ds_len; 422 } 423 424 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 425 426 /* Sync the DMA map. */ 427 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 428 BUS_DMASYNC_PREWRITE); 429 430 /* 431 * Store a pointer to the packet so we can free it later. 432 */ 433 ds->ds_mbuf = m0; 434 435 /* 436 * Fill in the transmit descriptor. The EPIC doesn't 437 * auto-pad, so we have to do this ourselves. 438 */ 439 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 440 txd->et_txlength = max(m0->m_pkthdr.len, 441 ETHER_MIN_LEN - ETHER_CRC_LEN); 442 443 /* 444 * If this is the first descriptor we're enqueueing, 445 * don't give it to the EPIC yet. That could cause 446 * a race condition. We'll do it below. 447 */ 448 if (nexttx == firsttx) 449 txd->et_txstatus = 0; 450 else 451 txd->et_txstatus = ET_TXSTAT_OWNER; 452 453 EPIC_CDTXSYNC(sc, nexttx, 454 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 455 456 /* Advance the tx pointer. */ 457 sc->sc_txpending++; 458 sc->sc_txlast = nexttx; 459 460 #if NBPFILTER > 0 461 /* 462 * Pass the packet to any BPF listeners. 463 */ 464 if (ifp->if_bpf) 465 bpf_mtap(ifp->if_bpf, m0); 466 #endif 467 } 468 469 if (sc->sc_txpending == EPIC_NTXDESC) { 470 /* No more slots left; notify upper layer. */ 471 ifp->if_flags |= IFF_OACTIVE; 472 } 473 474 if (sc->sc_txpending != opending) { 475 /* 476 * We enqueued packets. If the transmitter was idle, 477 * reset the txdirty pointer. 478 */ 479 if (opending == 0) 480 sc->sc_txdirty = firsttx; 481 482 /* 483 * Cause a transmit interrupt to happen on the 484 * last packet we enqueued. 485 */ 486 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 487 EPIC_CDTXSYNC(sc, sc->sc_txlast, 488 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 489 490 /* 491 * The entire packet chain is set up. Give the 492 * first descriptor to the EPIC now. 493 */ 494 EPIC_CDTX(sc, firsttx)->et_txstatus = ET_TXSTAT_OWNER; 495 EPIC_CDTXSYNC(sc, firsttx, 496 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 497 498 /* Start the transmitter. */ 499 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 500 COMMAND_TXQUEUED); 501 502 /* Set a watchdog timer in case the chip flakes out. */ 503 ifp->if_timer = 5; 504 } 505 } 506 507 /* 508 * Watchdog timer handler. 509 * [ifnet interface function] 510 */ 511 void 512 epic_watchdog(ifp) 513 struct ifnet *ifp; 514 { 515 struct epic_softc *sc = ifp->if_softc; 516 517 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 518 ifp->if_oerrors++; 519 520 (void) epic_init(ifp); 521 } 522 523 /* 524 * Handle control requests from the operator. 525 * [ifnet interface function] 526 */ 527 int 528 epic_ioctl(ifp, cmd, data) 529 struct ifnet *ifp; 530 u_long cmd; 531 caddr_t data; 532 { 533 struct epic_softc *sc = ifp->if_softc; 534 struct ifreq *ifr = (struct ifreq *)data; 535 int s, error; 536 537 s = splnet(); 538 539 switch (cmd) { 540 case SIOCSIFMEDIA: 541 case SIOCGIFMEDIA: 542 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 543 break; 544 545 default: 546 error = ether_ioctl(ifp, cmd, data); 547 if (error == ENETRESET) { 548 /* 549 * Multicast list has changed; set the hardware filter 550 * accordingly. Update our idea of the current media; 551 * epic_set_mchash() needs to know what it is. 552 */ 553 mii_pollstat(&sc->sc_mii); 554 epic_set_mchash(sc); 555 error = 0; 556 } 557 break; 558 } 559 560 splx(s); 561 return (error); 562 } 563 564 /* 565 * Interrupt handler. 566 */ 567 int 568 epic_intr(arg) 569 void *arg; 570 { 571 struct epic_softc *sc = arg; 572 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 573 struct epic_rxdesc *rxd; 574 struct epic_txdesc *txd; 575 struct epic_descsoft *ds; 576 struct mbuf *m; 577 u_int32_t intstat; 578 int i, claimed = 0; 579 u_int len; 580 581 top: 582 /* 583 * Get the interrupt status from the EPIC. 584 */ 585 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 586 if ((intstat & INTSTAT_INT_ACTV) == 0) 587 return (claimed); 588 589 claimed = 1; 590 591 /* 592 * Acknowledge the interrupt. 593 */ 594 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 595 intstat & INTMASK); 596 597 /* 598 * Check for receive interrupts. 599 */ 600 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 601 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 602 rxd = EPIC_CDRX(sc, i); 603 ds = EPIC_DSRX(sc, i); 604 605 EPIC_CDRXSYNC(sc, i, 606 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 607 608 if (rxd->er_rxstatus & ER_RXSTAT_OWNER) { 609 /* 610 * We have processed all of the 611 * receive buffers. 612 */ 613 break; 614 } 615 616 /* 617 * Make sure the packet arrived intact. If an error 618 * occurred, update stats and reset the descriptor. 619 * The buffer will be reused the next time the 620 * descriptor comes up in the ring. 621 */ 622 if ((rxd->er_rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 623 if (rxd->er_rxstatus & ER_RXSTAT_CRCERROR) 624 printf("%s: CRC error\n", 625 sc->sc_dev.dv_xname); 626 if (rxd->er_rxstatus & ER_RXSTAT_ALIGNERROR) 627 printf("%s: alignment error\n", 628 sc->sc_dev.dv_xname); 629 ifp->if_ierrors++; 630 EPIC_INIT_RXDESC(sc, i); 631 continue; 632 } 633 634 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 635 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 636 637 /* 638 * The EPIC includes the CRC with every packet. 639 */ 640 len = rxd->er_rxlength; 641 642 if (len < sizeof(struct ether_header)) { 643 /* 644 * Runt packet; drop it now. 645 */ 646 ifp->if_ierrors++; 647 EPIC_INIT_RXDESC(sc, i); 648 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 649 ds->ds_dmamap->dm_mapsize, 650 BUS_DMASYNC_PREREAD); 651 continue; 652 } 653 654 /* 655 * If the packet is small enough to fit in a 656 * single header mbuf, allocate one and copy 657 * the data into it. This greatly reduces 658 * memory consumption when we receive lots 659 * of small packets. 660 * 661 * Otherwise, we add a new buffer to the receive 662 * chain. If this fails, we drop the packet and 663 * recycle the old buffer. 664 */ 665 if (epic_copy_small != 0 && len <= MHLEN) { 666 MGETHDR(m, M_DONTWAIT, MT_DATA); 667 if (m == NULL) 668 goto dropit; 669 memcpy(mtod(m, caddr_t), 670 mtod(ds->ds_mbuf, caddr_t), len); 671 EPIC_INIT_RXDESC(sc, i); 672 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 673 ds->ds_dmamap->dm_mapsize, 674 BUS_DMASYNC_PREREAD); 675 } else { 676 m = ds->ds_mbuf; 677 if (epic_add_rxbuf(sc, i) != 0) { 678 dropit: 679 ifp->if_ierrors++; 680 EPIC_INIT_RXDESC(sc, i); 681 bus_dmamap_sync(sc->sc_dmat, 682 ds->ds_dmamap, 0, 683 ds->ds_dmamap->dm_mapsize, 684 BUS_DMASYNC_PREREAD); 685 continue; 686 } 687 } 688 689 m->m_flags |= M_HASFCS; 690 m->m_pkthdr.rcvif = ifp; 691 m->m_pkthdr.len = m->m_len = len; 692 693 #if NBPFILTER > 0 694 /* 695 * Pass this up to any BPF listeners, but only 696 * pass it up the stack if its for us. 697 */ 698 if (ifp->if_bpf) 699 bpf_mtap(ifp->if_bpf, m); 700 #endif 701 702 /* Pass it on. */ 703 (*ifp->if_input)(ifp, m); 704 ifp->if_ipackets++; 705 } 706 707 /* Update the receive pointer. */ 708 sc->sc_rxptr = i; 709 710 /* 711 * Check for receive queue underflow. 712 */ 713 if (intstat & INTSTAT_RQE) { 714 printf("%s: receiver queue empty\n", 715 sc->sc_dev.dv_xname); 716 /* 717 * Ring is already built; just restart the 718 * receiver. 719 */ 720 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 721 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 722 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 723 COMMAND_RXQUEUED | COMMAND_START_RX); 724 } 725 } 726 727 /* 728 * Check for transmission complete interrupts. 729 */ 730 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 731 ifp->if_flags &= ~IFF_OACTIVE; 732 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 733 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 734 txd = EPIC_CDTX(sc, i); 735 ds = EPIC_DSTX(sc, i); 736 737 EPIC_CDTXSYNC(sc, i, 738 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 739 740 if (txd->et_txstatus & ET_TXSTAT_OWNER) 741 break; 742 743 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 744 745 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 746 0, ds->ds_dmamap->dm_mapsize, 747 BUS_DMASYNC_POSTWRITE); 748 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 749 m_freem(ds->ds_mbuf); 750 ds->ds_mbuf = NULL; 751 752 /* 753 * Check for errors and collisions. 754 */ 755 if ((txd->et_txstatus & ET_TXSTAT_PACKETTX) == 0) 756 ifp->if_oerrors++; 757 else 758 ifp->if_opackets++; 759 ifp->if_collisions += 760 TXSTAT_COLLISIONS(txd->et_txstatus); 761 if (txd->et_txstatus & ET_TXSTAT_CARSENSELOST) 762 printf("%s: lost carrier\n", 763 sc->sc_dev.dv_xname); 764 } 765 766 /* Update the dirty transmit buffer pointer. */ 767 sc->sc_txdirty = i; 768 769 /* 770 * Cancel the watchdog timer if there are no pending 771 * transmissions. 772 */ 773 if (sc->sc_txpending == 0) 774 ifp->if_timer = 0; 775 776 /* 777 * Kick the transmitter after a DMA underrun. 778 */ 779 if (intstat & INTSTAT_TXU) { 780 printf("%s: transmit underrun\n", sc->sc_dev.dv_xname); 781 bus_space_write_4(sc->sc_st, sc->sc_sh, 782 EPIC_COMMAND, COMMAND_TXUGO); 783 if (sc->sc_txpending) 784 bus_space_write_4(sc->sc_st, sc->sc_sh, 785 EPIC_COMMAND, COMMAND_TXQUEUED); 786 } 787 788 /* 789 * Try to get more packets going. 790 */ 791 epic_start(ifp); 792 } 793 794 /* 795 * Check for fatal interrupts. 796 */ 797 if (intstat & INTSTAT_FATAL_INT) { 798 if (intstat & INTSTAT_PTA) 799 printf("%s: PCI target abort error\n", 800 sc->sc_dev.dv_xname); 801 else if (intstat & INTSTAT_PMA) 802 printf("%s: PCI master abort error\n", 803 sc->sc_dev.dv_xname); 804 else if (intstat & INTSTAT_APE) 805 printf("%s: PCI address parity error\n", 806 sc->sc_dev.dv_xname); 807 else if (intstat & INTSTAT_DPE) 808 printf("%s: PCI data parity error\n", 809 sc->sc_dev.dv_xname); 810 else 811 printf("%s: unknown fatal error\n", 812 sc->sc_dev.dv_xname); 813 (void) epic_init(ifp); 814 } 815 816 /* 817 * Check for more interrupts. 818 */ 819 goto top; 820 } 821 822 /* 823 * One second timer, used to tick the MII. 824 */ 825 void 826 epic_tick(arg) 827 void *arg; 828 { 829 struct epic_softc *sc = arg; 830 int s; 831 832 s = splnet(); 833 mii_tick(&sc->sc_mii); 834 splx(s); 835 836 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 837 } 838 839 /* 840 * Fixup the clock source on the EPIC. 841 */ 842 void 843 epic_fixup_clock_source(sc) 844 struct epic_softc *sc; 845 { 846 int i; 847 848 /* 849 * According to SMC Application Note 7-15, the EPIC's clock 850 * source is incorrect following a reset. This manifests itself 851 * as failure to recognize when host software has written to 852 * a register on the EPIC. The appnote recommends issuing at 853 * least 16 consecutive writes to the CLOCK TEST bit to correctly 854 * configure the clock source. 855 */ 856 for (i = 0; i < 16; i++) 857 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 858 TEST_CLOCKTEST); 859 } 860 861 /* 862 * Perform a soft reset on the EPIC. 863 */ 864 void 865 epic_reset(sc) 866 struct epic_softc *sc; 867 { 868 869 epic_fixup_clock_source(sc); 870 871 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 872 delay(100); 873 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 874 delay(100); 875 876 epic_fixup_clock_source(sc); 877 } 878 879 /* 880 * Initialize the interface. Must be called at splnet(). 881 */ 882 int 883 epic_init(ifp) 884 struct ifnet *ifp; 885 { 886 struct epic_softc *sc = ifp->if_softc; 887 bus_space_tag_t st = sc->sc_st; 888 bus_space_handle_t sh = sc->sc_sh; 889 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 890 struct epic_txdesc *txd; 891 struct epic_descsoft *ds; 892 u_int32_t genctl, reg0; 893 int i, error = 0; 894 895 /* 896 * Cancel any pending I/O. 897 */ 898 epic_stop(ifp, 0); 899 900 /* 901 * Reset the EPIC to a known state. 902 */ 903 epic_reset(sc); 904 905 /* 906 * Magical mystery initialization. 907 */ 908 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 909 910 /* 911 * Initialize the EPIC genctl register: 912 * 913 * - 64 byte receive FIFO threshold 914 * - automatic advance to next receive frame 915 */ 916 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 917 #if BYTE_ORDER == BIG_ENDIAN 918 genctl |= GENCTL_BIG_ENDIAN; 919 #endif 920 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 921 922 /* 923 * Reset the MII bus and PHY. 924 */ 925 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 926 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 927 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 928 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 929 delay(100); 930 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 931 delay(1000); 932 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 933 934 /* 935 * Initialize Ethernet address. 936 */ 937 reg0 = enaddr[1] << 8 | enaddr[0]; 938 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 939 reg0 = enaddr[3] << 8 | enaddr[2]; 940 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 941 reg0 = enaddr[5] << 8 | enaddr[4]; 942 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 943 944 /* 945 * Initialize receive control. Remember the external buffer 946 * size setting. 947 */ 948 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 949 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 950 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 951 if (ifp->if_flags & IFF_PROMISC) 952 reg0 |= RXCON_PROMISCMODE; 953 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 954 955 /* Set the current media. */ 956 epic_mediachange(ifp); 957 958 /* Set up the multicast hash table. */ 959 epic_set_mchash(sc); 960 961 /* 962 * Initialize the transmit descriptor ring. txlast is initialized 963 * to the end of the list so that it will wrap around to the first 964 * descriptor when the first packet is transmitted. 965 */ 966 for (i = 0; i < EPIC_NTXDESC; i++) { 967 txd = EPIC_CDTX(sc, i); 968 memset(txd, 0, sizeof(struct epic_txdesc)); 969 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 970 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 971 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 972 } 973 sc->sc_txpending = 0; 974 sc->sc_txdirty = 0; 975 sc->sc_txlast = EPIC_NTXDESC - 1; 976 977 /* 978 * Initialize the receive descriptor ring. 979 */ 980 for (i = 0; i < EPIC_NRXDESC; i++) { 981 ds = EPIC_DSRX(sc, i); 982 if (ds->ds_mbuf == NULL) { 983 if ((error = epic_add_rxbuf(sc, i)) != 0) { 984 printf("%s: unable to allocate or map rx " 985 "buffer %d error = %d\n", 986 sc->sc_dev.dv_xname, i, error); 987 /* 988 * XXX Should attempt to run with fewer receive 989 * XXX buffers instead of just failing. 990 */ 991 epic_rxdrain(sc); 992 goto out; 993 } 994 } else 995 EPIC_INIT_RXDESC(sc, i); 996 } 997 sc->sc_rxptr = 0; 998 999 /* 1000 * Initialize the interrupt mask and enable interrupts. 1001 */ 1002 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1003 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1004 1005 /* 1006 * Give the transmit and receive rings to the EPIC. 1007 */ 1008 bus_space_write_4(st, sh, EPIC_PTCDAR, 1009 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1010 bus_space_write_4(st, sh, EPIC_PRCDAR, 1011 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1012 1013 /* 1014 * Set the EPIC in motion. 1015 */ 1016 bus_space_write_4(st, sh, EPIC_COMMAND, 1017 COMMAND_RXQUEUED | COMMAND_START_RX); 1018 1019 /* 1020 * ...all done! 1021 */ 1022 ifp->if_flags |= IFF_RUNNING; 1023 ifp->if_flags &= ~IFF_OACTIVE; 1024 1025 /* 1026 * Start the one second clock. 1027 */ 1028 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 1029 1030 /* 1031 * Attempt to start output on the interface. 1032 */ 1033 epic_start(ifp); 1034 1035 out: 1036 if (error) 1037 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1038 return (error); 1039 } 1040 1041 /* 1042 * Drain the receive queue. 1043 */ 1044 void 1045 epic_rxdrain(sc) 1046 struct epic_softc *sc; 1047 { 1048 struct epic_descsoft *ds; 1049 int i; 1050 1051 for (i = 0; i < EPIC_NRXDESC; i++) { 1052 ds = EPIC_DSRX(sc, i); 1053 if (ds->ds_mbuf != NULL) { 1054 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1055 m_freem(ds->ds_mbuf); 1056 ds->ds_mbuf = NULL; 1057 } 1058 } 1059 } 1060 1061 /* 1062 * Stop transmission on the interface. 1063 */ 1064 void 1065 epic_stop(ifp, disable) 1066 struct ifnet *ifp; 1067 int disable; 1068 { 1069 struct epic_softc *sc = ifp->if_softc; 1070 bus_space_tag_t st = sc->sc_st; 1071 bus_space_handle_t sh = sc->sc_sh; 1072 struct epic_descsoft *ds; 1073 u_int32_t reg; 1074 int i; 1075 1076 /* 1077 * Stop the one second clock. 1078 */ 1079 callout_stop(&sc->sc_mii_callout); 1080 1081 /* Down the MII. */ 1082 mii_down(&sc->sc_mii); 1083 1084 /* Paranoia... */ 1085 epic_fixup_clock_source(sc); 1086 1087 /* 1088 * Disable interrupts. 1089 */ 1090 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1091 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1092 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1093 1094 /* 1095 * Stop the DMA engine and take the receiver off-line. 1096 */ 1097 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1098 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1099 1100 /* 1101 * Release any queued transmit buffers. 1102 */ 1103 for (i = 0; i < EPIC_NTXDESC; i++) { 1104 ds = EPIC_DSTX(sc, i); 1105 if (ds->ds_mbuf != NULL) { 1106 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1107 m_freem(ds->ds_mbuf); 1108 ds->ds_mbuf = NULL; 1109 } 1110 } 1111 1112 if (disable) 1113 epic_rxdrain(sc); 1114 1115 /* 1116 * Mark the interface down and cancel the watchdog timer. 1117 */ 1118 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1119 ifp->if_timer = 0; 1120 } 1121 1122 /* 1123 * Read the EPIC Serial EEPROM. 1124 */ 1125 void 1126 epic_read_eeprom(sc, word, wordcnt, data) 1127 struct epic_softc *sc; 1128 int word, wordcnt; 1129 u_int16_t *data; 1130 { 1131 bus_space_tag_t st = sc->sc_st; 1132 bus_space_handle_t sh = sc->sc_sh; 1133 u_int16_t reg; 1134 int i, x; 1135 1136 #define EEPROM_WAIT_READY(st, sh) \ 1137 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1138 /* nothing */ 1139 1140 /* 1141 * Enable the EEPROM. 1142 */ 1143 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1144 EEPROM_WAIT_READY(st, sh); 1145 1146 for (i = 0; i < wordcnt; i++) { 1147 /* Send CHIP SELECT for one clock tick. */ 1148 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1149 EEPROM_WAIT_READY(st, sh); 1150 1151 /* Shift in the READ opcode. */ 1152 for (x = 3; x > 0; x--) { 1153 reg = EECTL_ENABLE|EECTL_EECS; 1154 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1155 reg |= EECTL_EEDI; 1156 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1157 EEPROM_WAIT_READY(st, sh); 1158 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1159 EEPROM_WAIT_READY(st, sh); 1160 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1161 EEPROM_WAIT_READY(st, sh); 1162 } 1163 1164 /* Shift in address. */ 1165 for (x = 6; x > 0; x--) { 1166 reg = EECTL_ENABLE|EECTL_EECS; 1167 if ((word + i) & (1 << (x - 1))) 1168 reg |= EECTL_EEDI; 1169 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1170 EEPROM_WAIT_READY(st, sh); 1171 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1172 EEPROM_WAIT_READY(st, sh); 1173 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1174 EEPROM_WAIT_READY(st, sh); 1175 } 1176 1177 /* Shift out data. */ 1178 reg = EECTL_ENABLE|EECTL_EECS; 1179 data[i] = 0; 1180 for (x = 16; x > 0; x--) { 1181 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1182 EEPROM_WAIT_READY(st, sh); 1183 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1184 data[i] |= (1 << (x - 1)); 1185 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1186 EEPROM_WAIT_READY(st, sh); 1187 } 1188 1189 /* Clear CHIP SELECT. */ 1190 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1191 EEPROM_WAIT_READY(st, sh); 1192 } 1193 1194 /* 1195 * Disable the EEPROM. 1196 */ 1197 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1198 1199 #undef EEPROM_WAIT_READY 1200 } 1201 1202 /* 1203 * Add a receive buffer to the indicated descriptor. 1204 */ 1205 int 1206 epic_add_rxbuf(sc, idx) 1207 struct epic_softc *sc; 1208 int idx; 1209 { 1210 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1211 struct mbuf *m; 1212 int error; 1213 1214 MGETHDR(m, M_DONTWAIT, MT_DATA); 1215 if (m == NULL) 1216 return (ENOBUFS); 1217 1218 MCLGET(m, M_DONTWAIT); 1219 if ((m->m_flags & M_EXT) == 0) { 1220 m_freem(m); 1221 return (ENOBUFS); 1222 } 1223 1224 if (ds->ds_mbuf != NULL) 1225 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1226 1227 ds->ds_mbuf = m; 1228 1229 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1230 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1231 BUS_DMA_READ|BUS_DMA_NOWAIT); 1232 if (error) { 1233 printf("%s: can't load rx DMA map %d, error = %d\n", 1234 sc->sc_dev.dv_xname, idx, error); 1235 panic("epic_add_rxbuf"); /* XXX */ 1236 } 1237 1238 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1239 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1240 1241 EPIC_INIT_RXDESC(sc, idx); 1242 1243 return (0); 1244 } 1245 1246 /* 1247 * Set the EPIC multicast hash table. 1248 * 1249 * NOTE: We rely on a recently-updated mii_media_active here! 1250 */ 1251 void 1252 epic_set_mchash(sc) 1253 struct epic_softc *sc; 1254 { 1255 struct ethercom *ec = &sc->sc_ethercom; 1256 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1257 struct ether_multi *enm; 1258 struct ether_multistep step; 1259 u_int32_t hash, mchash[4]; 1260 1261 /* 1262 * Set up the multicast address filter by passing all multicast 1263 * addresses through a CRC generator, and then using the low-order 1264 * 6 bits as an index into the 64 bit multicast hash table (only 1265 * the lower 16 bits of each 32 bit multicast hash register are 1266 * valid). The high order bits select the register, while the 1267 * rest of the bits select the bit within the register. 1268 */ 1269 1270 if (ifp->if_flags & IFF_PROMISC) 1271 goto allmulti; 1272 1273 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1274 /* XXX hardware bug in 10Mbps mode. */ 1275 goto allmulti; 1276 } 1277 1278 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1279 1280 ETHER_FIRST_MULTI(step, ec, enm); 1281 while (enm != NULL) { 1282 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1283 /* 1284 * We must listen to a range of multicast addresses. 1285 * For now, just accept all multicasts, rather than 1286 * trying to set only those filter bits needed to match 1287 * the range. (At this time, the only use of address 1288 * ranges is for IP multicast routing, for which the 1289 * range is big enough to require all bits set.) 1290 */ 1291 goto allmulti; 1292 } 1293 1294 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1295 hash >>= 26; 1296 1297 /* Set the corresponding bit in the hash table. */ 1298 mchash[hash >> 4] |= 1 << (hash & 0xf); 1299 1300 ETHER_NEXT_MULTI(step, enm); 1301 } 1302 1303 ifp->if_flags &= ~IFF_ALLMULTI; 1304 goto sethash; 1305 1306 allmulti: 1307 ifp->if_flags |= IFF_ALLMULTI; 1308 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1309 1310 sethash: 1311 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1312 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1313 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1314 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1315 } 1316 1317 /* 1318 * Wait for the MII to become ready. 1319 */ 1320 int 1321 epic_mii_wait(sc, rw) 1322 struct epic_softc *sc; 1323 u_int32_t rw; 1324 { 1325 int i; 1326 1327 for (i = 0; i < 50; i++) { 1328 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1329 == 0) 1330 break; 1331 delay(2); 1332 } 1333 if (i == 50) { 1334 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1335 return (1); 1336 } 1337 1338 return (0); 1339 } 1340 1341 /* 1342 * Read from the MII. 1343 */ 1344 int 1345 epic_mii_read(self, phy, reg) 1346 struct device *self; 1347 int phy, reg; 1348 { 1349 struct epic_softc *sc = (struct epic_softc *)self; 1350 1351 if (epic_mii_wait(sc, MMCTL_WRITE)) 1352 return (0); 1353 1354 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1355 MMCTL_ARG(phy, reg, MMCTL_READ)); 1356 1357 if (epic_mii_wait(sc, MMCTL_READ)) 1358 return (0); 1359 1360 return (bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) & 1361 MMDATA_MASK); 1362 } 1363 1364 /* 1365 * Write to the MII. 1366 */ 1367 void 1368 epic_mii_write(self, phy, reg, val) 1369 struct device *self; 1370 int phy, reg, val; 1371 { 1372 struct epic_softc *sc = (struct epic_softc *)self; 1373 1374 if (epic_mii_wait(sc, MMCTL_WRITE)) 1375 return; 1376 1377 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1378 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1379 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1380 } 1381 1382 /* 1383 * Callback from PHY when media changes. 1384 */ 1385 void 1386 epic_statchg(self) 1387 struct device *self; 1388 { 1389 struct epic_softc *sc = (struct epic_softc *)self; 1390 u_int32_t txcon, miicfg; 1391 1392 /* 1393 * Update loopback bits in TXCON to reflect duplex mode. 1394 */ 1395 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1396 if (sc->sc_mii.mii_media_active & IFM_FDX) 1397 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1398 else 1399 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1400 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1401 1402 /* On some cards we need manualy set fullduplex led */ 1403 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1404 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1405 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1406 miicfg |= MIICFG_ENABLE; 1407 else 1408 miicfg &= ~MIICFG_ENABLE; 1409 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1410 } 1411 1412 /* 1413 * There is a multicast filter bug in 10Mbps mode. Kick the 1414 * multicast filter in case the speed changed. 1415 */ 1416 epic_set_mchash(sc); 1417 } 1418 1419 /* 1420 * Callback from ifmedia to request current media status. 1421 */ 1422 void 1423 epic_mediastatus(ifp, ifmr) 1424 struct ifnet *ifp; 1425 struct ifmediareq *ifmr; 1426 { 1427 struct epic_softc *sc = ifp->if_softc; 1428 1429 mii_pollstat(&sc->sc_mii); 1430 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1431 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1432 } 1433 1434 /* 1435 * Callback from ifmedia to request new media setting. 1436 */ 1437 int 1438 epic_mediachange(ifp) 1439 struct ifnet *ifp; 1440 { 1441 struct epic_softc *sc = ifp->if_softc; 1442 struct mii_data *mii = &sc->sc_mii; 1443 struct ifmedia *ifm = &mii->mii_media; 1444 int media = ifm->ifm_cur->ifm_media; 1445 u_int32_t miicfg; 1446 struct mii_softc *miisc; 1447 int cfg; 1448 1449 if (!(ifp->if_flags & IFF_UP)) 1450 return (0); 1451 1452 if (IFM_INST(media) != sc->sc_serinst) { 1453 /* If we're not selecting serial interface, select MII mode */ 1454 #ifdef EPICMEDIADEBUG 1455 printf("%s: parallel mode\n", ifp->if_xname); 1456 #endif 1457 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1458 miicfg &= ~MIICFG_SERMODEENA; 1459 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1460 } 1461 1462 mii_mediachg(mii); 1463 1464 if (IFM_INST(media) == sc->sc_serinst) { 1465 /* select serial interface */ 1466 #ifdef EPICMEDIADEBUG 1467 printf("%s: serial mode\n", ifp->if_xname); 1468 #endif 1469 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1470 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1471 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1472 1473 /* There is no driver to fill this */ 1474 mii->mii_media_active = media; 1475 mii->mii_media_status = 0; 1476 1477 epic_statchg(&sc->sc_dev); 1478 return (0); 1479 } 1480 1481 /* Lookup selected PHY */ 1482 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1483 miisc = LIST_NEXT(miisc, mii_list)) { 1484 if (IFM_INST(media) == miisc->mii_inst) 1485 break; 1486 } 1487 if (!miisc) { 1488 printf("epic_mediachange: can't happen\n"); /* ??? panic */ 1489 return (0); 1490 } 1491 #ifdef EPICMEDIADEBUG 1492 printf("%s: using phy %s\n", ifp->if_xname, 1493 miisc->mii_dev.dv_xname); 1494 #endif 1495 1496 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1497 /* XXX XXX assume it's a Level1 - should check */ 1498 1499 /* We have to powerup fiber tranceivers */ 1500 cfg = PHY_READ(miisc, MII_LXTPHY_CONFIG); 1501 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1502 #ifdef EPICMEDIADEBUG 1503 printf("%s: power up fiber\n", ifp->if_xname); 1504 #endif 1505 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1506 } else { 1507 #ifdef EPICMEDIADEBUG 1508 printf("%s: power down fiber\n", ifp->if_xname); 1509 #endif 1510 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1511 } 1512 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1513 } 1514 1515 return (0); 1516 } 1517
Indexes created Tue Sep 23 02:09:52 GMT 2025