smc83c170.c revision 1.7
1 /* $NetBSD: smc83c170.c,v 1.7 1998/08/08 23:51:40 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Device driver for the Standard Microsystems Corp. 83C170 42 * Ethernet PCI Integrated Controller (EPIC/100). 43 */ 44 45 #include "opt_inet.h" 46 #include "opt_ns.h" 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #endif 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 73 #ifdef NS 74 #include <netns/ns.h> 75 #include <netns/ns_if.h> 76 #endif 77 78 #include <machine/bus.h> 79 #include <machine/intr.h> 80 81 #include <dev/ic/smc83c170reg.h> 82 #include <dev/ic/smc83c170var.h> 83 84 void epic_start __P((struct ifnet *)); 85 void epic_watchdog __P((struct ifnet *)); 86 int epic_ioctl __P((struct ifnet *, u_long, caddr_t)); 87 88 void epic_shutdown __P((void *)); 89 90 void epic_reset __P((struct epic_softc *)); 91 void epic_init __P((struct epic_softc *)); 92 void epic_stop __P((struct epic_softc *)); 93 int epic_add_rxbuf __P((struct epic_softc *, int)); 94 void epic_read_eeprom __P((struct epic_softc *, int, int, u_int16_t *)); 95 void epic_set_mchash __P((struct epic_softc *)); 96 void epic_fixup_clock_source __P((struct epic_softc *)); 97 98 /* 99 * Fudge the incoming packets by this much, to ensure the data after 100 * the Ethernet header is aligned. 101 */ 102 #define RX_ALIGNMENT_FUDGE 2 103 104 /* XXX Should be somewhere else. */ 105 #define ETHER_MIN_LEN 60 106 107 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 108 INTSTAT_TXC | INTSTAT_RQE | INTSTAT_RCC) 109 110 /* 111 * Attach an EPIC interface to the system. 112 */ 113 void 114 epic_attach(sc) 115 struct epic_softc *sc; 116 { 117 bus_space_tag_t st = sc->sc_st; 118 bus_space_handle_t sh = sc->sc_sh; 119 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 120 int i, rseg, error, attach_stage; 121 bus_dma_segment_t seg; 122 u_int8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 123 u_int16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 124 125 attach_stage = 0; 126 127 /* 128 * Allocate the control data structures, and create and load the 129 * DMA map for it. 130 */ 131 if ((error = bus_dmamem_alloc(sc->sc_dmat, 132 sizeof(struct epic_control_data), NBPG, 0, &seg, 1, &rseg, 133 BUS_DMA_NOWAIT)) != 0) { 134 printf("%s: unable to allocate control data, error = %d\n", 135 sc->sc_dev.dv_xname, error); 136 goto fail; 137 } 138 139 attach_stage = 1; 140 141 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 142 sizeof(struct epic_control_data), (caddr_t *)&sc->sc_control_data, 143 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 144 printf("%s: unable to map control data, error = %d\n", 145 sc->sc_dev.dv_xname, error); 146 goto fail; 147 } 148 149 attach_stage = 2; 150 151 if ((error = bus_dmamap_create(sc->sc_dmat, 152 sizeof(struct epic_control_data), 1, 153 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 154 &sc->sc_cddmamap)) != 0) { 155 printf("%s: unable to create control data DMA map, " 156 "error = %d\n", sc->sc_dev.dv_xname, error); 157 goto fail; 158 } 159 160 attach_stage = 3; 161 162 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 163 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 164 BUS_DMA_NOWAIT)) != 0) { 165 printf("%s: unable to load control data DMA map, error = %d\n", 166 sc->sc_dev.dv_xname, error); 167 goto fail; 168 } 169 170 attach_stage = 4; 171 172 /* 173 * Create the transmit buffer DMA maps. 174 */ 175 for (i = 0; i < EPIC_NTXDESC; i++) { 176 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 177 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 178 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 179 printf("%s: unable to create tx DMA map %d, " 180 "error = %d\n", sc->sc_dev.dv_xname, i, error); 181 goto fail; 182 } 183 } 184 185 attach_stage = 5; 186 187 /* 188 * Create the recieve buffer DMA maps. 189 */ 190 for (i = 0; i < EPIC_NRXDESC; i++) { 191 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 192 MCLBYTES, 0, BUS_DMA_NOWAIT, 193 &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 194 printf("%s: unable to create rx DMA map %d, " 195 "error = %d\n", sc->sc_dev.dv_xname, i, error); 196 goto fail; 197 } 198 } 199 200 attach_stage = 6; 201 202 /* 203 * Pre-allocate the receive buffers. 204 */ 205 for (i = 0; i < EPIC_NRXDESC; i++) { 206 if ((error = epic_add_rxbuf(sc, i)) != 0) { 207 printf("%s: unable to allocate or map rx buffer %d\n," 208 " error = %d\n", sc->sc_dev.dv_xname, i, error); 209 goto fail; 210 } 211 } 212 213 attach_stage = 7; 214 215 /* 216 * Bring the chip out of low-power mode and reset it to a known state. 217 */ 218 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 219 epic_reset(sc); 220 221 /* 222 * Read the Ethernet address from the EEPROM. 223 */ 224 epic_read_eeprom(sc, 0, (sizeof(myea) / sizeof(myea[0])), myea); 225 bcopy(myea, enaddr, sizeof(myea)); 226 227 /* 228 * ...and the device name. 229 */ 230 epic_read_eeprom(sc, 0x2c, (sizeof(mydevname) / sizeof(mydevname[0])), 231 mydevname); 232 bcopy(mydevname, devname, sizeof(mydevname)); 233 devname[sizeof(mydevname)] = '\0'; 234 for (i = sizeof(mydevname) - 1; i >= 0; i--) { 235 if (devname[i] == ' ') 236 devname[i] = '\0'; 237 else 238 break; 239 } 240 241 printf("%s: %s, Ethernet address %s\n", sc->sc_dev.dv_xname, 242 devname, ether_sprintf(enaddr)); 243 244 ifp = &sc->sc_ethercom.ec_if; 245 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 246 ifp->if_softc = sc; 247 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 248 ifp->if_ioctl = epic_ioctl; 249 ifp->if_start = epic_start; 250 ifp->if_watchdog = epic_watchdog; 251 252 /* 253 * Attach the interface. 254 */ 255 if_attach(ifp); 256 ether_ifattach(ifp, enaddr); 257 #if NBPFILTER > 0 258 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 259 sizeof(struct ether_header)); 260 #endif 261 262 /* 263 * Make sure the interface is shutdown during reboot. 264 */ 265 sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc); 266 if (sc->sc_sdhook == NULL) 267 printf("%s: WARNING: unable to establish shutdown hook\n", 268 sc->sc_dev.dv_xname); 269 return; 270 271 fail: 272 /* 273 * Free any resources we've allocated during the failed attach 274 * attempt. Do this in reverse order and fall through. 275 */ 276 switch (attach_stage) { 277 case 7: 278 for (i = 0; i < EPIC_NRXDESC; i++) { 279 if (sc->sc_rxsoft[i].ds_mbuf != NULL) { 280 bus_dmamap_unload(sc->sc_dmat, 281 sc->sc_rxsoft[i].ds_dmamap); 282 m_freem(sc->sc_rxsoft[i].ds_mbuf); 283 } 284 } 285 /* FALLTHROUGH */ 286 287 case 6: 288 for (i = 0; i < EPIC_NRXDESC; i++) 289 bus_dmamap_destroy(sc->sc_dmat, 290 sc->sc_rxsoft[i].ds_dmamap); 291 /* FALLTHROUGH */ 292 293 case 5: 294 for (i = 0; i < EPIC_NTXDESC; i++) 295 bus_dmamap_destroy(sc->sc_dmat, 296 sc->sc_txsoft[i].ds_dmamap); 297 /* FALLTHROUGH */ 298 299 case 4: 300 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 301 /* FALLTHROUGH */ 302 303 case 3: 304 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 305 /* FALLTHROUGH */ 306 307 case 2: 308 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 309 sizeof(struct epic_control_data)); 310 /* FALLTHROUGH */ 311 312 case 1: 313 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 314 break; 315 } 316 } 317 318 /* 319 * Shutdown hook. Make sure the interface is stopped at reboot. 320 */ 321 void 322 epic_shutdown(arg) 323 void *arg; 324 { 325 struct epic_softc *sc = arg; 326 327 epic_stop(sc); 328 } 329 330 /* 331 * Start packet transmission on the interface. 332 * [ifnet interface function] 333 */ 334 void 335 epic_start(ifp) 336 struct ifnet *ifp; 337 { 338 struct epic_softc *sc = ifp->if_softc; 339 struct epic_txdesc *txd; 340 struct epic_descsoft *ds; 341 struct epic_fraglist *fr; 342 bus_dmamap_t dmamap; 343 struct mbuf *m0; 344 int nexttx, seg, error, txqueued; 345 346 txqueued = 0; 347 348 /* 349 * Loop through the send queue, setting up transmit descriptors 350 * until we drain the queue, or use up all available transmit 351 * descriptors. 352 */ 353 while (ifp->if_snd.ifq_head != NULL && 354 sc->sc_txpending < EPIC_NTXDESC) { 355 /* 356 * Grab a packet off the queue. 357 */ 358 IF_DEQUEUE(&ifp->if_snd, m0); 359 360 /* 361 * Get the last and next available transmit descriptor. 362 */ 363 nexttx = EPIC_NEXTTX(sc->sc_txlast); 364 txd = &sc->sc_control_data->ecd_txdescs[nexttx]; 365 fr = &sc->sc_control_data->ecd_txfrags[nexttx]; 366 ds = &sc->sc_txsoft[nexttx]; 367 dmamap = ds->ds_dmamap; 368 369 loadmap: 370 /* 371 * Load the DMA map with the packet. 372 */ 373 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 374 BUS_DMA_NOWAIT); 375 switch (error) { 376 case 0: 377 /* Success. */ 378 break; 379 380 case EFBIG: 381 { 382 struct mbuf *mn; 383 384 /* 385 * We ran out of segments. We have to recopy this 386 * mbuf chain first. Bail out if we can't get the 387 * new buffers. 388 */ 389 printf("%s: too many segments, ", sc->sc_dev.dv_xname); 390 391 MGETHDR(mn, M_DONTWAIT, MT_DATA); 392 if (mn == NULL) { 393 m_freem(m0); 394 printf("aborting\n"); 395 goto out; 396 } 397 if (m0->m_pkthdr.len > MHLEN) { 398 MCLGET(mn, M_DONTWAIT); 399 if ((mn->m_flags & M_EXT) == 0) { 400 m_freem(mn); 401 m_freem(m0); 402 printf("aborting\n"); 403 goto out; 404 } 405 } 406 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mn, caddr_t)); 407 mn->m_pkthdr.len = mn->m_len = m0->m_pkthdr.len; 408 m_freem(m0); 409 m0 = mn; 410 printf("retrying\n"); 411 goto loadmap; 412 } 413 414 default: 415 /* 416 * Some other problem; report it. 417 */ 418 printf("%s: can't load mbuf chain, error = %d\n", 419 sc->sc_dev.dv_xname, error); 420 m_freem(m0); 421 goto out; 422 } 423 424 /* 425 * Initialize the fraglist. 426 */ 427 fr->ef_nfrags = dmamap->dm_nsegs; 428 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 429 fr->ef_frags[seg].ef_addr = 430 dmamap->dm_segs[seg].ds_addr; 431 fr->ef_frags[seg].ef_length = 432 dmamap->dm_segs[seg].ds_len; 433 } 434 435 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 436 BUS_DMASYNC_PREWRITE); 437 438 /* 439 * Store a pointer to the packet so we can free it later. 440 */ 441 ds->ds_mbuf = m0; 442 443 /* 444 * Finish setting up the new transmit descriptor: set the 445 * packet length and give it to the EPIC. 446 */ 447 txd->et_txlength = max(m0->m_pkthdr.len, ETHER_MIN_LEN); 448 txd->et_txstatus = ET_TXSTAT_OWNER; 449 450 /* 451 * Committed; advance the lasttx pointer. If nothing was 452 * previously queued, reset the dirty pointer. 453 */ 454 sc->sc_txlast = nexttx; 455 if (sc->sc_txpending == 0) 456 sc->sc_txdirty = nexttx; 457 458 sc->sc_txpending++; 459 460 txqueued = 1; 461 462 #if NBPFILTER > 0 463 /* 464 * Pass the packet to any BPF listeners. 465 */ 466 if (ifp->if_bpf) 467 bpf_mtap(ifp->if_bpf, m0); 468 #endif 469 } 470 471 out: 472 /* 473 * We're finished. If we added more packets, make sure the 474 * transmit DMA engine is running. 475 */ 476 if (txqueued) { 477 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 478 COMMAND_TXQUEUED); 479 480 /* 481 * Set a 5 second watchdog timer. 482 */ 483 ifp->if_timer = 5; 484 } 485 } 486 487 /* 488 * Watchdog timer handler. 489 * [ifnet interface function] 490 */ 491 void 492 epic_watchdog(ifp) 493 struct ifnet *ifp; 494 { 495 struct epic_softc *sc = ifp->if_softc; 496 497 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 498 ifp->if_oerrors++; 499 500 epic_init(sc); 501 } 502 503 /* 504 * Handle control requests from the operator. 505 * [ifnet interface function] 506 */ 507 int 508 epic_ioctl(ifp, cmd, data) 509 struct ifnet *ifp; 510 u_long cmd; 511 caddr_t data; 512 { 513 struct epic_softc *sc = ifp->if_softc; 514 struct ifreq *ifr = (struct ifreq *)data; 515 struct ifaddr *ifa = (struct ifaddr *)data; 516 int s, error = 0; 517 518 s = splnet(); 519 520 switch (cmd) { 521 case SIOCSIFADDR: 522 ifp->if_flags |= IFF_UP; 523 524 switch (ifa->ifa_addr->sa_family) { 525 #ifdef INET 526 case AF_INET: 527 epic_init(sc); 528 arp_ifinit(ifp, ifa); 529 break; 530 #endif /* INET */ 531 #ifdef NS 532 case AF_NS: 533 { 534 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 535 536 if (ns_nullhost(*ina)) 537 ina->x_host = *(union ns_host *) 538 LLADDR(ifp->if_sadl); 539 else 540 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 541 ifp->if_addrlen); 542 /* Set new address. */ 543 epic_init(sc); 544 break; 545 } 546 #endif /* NS */ 547 default: 548 epic_init(sc); 549 break; 550 } 551 break; 552 553 case SIOCSIFMTU: 554 if (ifr->ifr_mtu > ETHERMTU) 555 error = EINVAL; 556 else 557 ifp->if_mtu = ifr->ifr_mtu; 558 break; 559 560 case SIOCSIFFLAGS: 561 if ((ifp->if_flags & IFF_UP) == 0 && 562 (ifp->if_flags & IFF_RUNNING) != 0) { 563 /* 564 * If interface is marked down and it is running, then 565 * stop it. 566 */ 567 epic_stop(sc); 568 ifp->if_flags &= ~IFF_RUNNING; 569 } else if ((ifp->if_flags & IFF_UP) != 0 && 570 (ifp->if_flags & IFF_RUNNING) == 0) { 571 /* 572 * If interfase it marked up and it is stopped, then 573 * start it. 574 */ 575 epic_init(sc); 576 } else { 577 /* 578 * Reset the interface to pick up changes in any other 579 * flags that affect the hardware state. 580 */ 581 epic_init(sc); 582 } 583 break; 584 585 case SIOCADDMULTI: 586 case SIOCDELMULTI: 587 error = (cmd == SIOCADDMULTI) ? 588 ether_addmulti(ifr, &sc->sc_ethercom) : 589 ether_delmulti(ifr, &sc->sc_ethercom); 590 591 if (error == ENETRESET) { 592 /* 593 * Multicast list has changed; set the hardware filter 594 * accordingly. 595 */ 596 epic_init(sc); 597 error = 0; 598 } 599 break; 600 601 default: 602 error = EINVAL; 603 break; 604 } 605 606 splx(s); 607 return (error); 608 } 609 610 /* 611 * Interrupt handler. 612 */ 613 int 614 epic_intr(arg) 615 void *arg; 616 { 617 struct epic_softc *sc = arg; 618 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 619 struct ether_header *eh; 620 struct epic_rxdesc *rxd; 621 struct epic_txdesc *txd; 622 struct epic_descsoft *ds; 623 struct mbuf *m; 624 u_int32_t intstat; 625 int i, len, claimed = 0, error; 626 627 top: 628 /* 629 * Get the interrupt status from the EPIC. 630 */ 631 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 632 if ((intstat & INTSTAT_INT_ACTV) == 0) 633 return (claimed); 634 635 claimed = 1; 636 637 /* 638 * Acknowledge the interrupt. 639 */ 640 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 641 intstat & INTMASK); 642 643 /* 644 * Check for receive interrupts. 645 */ 646 if (intstat & (INTSTAT_RCC | INTSTAT_RQE)) { 647 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 648 rxd = &sc->sc_control_data->ecd_rxdescs[i]; 649 ds = &sc->sc_rxsoft[i]; 650 m = ds->ds_mbuf; 651 error = 0; 652 653 if (rxd->er_rxstatus & ER_RXSTAT_OWNER) { 654 /* 655 * We have processed all of the 656 * receive buffers. 657 */ 658 break; 659 } 660 661 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 662 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 663 664 /* 665 * Make sure the packet arrived intact. 666 */ 667 if ((rxd->er_rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 668 #if 1 669 if (rxd->er_rxstatus & ER_RXSTAT_CRCERROR) 670 printf("%s: CRC error\n", 671 sc->sc_dev.dv_xname); 672 if (rxd->er_rxstatus & ER_RXSTAT_ALIGNERROR) 673 printf("%s: alignment error\n", 674 sc->sc_dev.dv_xname); 675 #endif 676 ifp->if_ierrors++; 677 error = 1; 678 } 679 680 /* 681 * Add a new buffer to the receive chain. If this 682 * fails, the old buffer is recycled. 683 */ 684 if (epic_add_rxbuf(sc, i) == 0) { 685 /* 686 * We wanted to reset the buffer, but 687 * didn't want to pass it on up. 688 */ 689 if (error) { 690 m_freem(m); 691 continue; 692 } 693 694 len = rxd->er_buflength; 695 if (len < sizeof(struct ether_header)) { 696 m_freem(m); 697 continue; 698 } 699 700 m->m_pkthdr.rcvif = ifp; 701 m->m_pkthdr.len = m->m_len = len; 702 eh = mtod(m, struct ether_header *); 703 #if NBPFILTER > 0 704 /* 705 * Pass this up to any BPF listeners. 706 */ 707 if (ifp->if_bpf) { 708 bpf_mtap(ifp->if_bpf, m); 709 710 /* 711 * Only pass this up the stack 712 * if it's for us. 713 */ 714 if ((ifp->if_flags & IFF_PROMISC) && 715 bcmp(LLADDR(ifp->if_sadl), 716 eh->ether_dhost, 717 ETHER_ADDR_LEN) != 0 && 718 (rxd->er_rxstatus & 719 (ER_RXSTAT_BCAST|ER_RXSTAT_MCAST)) 720 == 0) { 721 m_freem(m); 722 continue; 723 } 724 } 725 #endif /* NPBFILTER > 0 */ 726 m->m_data += sizeof(struct ether_header); 727 m->m_len -= sizeof(struct ether_header); 728 m->m_pkthdr.len = m->m_len; 729 ether_input(ifp, eh, m); 730 } 731 } 732 733 /* 734 * Update the recieve pointer. 735 */ 736 sc->sc_rxptr = i; 737 738 /* 739 * Check for receive queue underflow. 740 */ 741 if (intstat & INTSTAT_RQE) { 742 printf("%s: receiver queue empty\n", 743 sc->sc_dev.dv_xname); 744 /* 745 * Ring is already built; just restart the 746 * receiver. 747 */ 748 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 749 sc->sc_cddma + EPIC_CDOFF(ecd_rxdescs[0])); 750 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 751 COMMAND_RXQUEUED | COMMAND_START_RX); 752 } 753 } 754 755 /* 756 * Check for transmission complete interrupts. 757 */ 758 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 759 for (i = sc->sc_txdirty;; i = EPIC_NEXTTX(i)) { 760 txd = &sc->sc_control_data->ecd_txdescs[i]; 761 ds = &sc->sc_txsoft[i]; 762 763 if (sc->sc_txpending == 0 || 764 (txd->et_txstatus & ET_TXSTAT_OWNER) != 0) 765 break; 766 767 if (ds->ds_mbuf != NULL) { 768 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 769 0, ds->ds_dmamap->dm_mapsize, 770 BUS_DMASYNC_POSTWRITE); 771 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 772 m_freem(ds->ds_mbuf); 773 ds->ds_mbuf = NULL; 774 } 775 sc->sc_txpending--; 776 777 /* 778 * Check for errors and collisions. 779 */ 780 if ((txd->et_txstatus & ET_TXSTAT_PACKETTX) == 0) 781 ifp->if_oerrors++; 782 ifp->if_collisions += 783 TXSTAT_COLLISIONS(txd->et_txstatus); 784 if (txd->et_txstatus & ET_TXSTAT_CARSENSELOST) { 785 #if 1 786 printf("%s: lost carrier\n", 787 sc->sc_dev.dv_xname); 788 #endif 789 /* XXX clear "active" but in media data */ 790 } 791 } 792 793 /* 794 * Update the dirty transmit buffer pointer. 795 */ 796 sc->sc_txdirty = i; 797 798 /* 799 * Cancel the watchdog timer if there are no pending 800 * transmissions. 801 */ 802 if (sc->sc_txpending == 0) 803 ifp->if_timer = 0; 804 805 /* 806 * Kick the transmitter after a DMA underrun. 807 */ 808 if (intstat & INTSTAT_TXU) { 809 printf("%s: transmit underrun\n", sc->sc_dev.dv_xname); 810 bus_space_write_4(sc->sc_st, sc->sc_sh, 811 EPIC_COMMAND, COMMAND_TXUGO); 812 if (sc->sc_txpending) 813 bus_space_write_4(sc->sc_st, sc->sc_sh, 814 EPIC_COMMAND, COMMAND_TXQUEUED); 815 } 816 817 /* 818 * Try to get more packets going. 819 */ 820 epic_start(ifp); 821 } 822 823 /* 824 * Check for fatal interrupts. 825 */ 826 if (intstat & INTSTAT_FATAL_INT) { 827 printf("%s: fatal error, resetting\n", sc->sc_dev.dv_xname); 828 epic_init(sc); 829 } 830 831 /* 832 * Check for more interrupts. 833 */ 834 goto top; 835 } 836 837 /* 838 * Fixup the clock source on the EPIC. 839 */ 840 void 841 epic_fixup_clock_source(sc) 842 struct epic_softc *sc; 843 { 844 int i; 845 846 /* 847 * According to SMC Application Note 7-15, the EPIC's clock 848 * source is incorrect following a reset. This manifests itself 849 * as failure to recognize when host software has written to 850 * a register on the EPIC. The appnote recommends issuing at 851 * least 16 consecutive writes to the CLOCK TEST bit to correctly 852 * configure the clock source. 853 */ 854 for (i = 0; i < 16; i++) 855 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 856 TEST_CLOCKTEST); 857 } 858 859 /* 860 * Perform a soft reset on the EPIC. 861 */ 862 void 863 epic_reset(sc) 864 struct epic_softc *sc; 865 { 866 867 epic_fixup_clock_source(sc); 868 869 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 870 delay(100); 871 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 872 delay(100); 873 874 epic_fixup_clock_source(sc); 875 } 876 877 /* 878 * Initialize the interface. Must be called at splnet(). 879 */ 880 void 881 epic_init(sc) 882 struct epic_softc *sc; 883 { 884 bus_space_tag_t st = sc->sc_st; 885 bus_space_handle_t sh = sc->sc_sh; 886 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 887 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 888 struct epic_txdesc *txd; 889 struct epic_rxdesc *rxd; 890 u_int32_t genctl, reg0; 891 int i; 892 893 /* 894 * Cancel any pending I/O. 895 */ 896 epic_stop(sc); 897 898 /* 899 * Reset the EPIC to a known state. 900 */ 901 epic_reset(sc); 902 903 /* 904 * Magical mystery initialization. 905 */ 906 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 907 908 /* 909 * Initialize the EPIC genctl register: 910 * 911 * - 64 byte receive FIFO threshold 912 * - automatic advance to next receive frame 913 */ 914 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 915 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 916 917 /* 918 * Reset the MII bus and PHY. 919 */ 920 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 921 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 922 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 923 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 924 delay(100); 925 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 926 delay(100); 927 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 928 929 /* 930 * Initialize Ethernet address. 931 */ 932 reg0 = enaddr[1] << 8 | enaddr[0]; 933 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 934 reg0 = enaddr[3] << 8 | enaddr[2]; 935 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 936 reg0 = enaddr[5] << 8 | enaddr[4]; 937 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 938 939 /* 940 * Set up the multicast hash table. 941 */ 942 epic_set_mchash(sc); 943 944 /* 945 * Initialize receive control. Remember the external buffer 946 * size setting. 947 */ 948 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 949 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 950 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 951 if (ifp->if_flags & IFF_PROMISC) 952 reg0 |= RXCON_PROMISCMODE; 953 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 954 955 /* 956 * XXX Media (full-duplex in TXCON). 957 */ 958 959 /* 960 * Initialize the transmit descriptors. 961 */ 962 txd = sc->sc_control_data->ecd_txdescs; 963 bzero(txd, sizeof(sc->sc_control_data->ecd_txdescs)); 964 for (i = 0; i < EPIC_NTXDESC; i++) { 965 txd[i].et_control = ET_TXCTL_LASTDESC | ET_TXCTL_IAF | 966 ET_TXCTL_FRAGLIST; 967 txd[i].et_bufaddr = sc->sc_cddma + EPIC_CDOFF(ecd_txfrags[i]); 968 txd[i].et_nextdesc = sc->sc_cddma + 969 EPIC_CDOFF(ecd_txdescs[(i + 1) & EPIC_NTXDESC_MASK]); 970 } 971 972 /* 973 * Initialize the receive descriptors. Note the buffers 974 * and control word have already been initialized; we only 975 * need to initialize the ring. 976 */ 977 rxd = sc->sc_control_data->ecd_rxdescs; 978 for (i = 0; i < EPIC_NRXDESC; i++) { 979 rxd[i].er_nextdesc = sc->sc_cddma + 980 EPIC_CDOFF(ecd_rxdescs[(i + 1) & EPIC_NRXDESC_MASK]); 981 } 982 983 /* 984 * Initialize the interrupt mask and enable interrupts. 985 */ 986 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 987 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 988 989 /* 990 * Give the transmit and receive rings to the EPIC. 991 */ 992 bus_space_write_4(st, sh, EPIC_PTCDAR, 993 sc->sc_cddma + EPIC_CDOFF(ecd_txdescs[0])); 994 bus_space_write_4(st, sh, EPIC_PRCDAR, 995 sc->sc_cddma + EPIC_CDOFF(ecd_rxdescs[0])); 996 997 /* 998 * Initialize our ring pointers. txlast it initialized to 999 * the end of the list so that it will wrap around to the 1000 * first descriptor when the first packet is transmitted. 1001 */ 1002 sc->sc_txpending = 0; 1003 sc->sc_txdirty = 0; 1004 sc->sc_txlast = EPIC_NTXDESC - 1; 1005 1006 sc->sc_rxptr = 0; 1007 1008 /* 1009 * Set the EPIC in motion. 1010 */ 1011 bus_space_write_4(st, sh, EPIC_COMMAND, 1012 COMMAND_RXQUEUED | COMMAND_START_RX); 1013 1014 /* 1015 * ...all done! 1016 */ 1017 ifp->if_flags |= IFF_RUNNING; 1018 ifp->if_flags &= ~IFF_OACTIVE; 1019 } 1020 1021 /* 1022 * Stop transmission on the interface. 1023 */ 1024 void 1025 epic_stop(sc) 1026 struct epic_softc *sc; 1027 { 1028 bus_space_tag_t st = sc->sc_st; 1029 bus_space_handle_t sh = sc->sc_sh; 1030 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1031 struct epic_descsoft *ds; 1032 u_int32_t reg; 1033 int i; 1034 1035 /* Paranoia... */ 1036 epic_fixup_clock_source(sc); 1037 1038 /* 1039 * Disable interrupts. 1040 */ 1041 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1042 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1043 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1044 1045 /* 1046 * Stop the DMA engine and take the receiver off-line. 1047 */ 1048 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1049 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1050 1051 /* 1052 * Release any queued transmit buffers. 1053 */ 1054 for (i = 0; i < EPIC_NTXDESC; i++) { 1055 ds = &sc->sc_txsoft[i]; 1056 if (ds->ds_mbuf != NULL) { 1057 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1058 m_freem(ds->ds_mbuf); 1059 ds->ds_mbuf = NULL; 1060 } 1061 } 1062 sc->sc_txpending = 0; 1063 1064 /* 1065 * Release the receive buffers, then reallocate/reinitialize. 1066 */ 1067 for (i = 0; i < EPIC_NRXDESC; i++) { 1068 ds = &sc->sc_rxsoft[i]; 1069 if (ds->ds_mbuf != NULL) { 1070 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1071 m_freem(ds->ds_mbuf); 1072 ds->ds_mbuf = NULL; 1073 } 1074 if (epic_add_rxbuf(sc, i) != 0) { 1075 /* 1076 * This "can't happen" - we're at splnet() 1077 * and we just freed the buffer we need 1078 * above. 1079 */ 1080 panic("epic_stop: no buffers!"); 1081 } 1082 } 1083 1084 /* 1085 * Mark the interface down and cancel the watchdog timer. 1086 */ 1087 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1088 ifp->if_timer = 0; 1089 } 1090 1091 /* 1092 * Read the EPIC Serial EEPROM. 1093 */ 1094 void 1095 epic_read_eeprom(sc, word, wordcnt, data) 1096 struct epic_softc *sc; 1097 int word, wordcnt; 1098 u_int16_t *data; 1099 { 1100 bus_space_tag_t st = sc->sc_st; 1101 bus_space_handle_t sh = sc->sc_sh; 1102 u_int16_t reg; 1103 int i, x; 1104 1105 #define EEPROM_WAIT_READY(st, sh) \ 1106 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1107 /* nothing */ 1108 1109 /* 1110 * Enable the EEPROM. 1111 */ 1112 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1113 EEPROM_WAIT_READY(st, sh); 1114 1115 for (i = 0; i < wordcnt; i++) { 1116 /* Send CHIP SELECT for one clock tick. */ 1117 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1118 EEPROM_WAIT_READY(st, sh); 1119 1120 /* Shift in the READ opcode. */ 1121 for (x = 3; x > 0; x--) { 1122 reg = EECTL_ENABLE|EECTL_EECS; 1123 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1124 reg |= EECTL_EEDI; 1125 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1126 EEPROM_WAIT_READY(st, sh); 1127 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1128 EEPROM_WAIT_READY(st, sh); 1129 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1130 EEPROM_WAIT_READY(st, sh); 1131 } 1132 1133 /* Shift in address. */ 1134 for (x = 6; x > 0; x--) { 1135 reg = EECTL_ENABLE|EECTL_EECS; 1136 if ((word + i) & (1 << (x - 1))) 1137 reg |= EECTL_EEDI; 1138 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1139 EEPROM_WAIT_READY(st, sh); 1140 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1141 EEPROM_WAIT_READY(st, sh); 1142 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1143 EEPROM_WAIT_READY(st, sh); 1144 } 1145 1146 /* Shift out data. */ 1147 reg = EECTL_ENABLE|EECTL_EECS; 1148 data[i] = 0; 1149 for (x = 16; x > 0; x--) { 1150 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1151 EEPROM_WAIT_READY(st, sh); 1152 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1153 data[i] |= (1 << (x - 1)); 1154 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1155 EEPROM_WAIT_READY(st, sh); 1156 } 1157 1158 /* Clear CHIP SELECT. */ 1159 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1160 EEPROM_WAIT_READY(st, sh); 1161 } 1162 1163 /* 1164 * Disable the EEPROM. 1165 */ 1166 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1167 1168 #undef EEPROM_WAIT_READY 1169 } 1170 1171 /* 1172 * Add a receive buffer to the indicated descriptor. 1173 */ 1174 int 1175 epic_add_rxbuf(sc, idx) 1176 struct epic_softc *sc; 1177 int idx; 1178 { 1179 struct epic_rxdesc *rxd = &sc->sc_control_data->ecd_rxdescs[idx]; 1180 struct epic_descsoft *ds = &sc->sc_rxsoft[idx]; 1181 struct mbuf *m, *oldm; 1182 int error = 0; 1183 1184 oldm = ds->ds_mbuf; 1185 1186 MGETHDR(m, M_DONTWAIT, MT_DATA); 1187 if (m != NULL) { 1188 MCLGET(m, M_DONTWAIT); 1189 if ((m->m_flags & M_EXT) == 0) { 1190 error = ENOMEM; 1191 m_freem(m); 1192 if (oldm == NULL) 1193 return (error); 1194 m = oldm; 1195 m->m_data = m->m_ext.ext_buf; 1196 } 1197 } else { 1198 error = ENOMEM; 1199 if (oldm == NULL) 1200 return (error); 1201 m = oldm; 1202 m->m_data = m->m_ext.ext_buf; 1203 } 1204 1205 ds->ds_mbuf = m; 1206 1207 /* 1208 * Set up the DMA map for this receive buffer. 1209 */ 1210 if (m != oldm) { 1211 if (oldm != NULL) 1212 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1213 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1214 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1215 if (error) { 1216 printf("%s: can't load rx buffer, error = %d\n", 1217 sc->sc_dev.dv_xname, error); 1218 panic("epic_add_rxbuf"); /* XXX */ 1219 } 1220 } 1221 1222 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1223 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1224 1225 /* 1226 * Move the data pointer up so that the incoming packet 1227 * will be 32-bit aligned. 1228 */ 1229 m->m_data += RX_ALIGNMENT_FUDGE; 1230 1231 /* 1232 * Initialize the receive descriptor. 1233 */ 1234 rxd->er_bufaddr = ds->ds_dmamap->dm_segs[0].ds_addr + 1235 RX_ALIGNMENT_FUDGE; 1236 rxd->er_buflength = m->m_ext.ext_size - RX_ALIGNMENT_FUDGE; 1237 rxd->er_control = 0; 1238 rxd->er_rxstatus = ER_RXSTAT_OWNER; 1239 1240 return (error); 1241 } 1242 1243 /* 1244 * Set the EPIC multicast hash table. 1245 */ 1246 void 1247 epic_set_mchash(sc) 1248 struct epic_softc *sc; 1249 { 1250 struct ethercom *ec = &sc->sc_ethercom; 1251 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1252 struct ether_multi *enm; 1253 struct ether_multistep step; 1254 u_int8_t *cp; 1255 u_int32_t crc, mchash[4]; 1256 int len; 1257 static const u_int32_t crctab[] = { 1258 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, 1259 0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c, 1260 0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c, 1261 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c 1262 }; 1263 1264 /* 1265 * Set up the multicast address filter by passing all multicast 1266 * addresses through a CRC generator, and then using the high-order 1267 * 6 bits as an index into the 64 bit multicast hash table (only 1268 * the lower 16 bits of each 32 bit multicast hash register are 1269 * valid). The high order bit selects the register, while the 1270 * rest of the bits select the bit within the register. 1271 */ 1272 1273 if (ifp->if_flags & IFF_PROMISC) 1274 goto allmulti; 1275 1276 #if 1 /* XXX thorpej - hardware bug in 10Mb mode */ 1277 goto allmulti; 1278 #endif 1279 1280 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1281 1282 ETHER_FIRST_MULTI(step, ec, enm); 1283 while (enm != NULL) { 1284 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1285 /* 1286 * We must listen to a range of multicast addresses. 1287 * For now, just accept all multicasts, rather than 1288 * trying to set only those filter bits needed to match 1289 * the range. (At this time, the only use of address 1290 * ranges is for IP multicast routing, for which the 1291 * range is big enough to require all bits set.) 1292 */ 1293 goto allmulti; 1294 } 1295 1296 cp = enm->enm_addrlo; 1297 crc = 0xffffffff; 1298 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1299 crc ^= *cp++; 1300 crc = (crc >> 4) ^ crctab[crc & 0xf]; 1301 crc = (crc >> 4) ^ crctab[crc & 0xf]; 1302 } 1303 /* Just want the 6 most significant bits. */ 1304 crc >>= 26; 1305 1306 /* Set the corresponding bit in the hash table. */ 1307 mchash[crc >> 4] |= 1 << (crc & 0xf); 1308 1309 ETHER_NEXT_MULTI(step, enm); 1310 } 1311 1312 ifp->if_flags &= ~IFF_ALLMULTI; 1313 goto sethash; 1314 1315 allmulti: 1316 ifp->if_flags |= IFF_ALLMULTI; 1317 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1318 1319 sethash: 1320 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1321 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1322 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1323 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1324 } 1325
Indexes created Fri Sep 26 20:09:58 GMT 2025