smc83c170.c revision 1.79
1 /* $NetBSD: smc83c170.c,v 1.79 2010/04/05 07:19:36 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the Standard Microsystems Corp. 83C170 35 * Ethernet PCI Integrated Controller (EPIC/100). 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.79 2010/04/05 07:19:36 joerg Exp $"); 40 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #include <net/bpf.h> 61 62 #include <sys/bus.h> 63 #include <sys/intr.h> 64 65 #include <dev/mii/miivar.h> 66 #include <dev/mii/lxtphyreg.h> 67 68 #include <dev/ic/smc83c170reg.h> 69 #include <dev/ic/smc83c170var.h> 70 71 void epic_start(struct ifnet *); 72 void epic_watchdog(struct ifnet *); 73 int epic_ioctl(struct ifnet *, u_long, void *); 74 int epic_init(struct ifnet *); 75 void epic_stop(struct ifnet *, int); 76 77 bool epic_shutdown(device_t, int); 78 79 void epic_reset(struct epic_softc *); 80 void epic_rxdrain(struct epic_softc *); 81 int epic_add_rxbuf(struct epic_softc *, int); 82 void epic_read_eeprom(struct epic_softc *, int, int, uint16_t *); 83 void epic_set_mchash(struct epic_softc *); 84 void epic_fixup_clock_source(struct epic_softc *); 85 int epic_mii_read(device_t, int, int); 86 void epic_mii_write(device_t, int, int, int); 87 int epic_mii_wait(struct epic_softc *, uint32_t); 88 void epic_tick(void *); 89 90 void epic_statchg(device_t); 91 int epic_mediachange(struct ifnet *); 92 93 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 94 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 95 96 int epic_copy_small = 0; 97 98 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 99 100 /* 101 * Attach an EPIC interface to the system. 102 */ 103 void 104 epic_attach(struct epic_softc *sc) 105 { 106 bus_space_tag_t st = sc->sc_st; 107 bus_space_handle_t sh = sc->sc_sh; 108 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 109 int rseg, error, miiflags; 110 u_int i; 111 bus_dma_segment_t seg; 112 uint8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 113 uint16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 114 char *nullbuf; 115 116 callout_init(&sc->sc_mii_callout, 0); 117 118 /* 119 * Allocate the control data structures, and create and load the 120 * DMA map for it. 121 */ 122 if ((error = bus_dmamem_alloc(sc->sc_dmat, 123 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0, 124 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 125 aprint_error_dev(sc->sc_dev, 126 "unable to allocate control data, error = %d\n", error); 127 goto fail_0; 128 } 129 130 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 131 sizeof(struct epic_control_data) + ETHER_PAD_LEN, 132 (void **)&sc->sc_control_data, 133 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 134 aprint_error_dev(sc->sc_dev, 135 "unable to map control data, error = %d\n", error); 136 goto fail_1; 137 } 138 nullbuf = 139 (char *)sc->sc_control_data + sizeof(struct epic_control_data); 140 memset(nullbuf, 0, ETHER_PAD_LEN); 141 142 if ((error = bus_dmamap_create(sc->sc_dmat, 143 sizeof(struct epic_control_data), 1, 144 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 145 &sc->sc_cddmamap)) != 0) { 146 aprint_error_dev(sc->sc_dev, 147 "unable to create control data DMA map, error = %d\n", 148 error); 149 goto fail_2; 150 } 151 152 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 153 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 154 BUS_DMA_NOWAIT)) != 0) { 155 aprint_error_dev(sc->sc_dev, 156 "unable to load control data DMA map, error = %d\n", 157 error); 158 goto fail_3; 159 } 160 161 /* 162 * Create the transmit buffer DMA maps. 163 */ 164 for (i = 0; i < EPIC_NTXDESC; i++) { 165 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 166 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 167 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 168 aprint_error_dev(sc->sc_dev, 169 "unable to create tx DMA map %d, error = %d\n", 170 i, error); 171 goto fail_4; 172 } 173 } 174 175 /* 176 * Create the receive buffer DMA maps. 177 */ 178 for (i = 0; i < EPIC_NRXDESC; i++) { 179 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 180 MCLBYTES, 0, BUS_DMA_NOWAIT, 181 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 182 aprint_error_dev(sc->sc_dev, 183 "unable to create rx DMA map %d, error = %d\n", 184 i, error); 185 goto fail_5; 186 } 187 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 188 } 189 190 /* 191 * create and map the pad buffer 192 */ 193 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 194 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) { 195 aprint_error_dev(sc->sc_dev, 196 "unable to create pad buffer DMA map, error = %d\n", error); 197 goto fail_5; 198 } 199 200 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 201 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "unable to load pad buffer DMA map, error = %d\n", error); 204 goto fail_6; 205 } 206 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 207 BUS_DMASYNC_PREWRITE); 208 209 /* 210 * Bring the chip out of low-power mode and reset it to a known state. 211 */ 212 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 213 epic_reset(sc); 214 215 /* 216 * Read the Ethernet address from the EEPROM. 217 */ 218 epic_read_eeprom(sc, 0, __arraycount(myea), myea); 219 for (i = 0; i < __arraycount(myea); i++) { 220 enaddr[i * 2] = myea[i] & 0xff; 221 enaddr[i * 2 + 1] = myea[i] >> 8; 222 } 223 224 /* 225 * ...and the device name. 226 */ 227 epic_read_eeprom(sc, 0x2c, __arraycount(mydevname), mydevname); 228 for (i = 0; i < __arraycount(mydevname); i++) { 229 devname[i * 2] = mydevname[i] & 0xff; 230 devname[i * 2 + 1] = mydevname[i] >> 8; 231 } 232 233 devname[sizeof(mydevname)] = '\0'; 234 for (i = sizeof(mydevname) ; i > 0; i--) { 235 if (devname[i - 1] == ' ') 236 devname[i - 1] = '\0'; 237 else 238 break; 239 } 240 241 aprint_normal_dev(sc->sc_dev, "%s, Ethernet address %s\n", 242 devname, ether_sprintf(enaddr)); 243 244 miiflags = 0; 245 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 246 miiflags |= MIIF_HAVEFIBER; 247 248 /* 249 * Initialize our media structures and probe the MII. 250 */ 251 sc->sc_mii.mii_ifp = ifp; 252 sc->sc_mii.mii_readreg = epic_mii_read; 253 sc->sc_mii.mii_writereg = epic_mii_write; 254 sc->sc_mii.mii_statchg = epic_statchg; 255 256 sc->sc_ethercom.ec_mii = &sc->sc_mii; 257 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epic_mediachange, 258 ether_mediastatus); 259 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 260 MII_OFFSET_ANY, miiflags); 261 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 262 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 263 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 264 } else 265 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 266 267 if (sc->sc_hwflags & EPIC_HAS_BNC) { 268 /* use the next free media instance */ 269 sc->sc_serinst = sc->sc_mii.mii_instance++; 270 ifmedia_add(&sc->sc_mii.mii_media, 271 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->sc_serinst), 272 0, NULL); 273 aprint_normal_dev(sc->sc_dev, "10base2/BNC\n"); 274 } else 275 sc->sc_serinst = -1; 276 277 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 278 ifp->if_softc = sc; 279 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 280 ifp->if_ioctl = epic_ioctl; 281 ifp->if_start = epic_start; 282 ifp->if_watchdog = epic_watchdog; 283 ifp->if_init = epic_init; 284 ifp->if_stop = epic_stop; 285 IFQ_SET_READY(&ifp->if_snd); 286 287 /* 288 * We can support 802.1Q VLAN-sized frames. 289 */ 290 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 291 292 /* 293 * Attach the interface. 294 */ 295 if_attach(ifp); 296 ether_ifattach(ifp, enaddr); 297 298 /* 299 * Make sure the interface is shutdown during reboot. 300 */ 301 if (pmf_device_register1(sc->sc_dev, NULL, NULL, epic_shutdown)) 302 pmf_class_network_register(sc->sc_dev, ifp); 303 else 304 aprint_error_dev(sc->sc_dev, 305 "couldn't establish power handler\n"); 306 307 return; 308 309 /* 310 * Free any resources we've allocated during the failed attach 311 * attempt. Do this in reverse order and fall through. 312 */ 313 fail_6: 314 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 315 fail_5: 316 for (i = 0; i < EPIC_NRXDESC; i++) { 317 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 318 bus_dmamap_destroy(sc->sc_dmat, 319 EPIC_DSRX(sc, i)->ds_dmamap); 320 } 321 fail_4: 322 for (i = 0; i < EPIC_NTXDESC; i++) { 323 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 324 bus_dmamap_destroy(sc->sc_dmat, 325 EPIC_DSTX(sc, i)->ds_dmamap); 326 } 327 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 328 fail_3: 329 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 330 fail_2: 331 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 332 sizeof(struct epic_control_data)); 333 fail_1: 334 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 335 fail_0: 336 return; 337 } 338 339 /* 340 * Shutdown hook. Make sure the interface is stopped at reboot. 341 */ 342 bool 343 epic_shutdown(device_t self, int howto) 344 { 345 struct epic_softc *sc = device_private(self); 346 347 epic_stop(&sc->sc_ethercom.ec_if, 1); 348 349 return true; 350 } 351 352 /* 353 * Start packet transmission on the interface. 354 * [ifnet interface function] 355 */ 356 void 357 epic_start(struct ifnet *ifp) 358 { 359 struct epic_softc *sc = ifp->if_softc; 360 struct mbuf *m0, *m; 361 struct epic_txdesc *txd; 362 struct epic_descsoft *ds; 363 struct epic_fraglist *fr; 364 bus_dmamap_t dmamap; 365 int error, firsttx, nexttx, opending, seg; 366 u_int len; 367 368 /* 369 * Remember the previous txpending and the first transmit 370 * descriptor we use. 371 */ 372 opending = sc->sc_txpending; 373 firsttx = EPIC_NEXTTX(sc->sc_txlast); 374 375 /* 376 * Loop through the send queue, setting up transmit descriptors 377 * until we drain the queue, or use up all available transmit 378 * descriptors. 379 */ 380 while (sc->sc_txpending < EPIC_NTXDESC) { 381 /* 382 * Grab a packet off the queue. 383 */ 384 IFQ_POLL(&ifp->if_snd, m0); 385 if (m0 == NULL) 386 break; 387 m = NULL; 388 389 /* 390 * Get the last and next available transmit descriptor. 391 */ 392 nexttx = EPIC_NEXTTX(sc->sc_txlast); 393 txd = EPIC_CDTX(sc, nexttx); 394 fr = EPIC_CDFL(sc, nexttx); 395 ds = EPIC_DSTX(sc, nexttx); 396 dmamap = ds->ds_dmamap; 397 398 /* 399 * Load the DMA map. If this fails, the packet either 400 * didn't fit in the alloted number of frags, or we were 401 * short on resources. In this case, we'll copy and try 402 * again. 403 */ 404 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 405 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 406 (m0->m_pkthdr.len < ETHER_PAD_LEN && 407 dmamap-> dm_nsegs == EPIC_NFRAGS)) { 408 if (error == 0) 409 bus_dmamap_unload(sc->sc_dmat, dmamap); 410 411 MGETHDR(m, M_DONTWAIT, MT_DATA); 412 if (m == NULL) { 413 printf("%s: unable to allocate Tx mbuf\n", 414 device_xname(sc->sc_dev)); 415 break; 416 } 417 if (m0->m_pkthdr.len > MHLEN) { 418 MCLGET(m, M_DONTWAIT); 419 if ((m->m_flags & M_EXT) == 0) { 420 printf("%s: unable to allocate Tx " 421 "cluster\n", 422 device_xname(sc->sc_dev)); 423 m_freem(m); 424 break; 425 } 426 } 427 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 428 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 429 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 430 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 431 if (error) { 432 printf("%s: unable to load Tx buffer, " 433 "error = %d\n", device_xname(sc->sc_dev), 434 error); 435 break; 436 } 437 } 438 IFQ_DEQUEUE(&ifp->if_snd, m0); 439 if (m != NULL) { 440 m_freem(m0); 441 m0 = m; 442 } 443 444 /* Initialize the fraglist. */ 445 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 446 fr->ef_frags[seg].ef_addr = 447 dmamap->dm_segs[seg].ds_addr; 448 fr->ef_frags[seg].ef_length = 449 dmamap->dm_segs[seg].ds_len; 450 } 451 len = m0->m_pkthdr.len; 452 if (len < ETHER_PAD_LEN) { 453 fr->ef_frags[seg].ef_addr = sc->sc_nulldma; 454 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len; 455 len = ETHER_PAD_LEN; 456 seg++; 457 } 458 fr->ef_nfrags = seg; 459 460 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 461 462 /* Sync the DMA map. */ 463 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 464 BUS_DMASYNC_PREWRITE); 465 466 /* 467 * Store a pointer to the packet so we can free it later. 468 */ 469 ds->ds_mbuf = m0; 470 471 /* 472 * Fill in the transmit descriptor. 473 */ 474 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 475 476 /* 477 * If this is the first descriptor we're enqueueing, 478 * don't give it to the EPIC yet. That could cause 479 * a race condition. We'll do it below. 480 */ 481 if (nexttx == firsttx) 482 txd->et_txstatus = TXSTAT_TXLENGTH(len); 483 else 484 txd->et_txstatus = 485 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER; 486 487 EPIC_CDTXSYNC(sc, nexttx, 488 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 489 490 /* Advance the tx pointer. */ 491 sc->sc_txpending++; 492 sc->sc_txlast = nexttx; 493 494 /* 495 * Pass the packet to any BPF listeners. 496 */ 497 bpf_mtap(ifp, m0); 498 } 499 500 if (sc->sc_txpending == EPIC_NTXDESC) { 501 /* No more slots left; notify upper layer. */ 502 ifp->if_flags |= IFF_OACTIVE; 503 } 504 505 if (sc->sc_txpending != opending) { 506 /* 507 * We enqueued packets. If the transmitter was idle, 508 * reset the txdirty pointer. 509 */ 510 if (opending == 0) 511 sc->sc_txdirty = firsttx; 512 513 /* 514 * Cause a transmit interrupt to happen on the 515 * last packet we enqueued. 516 */ 517 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 518 EPIC_CDTXSYNC(sc, sc->sc_txlast, 519 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 520 521 /* 522 * The entire packet chain is set up. Give the 523 * first descriptor to the EPIC now. 524 */ 525 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER; 526 EPIC_CDTXSYNC(sc, firsttx, 527 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 528 529 /* Start the transmitter. */ 530 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 531 COMMAND_TXQUEUED); 532 533 /* Set a watchdog timer in case the chip flakes out. */ 534 ifp->if_timer = 5; 535 } 536 } 537 538 /* 539 * Watchdog timer handler. 540 * [ifnet interface function] 541 */ 542 void 543 epic_watchdog(struct ifnet *ifp) 544 { 545 struct epic_softc *sc = ifp->if_softc; 546 547 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 548 ifp->if_oerrors++; 549 550 (void)epic_init(ifp); 551 } 552 553 /* 554 * Handle control requests from the operator. 555 * [ifnet interface function] 556 */ 557 int 558 epic_ioctl(struct ifnet *ifp, u_long cmd, void *data) 559 { 560 struct epic_softc *sc = ifp->if_softc; 561 int s, error; 562 563 s = splnet(); 564 565 error = ether_ioctl(ifp, cmd, data); 566 if (error == ENETRESET) { 567 /* 568 * Multicast list has changed; set the hardware filter 569 * accordingly. Update our idea of the current media; 570 * epic_set_mchash() needs to know what it is. 571 */ 572 if (ifp->if_flags & IFF_RUNNING) { 573 mii_pollstat(&sc->sc_mii); 574 epic_set_mchash(sc); 575 } 576 error = 0; 577 } 578 579 splx(s); 580 return error; 581 } 582 583 /* 584 * Interrupt handler. 585 */ 586 int 587 epic_intr(void *arg) 588 { 589 struct epic_softc *sc = arg; 590 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 591 struct epic_rxdesc *rxd; 592 struct epic_txdesc *txd; 593 struct epic_descsoft *ds; 594 struct mbuf *m; 595 uint32_t intstat, rxstatus, txstatus; 596 int i, claimed = 0; 597 u_int len; 598 599 top: 600 /* 601 * Get the interrupt status from the EPIC. 602 */ 603 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 604 if ((intstat & INTSTAT_INT_ACTV) == 0) 605 return claimed; 606 607 claimed = 1; 608 609 /* 610 * Acknowledge the interrupt. 611 */ 612 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 613 intstat & INTMASK); 614 615 /* 616 * Check for receive interrupts. 617 */ 618 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 619 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 620 rxd = EPIC_CDRX(sc, i); 621 ds = EPIC_DSRX(sc, i); 622 623 EPIC_CDRXSYNC(sc, i, 624 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 625 626 rxstatus = rxd->er_rxstatus; 627 if (rxstatus & ER_RXSTAT_OWNER) { 628 /* 629 * We have processed all of the 630 * receive buffers. 631 */ 632 break; 633 } 634 635 /* 636 * Make sure the packet arrived intact. If an error 637 * occurred, update stats and reset the descriptor. 638 * The buffer will be reused the next time the 639 * descriptor comes up in the ring. 640 */ 641 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 642 if (rxstatus & ER_RXSTAT_CRCERROR) 643 printf("%s: CRC error\n", 644 device_xname(sc->sc_dev)); 645 if (rxstatus & ER_RXSTAT_ALIGNERROR) 646 printf("%s: alignment error\n", 647 device_xname(sc->sc_dev)); 648 ifp->if_ierrors++; 649 EPIC_INIT_RXDESC(sc, i); 650 continue; 651 } 652 653 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 654 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 655 656 /* 657 * The EPIC includes the CRC with every packet; 658 * trim it. 659 */ 660 len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN; 661 662 if (len < sizeof(struct ether_header)) { 663 /* 664 * Runt packet; drop it now. 665 */ 666 ifp->if_ierrors++; 667 EPIC_INIT_RXDESC(sc, i); 668 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 669 ds->ds_dmamap->dm_mapsize, 670 BUS_DMASYNC_PREREAD); 671 continue; 672 } 673 674 /* 675 * If the packet is small enough to fit in a 676 * single header mbuf, allocate one and copy 677 * the data into it. This greatly reduces 678 * memory consumption when we receive lots 679 * of small packets. 680 * 681 * Otherwise, we add a new buffer to the receive 682 * chain. If this fails, we drop the packet and 683 * recycle the old buffer. 684 */ 685 if (epic_copy_small != 0 && len <= MHLEN) { 686 MGETHDR(m, M_DONTWAIT, MT_DATA); 687 if (m == NULL) 688 goto dropit; 689 memcpy(mtod(m, void *), 690 mtod(ds->ds_mbuf, void *), len); 691 EPIC_INIT_RXDESC(sc, i); 692 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 693 ds->ds_dmamap->dm_mapsize, 694 BUS_DMASYNC_PREREAD); 695 } else { 696 m = ds->ds_mbuf; 697 if (epic_add_rxbuf(sc, i) != 0) { 698 dropit: 699 ifp->if_ierrors++; 700 EPIC_INIT_RXDESC(sc, i); 701 bus_dmamap_sync(sc->sc_dmat, 702 ds->ds_dmamap, 0, 703 ds->ds_dmamap->dm_mapsize, 704 BUS_DMASYNC_PREREAD); 705 continue; 706 } 707 } 708 709 m->m_pkthdr.rcvif = ifp; 710 m->m_pkthdr.len = m->m_len = len; 711 712 /* 713 * Pass this up to any BPF listeners, but only 714 * pass it up the stack if it's for us. 715 */ 716 bpf_mtap(ifp, m); 717 718 /* Pass it on. */ 719 (*ifp->if_input)(ifp, m); 720 ifp->if_ipackets++; 721 } 722 723 /* Update the receive pointer. */ 724 sc->sc_rxptr = i; 725 726 /* 727 * Check for receive queue underflow. 728 */ 729 if (intstat & INTSTAT_RQE) { 730 printf("%s: receiver queue empty\n", 731 device_xname(sc->sc_dev)); 732 /* 733 * Ring is already built; just restart the 734 * receiver. 735 */ 736 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 737 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 738 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 739 COMMAND_RXQUEUED | COMMAND_START_RX); 740 } 741 } 742 743 /* 744 * Check for transmission complete interrupts. 745 */ 746 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 747 ifp->if_flags &= ~IFF_OACTIVE; 748 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 749 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 750 txd = EPIC_CDTX(sc, i); 751 ds = EPIC_DSTX(sc, i); 752 753 EPIC_CDTXSYNC(sc, i, 754 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 755 756 txstatus = txd->et_txstatus; 757 if (txstatus & ET_TXSTAT_OWNER) 758 break; 759 760 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 761 762 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 763 0, ds->ds_dmamap->dm_mapsize, 764 BUS_DMASYNC_POSTWRITE); 765 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 766 m_freem(ds->ds_mbuf); 767 ds->ds_mbuf = NULL; 768 769 /* 770 * Check for errors and collisions. 771 */ 772 if ((txstatus & ET_TXSTAT_PACKETTX) == 0) 773 ifp->if_oerrors++; 774 else 775 ifp->if_opackets++; 776 ifp->if_collisions += 777 TXSTAT_COLLISIONS(txstatus); 778 if (txstatus & ET_TXSTAT_CARSENSELOST) 779 printf("%s: lost carrier\n", 780 device_xname(sc->sc_dev)); 781 } 782 783 /* Update the dirty transmit buffer pointer. */ 784 sc->sc_txdirty = i; 785 786 /* 787 * Cancel the watchdog timer if there are no pending 788 * transmissions. 789 */ 790 if (sc->sc_txpending == 0) 791 ifp->if_timer = 0; 792 793 /* 794 * Kick the transmitter after a DMA underrun. 795 */ 796 if (intstat & INTSTAT_TXU) { 797 printf("%s: transmit underrun\n", 798 device_xname(sc->sc_dev)); 799 bus_space_write_4(sc->sc_st, sc->sc_sh, 800 EPIC_COMMAND, COMMAND_TXUGO); 801 if (sc->sc_txpending) 802 bus_space_write_4(sc->sc_st, sc->sc_sh, 803 EPIC_COMMAND, COMMAND_TXQUEUED); 804 } 805 806 /* 807 * Try to get more packets going. 808 */ 809 epic_start(ifp); 810 } 811 812 /* 813 * Check for fatal interrupts. 814 */ 815 if (intstat & INTSTAT_FATAL_INT) { 816 if (intstat & INTSTAT_PTA) 817 printf("%s: PCI target abort error\n", 818 device_xname(sc->sc_dev)); 819 else if (intstat & INTSTAT_PMA) 820 printf("%s: PCI master abort error\n", 821 device_xname(sc->sc_dev)); 822 else if (intstat & INTSTAT_APE) 823 printf("%s: PCI address parity error\n", 824 device_xname(sc->sc_dev)); 825 else if (intstat & INTSTAT_DPE) 826 printf("%s: PCI data parity error\n", 827 device_xname(sc->sc_dev)); 828 else 829 printf("%s: unknown fatal error\n", 830 device_xname(sc->sc_dev)); 831 (void)epic_init(ifp); 832 } 833 834 /* 835 * Check for more interrupts. 836 */ 837 goto top; 838 } 839 840 /* 841 * One second timer, used to tick the MII. 842 */ 843 void 844 epic_tick(void *arg) 845 { 846 struct epic_softc *sc = arg; 847 int s; 848 849 s = splnet(); 850 mii_tick(&sc->sc_mii); 851 splx(s); 852 853 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 854 } 855 856 /* 857 * Fixup the clock source on the EPIC. 858 */ 859 void 860 epic_fixup_clock_source(struct epic_softc *sc) 861 { 862 int i; 863 864 /* 865 * According to SMC Application Note 7-15, the EPIC's clock 866 * source is incorrect following a reset. This manifests itself 867 * as failure to recognize when host software has written to 868 * a register on the EPIC. The appnote recommends issuing at 869 * least 16 consecutive writes to the CLOCK TEST bit to correctly 870 * configure the clock source. 871 */ 872 for (i = 0; i < 16; i++) 873 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 874 TEST_CLOCKTEST); 875 } 876 877 /* 878 * Perform a soft reset on the EPIC. 879 */ 880 void 881 epic_reset(struct epic_softc *sc) 882 { 883 884 epic_fixup_clock_source(sc); 885 886 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 887 delay(100); 888 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 889 delay(100); 890 891 epic_fixup_clock_source(sc); 892 } 893 894 /* 895 * Initialize the interface. Must be called at splnet(). 896 */ 897 int 898 epic_init(struct ifnet *ifp) 899 { 900 struct epic_softc *sc = ifp->if_softc; 901 bus_space_tag_t st = sc->sc_st; 902 bus_space_handle_t sh = sc->sc_sh; 903 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 904 struct epic_txdesc *txd; 905 struct epic_descsoft *ds; 906 uint32_t genctl, reg0; 907 int i, error = 0; 908 909 /* 910 * Cancel any pending I/O. 911 */ 912 epic_stop(ifp, 0); 913 914 /* 915 * Reset the EPIC to a known state. 916 */ 917 epic_reset(sc); 918 919 /* 920 * Magical mystery initialization. 921 */ 922 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 923 924 /* 925 * Initialize the EPIC genctl register: 926 * 927 * - 64 byte receive FIFO threshold 928 * - automatic advance to next receive frame 929 */ 930 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 931 #if BYTE_ORDER == BIG_ENDIAN 932 genctl |= GENCTL_BIG_ENDIAN; 933 #endif 934 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 935 936 /* 937 * Reset the MII bus and PHY. 938 */ 939 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 940 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 941 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 942 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 943 delay(100); 944 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 945 delay(1000); 946 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 947 948 /* 949 * Initialize Ethernet address. 950 */ 951 reg0 = enaddr[1] << 8 | enaddr[0]; 952 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 953 reg0 = enaddr[3] << 8 | enaddr[2]; 954 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 955 reg0 = enaddr[5] << 8 | enaddr[4]; 956 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 957 958 /* 959 * Initialize receive control. Remember the external buffer 960 * size setting. 961 */ 962 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 963 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 964 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 965 if (ifp->if_flags & IFF_PROMISC) 966 reg0 |= RXCON_PROMISCMODE; 967 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 968 969 /* Set the current media. */ 970 if ((error = epic_mediachange(ifp)) != 0) 971 goto out; 972 973 /* Set up the multicast hash table. */ 974 epic_set_mchash(sc); 975 976 /* 977 * Initialize the transmit descriptor ring. txlast is initialized 978 * to the end of the list so that it will wrap around to the first 979 * descriptor when the first packet is transmitted. 980 */ 981 for (i = 0; i < EPIC_NTXDESC; i++) { 982 txd = EPIC_CDTX(sc, i); 983 memset(txd, 0, sizeof(struct epic_txdesc)); 984 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 985 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 986 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 987 } 988 sc->sc_txpending = 0; 989 sc->sc_txdirty = 0; 990 sc->sc_txlast = EPIC_NTXDESC - 1; 991 992 /* 993 * Initialize the receive descriptor ring. 994 */ 995 for (i = 0; i < EPIC_NRXDESC; i++) { 996 ds = EPIC_DSRX(sc, i); 997 if (ds->ds_mbuf == NULL) { 998 if ((error = epic_add_rxbuf(sc, i)) != 0) { 999 printf("%s: unable to allocate or map rx " 1000 "buffer %d error = %d\n", 1001 device_xname(sc->sc_dev), i, error); 1002 /* 1003 * XXX Should attempt to run with fewer receive 1004 * XXX buffers instead of just failing. 1005 */ 1006 epic_rxdrain(sc); 1007 goto out; 1008 } 1009 } else 1010 EPIC_INIT_RXDESC(sc, i); 1011 } 1012 sc->sc_rxptr = 0; 1013 1014 /* 1015 * Initialize the interrupt mask and enable interrupts. 1016 */ 1017 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1018 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1019 1020 /* 1021 * Give the transmit and receive rings to the EPIC. 1022 */ 1023 bus_space_write_4(st, sh, EPIC_PTCDAR, 1024 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1025 bus_space_write_4(st, sh, EPIC_PRCDAR, 1026 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1027 1028 /* 1029 * Set the EPIC in motion. 1030 */ 1031 bus_space_write_4(st, sh, EPIC_COMMAND, 1032 COMMAND_RXQUEUED | COMMAND_START_RX); 1033 1034 /* 1035 * ...all done! 1036 */ 1037 ifp->if_flags |= IFF_RUNNING; 1038 ifp->if_flags &= ~IFF_OACTIVE; 1039 1040 /* 1041 * Start the one second clock. 1042 */ 1043 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 1044 1045 /* 1046 * Attempt to start output on the interface. 1047 */ 1048 epic_start(ifp); 1049 1050 out: 1051 if (error) 1052 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1053 return error; 1054 } 1055 1056 /* 1057 * Drain the receive queue. 1058 */ 1059 void 1060 epic_rxdrain(struct epic_softc *sc) 1061 { 1062 struct epic_descsoft *ds; 1063 int i; 1064 1065 for (i = 0; i < EPIC_NRXDESC; i++) { 1066 ds = EPIC_DSRX(sc, i); 1067 if (ds->ds_mbuf != NULL) { 1068 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1069 m_freem(ds->ds_mbuf); 1070 ds->ds_mbuf = NULL; 1071 } 1072 } 1073 } 1074 1075 /* 1076 * Stop transmission on the interface. 1077 */ 1078 void 1079 epic_stop(struct ifnet *ifp, int disable) 1080 { 1081 struct epic_softc *sc = ifp->if_softc; 1082 bus_space_tag_t st = sc->sc_st; 1083 bus_space_handle_t sh = sc->sc_sh; 1084 struct epic_descsoft *ds; 1085 uint32_t reg; 1086 int i; 1087 1088 /* 1089 * Stop the one second clock. 1090 */ 1091 callout_stop(&sc->sc_mii_callout); 1092 1093 /* Down the MII. */ 1094 mii_down(&sc->sc_mii); 1095 1096 /* Paranoia... */ 1097 epic_fixup_clock_source(sc); 1098 1099 /* 1100 * Disable interrupts. 1101 */ 1102 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1103 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1104 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1105 1106 /* 1107 * Stop the DMA engine and take the receiver off-line. 1108 */ 1109 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1110 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1111 1112 /* 1113 * Release any queued transmit buffers. 1114 */ 1115 for (i = 0; i < EPIC_NTXDESC; i++) { 1116 ds = EPIC_DSTX(sc, i); 1117 if (ds->ds_mbuf != NULL) { 1118 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1119 m_freem(ds->ds_mbuf); 1120 ds->ds_mbuf = NULL; 1121 } 1122 } 1123 1124 /* 1125 * Mark the interface down and cancel the watchdog timer. 1126 */ 1127 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1128 ifp->if_timer = 0; 1129 1130 if (disable) 1131 epic_rxdrain(sc); 1132 } 1133 1134 /* 1135 * Read the EPIC Serial EEPROM. 1136 */ 1137 void 1138 epic_read_eeprom(struct epic_softc *sc, int word, int wordcnt, uint16_t *data) 1139 { 1140 bus_space_tag_t st = sc->sc_st; 1141 bus_space_handle_t sh = sc->sc_sh; 1142 uint16_t reg; 1143 int i, x; 1144 1145 #define EEPROM_WAIT_READY(st, sh) \ 1146 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1147 /* nothing */ 1148 1149 /* 1150 * Enable the EEPROM. 1151 */ 1152 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1153 EEPROM_WAIT_READY(st, sh); 1154 1155 for (i = 0; i < wordcnt; i++) { 1156 /* Send CHIP SELECT for one clock tick. */ 1157 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1158 EEPROM_WAIT_READY(st, sh); 1159 1160 /* Shift in the READ opcode. */ 1161 for (x = 3; x > 0; x--) { 1162 reg = EECTL_ENABLE|EECTL_EECS; 1163 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1164 reg |= EECTL_EEDI; 1165 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1166 EEPROM_WAIT_READY(st, sh); 1167 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1168 EEPROM_WAIT_READY(st, sh); 1169 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1170 EEPROM_WAIT_READY(st, sh); 1171 } 1172 1173 /* Shift in address. */ 1174 for (x = 6; x > 0; x--) { 1175 reg = EECTL_ENABLE|EECTL_EECS; 1176 if ((word + i) & (1 << (x - 1))) 1177 reg |= EECTL_EEDI; 1178 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1179 EEPROM_WAIT_READY(st, sh); 1180 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1181 EEPROM_WAIT_READY(st, sh); 1182 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1183 EEPROM_WAIT_READY(st, sh); 1184 } 1185 1186 /* Shift out data. */ 1187 reg = EECTL_ENABLE|EECTL_EECS; 1188 data[i] = 0; 1189 for (x = 16; x > 0; x--) { 1190 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1191 EEPROM_WAIT_READY(st, sh); 1192 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1193 data[i] |= (1 << (x - 1)); 1194 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1195 EEPROM_WAIT_READY(st, sh); 1196 } 1197 1198 /* Clear CHIP SELECT. */ 1199 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1200 EEPROM_WAIT_READY(st, sh); 1201 } 1202 1203 /* 1204 * Disable the EEPROM. 1205 */ 1206 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1207 1208 #undef EEPROM_WAIT_READY 1209 } 1210 1211 /* 1212 * Add a receive buffer to the indicated descriptor. 1213 */ 1214 int 1215 epic_add_rxbuf(struct epic_softc *sc, int idx) 1216 { 1217 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1218 struct mbuf *m; 1219 int error; 1220 1221 MGETHDR(m, M_DONTWAIT, MT_DATA); 1222 if (m == NULL) 1223 return ENOBUFS; 1224 1225 MCLGET(m, M_DONTWAIT); 1226 if ((m->m_flags & M_EXT) == 0) { 1227 m_freem(m); 1228 return ENOBUFS; 1229 } 1230 1231 if (ds->ds_mbuf != NULL) 1232 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1233 1234 ds->ds_mbuf = m; 1235 1236 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1237 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1238 BUS_DMA_READ|BUS_DMA_NOWAIT); 1239 if (error) { 1240 printf("%s: can't load rx DMA map %d, error = %d\n", 1241 device_xname(sc->sc_dev), idx, error); 1242 panic("%s", __func__); /* XXX */ 1243 } 1244 1245 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1246 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1247 1248 EPIC_INIT_RXDESC(sc, idx); 1249 1250 return 0; 1251 } 1252 1253 /* 1254 * Set the EPIC multicast hash table. 1255 * 1256 * NOTE: We rely on a recently-updated mii_media_active here! 1257 */ 1258 void 1259 epic_set_mchash(struct epic_softc *sc) 1260 { 1261 struct ethercom *ec = &sc->sc_ethercom; 1262 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1263 struct ether_multi *enm; 1264 struct ether_multistep step; 1265 uint32_t hash, mchash[4]; 1266 1267 /* 1268 * Set up the multicast address filter by passing all multicast 1269 * addresses through a CRC generator, and then using the low-order 1270 * 6 bits as an index into the 64 bit multicast hash table (only 1271 * the lower 16 bits of each 32 bit multicast hash register are 1272 * valid). The high order bits select the register, while the 1273 * rest of the bits select the bit within the register. 1274 */ 1275 1276 if (ifp->if_flags & IFF_PROMISC) 1277 goto allmulti; 1278 1279 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1280 /* XXX hardware bug in 10Mbps mode. */ 1281 goto allmulti; 1282 } 1283 1284 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1285 1286 ETHER_FIRST_MULTI(step, ec, enm); 1287 while (enm != NULL) { 1288 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1289 /* 1290 * We must listen to a range of multicast addresses. 1291 * For now, just accept all multicasts, rather than 1292 * trying to set only those filter bits needed to match 1293 * the range. (At this time, the only use of address 1294 * ranges is for IP multicast routing, for which the 1295 * range is big enough to require all bits set.) 1296 */ 1297 goto allmulti; 1298 } 1299 1300 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1301 hash >>= 26; 1302 1303 /* Set the corresponding bit in the hash table. */ 1304 mchash[hash >> 4] |= 1 << (hash & 0xf); 1305 1306 ETHER_NEXT_MULTI(step, enm); 1307 } 1308 1309 ifp->if_flags &= ~IFF_ALLMULTI; 1310 goto sethash; 1311 1312 allmulti: 1313 ifp->if_flags |= IFF_ALLMULTI; 1314 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1315 1316 sethash: 1317 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1318 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1319 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1320 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1321 } 1322 1323 /* 1324 * Wait for the MII to become ready. 1325 */ 1326 int 1327 epic_mii_wait(struct epic_softc *sc, uint32_t rw) 1328 { 1329 int i; 1330 1331 for (i = 0; i < 50; i++) { 1332 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1333 == 0) 1334 break; 1335 delay(2); 1336 } 1337 if (i == 50) { 1338 printf("%s: MII timed out\n", device_xname(sc->sc_dev)); 1339 return 1; 1340 } 1341 1342 return 0; 1343 } 1344 1345 /* 1346 * Read from the MII. 1347 */ 1348 int 1349 epic_mii_read(device_t self, int phy, int reg) 1350 { 1351 struct epic_softc *sc = device_private(self); 1352 1353 if (epic_mii_wait(sc, MMCTL_WRITE)) 1354 return 0; 1355 1356 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1357 MMCTL_ARG(phy, reg, MMCTL_READ)); 1358 1359 if (epic_mii_wait(sc, MMCTL_READ)) 1360 return 0; 1361 1362 return bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) & 1363 MMDATA_MASK; 1364 } 1365 1366 /* 1367 * Write to the MII. 1368 */ 1369 void 1370 epic_mii_write(device_t self, int phy, int reg, int val) 1371 { 1372 struct epic_softc *sc = device_private(self); 1373 1374 if (epic_mii_wait(sc, MMCTL_WRITE)) 1375 return; 1376 1377 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1378 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1379 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1380 } 1381 1382 /* 1383 * Callback from PHY when media changes. 1384 */ 1385 void 1386 epic_statchg(device_t self) 1387 { 1388 struct epic_softc *sc = device_private(self); 1389 uint32_t txcon, miicfg; 1390 1391 /* 1392 * Update loopback bits in TXCON to reflect duplex mode. 1393 */ 1394 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1395 if (sc->sc_mii.mii_media_active & IFM_FDX) 1396 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1397 else 1398 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1399 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1400 1401 /* On some cards we need manualy set fullduplex led */ 1402 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1403 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1404 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1405 miicfg |= MIICFG_ENABLE; 1406 else 1407 miicfg &= ~MIICFG_ENABLE; 1408 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1409 } 1410 1411 /* 1412 * There is a multicast filter bug in 10Mbps mode. Kick the 1413 * multicast filter in case the speed changed. 1414 */ 1415 epic_set_mchash(sc); 1416 } 1417 1418 /* 1419 * Callback from ifmedia to request new media setting. 1420 * 1421 * XXX Looks to me like some of this complexity should move into 1422 * XXX one or two custom PHY drivers. --dyoung 1423 */ 1424 int 1425 epic_mediachange(struct ifnet *ifp) 1426 { 1427 struct epic_softc *sc = ifp->if_softc; 1428 struct mii_data *mii = &sc->sc_mii; 1429 struct ifmedia *ifm = &mii->mii_media; 1430 int media = ifm->ifm_cur->ifm_media; 1431 uint32_t miicfg; 1432 struct mii_softc *miisc; 1433 int cfg, rc; 1434 1435 if ((ifp->if_flags & IFF_UP) == 0) 1436 return 0; 1437 1438 if (IFM_INST(media) != sc->sc_serinst) { 1439 /* If we're not selecting serial interface, select MII mode */ 1440 #ifdef EPICMEDIADEBUG 1441 printf("%s: parallel mode\n", ifp->if_xname); 1442 #endif 1443 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1444 miicfg &= ~MIICFG_SERMODEENA; 1445 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1446 } 1447 1448 if ((rc = mii_mediachg(mii)) == ENXIO) 1449 rc = 0; 1450 1451 if (IFM_INST(media) == sc->sc_serinst) { 1452 /* select serial interface */ 1453 #ifdef EPICMEDIADEBUG 1454 printf("%s: serial mode\n", ifp->if_xname); 1455 #endif 1456 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1457 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1458 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1459 1460 /* There is no driver to fill this */ 1461 mii->mii_media_active = media; 1462 mii->mii_media_status = 0; 1463 1464 epic_statchg(sc->sc_dev); 1465 return 0; 1466 } 1467 1468 /* Lookup selected PHY */ 1469 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1470 if (IFM_INST(media) == miisc->mii_inst) 1471 break; 1472 } 1473 if (!miisc) { 1474 printf("%s: can't happen\n", __func__); /* ??? panic */ 1475 return 0; 1476 } 1477 #ifdef EPICMEDIADEBUG 1478 printf("%s: using phy %s\n", ifp->if_xname, 1479 device_xname(miisc->mii_dev)); 1480 #endif 1481 1482 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1483 /* XXX XXX assume it's a Level1 - should check */ 1484 1485 /* We have to powerup fiber transceivers */ 1486 cfg = PHY_READ(miisc, MII_LXTPHY_CONFIG); 1487 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1488 #ifdef EPICMEDIADEBUG 1489 printf("%s: power up fiber\n", ifp->if_xname); 1490 #endif 1491 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1492 } else { 1493 #ifdef EPICMEDIADEBUG 1494 printf("%s: power down fiber\n", ifp->if_xname); 1495 #endif 1496 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1497 } 1498 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1499 } 1500 1501 return rc; 1502 } 1503
Indexes created Sun Sep 28 07:09:56 GMT 2025