smc83c170.c revision 1.86
1 /* $NetBSD: smc83c170.c,v 1.86 2018/06/26 06:48:00 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the Standard Microsystems Corp. 83C170 35 * Ethernet PCI Integrated Controller (EPIC/100). 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.86 2018/06/26 06:48:00 msaitoh Exp $"); 40 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/miivar.h> 64 #include <dev/mii/lxtphyreg.h> 65 66 #include <dev/ic/smc83c170reg.h> 67 #include <dev/ic/smc83c170var.h> 68 69 void epic_start(struct ifnet *); 70 void epic_watchdog(struct ifnet *); 71 int epic_ioctl(struct ifnet *, u_long, void *); 72 int epic_init(struct ifnet *); 73 void epic_stop(struct ifnet *, int); 74 75 bool epic_shutdown(device_t, int); 76 77 void epic_reset(struct epic_softc *); 78 void epic_rxdrain(struct epic_softc *); 79 int epic_add_rxbuf(struct epic_softc *, int); 80 void epic_read_eeprom(struct epic_softc *, int, int, uint16_t *); 81 void epic_set_mchash(struct epic_softc *); 82 void epic_fixup_clock_source(struct epic_softc *); 83 int epic_mii_read(device_t, int, int); 84 void epic_mii_write(device_t, int, int, int); 85 int epic_mii_wait(struct epic_softc *, uint32_t); 86 void epic_tick(void *); 87 88 void epic_statchg(struct ifnet *); 89 int epic_mediachange(struct ifnet *); 90 91 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 92 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 93 94 int epic_copy_small = 0; 95 96 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 97 98 /* 99 * Attach an EPIC interface to the system. 100 */ 101 void 102 epic_attach(struct epic_softc *sc) 103 { 104 bus_space_tag_t st = sc->sc_st; 105 bus_space_handle_t sh = sc->sc_sh; 106 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 107 int rseg, error, miiflags; 108 u_int i; 109 bus_dma_segment_t seg; 110 uint8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 111 uint16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 112 char *nullbuf; 113 114 callout_init(&sc->sc_mii_callout, 0); 115 116 /* 117 * Allocate the control data structures, and create and load the 118 * DMA map for it. 119 */ 120 if ((error = bus_dmamem_alloc(sc->sc_dmat, 121 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0, 122 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 123 aprint_error_dev(sc->sc_dev, 124 "unable to allocate control data, error = %d\n", error); 125 goto fail_0; 126 } 127 128 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 129 sizeof(struct epic_control_data) + ETHER_PAD_LEN, 130 (void **)&sc->sc_control_data, 131 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 132 aprint_error_dev(sc->sc_dev, 133 "unable to map control data, error = %d\n", error); 134 goto fail_1; 135 } 136 nullbuf = 137 (char *)sc->sc_control_data + sizeof(struct epic_control_data); 138 memset(nullbuf, 0, ETHER_PAD_LEN); 139 140 if ((error = bus_dmamap_create(sc->sc_dmat, 141 sizeof(struct epic_control_data), 1, 142 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 143 &sc->sc_cddmamap)) != 0) { 144 aprint_error_dev(sc->sc_dev, 145 "unable to create control data DMA map, error = %d\n", 146 error); 147 goto fail_2; 148 } 149 150 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 151 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 152 BUS_DMA_NOWAIT)) != 0) { 153 aprint_error_dev(sc->sc_dev, 154 "unable to load control data DMA map, error = %d\n", 155 error); 156 goto fail_3; 157 } 158 159 /* 160 * Create the transmit buffer DMA maps. 161 */ 162 for (i = 0; i < EPIC_NTXDESC; i++) { 163 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 164 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 165 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 166 aprint_error_dev(sc->sc_dev, 167 "unable to create tx DMA map %d, error = %d\n", 168 i, error); 169 goto fail_4; 170 } 171 } 172 173 /* 174 * Create the receive buffer DMA maps. 175 */ 176 for (i = 0; i < EPIC_NRXDESC; i++) { 177 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 178 MCLBYTES, 0, BUS_DMA_NOWAIT, 179 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 180 aprint_error_dev(sc->sc_dev, 181 "unable to create rx DMA map %d, error = %d\n", 182 i, error); 183 goto fail_5; 184 } 185 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 186 } 187 188 /* 189 * create and map the pad buffer 190 */ 191 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 192 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) { 193 aprint_error_dev(sc->sc_dev, 194 "unable to create pad buffer DMA map, error = %d\n", error); 195 goto fail_5; 196 } 197 198 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 199 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 200 aprint_error_dev(sc->sc_dev, 201 "unable to load pad buffer DMA map, error = %d\n", error); 202 goto fail_6; 203 } 204 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 205 BUS_DMASYNC_PREWRITE); 206 207 /* 208 * Bring the chip out of low-power mode and reset it to a known state. 209 */ 210 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 211 epic_reset(sc); 212 213 /* 214 * Read the Ethernet address from the EEPROM. 215 */ 216 epic_read_eeprom(sc, 0, __arraycount(myea), myea); 217 for (i = 0; i < __arraycount(myea); i++) { 218 enaddr[i * 2] = myea[i] & 0xff; 219 enaddr[i * 2 + 1] = myea[i] >> 8; 220 } 221 222 /* 223 * ...and the device name. 224 */ 225 epic_read_eeprom(sc, 0x2c, __arraycount(mydevname), mydevname); 226 for (i = 0; i < __arraycount(mydevname); i++) { 227 devname[i * 2] = mydevname[i] & 0xff; 228 devname[i * 2 + 1] = mydevname[i] >> 8; 229 } 230 231 devname[sizeof(mydevname)] = '\0'; 232 for (i = sizeof(mydevname) ; i > 0; i--) { 233 if (devname[i - 1] == ' ') 234 devname[i - 1] = '\0'; 235 else 236 break; 237 } 238 239 aprint_normal_dev(sc->sc_dev, "%s, Ethernet address %s\n", 240 devname, ether_sprintf(enaddr)); 241 242 miiflags = 0; 243 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 244 miiflags |= MIIF_HAVEFIBER; 245 246 /* 247 * Initialize our media structures and probe the MII. 248 */ 249 sc->sc_mii.mii_ifp = ifp; 250 sc->sc_mii.mii_readreg = epic_mii_read; 251 sc->sc_mii.mii_writereg = epic_mii_write; 252 sc->sc_mii.mii_statchg = epic_statchg; 253 254 sc->sc_ethercom.ec_mii = &sc->sc_mii; 255 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epic_mediachange, 256 ether_mediastatus); 257 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 258 MII_OFFSET_ANY, miiflags); 259 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 260 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 261 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 262 } else 263 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 264 265 if (sc->sc_hwflags & EPIC_HAS_BNC) { 266 /* use the next free media instance */ 267 sc->sc_serinst = sc->sc_mii.mii_instance++; 268 ifmedia_add(&sc->sc_mii.mii_media, 269 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->sc_serinst), 270 0, NULL); 271 aprint_normal_dev(sc->sc_dev, "10base2/BNC\n"); 272 } else 273 sc->sc_serinst = -1; 274 275 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 276 ifp->if_softc = sc; 277 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 278 ifp->if_ioctl = epic_ioctl; 279 ifp->if_start = epic_start; 280 ifp->if_watchdog = epic_watchdog; 281 ifp->if_init = epic_init; 282 ifp->if_stop = epic_stop; 283 IFQ_SET_READY(&ifp->if_snd); 284 285 /* 286 * We can support 802.1Q VLAN-sized frames. 287 */ 288 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 289 290 /* 291 * Attach the interface. 292 */ 293 if_attach(ifp); 294 if_deferred_start_init(ifp, NULL); 295 ether_ifattach(ifp, enaddr); 296 297 /* 298 * Make sure the interface is shutdown during reboot. 299 */ 300 if (pmf_device_register1(sc->sc_dev, NULL, NULL, epic_shutdown)) 301 pmf_class_network_register(sc->sc_dev, ifp); 302 else 303 aprint_error_dev(sc->sc_dev, 304 "couldn't establish power handler\n"); 305 306 return; 307 308 /* 309 * Free any resources we've allocated during the failed attach 310 * attempt. Do this in reverse order and fall through. 311 */ 312 fail_6: 313 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 314 fail_5: 315 for (i = 0; i < EPIC_NRXDESC; i++) { 316 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 317 bus_dmamap_destroy(sc->sc_dmat, 318 EPIC_DSRX(sc, i)->ds_dmamap); 319 } 320 fail_4: 321 for (i = 0; i < EPIC_NTXDESC; i++) { 322 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 323 bus_dmamap_destroy(sc->sc_dmat, 324 EPIC_DSTX(sc, i)->ds_dmamap); 325 } 326 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 327 fail_3: 328 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 329 fail_2: 330 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 331 sizeof(struct epic_control_data)); 332 fail_1: 333 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 334 fail_0: 335 return; 336 } 337 338 /* 339 * Shutdown hook. Make sure the interface is stopped at reboot. 340 */ 341 bool 342 epic_shutdown(device_t self, int howto) 343 { 344 struct epic_softc *sc = device_private(self); 345 346 epic_stop(&sc->sc_ethercom.ec_if, 1); 347 348 return true; 349 } 350 351 /* 352 * Start packet transmission on the interface. 353 * [ifnet interface function] 354 */ 355 void 356 epic_start(struct ifnet *ifp) 357 { 358 struct epic_softc *sc = ifp->if_softc; 359 struct mbuf *m0, *m; 360 struct epic_txdesc *txd; 361 struct epic_descsoft *ds; 362 struct epic_fraglist *fr; 363 bus_dmamap_t dmamap; 364 int error, firsttx, nexttx, opending, seg; 365 u_int len; 366 367 /* 368 * Remember the previous txpending and the first transmit 369 * descriptor we use. 370 */ 371 opending = sc->sc_txpending; 372 firsttx = EPIC_NEXTTX(sc->sc_txlast); 373 374 /* 375 * Loop through the send queue, setting up transmit descriptors 376 * until we drain the queue, or use up all available transmit 377 * descriptors. 378 */ 379 while (sc->sc_txpending < EPIC_NTXDESC) { 380 /* 381 * Grab a packet off the queue. 382 */ 383 IFQ_POLL(&ifp->if_snd, m0); 384 if (m0 == NULL) 385 break; 386 m = NULL; 387 388 /* 389 * Get the last and next available transmit descriptor. 390 */ 391 nexttx = EPIC_NEXTTX(sc->sc_txlast); 392 txd = EPIC_CDTX(sc, nexttx); 393 fr = EPIC_CDFL(sc, nexttx); 394 ds = EPIC_DSTX(sc, nexttx); 395 dmamap = ds->ds_dmamap; 396 397 /* 398 * Load the DMA map. If this fails, the packet either 399 * didn't fit in the alloted number of frags, or we were 400 * short on resources. In this case, we'll copy and try 401 * again. 402 */ 403 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 404 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 405 (m0->m_pkthdr.len < ETHER_PAD_LEN && 406 dmamap-> dm_nsegs == EPIC_NFRAGS)) { 407 if (error == 0) 408 bus_dmamap_unload(sc->sc_dmat, dmamap); 409 410 MGETHDR(m, M_DONTWAIT, MT_DATA); 411 if (m == NULL) { 412 printf("%s: unable to allocate Tx mbuf\n", 413 device_xname(sc->sc_dev)); 414 break; 415 } 416 if (m0->m_pkthdr.len > MHLEN) { 417 MCLGET(m, M_DONTWAIT); 418 if ((m->m_flags & M_EXT) == 0) { 419 printf("%s: unable to allocate Tx " 420 "cluster\n", 421 device_xname(sc->sc_dev)); 422 m_freem(m); 423 break; 424 } 425 } 426 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 427 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 428 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 429 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 430 if (error) { 431 printf("%s: unable to load Tx buffer, " 432 "error = %d\n", device_xname(sc->sc_dev), 433 error); 434 break; 435 } 436 } 437 IFQ_DEQUEUE(&ifp->if_snd, m0); 438 if (m != NULL) { 439 m_freem(m0); 440 m0 = m; 441 } 442 443 /* Initialize the fraglist. */ 444 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 445 fr->ef_frags[seg].ef_addr = 446 dmamap->dm_segs[seg].ds_addr; 447 fr->ef_frags[seg].ef_length = 448 dmamap->dm_segs[seg].ds_len; 449 } 450 len = m0->m_pkthdr.len; 451 if (len < ETHER_PAD_LEN) { 452 fr->ef_frags[seg].ef_addr = sc->sc_nulldma; 453 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len; 454 len = ETHER_PAD_LEN; 455 seg++; 456 } 457 fr->ef_nfrags = seg; 458 459 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 460 461 /* Sync the DMA map. */ 462 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 463 BUS_DMASYNC_PREWRITE); 464 465 /* 466 * Store a pointer to the packet so we can free it later. 467 */ 468 ds->ds_mbuf = m0; 469 470 /* 471 * Fill in the transmit descriptor. 472 */ 473 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 474 475 /* 476 * If this is the first descriptor we're enqueueing, 477 * don't give it to the EPIC yet. That could cause 478 * a race condition. We'll do it below. 479 */ 480 if (nexttx == firsttx) 481 txd->et_txstatus = TXSTAT_TXLENGTH(len); 482 else 483 txd->et_txstatus = 484 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER; 485 486 EPIC_CDTXSYNC(sc, nexttx, 487 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 488 489 /* Advance the tx pointer. */ 490 sc->sc_txpending++; 491 sc->sc_txlast = nexttx; 492 493 /* 494 * Pass the packet to any BPF listeners. 495 */ 496 bpf_mtap(ifp, m0, BPF_D_OUT); 497 } 498 499 if (sc->sc_txpending == EPIC_NTXDESC) { 500 /* No more slots left; notify upper layer. */ 501 ifp->if_flags |= IFF_OACTIVE; 502 } 503 504 if (sc->sc_txpending != opending) { 505 /* 506 * We enqueued packets. If the transmitter was idle, 507 * reset the txdirty pointer. 508 */ 509 if (opending == 0) 510 sc->sc_txdirty = firsttx; 511 512 /* 513 * Cause a transmit interrupt to happen on the 514 * last packet we enqueued. 515 */ 516 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 517 EPIC_CDTXSYNC(sc, sc->sc_txlast, 518 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 519 520 /* 521 * The entire packet chain is set up. Give the 522 * first descriptor to the EPIC now. 523 */ 524 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER; 525 EPIC_CDTXSYNC(sc, firsttx, 526 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 527 528 /* Start the transmitter. */ 529 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 530 COMMAND_TXQUEUED); 531 532 /* Set a watchdog timer in case the chip flakes out. */ 533 ifp->if_timer = 5; 534 } 535 } 536 537 /* 538 * Watchdog timer handler. 539 * [ifnet interface function] 540 */ 541 void 542 epic_watchdog(struct ifnet *ifp) 543 { 544 struct epic_softc *sc = ifp->if_softc; 545 546 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 547 ifp->if_oerrors++; 548 549 (void)epic_init(ifp); 550 } 551 552 /* 553 * Handle control requests from the operator. 554 * [ifnet interface function] 555 */ 556 int 557 epic_ioctl(struct ifnet *ifp, u_long cmd, void *data) 558 { 559 struct epic_softc *sc = ifp->if_softc; 560 int s, error; 561 562 s = splnet(); 563 564 error = ether_ioctl(ifp, cmd, data); 565 if (error == ENETRESET) { 566 /* 567 * Multicast list has changed; set the hardware filter 568 * accordingly. Update our idea of the current media; 569 * epic_set_mchash() needs to know what it is. 570 */ 571 if (ifp->if_flags & IFF_RUNNING) { 572 mii_pollstat(&sc->sc_mii); 573 epic_set_mchash(sc); 574 } 575 error = 0; 576 } 577 578 splx(s); 579 return error; 580 } 581 582 /* 583 * Interrupt handler. 584 */ 585 int 586 epic_intr(void *arg) 587 { 588 struct epic_softc *sc = arg; 589 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 590 struct epic_rxdesc *rxd; 591 struct epic_txdesc *txd; 592 struct epic_descsoft *ds; 593 struct mbuf *m; 594 uint32_t intstat, rxstatus, txstatus; 595 int i, claimed = 0; 596 u_int len; 597 598 top: 599 /* 600 * Get the interrupt status from the EPIC. 601 */ 602 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 603 if ((intstat & INTSTAT_INT_ACTV) == 0) 604 return claimed; 605 606 claimed = 1; 607 608 /* 609 * Acknowledge the interrupt. 610 */ 611 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 612 intstat & INTMASK); 613 614 /* 615 * Check for receive interrupts. 616 */ 617 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 618 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 619 rxd = EPIC_CDRX(sc, i); 620 ds = EPIC_DSRX(sc, i); 621 622 EPIC_CDRXSYNC(sc, i, 623 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 624 625 rxstatus = rxd->er_rxstatus; 626 if (rxstatus & ER_RXSTAT_OWNER) { 627 /* 628 * We have processed all of the 629 * receive buffers. 630 */ 631 break; 632 } 633 634 /* 635 * Make sure the packet arrived intact. If an error 636 * occurred, update stats and reset the descriptor. 637 * The buffer will be reused the next time the 638 * descriptor comes up in the ring. 639 */ 640 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 641 if (rxstatus & ER_RXSTAT_CRCERROR) 642 printf("%s: CRC error\n", 643 device_xname(sc->sc_dev)); 644 if (rxstatus & ER_RXSTAT_ALIGNERROR) 645 printf("%s: alignment error\n", 646 device_xname(sc->sc_dev)); 647 ifp->if_ierrors++; 648 EPIC_INIT_RXDESC(sc, i); 649 continue; 650 } 651 652 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 653 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 654 655 /* 656 * The EPIC includes the CRC with every packet; 657 * trim it. 658 */ 659 len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN; 660 661 if (len < sizeof(struct ether_header)) { 662 /* 663 * Runt packet; drop it now. 664 */ 665 ifp->if_ierrors++; 666 EPIC_INIT_RXDESC(sc, i); 667 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 668 ds->ds_dmamap->dm_mapsize, 669 BUS_DMASYNC_PREREAD); 670 continue; 671 } 672 673 /* 674 * If the packet is small enough to fit in a 675 * single header mbuf, allocate one and copy 676 * the data into it. This greatly reduces 677 * memory consumption when we receive lots 678 * of small packets. 679 * 680 * Otherwise, we add a new buffer to the receive 681 * chain. If this fails, we drop the packet and 682 * recycle the old buffer. 683 */ 684 if (epic_copy_small != 0 && len <= MHLEN) { 685 MGETHDR(m, M_DONTWAIT, MT_DATA); 686 if (m == NULL) 687 goto dropit; 688 memcpy(mtod(m, void *), 689 mtod(ds->ds_mbuf, void *), len); 690 EPIC_INIT_RXDESC(sc, i); 691 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 692 ds->ds_dmamap->dm_mapsize, 693 BUS_DMASYNC_PREREAD); 694 } else { 695 m = ds->ds_mbuf; 696 if (epic_add_rxbuf(sc, i) != 0) { 697 dropit: 698 ifp->if_ierrors++; 699 EPIC_INIT_RXDESC(sc, i); 700 bus_dmamap_sync(sc->sc_dmat, 701 ds->ds_dmamap, 0, 702 ds->ds_dmamap->dm_mapsize, 703 BUS_DMASYNC_PREREAD); 704 continue; 705 } 706 } 707 708 m_set_rcvif(m, ifp); 709 m->m_pkthdr.len = m->m_len = len; 710 711 /* Pass it on. */ 712 if_percpuq_enqueue(ifp->if_percpuq, m); 713 } 714 715 /* Update the receive pointer. */ 716 sc->sc_rxptr = i; 717 718 /* 719 * Check for receive queue underflow. 720 */ 721 if (intstat & INTSTAT_RQE) { 722 printf("%s: receiver queue empty\n", 723 device_xname(sc->sc_dev)); 724 /* 725 * Ring is already built; just restart the 726 * receiver. 727 */ 728 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 729 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 730 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 731 COMMAND_RXQUEUED | COMMAND_START_RX); 732 } 733 } 734 735 /* 736 * Check for transmission complete interrupts. 737 */ 738 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 739 ifp->if_flags &= ~IFF_OACTIVE; 740 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 741 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 742 txd = EPIC_CDTX(sc, i); 743 ds = EPIC_DSTX(sc, i); 744 745 EPIC_CDTXSYNC(sc, i, 746 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 747 748 txstatus = txd->et_txstatus; 749 if (txstatus & ET_TXSTAT_OWNER) 750 break; 751 752 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 753 754 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 755 0, ds->ds_dmamap->dm_mapsize, 756 BUS_DMASYNC_POSTWRITE); 757 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 758 m_freem(ds->ds_mbuf); 759 ds->ds_mbuf = NULL; 760 761 /* 762 * Check for errors and collisions. 763 */ 764 if ((txstatus & ET_TXSTAT_PACKETTX) == 0) 765 ifp->if_oerrors++; 766 else 767 ifp->if_opackets++; 768 ifp->if_collisions += 769 TXSTAT_COLLISIONS(txstatus); 770 if (txstatus & ET_TXSTAT_CARSENSELOST) 771 printf("%s: lost carrier\n", 772 device_xname(sc->sc_dev)); 773 } 774 775 /* Update the dirty transmit buffer pointer. */ 776 sc->sc_txdirty = i; 777 778 /* 779 * Cancel the watchdog timer if there are no pending 780 * transmissions. 781 */ 782 if (sc->sc_txpending == 0) 783 ifp->if_timer = 0; 784 785 /* 786 * Kick the transmitter after a DMA underrun. 787 */ 788 if (intstat & INTSTAT_TXU) { 789 printf("%s: transmit underrun\n", 790 device_xname(sc->sc_dev)); 791 bus_space_write_4(sc->sc_st, sc->sc_sh, 792 EPIC_COMMAND, COMMAND_TXUGO); 793 if (sc->sc_txpending) 794 bus_space_write_4(sc->sc_st, sc->sc_sh, 795 EPIC_COMMAND, COMMAND_TXQUEUED); 796 } 797 798 /* 799 * Try to get more packets going. 800 */ 801 if_schedule_deferred_start(ifp); 802 } 803 804 /* 805 * Check for fatal interrupts. 806 */ 807 if (intstat & INTSTAT_FATAL_INT) { 808 if (intstat & INTSTAT_PTA) 809 printf("%s: PCI target abort error\n", 810 device_xname(sc->sc_dev)); 811 else if (intstat & INTSTAT_PMA) 812 printf("%s: PCI master abort error\n", 813 device_xname(sc->sc_dev)); 814 else if (intstat & INTSTAT_APE) 815 printf("%s: PCI address parity error\n", 816 device_xname(sc->sc_dev)); 817 else if (intstat & INTSTAT_DPE) 818 printf("%s: PCI data parity error\n", 819 device_xname(sc->sc_dev)); 820 else 821 printf("%s: unknown fatal error\n", 822 device_xname(sc->sc_dev)); 823 (void)epic_init(ifp); 824 } 825 826 /* 827 * Check for more interrupts. 828 */ 829 goto top; 830 } 831 832 /* 833 * One second timer, used to tick the MII. 834 */ 835 void 836 epic_tick(void *arg) 837 { 838 struct epic_softc *sc = arg; 839 int s; 840 841 s = splnet(); 842 mii_tick(&sc->sc_mii); 843 splx(s); 844 845 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 846 } 847 848 /* 849 * Fixup the clock source on the EPIC. 850 */ 851 void 852 epic_fixup_clock_source(struct epic_softc *sc) 853 { 854 int i; 855 856 /* 857 * According to SMC Application Note 7-15, the EPIC's clock 858 * source is incorrect following a reset. This manifests itself 859 * as failure to recognize when host software has written to 860 * a register on the EPIC. The appnote recommends issuing at 861 * least 16 consecutive writes to the CLOCK TEST bit to correctly 862 * configure the clock source. 863 */ 864 for (i = 0; i < 16; i++) 865 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 866 TEST_CLOCKTEST); 867 } 868 869 /* 870 * Perform a soft reset on the EPIC. 871 */ 872 void 873 epic_reset(struct epic_softc *sc) 874 { 875 876 epic_fixup_clock_source(sc); 877 878 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 879 delay(100); 880 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 881 delay(100); 882 883 epic_fixup_clock_source(sc); 884 } 885 886 /* 887 * Initialize the interface. Must be called at splnet(). 888 */ 889 int 890 epic_init(struct ifnet *ifp) 891 { 892 struct epic_softc *sc = ifp->if_softc; 893 bus_space_tag_t st = sc->sc_st; 894 bus_space_handle_t sh = sc->sc_sh; 895 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 896 struct epic_txdesc *txd; 897 struct epic_descsoft *ds; 898 uint32_t genctl, reg0; 899 int i, error = 0; 900 901 /* 902 * Cancel any pending I/O. 903 */ 904 epic_stop(ifp, 0); 905 906 /* 907 * Reset the EPIC to a known state. 908 */ 909 epic_reset(sc); 910 911 /* 912 * Magical mystery initialization. 913 */ 914 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 915 916 /* 917 * Initialize the EPIC genctl register: 918 * 919 * - 64 byte receive FIFO threshold 920 * - automatic advance to next receive frame 921 */ 922 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 923 #if BYTE_ORDER == BIG_ENDIAN 924 genctl |= GENCTL_BIG_ENDIAN; 925 #endif 926 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 927 928 /* 929 * Reset the MII bus and PHY. 930 */ 931 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 932 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 933 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 934 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 935 delay(100); 936 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 937 delay(1000); 938 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 939 940 /* 941 * Initialize Ethernet address. 942 */ 943 reg0 = enaddr[1] << 8 | enaddr[0]; 944 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 945 reg0 = enaddr[3] << 8 | enaddr[2]; 946 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 947 reg0 = enaddr[5] << 8 | enaddr[4]; 948 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 949 950 /* 951 * Initialize receive control. Remember the external buffer 952 * size setting. 953 */ 954 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 955 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 956 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 957 if (ifp->if_flags & IFF_PROMISC) 958 reg0 |= RXCON_PROMISCMODE; 959 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 960 961 /* Set the current media. */ 962 if ((error = epic_mediachange(ifp)) != 0) 963 goto out; 964 965 /* Set up the multicast hash table. */ 966 epic_set_mchash(sc); 967 968 /* 969 * Initialize the transmit descriptor ring. txlast is initialized 970 * to the end of the list so that it will wrap around to the first 971 * descriptor when the first packet is transmitted. 972 */ 973 for (i = 0; i < EPIC_NTXDESC; i++) { 974 txd = EPIC_CDTX(sc, i); 975 memset(txd, 0, sizeof(struct epic_txdesc)); 976 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 977 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 978 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 979 } 980 sc->sc_txpending = 0; 981 sc->sc_txdirty = 0; 982 sc->sc_txlast = EPIC_NTXDESC - 1; 983 984 /* 985 * Initialize the receive descriptor ring. 986 */ 987 for (i = 0; i < EPIC_NRXDESC; i++) { 988 ds = EPIC_DSRX(sc, i); 989 if (ds->ds_mbuf == NULL) { 990 if ((error = epic_add_rxbuf(sc, i)) != 0) { 991 printf("%s: unable to allocate or map rx " 992 "buffer %d error = %d\n", 993 device_xname(sc->sc_dev), i, error); 994 /* 995 * XXX Should attempt to run with fewer receive 996 * XXX buffers instead of just failing. 997 */ 998 epic_rxdrain(sc); 999 goto out; 1000 } 1001 } else 1002 EPIC_INIT_RXDESC(sc, i); 1003 } 1004 sc->sc_rxptr = 0; 1005 1006 /* 1007 * Initialize the interrupt mask and enable interrupts. 1008 */ 1009 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1010 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1011 1012 /* 1013 * Give the transmit and receive rings to the EPIC. 1014 */ 1015 bus_space_write_4(st, sh, EPIC_PTCDAR, 1016 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1017 bus_space_write_4(st, sh, EPIC_PRCDAR, 1018 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1019 1020 /* 1021 * Set the EPIC in motion. 1022 */ 1023 bus_space_write_4(st, sh, EPIC_COMMAND, 1024 COMMAND_RXQUEUED | COMMAND_START_RX); 1025 1026 /* 1027 * ...all done! 1028 */ 1029 ifp->if_flags |= IFF_RUNNING; 1030 ifp->if_flags &= ~IFF_OACTIVE; 1031 1032 /* 1033 * Start the one second clock. 1034 */ 1035 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 1036 1037 /* 1038 * Attempt to start output on the interface. 1039 */ 1040 epic_start(ifp); 1041 1042 out: 1043 if (error) 1044 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1045 return error; 1046 } 1047 1048 /* 1049 * Drain the receive queue. 1050 */ 1051 void 1052 epic_rxdrain(struct epic_softc *sc) 1053 { 1054 struct epic_descsoft *ds; 1055 int i; 1056 1057 for (i = 0; i < EPIC_NRXDESC; i++) { 1058 ds = EPIC_DSRX(sc, i); 1059 if (ds->ds_mbuf != NULL) { 1060 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1061 m_freem(ds->ds_mbuf); 1062 ds->ds_mbuf = NULL; 1063 } 1064 } 1065 } 1066 1067 /* 1068 * Stop transmission on the interface. 1069 */ 1070 void 1071 epic_stop(struct ifnet *ifp, int disable) 1072 { 1073 struct epic_softc *sc = ifp->if_softc; 1074 bus_space_tag_t st = sc->sc_st; 1075 bus_space_handle_t sh = sc->sc_sh; 1076 struct epic_descsoft *ds; 1077 uint32_t reg; 1078 int i; 1079 1080 /* 1081 * Stop the one second clock. 1082 */ 1083 callout_stop(&sc->sc_mii_callout); 1084 1085 /* Down the MII. */ 1086 mii_down(&sc->sc_mii); 1087 1088 /* Paranoia... */ 1089 epic_fixup_clock_source(sc); 1090 1091 /* 1092 * Disable interrupts. 1093 */ 1094 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1095 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1096 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1097 1098 /* 1099 * Stop the DMA engine and take the receiver off-line. 1100 */ 1101 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1102 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1103 1104 /* 1105 * Release any queued transmit buffers. 1106 */ 1107 for (i = 0; i < EPIC_NTXDESC; i++) { 1108 ds = EPIC_DSTX(sc, i); 1109 if (ds->ds_mbuf != NULL) { 1110 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1111 m_freem(ds->ds_mbuf); 1112 ds->ds_mbuf = NULL; 1113 } 1114 } 1115 1116 /* 1117 * Mark the interface down and cancel the watchdog timer. 1118 */ 1119 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1120 ifp->if_timer = 0; 1121 1122 if (disable) 1123 epic_rxdrain(sc); 1124 } 1125 1126 /* 1127 * Read the EPIC Serial EEPROM. 1128 */ 1129 void 1130 epic_read_eeprom(struct epic_softc *sc, int word, int wordcnt, uint16_t *data) 1131 { 1132 bus_space_tag_t st = sc->sc_st; 1133 bus_space_handle_t sh = sc->sc_sh; 1134 uint16_t reg; 1135 int i, x; 1136 1137 #define EEPROM_WAIT_READY(st, sh) \ 1138 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1139 /* nothing */ 1140 1141 /* 1142 * Enable the EEPROM. 1143 */ 1144 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1145 EEPROM_WAIT_READY(st, sh); 1146 1147 for (i = 0; i < wordcnt; i++) { 1148 /* Send CHIP SELECT for one clock tick. */ 1149 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1150 EEPROM_WAIT_READY(st, sh); 1151 1152 /* Shift in the READ opcode. */ 1153 for (x = 3; x > 0; x--) { 1154 reg = EECTL_ENABLE|EECTL_EECS; 1155 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1156 reg |= EECTL_EEDI; 1157 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1158 EEPROM_WAIT_READY(st, sh); 1159 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1160 EEPROM_WAIT_READY(st, sh); 1161 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1162 EEPROM_WAIT_READY(st, sh); 1163 } 1164 1165 /* Shift in address. */ 1166 for (x = 6; x > 0; x--) { 1167 reg = EECTL_ENABLE|EECTL_EECS; 1168 if ((word + i) & (1 << (x - 1))) 1169 reg |= EECTL_EEDI; 1170 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1171 EEPROM_WAIT_READY(st, sh); 1172 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1173 EEPROM_WAIT_READY(st, sh); 1174 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1175 EEPROM_WAIT_READY(st, sh); 1176 } 1177 1178 /* Shift out data. */ 1179 reg = EECTL_ENABLE|EECTL_EECS; 1180 data[i] = 0; 1181 for (x = 16; x > 0; x--) { 1182 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1183 EEPROM_WAIT_READY(st, sh); 1184 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1185 data[i] |= (1 << (x - 1)); 1186 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1187 EEPROM_WAIT_READY(st, sh); 1188 } 1189 1190 /* Clear CHIP SELECT. */ 1191 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1192 EEPROM_WAIT_READY(st, sh); 1193 } 1194 1195 /* 1196 * Disable the EEPROM. 1197 */ 1198 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1199 1200 #undef EEPROM_WAIT_READY 1201 } 1202 1203 /* 1204 * Add a receive buffer to the indicated descriptor. 1205 */ 1206 int 1207 epic_add_rxbuf(struct epic_softc *sc, int idx) 1208 { 1209 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1210 struct mbuf *m; 1211 int error; 1212 1213 MGETHDR(m, M_DONTWAIT, MT_DATA); 1214 if (m == NULL) 1215 return ENOBUFS; 1216 1217 MCLGET(m, M_DONTWAIT); 1218 if ((m->m_flags & M_EXT) == 0) { 1219 m_freem(m); 1220 return ENOBUFS; 1221 } 1222 1223 if (ds->ds_mbuf != NULL) 1224 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1225 1226 ds->ds_mbuf = m; 1227 1228 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1229 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1230 BUS_DMA_READ|BUS_DMA_NOWAIT); 1231 if (error) { 1232 printf("%s: can't load rx DMA map %d, error = %d\n", 1233 device_xname(sc->sc_dev), idx, error); 1234 panic("%s", __func__); /* XXX */ 1235 } 1236 1237 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1238 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1239 1240 EPIC_INIT_RXDESC(sc, idx); 1241 1242 return 0; 1243 } 1244 1245 /* 1246 * Set the EPIC multicast hash table. 1247 * 1248 * NOTE: We rely on a recently-updated mii_media_active here! 1249 */ 1250 void 1251 epic_set_mchash(struct epic_softc *sc) 1252 { 1253 struct ethercom *ec = &sc->sc_ethercom; 1254 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1255 struct ether_multi *enm; 1256 struct ether_multistep step; 1257 uint32_t hash, mchash[4]; 1258 1259 /* 1260 * Set up the multicast address filter by passing all multicast 1261 * addresses through a CRC generator, and then using the low-order 1262 * 6 bits as an index into the 64 bit multicast hash table (only 1263 * the lower 16 bits of each 32 bit multicast hash register are 1264 * valid). The high order bits select the register, while the 1265 * rest of the bits select the bit within the register. 1266 */ 1267 1268 if (ifp->if_flags & IFF_PROMISC) 1269 goto allmulti; 1270 1271 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1272 /* XXX hardware bug in 10Mbps mode. */ 1273 goto allmulti; 1274 } 1275 1276 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1277 1278 ETHER_FIRST_MULTI(step, ec, enm); 1279 while (enm != NULL) { 1280 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1281 /* 1282 * We must listen to a range of multicast addresses. 1283 * For now, just accept all multicasts, rather than 1284 * trying to set only those filter bits needed to match 1285 * the range. (At this time, the only use of address 1286 * ranges is for IP multicast routing, for which the 1287 * range is big enough to require all bits set.) 1288 */ 1289 goto allmulti; 1290 } 1291 1292 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1293 hash >>= 26; 1294 1295 /* Set the corresponding bit in the hash table. */ 1296 mchash[hash >> 4] |= 1 << (hash & 0xf); 1297 1298 ETHER_NEXT_MULTI(step, enm); 1299 } 1300 1301 ifp->if_flags &= ~IFF_ALLMULTI; 1302 goto sethash; 1303 1304 allmulti: 1305 ifp->if_flags |= IFF_ALLMULTI; 1306 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1307 1308 sethash: 1309 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1310 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1311 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1312 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1313 } 1314 1315 /* 1316 * Wait for the MII to become ready. 1317 */ 1318 int 1319 epic_mii_wait(struct epic_softc *sc, uint32_t rw) 1320 { 1321 int i; 1322 1323 for (i = 0; i < 50; i++) { 1324 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1325 == 0) 1326 break; 1327 delay(2); 1328 } 1329 if (i == 50) { 1330 printf("%s: MII timed out\n", device_xname(sc->sc_dev)); 1331 return 1; 1332 } 1333 1334 return 0; 1335 } 1336 1337 /* 1338 * Read from the MII. 1339 */ 1340 int 1341 epic_mii_read(device_t self, int phy, int reg) 1342 { 1343 struct epic_softc *sc = device_private(self); 1344 1345 if (epic_mii_wait(sc, MMCTL_WRITE)) 1346 return 0; 1347 1348 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1349 MMCTL_ARG(phy, reg, MMCTL_READ)); 1350 1351 if (epic_mii_wait(sc, MMCTL_READ)) 1352 return 0; 1353 1354 return bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) & 1355 MMDATA_MASK; 1356 } 1357 1358 /* 1359 * Write to the MII. 1360 */ 1361 void 1362 epic_mii_write(device_t self, int phy, int reg, int val) 1363 { 1364 struct epic_softc *sc = device_private(self); 1365 1366 if (epic_mii_wait(sc, MMCTL_WRITE)) 1367 return; 1368 1369 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1370 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1371 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1372 } 1373 1374 /* 1375 * Callback from PHY when media changes. 1376 */ 1377 void 1378 epic_statchg(struct ifnet *ifp) 1379 { 1380 struct epic_softc *sc = ifp->if_softc; 1381 uint32_t txcon, miicfg; 1382 1383 /* 1384 * Update loopback bits in TXCON to reflect duplex mode. 1385 */ 1386 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1387 if (sc->sc_mii.mii_media_active & IFM_FDX) 1388 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1389 else 1390 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1391 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1392 1393 /* On some cards we need manualy set fullduplex led */ 1394 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1395 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1396 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1397 miicfg |= MIICFG_ENABLE; 1398 else 1399 miicfg &= ~MIICFG_ENABLE; 1400 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1401 } 1402 1403 /* 1404 * There is a multicast filter bug in 10Mbps mode. Kick the 1405 * multicast filter in case the speed changed. 1406 */ 1407 epic_set_mchash(sc); 1408 } 1409 1410 /* 1411 * Callback from ifmedia to request new media setting. 1412 * 1413 * XXX Looks to me like some of this complexity should move into 1414 * XXX one or two custom PHY drivers. --dyoung 1415 */ 1416 int 1417 epic_mediachange(struct ifnet *ifp) 1418 { 1419 struct epic_softc *sc = ifp->if_softc; 1420 struct mii_data *mii = &sc->sc_mii; 1421 struct ifmedia *ifm = &mii->mii_media; 1422 int media = ifm->ifm_cur->ifm_media; 1423 uint32_t miicfg; 1424 struct mii_softc *miisc; 1425 int cfg, rc; 1426 1427 if ((ifp->if_flags & IFF_UP) == 0) 1428 return 0; 1429 1430 if (IFM_INST(media) != sc->sc_serinst) { 1431 /* If we're not selecting serial interface, select MII mode */ 1432 #ifdef EPICMEDIADEBUG 1433 printf("%s: parallel mode\n", ifp->if_xname); 1434 #endif 1435 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1436 miicfg &= ~MIICFG_SERMODEENA; 1437 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1438 } 1439 1440 if ((rc = mii_mediachg(mii)) == ENXIO) 1441 rc = 0; 1442 1443 if (IFM_INST(media) == sc->sc_serinst) { 1444 /* select serial interface */ 1445 #ifdef EPICMEDIADEBUG 1446 printf("%s: serial mode\n", ifp->if_xname); 1447 #endif 1448 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1449 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1450 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1451 1452 /* There is no driver to fill this */ 1453 mii->mii_media_active = media; 1454 mii->mii_media_status = 0; 1455 1456 epic_statchg(mii->mii_ifp); 1457 return 0; 1458 } 1459 1460 /* Lookup selected PHY */ 1461 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1462 if (IFM_INST(media) == miisc->mii_inst) 1463 break; 1464 } 1465 if (!miisc) { 1466 printf("%s: can't happen\n", __func__); /* ??? panic */ 1467 return 0; 1468 } 1469 #ifdef EPICMEDIADEBUG 1470 printf("%s: using phy %s\n", ifp->if_xname, 1471 device_xname(miisc->mii_dev)); 1472 #endif 1473 1474 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1475 /* XXX XXX assume it's a Level1 - should check */ 1476 1477 /* We have to powerup fiber transceivers */ 1478 cfg = PHY_READ(miisc, MII_LXTPHY_CONFIG); 1479 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1480 #ifdef EPICMEDIADEBUG 1481 printf("%s: power up fiber\n", ifp->if_xname); 1482 #endif 1483 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1484 } else { 1485 #ifdef EPICMEDIADEBUG 1486 printf("%s: power down fiber\n", ifp->if_xname); 1487 #endif 1488 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1489 } 1490 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1491 } 1492 1493 return rc; 1494 } 1495
Indexes created Tue Sep 23 21:09:50 GMT 2025