smc83c170.c revision 1.89
1 /* $NetBSD: smc83c170.c,v 1.89 2019/05/23 13:10:51 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the Standard Microsystems Corp. 83C170 35 * Ethernet PCI Integrated Controller (EPIC/100). 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.89 2019/05/23 13:10:51 msaitoh Exp $"); 40 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/miivar.h> 64 #include <dev/mii/lxtphyreg.h> 65 66 #include <dev/ic/smc83c170reg.h> 67 #include <dev/ic/smc83c170var.h> 68 69 void epic_start(struct ifnet *); 70 void epic_watchdog(struct ifnet *); 71 int epic_ioctl(struct ifnet *, u_long, void *); 72 int epic_init(struct ifnet *); 73 void epic_stop(struct ifnet *, int); 74 75 bool epic_shutdown(device_t, int); 76 77 void epic_reset(struct epic_softc *); 78 void epic_rxdrain(struct epic_softc *); 79 int epic_add_rxbuf(struct epic_softc *, int); 80 void epic_read_eeprom(struct epic_softc *, int, int, uint16_t *); 81 void epic_set_mchash(struct epic_softc *); 82 void epic_fixup_clock_source(struct epic_softc *); 83 int epic_mii_read(device_t, int, int, uint16_t *); 84 int epic_mii_write(device_t, int, int, uint16_t); 85 int epic_mii_wait(struct epic_softc *, uint32_t); 86 void epic_tick(void *); 87 88 void epic_statchg(struct ifnet *); 89 int epic_mediachange(struct ifnet *); 90 91 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 92 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 93 94 int epic_copy_small = 0; 95 96 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 97 98 /* 99 * Attach an EPIC interface to the system. 100 */ 101 void 102 epic_attach(struct epic_softc *sc) 103 { 104 bus_space_tag_t st = sc->sc_st; 105 bus_space_handle_t sh = sc->sc_sh; 106 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 107 struct mii_data * const mii = &sc->sc_mii; 108 int rseg, error, miiflags; 109 u_int i; 110 bus_dma_segment_t seg; 111 uint8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 112 uint16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 113 char *nullbuf; 114 115 callout_init(&sc->sc_mii_callout, 0); 116 117 /* 118 * Allocate the control data structures, and create and load the 119 * DMA map for it. 120 */ 121 if ((error = bus_dmamem_alloc(sc->sc_dmat, 122 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0, 123 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 124 aprint_error_dev(sc->sc_dev, 125 "unable to allocate control data, error = %d\n", error); 126 goto fail_0; 127 } 128 129 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 130 sizeof(struct epic_control_data) + ETHER_PAD_LEN, 131 (void **)&sc->sc_control_data, 132 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 133 aprint_error_dev(sc->sc_dev, 134 "unable to map control data, error = %d\n", error); 135 goto fail_1; 136 } 137 nullbuf = 138 (char *)sc->sc_control_data + sizeof(struct epic_control_data); 139 memset(nullbuf, 0, ETHER_PAD_LEN); 140 141 if ((error = bus_dmamap_create(sc->sc_dmat, 142 sizeof(struct epic_control_data), 1, 143 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 144 &sc->sc_cddmamap)) != 0) { 145 aprint_error_dev(sc->sc_dev, 146 "unable to create control data DMA map, error = %d\n", 147 error); 148 goto fail_2; 149 } 150 151 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 152 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 153 BUS_DMA_NOWAIT)) != 0) { 154 aprint_error_dev(sc->sc_dev, 155 "unable to load control data DMA map, error = %d\n", 156 error); 157 goto fail_3; 158 } 159 160 /* 161 * Create the transmit buffer DMA maps. 162 */ 163 for (i = 0; i < EPIC_NTXDESC; i++) { 164 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 165 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 166 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 167 aprint_error_dev(sc->sc_dev, 168 "unable to create tx DMA map %d, error = %d\n", 169 i, error); 170 goto fail_4; 171 } 172 } 173 174 /* 175 * Create the receive buffer DMA maps. 176 */ 177 for (i = 0; i < EPIC_NRXDESC; i++) { 178 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 179 MCLBYTES, 0, BUS_DMA_NOWAIT, 180 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 181 aprint_error_dev(sc->sc_dev, 182 "unable to create rx DMA map %d, error = %d\n", 183 i, error); 184 goto fail_5; 185 } 186 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 187 } 188 189 /* 190 * create and map the pad buffer 191 */ 192 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 193 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) { 194 aprint_error_dev(sc->sc_dev, 195 "unable to create pad buffer DMA map, error = %d\n", error); 196 goto fail_5; 197 } 198 199 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 200 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 201 aprint_error_dev(sc->sc_dev, 202 "unable to load pad buffer DMA map, error = %d\n", error); 203 goto fail_6; 204 } 205 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 206 BUS_DMASYNC_PREWRITE); 207 208 /* 209 * Bring the chip out of low-power mode and reset it to a known state. 210 */ 211 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 212 epic_reset(sc); 213 214 /* 215 * Read the Ethernet address from the EEPROM. 216 */ 217 epic_read_eeprom(sc, 0, __arraycount(myea), myea); 218 for (i = 0; i < __arraycount(myea); i++) { 219 enaddr[i * 2] = myea[i] & 0xff; 220 enaddr[i * 2 + 1] = myea[i] >> 8; 221 } 222 223 /* 224 * ...and the device name. 225 */ 226 epic_read_eeprom(sc, 0x2c, __arraycount(mydevname), mydevname); 227 for (i = 0; i < __arraycount(mydevname); i++) { 228 devname[i * 2] = mydevname[i] & 0xff; 229 devname[i * 2 + 1] = mydevname[i] >> 8; 230 } 231 232 devname[sizeof(mydevname)] = '\0'; 233 for (i = sizeof(mydevname) ; i > 0; i--) { 234 if (devname[i - 1] == ' ') 235 devname[i - 1] = '\0'; 236 else 237 break; 238 } 239 240 aprint_normal_dev(sc->sc_dev, "%s, Ethernet address %s\n", 241 devname, ether_sprintf(enaddr)); 242 243 miiflags = 0; 244 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 245 miiflags |= MIIF_HAVEFIBER; 246 247 /* 248 * Initialize our media structures and probe the MII. 249 */ 250 mii->mii_ifp = ifp; 251 mii->mii_readreg = epic_mii_read; 252 mii->mii_writereg = epic_mii_write; 253 mii->mii_statchg = epic_statchg; 254 255 sc->sc_ethercom.ec_mii = mii; 256 ifmedia_init(&mii->mii_media, IFM_IMASK, epic_mediachange, 257 ether_mediastatus); 258 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 259 MII_OFFSET_ANY, miiflags); 260 if (LIST_EMPTY(&mii->mii_phys)) { 261 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 262 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 263 } else 264 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 265 266 if (sc->sc_hwflags & EPIC_HAS_BNC) { 267 /* use the next free media instance */ 268 sc->sc_serinst = mii->mii_instance++; 269 ifmedia_add(&mii->mii_media, 270 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->sc_serinst), 271 0, NULL); 272 aprint_normal_dev(sc->sc_dev, "10base2/BNC\n"); 273 } else 274 sc->sc_serinst = -1; 275 276 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 277 ifp->if_softc = sc; 278 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 279 ifp->if_ioctl = epic_ioctl; 280 ifp->if_start = epic_start; 281 ifp->if_watchdog = epic_watchdog; 282 ifp->if_init = epic_init; 283 ifp->if_stop = epic_stop; 284 IFQ_SET_READY(&ifp->if_snd); 285 286 /* 287 * We can support 802.1Q VLAN-sized frames. 288 */ 289 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 290 291 /* 292 * Attach the interface. 293 */ 294 if_attach(ifp); 295 if_deferred_start_init(ifp, NULL); 296 ether_ifattach(ifp, enaddr); 297 298 /* 299 * Make sure the interface is shutdown during reboot. 300 */ 301 if (pmf_device_register1(sc->sc_dev, NULL, NULL, epic_shutdown)) 302 pmf_class_network_register(sc->sc_dev, ifp); 303 else 304 aprint_error_dev(sc->sc_dev, 305 "couldn't establish power handler\n"); 306 307 return; 308 309 /* 310 * Free any resources we've allocated during the failed attach 311 * attempt. Do this in reverse order and fall through. 312 */ 313 fail_6: 314 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 315 fail_5: 316 for (i = 0; i < EPIC_NRXDESC; i++) { 317 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 318 bus_dmamap_destroy(sc->sc_dmat, 319 EPIC_DSRX(sc, i)->ds_dmamap); 320 } 321 fail_4: 322 for (i = 0; i < EPIC_NTXDESC; i++) { 323 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 324 bus_dmamap_destroy(sc->sc_dmat, 325 EPIC_DSTX(sc, i)->ds_dmamap); 326 } 327 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 328 fail_3: 329 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 330 fail_2: 331 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 332 sizeof(struct epic_control_data)); 333 fail_1: 334 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 335 fail_0: 336 return; 337 } 338 339 /* 340 * Shutdown hook. Make sure the interface is stopped at reboot. 341 */ 342 bool 343 epic_shutdown(device_t self, int howto) 344 { 345 struct epic_softc *sc = device_private(self); 346 347 epic_stop(&sc->sc_ethercom.ec_if, 1); 348 349 return true; 350 } 351 352 /* 353 * Start packet transmission on the interface. 354 * [ifnet interface function] 355 */ 356 void 357 epic_start(struct ifnet *ifp) 358 { 359 struct epic_softc *sc = ifp->if_softc; 360 struct mbuf *m0, *m; 361 struct epic_txdesc *txd; 362 struct epic_descsoft *ds; 363 struct epic_fraglist *fr; 364 bus_dmamap_t dmamap; 365 int error, firsttx, nexttx, opending, seg; 366 u_int len; 367 368 /* 369 * Remember the previous txpending and the first transmit 370 * descriptor we use. 371 */ 372 opending = sc->sc_txpending; 373 firsttx = EPIC_NEXTTX(sc->sc_txlast); 374 375 /* 376 * Loop through the send queue, setting up transmit descriptors 377 * until we drain the queue, or use up all available transmit 378 * descriptors. 379 */ 380 while (sc->sc_txpending < EPIC_NTXDESC) { 381 /* 382 * Grab a packet off the queue. 383 */ 384 IFQ_POLL(&ifp->if_snd, m0); 385 if (m0 == NULL) 386 break; 387 m = NULL; 388 389 /* 390 * Get the last and next available transmit descriptor. 391 */ 392 nexttx = EPIC_NEXTTX(sc->sc_txlast); 393 txd = EPIC_CDTX(sc, nexttx); 394 fr = EPIC_CDFL(sc, nexttx); 395 ds = EPIC_DSTX(sc, nexttx); 396 dmamap = ds->ds_dmamap; 397 398 /* 399 * Load the DMA map. If this fails, the packet either 400 * didn't fit in the alloted number of frags, or we were 401 * short on resources. In this case, we'll copy and try 402 * again. 403 */ 404 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 405 BUS_DMA_WRITE | BUS_DMA_NOWAIT)) != 0 || 406 (m0->m_pkthdr.len < ETHER_PAD_LEN && 407 dmamap-> dm_nsegs == EPIC_NFRAGS)) { 408 if (error == 0) 409 bus_dmamap_unload(sc->sc_dmat, dmamap); 410 411 MGETHDR(m, M_DONTWAIT, MT_DATA); 412 if (m == NULL) { 413 printf("%s: unable to allocate Tx mbuf\n", 414 device_xname(sc->sc_dev)); 415 break; 416 } 417 if (m0->m_pkthdr.len > MHLEN) { 418 MCLGET(m, M_DONTWAIT); 419 if ((m->m_flags & M_EXT) == 0) { 420 printf("%s: unable to allocate Tx " 421 "cluster\n", 422 device_xname(sc->sc_dev)); 423 m_freem(m); 424 break; 425 } 426 } 427 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 428 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 429 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 430 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 431 if (error) { 432 printf("%s: unable to load Tx buffer, " 433 "error = %d\n", device_xname(sc->sc_dev), 434 error); 435 break; 436 } 437 } 438 IFQ_DEQUEUE(&ifp->if_snd, m0); 439 if (m != NULL) { 440 m_freem(m0); 441 m0 = m; 442 } 443 444 /* Initialize the fraglist. */ 445 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 446 fr->ef_frags[seg].ef_addr = 447 dmamap->dm_segs[seg].ds_addr; 448 fr->ef_frags[seg].ef_length = 449 dmamap->dm_segs[seg].ds_len; 450 } 451 len = m0->m_pkthdr.len; 452 if (len < ETHER_PAD_LEN) { 453 fr->ef_frags[seg].ef_addr = sc->sc_nulldma; 454 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len; 455 len = ETHER_PAD_LEN; 456 seg++; 457 } 458 fr->ef_nfrags = seg; 459 460 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 461 462 /* Sync the DMA map. */ 463 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 464 BUS_DMASYNC_PREWRITE); 465 466 /* 467 * Store a pointer to the packet so we can free it later. 468 */ 469 ds->ds_mbuf = m0; 470 471 /* 472 * Fill in the transmit descriptor. 473 */ 474 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 475 476 /* 477 * If this is the first descriptor we're enqueueing, 478 * don't give it to the EPIC yet. That could cause 479 * a race condition. We'll do it below. 480 */ 481 if (nexttx == firsttx) 482 txd->et_txstatus = TXSTAT_TXLENGTH(len); 483 else 484 txd->et_txstatus = 485 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER; 486 487 EPIC_CDTXSYNC(sc, nexttx, 488 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 489 490 /* Advance the tx pointer. */ 491 sc->sc_txpending++; 492 sc->sc_txlast = nexttx; 493 494 /* 495 * Pass the packet to any BPF listeners. 496 */ 497 bpf_mtap(ifp, m0, BPF_D_OUT); 498 } 499 500 if (sc->sc_txpending == EPIC_NTXDESC) { 501 /* No more slots left; notify upper layer. */ 502 ifp->if_flags |= IFF_OACTIVE; 503 } 504 505 if (sc->sc_txpending != opending) { 506 /* 507 * We enqueued packets. If the transmitter was idle, 508 * reset the txdirty pointer. 509 */ 510 if (opending == 0) 511 sc->sc_txdirty = firsttx; 512 513 /* 514 * Cause a transmit interrupt to happen on the 515 * last packet we enqueued. 516 */ 517 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 518 EPIC_CDTXSYNC(sc, sc->sc_txlast, 519 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 520 521 /* 522 * The entire packet chain is set up. Give the 523 * first descriptor to the EPIC now. 524 */ 525 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER; 526 EPIC_CDTXSYNC(sc, firsttx, 527 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 528 529 /* Start the transmitter. */ 530 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 531 COMMAND_TXQUEUED); 532 533 /* Set a watchdog timer in case the chip flakes out. */ 534 ifp->if_timer = 5; 535 } 536 } 537 538 /* 539 * Watchdog timer handler. 540 * [ifnet interface function] 541 */ 542 void 543 epic_watchdog(struct ifnet *ifp) 544 { 545 struct epic_softc *sc = ifp->if_softc; 546 547 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 548 ifp->if_oerrors++; 549 550 (void)epic_init(ifp); 551 } 552 553 /* 554 * Handle control requests from the operator. 555 * [ifnet interface function] 556 */ 557 int 558 epic_ioctl(struct ifnet *ifp, u_long cmd, void *data) 559 { 560 struct epic_softc *sc = ifp->if_softc; 561 int s, error; 562 563 s = splnet(); 564 565 error = ether_ioctl(ifp, cmd, data); 566 if (error == ENETRESET) { 567 /* 568 * Multicast list has changed; set the hardware filter 569 * accordingly. Update our idea of the current media; 570 * epic_set_mchash() needs to know what it is. 571 */ 572 if (ifp->if_flags & IFF_RUNNING) { 573 mii_pollstat(&sc->sc_mii); 574 epic_set_mchash(sc); 575 } 576 error = 0; 577 } 578 579 splx(s); 580 return error; 581 } 582 583 /* 584 * Interrupt handler. 585 */ 586 int 587 epic_intr(void *arg) 588 { 589 struct epic_softc *sc = arg; 590 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 591 struct epic_rxdesc *rxd; 592 struct epic_txdesc *txd; 593 struct epic_descsoft *ds; 594 struct mbuf *m; 595 uint32_t intstat, rxstatus, txstatus; 596 int i, claimed = 0; 597 u_int len; 598 599 top: 600 /* 601 * Get the interrupt status from the EPIC. 602 */ 603 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 604 if ((intstat & INTSTAT_INT_ACTV) == 0) 605 return claimed; 606 607 claimed = 1; 608 609 /* 610 * Acknowledge the interrupt. 611 */ 612 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 613 intstat & INTMASK); 614 615 /* 616 * Check for receive interrupts. 617 */ 618 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 619 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 620 rxd = EPIC_CDRX(sc, i); 621 ds = EPIC_DSRX(sc, i); 622 623 EPIC_CDRXSYNC(sc, i, 624 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 625 626 rxstatus = rxd->er_rxstatus; 627 if (rxstatus & ER_RXSTAT_OWNER) { 628 /* 629 * We have processed all of the 630 * receive buffers. 631 */ 632 break; 633 } 634 635 /* 636 * Make sure the packet arrived intact. If an error 637 * occurred, update stats and reset the descriptor. 638 * The buffer will be reused the next time the 639 * descriptor comes up in the ring. 640 */ 641 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 642 if (rxstatus & ER_RXSTAT_CRCERROR) 643 printf("%s: CRC error\n", 644 device_xname(sc->sc_dev)); 645 if (rxstatus & ER_RXSTAT_ALIGNERROR) 646 printf("%s: alignment error\n", 647 device_xname(sc->sc_dev)); 648 ifp->if_ierrors++; 649 EPIC_INIT_RXDESC(sc, i); 650 continue; 651 } 652 653 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 654 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 655 656 /* 657 * The EPIC includes the CRC with every packet; 658 * trim it. 659 */ 660 len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN; 661 662 if (len < sizeof(struct ether_header)) { 663 /* 664 * Runt packet; drop it now. 665 */ 666 ifp->if_ierrors++; 667 EPIC_INIT_RXDESC(sc, i); 668 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 669 ds->ds_dmamap->dm_mapsize, 670 BUS_DMASYNC_PREREAD); 671 continue; 672 } 673 674 /* 675 * If the packet is small enough to fit in a 676 * single header mbuf, allocate one and copy 677 * the data into it. This greatly reduces 678 * memory consumption when we receive lots 679 * of small packets. 680 * 681 * Otherwise, we add a new buffer to the receive 682 * chain. If this fails, we drop the packet and 683 * recycle the old buffer. 684 */ 685 if (epic_copy_small != 0 && len <= MHLEN) { 686 MGETHDR(m, M_DONTWAIT, MT_DATA); 687 if (m == NULL) 688 goto dropit; 689 memcpy(mtod(m, void *), 690 mtod(ds->ds_mbuf, void *), len); 691 EPIC_INIT_RXDESC(sc, i); 692 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 693 ds->ds_dmamap->dm_mapsize, 694 BUS_DMASYNC_PREREAD); 695 } else { 696 m = ds->ds_mbuf; 697 if (epic_add_rxbuf(sc, i) != 0) { 698 dropit: 699 ifp->if_ierrors++; 700 EPIC_INIT_RXDESC(sc, i); 701 bus_dmamap_sync(sc->sc_dmat, 702 ds->ds_dmamap, 0, 703 ds->ds_dmamap->dm_mapsize, 704 BUS_DMASYNC_PREREAD); 705 continue; 706 } 707 } 708 709 m_set_rcvif(m, ifp); 710 m->m_pkthdr.len = m->m_len = len; 711 712 /* Pass it on. */ 713 if_percpuq_enqueue(ifp->if_percpuq, m); 714 } 715 716 /* Update the receive pointer. */ 717 sc->sc_rxptr = i; 718 719 /* 720 * Check for receive queue underflow. 721 */ 722 if (intstat & INTSTAT_RQE) { 723 printf("%s: receiver queue empty\n", 724 device_xname(sc->sc_dev)); 725 /* 726 * Ring is already built; just restart the 727 * receiver. 728 */ 729 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 730 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 731 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 732 COMMAND_RXQUEUED | COMMAND_START_RX); 733 } 734 } 735 736 /* 737 * Check for transmission complete interrupts. 738 */ 739 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 740 ifp->if_flags &= ~IFF_OACTIVE; 741 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 742 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 743 txd = EPIC_CDTX(sc, i); 744 ds = EPIC_DSTX(sc, i); 745 746 EPIC_CDTXSYNC(sc, i, 747 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 748 749 txstatus = txd->et_txstatus; 750 if (txstatus & ET_TXSTAT_OWNER) 751 break; 752 753 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 754 755 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 756 0, ds->ds_dmamap->dm_mapsize, 757 BUS_DMASYNC_POSTWRITE); 758 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 759 m_freem(ds->ds_mbuf); 760 ds->ds_mbuf = NULL; 761 762 /* 763 * Check for errors and collisions. 764 */ 765 if ((txstatus & ET_TXSTAT_PACKETTX) == 0) 766 ifp->if_oerrors++; 767 else 768 ifp->if_opackets++; 769 ifp->if_collisions += 770 TXSTAT_COLLISIONS(txstatus); 771 if (txstatus & ET_TXSTAT_CARSENSELOST) 772 printf("%s: lost carrier\n", 773 device_xname(sc->sc_dev)); 774 } 775 776 /* Update the dirty transmit buffer pointer. */ 777 sc->sc_txdirty = i; 778 779 /* 780 * Cancel the watchdog timer if there are no pending 781 * transmissions. 782 */ 783 if (sc->sc_txpending == 0) 784 ifp->if_timer = 0; 785 786 /* 787 * Kick the transmitter after a DMA underrun. 788 */ 789 if (intstat & INTSTAT_TXU) { 790 printf("%s: transmit underrun\n", 791 device_xname(sc->sc_dev)); 792 bus_space_write_4(sc->sc_st, sc->sc_sh, 793 EPIC_COMMAND, COMMAND_TXUGO); 794 if (sc->sc_txpending) 795 bus_space_write_4(sc->sc_st, sc->sc_sh, 796 EPIC_COMMAND, COMMAND_TXQUEUED); 797 } 798 799 /* 800 * Try to get more packets going. 801 */ 802 if_schedule_deferred_start(ifp); 803 } 804 805 /* 806 * Check for fatal interrupts. 807 */ 808 if (intstat & INTSTAT_FATAL_INT) { 809 if (intstat & INTSTAT_PTA) 810 printf("%s: PCI target abort error\n", 811 device_xname(sc->sc_dev)); 812 else if (intstat & INTSTAT_PMA) 813 printf("%s: PCI master abort error\n", 814 device_xname(sc->sc_dev)); 815 else if (intstat & INTSTAT_APE) 816 printf("%s: PCI address parity error\n", 817 device_xname(sc->sc_dev)); 818 else if (intstat & INTSTAT_DPE) 819 printf("%s: PCI data parity error\n", 820 device_xname(sc->sc_dev)); 821 else 822 printf("%s: unknown fatal error\n", 823 device_xname(sc->sc_dev)); 824 (void)epic_init(ifp); 825 } 826 827 /* 828 * Check for more interrupts. 829 */ 830 goto top; 831 } 832 833 /* 834 * One second timer, used to tick the MII. 835 */ 836 void 837 epic_tick(void *arg) 838 { 839 struct epic_softc *sc = arg; 840 int s; 841 842 s = splnet(); 843 mii_tick(&sc->sc_mii); 844 splx(s); 845 846 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 847 } 848 849 /* 850 * Fixup the clock source on the EPIC. 851 */ 852 void 853 epic_fixup_clock_source(struct epic_softc *sc) 854 { 855 int i; 856 857 /* 858 * According to SMC Application Note 7-15, the EPIC's clock 859 * source is incorrect following a reset. This manifests itself 860 * as failure to recognize when host software has written to 861 * a register on the EPIC. The appnote recommends issuing at 862 * least 16 consecutive writes to the CLOCK TEST bit to correctly 863 * configure the clock source. 864 */ 865 for (i = 0; i < 16; i++) 866 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 867 TEST_CLOCKTEST); 868 } 869 870 /* 871 * Perform a soft reset on the EPIC. 872 */ 873 void 874 epic_reset(struct epic_softc *sc) 875 { 876 877 epic_fixup_clock_source(sc); 878 879 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 880 delay(100); 881 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 882 delay(100); 883 884 epic_fixup_clock_source(sc); 885 } 886 887 /* 888 * Initialize the interface. Must be called at splnet(). 889 */ 890 int 891 epic_init(struct ifnet *ifp) 892 { 893 struct epic_softc *sc = ifp->if_softc; 894 bus_space_tag_t st = sc->sc_st; 895 bus_space_handle_t sh = sc->sc_sh; 896 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 897 struct epic_txdesc *txd; 898 struct epic_descsoft *ds; 899 uint32_t genctl, reg0; 900 int i, error = 0; 901 902 /* 903 * Cancel any pending I/O. 904 */ 905 epic_stop(ifp, 0); 906 907 /* 908 * Reset the EPIC to a known state. 909 */ 910 epic_reset(sc); 911 912 /* 913 * Magical mystery initialization. 914 */ 915 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 916 917 /* 918 * Initialize the EPIC genctl register: 919 * 920 * - 64 byte receive FIFO threshold 921 * - automatic advance to next receive frame 922 */ 923 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 924 #if BYTE_ORDER == BIG_ENDIAN 925 genctl |= GENCTL_BIG_ENDIAN; 926 #endif 927 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 928 929 /* 930 * Reset the MII bus and PHY. 931 */ 932 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 933 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 934 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 935 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 936 delay(100); 937 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 938 delay(1000); 939 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 940 941 /* 942 * Initialize Ethernet address. 943 */ 944 reg0 = enaddr[1] << 8 | enaddr[0]; 945 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 946 reg0 = enaddr[3] << 8 | enaddr[2]; 947 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 948 reg0 = enaddr[5] << 8 | enaddr[4]; 949 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 950 951 /* 952 * Initialize receive control. Remember the external buffer 953 * size setting. 954 */ 955 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 956 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 957 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 958 if (ifp->if_flags & IFF_PROMISC) 959 reg0 |= RXCON_PROMISCMODE; 960 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 961 962 /* Set the current media. */ 963 if ((error = epic_mediachange(ifp)) != 0) 964 goto out; 965 966 /* Set up the multicast hash table. */ 967 epic_set_mchash(sc); 968 969 /* 970 * Initialize the transmit descriptor ring. txlast is initialized 971 * to the end of the list so that it will wrap around to the first 972 * descriptor when the first packet is transmitted. 973 */ 974 for (i = 0; i < EPIC_NTXDESC; i++) { 975 txd = EPIC_CDTX(sc, i); 976 memset(txd, 0, sizeof(struct epic_txdesc)); 977 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 978 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 979 EPIC_CDTXSYNC(sc, i, 980 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 981 } 982 sc->sc_txpending = 0; 983 sc->sc_txdirty = 0; 984 sc->sc_txlast = EPIC_NTXDESC - 1; 985 986 /* 987 * Initialize the receive descriptor ring. 988 */ 989 for (i = 0; i < EPIC_NRXDESC; i++) { 990 ds = EPIC_DSRX(sc, i); 991 if (ds->ds_mbuf == NULL) { 992 if ((error = epic_add_rxbuf(sc, i)) != 0) { 993 printf("%s: unable to allocate or map rx " 994 "buffer %d error = %d\n", 995 device_xname(sc->sc_dev), i, error); 996 /* 997 * XXX Should attempt to run with fewer receive 998 * XXX buffers instead of just failing. 999 */ 1000 epic_rxdrain(sc); 1001 goto out; 1002 } 1003 } else 1004 EPIC_INIT_RXDESC(sc, i); 1005 } 1006 sc->sc_rxptr = 0; 1007 1008 /* 1009 * Initialize the interrupt mask and enable interrupts. 1010 */ 1011 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1012 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1013 1014 /* 1015 * Give the transmit and receive rings to the EPIC. 1016 */ 1017 bus_space_write_4(st, sh, EPIC_PTCDAR, 1018 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1019 bus_space_write_4(st, sh, EPIC_PRCDAR, 1020 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1021 1022 /* 1023 * Set the EPIC in motion. 1024 */ 1025 bus_space_write_4(st, sh, EPIC_COMMAND, 1026 COMMAND_RXQUEUED | COMMAND_START_RX); 1027 1028 /* 1029 * ...all done! 1030 */ 1031 ifp->if_flags |= IFF_RUNNING; 1032 ifp->if_flags &= ~IFF_OACTIVE; 1033 1034 /* 1035 * Start the one second clock. 1036 */ 1037 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 1038 1039 /* 1040 * Attempt to start output on the interface. 1041 */ 1042 epic_start(ifp); 1043 1044 out: 1045 if (error) 1046 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1047 return error; 1048 } 1049 1050 /* 1051 * Drain the receive queue. 1052 */ 1053 void 1054 epic_rxdrain(struct epic_softc *sc) 1055 { 1056 struct epic_descsoft *ds; 1057 int i; 1058 1059 for (i = 0; i < EPIC_NRXDESC; i++) { 1060 ds = EPIC_DSRX(sc, i); 1061 if (ds->ds_mbuf != NULL) { 1062 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1063 m_freem(ds->ds_mbuf); 1064 ds->ds_mbuf = NULL; 1065 } 1066 } 1067 } 1068 1069 /* 1070 * Stop transmission on the interface. 1071 */ 1072 void 1073 epic_stop(struct ifnet *ifp, int disable) 1074 { 1075 struct epic_softc *sc = ifp->if_softc; 1076 bus_space_tag_t st = sc->sc_st; 1077 bus_space_handle_t sh = sc->sc_sh; 1078 struct epic_descsoft *ds; 1079 uint32_t reg; 1080 int i; 1081 1082 /* 1083 * Stop the one second clock. 1084 */ 1085 callout_stop(&sc->sc_mii_callout); 1086 1087 /* Down the MII. */ 1088 mii_down(&sc->sc_mii); 1089 1090 /* Paranoia... */ 1091 epic_fixup_clock_source(sc); 1092 1093 /* 1094 * Disable interrupts. 1095 */ 1096 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1097 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1098 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1099 1100 /* 1101 * Stop the DMA engine and take the receiver off-line. 1102 */ 1103 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1104 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1105 1106 /* 1107 * Release any queued transmit buffers. 1108 */ 1109 for (i = 0; i < EPIC_NTXDESC; i++) { 1110 ds = EPIC_DSTX(sc, i); 1111 if (ds->ds_mbuf != NULL) { 1112 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1113 m_freem(ds->ds_mbuf); 1114 ds->ds_mbuf = NULL; 1115 } 1116 } 1117 1118 /* 1119 * Mark the interface down and cancel the watchdog timer. 1120 */ 1121 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1122 ifp->if_timer = 0; 1123 1124 if (disable) 1125 epic_rxdrain(sc); 1126 } 1127 1128 /* 1129 * Read the EPIC Serial EEPROM. 1130 */ 1131 void 1132 epic_read_eeprom(struct epic_softc *sc, int word, int wordcnt, uint16_t *data) 1133 { 1134 bus_space_tag_t st = sc->sc_st; 1135 bus_space_handle_t sh = sc->sc_sh; 1136 uint16_t reg; 1137 int i, x; 1138 1139 #define EEPROM_WAIT_READY(st, sh) \ 1140 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1141 /* nothing */ 1142 1143 /* 1144 * Enable the EEPROM. 1145 */ 1146 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1147 EEPROM_WAIT_READY(st, sh); 1148 1149 for (i = 0; i < wordcnt; i++) { 1150 /* Send CHIP SELECT for one clock tick. */ 1151 bus_space_write_4(st, sh, EPIC_EECTL, 1152 EECTL_ENABLE | EECTL_EECS); 1153 EEPROM_WAIT_READY(st, sh); 1154 1155 /* Shift in the READ opcode. */ 1156 for (x = 3; x > 0; x--) { 1157 reg = EECTL_ENABLE | EECTL_EECS; 1158 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1159 reg |= EECTL_EEDI; 1160 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1161 EEPROM_WAIT_READY(st, sh); 1162 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1163 EEPROM_WAIT_READY(st, sh); 1164 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1165 EEPROM_WAIT_READY(st, sh); 1166 } 1167 1168 /* Shift in address. */ 1169 for (x = 6; x > 0; x--) { 1170 reg = EECTL_ENABLE | EECTL_EECS; 1171 if ((word + i) & (1 << (x - 1))) 1172 reg |= EECTL_EEDI; 1173 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1174 EEPROM_WAIT_READY(st, sh); 1175 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1176 EEPROM_WAIT_READY(st, sh); 1177 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1178 EEPROM_WAIT_READY(st, sh); 1179 } 1180 1181 /* Shift out data. */ 1182 reg = EECTL_ENABLE | EECTL_EECS; 1183 data[i] = 0; 1184 for (x = 16; x > 0; x--) { 1185 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1186 EEPROM_WAIT_READY(st, sh); 1187 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1188 data[i] |= (1 << (x - 1)); 1189 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1190 EEPROM_WAIT_READY(st, sh); 1191 } 1192 1193 /* Clear CHIP SELECT. */ 1194 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1195 EEPROM_WAIT_READY(st, sh); 1196 } 1197 1198 /* 1199 * Disable the EEPROM. 1200 */ 1201 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1202 1203 #undef EEPROM_WAIT_READY 1204 } 1205 1206 /* 1207 * Add a receive buffer to the indicated descriptor. 1208 */ 1209 int 1210 epic_add_rxbuf(struct epic_softc *sc, int idx) 1211 { 1212 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1213 struct mbuf *m; 1214 int error; 1215 1216 MGETHDR(m, M_DONTWAIT, MT_DATA); 1217 if (m == NULL) 1218 return ENOBUFS; 1219 1220 MCLGET(m, M_DONTWAIT); 1221 if ((m->m_flags & M_EXT) == 0) { 1222 m_freem(m); 1223 return ENOBUFS; 1224 } 1225 1226 if (ds->ds_mbuf != NULL) 1227 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1228 1229 ds->ds_mbuf = m; 1230 1231 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1232 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1233 BUS_DMA_READ | BUS_DMA_NOWAIT); 1234 if (error) { 1235 printf("%s: can't load rx DMA map %d, error = %d\n", 1236 device_xname(sc->sc_dev), idx, error); 1237 panic("%s", __func__); /* XXX */ 1238 } 1239 1240 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1241 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1242 1243 EPIC_INIT_RXDESC(sc, idx); 1244 1245 return 0; 1246 } 1247 1248 /* 1249 * Set the EPIC multicast hash table. 1250 * 1251 * NOTE: We rely on a recently-updated mii_media_active here! 1252 */ 1253 void 1254 epic_set_mchash(struct epic_softc *sc) 1255 { 1256 struct ethercom *ec = &sc->sc_ethercom; 1257 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1258 struct ether_multi *enm; 1259 struct ether_multistep step; 1260 uint32_t hash, mchash[4]; 1261 1262 /* 1263 * Set up the multicast address filter by passing all multicast 1264 * addresses through a CRC generator, and then using the low-order 1265 * 6 bits as an index into the 64 bit multicast hash table (only 1266 * the lower 16 bits of each 32 bit multicast hash register are 1267 * valid). The high order bits select the register, while the 1268 * rest of the bits select the bit within the register. 1269 */ 1270 1271 if (ifp->if_flags & IFF_PROMISC) 1272 goto allmulti; 1273 1274 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1275 /* XXX hardware bug in 10Mbps mode. */ 1276 goto allmulti; 1277 } 1278 1279 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1280 1281 ETHER_FIRST_MULTI(step, ec, enm); 1282 while (enm != NULL) { 1283 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1284 /* 1285 * We must listen to a range of multicast addresses. 1286 * For now, just accept all multicasts, rather than 1287 * trying to set only those filter bits needed to match 1288 * the range. (At this time, the only use of address 1289 * ranges is for IP multicast routing, for which the 1290 * range is big enough to require all bits set.) 1291 */ 1292 goto allmulti; 1293 } 1294 1295 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1296 hash >>= 26; 1297 1298 /* Set the corresponding bit in the hash table. */ 1299 mchash[hash >> 4] |= 1 << (hash & 0xf); 1300 1301 ETHER_NEXT_MULTI(step, enm); 1302 } 1303 1304 ifp->if_flags &= ~IFF_ALLMULTI; 1305 goto sethash; 1306 1307 allmulti: 1308 ifp->if_flags |= IFF_ALLMULTI; 1309 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1310 1311 sethash: 1312 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1313 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1314 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1315 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1316 } 1317 1318 /* 1319 * Wait for the MII to become ready. 1320 */ 1321 int 1322 epic_mii_wait(struct epic_softc *sc, uint32_t rw) 1323 { 1324 int i; 1325 1326 for (i = 0; i < 50; i++) { 1327 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1328 == 0) 1329 break; 1330 delay(2); 1331 } 1332 if (i == 50) { 1333 printf("%s: MII timed out\n", device_xname(sc->sc_dev)); 1334 return ETIMEDOUT; 1335 } 1336 1337 return 0; 1338 } 1339 1340 /* 1341 * Read from the MII. 1342 */ 1343 int 1344 epic_mii_read(device_t self, int phy, int reg, uint16_t *val) 1345 { 1346 struct epic_softc *sc = device_private(self); 1347 int rv; 1348 1349 if ((rv = epic_mii_wait(sc, MMCTL_WRITE)) != 0) 1350 return rv; 1351 1352 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1353 MMCTL_ARG(phy, reg, MMCTL_READ)); 1354 1355 if ((rv = epic_mii_wait(sc, MMCTL_READ)) != 0) 1356 return rv; 1357 1358 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) 1359 & MMDATA_MASK; 1360 return 0; 1361 } 1362 1363 /* 1364 * Write to the MII. 1365 */ 1366 int 1367 epic_mii_write(device_t self, int phy, int reg, uint16_t val) 1368 { 1369 struct epic_softc *sc = device_private(self); 1370 int rv; 1371 1372 if ((rv = epic_mii_wait(sc, MMCTL_WRITE)) != 0) 1373 return rv; 1374 1375 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1376 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1377 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1378 1379 return 0; 1380 } 1381 1382 /* 1383 * Callback from PHY when media changes. 1384 */ 1385 void 1386 epic_statchg(struct ifnet *ifp) 1387 { 1388 struct epic_softc *sc = ifp->if_softc; 1389 uint32_t txcon, miicfg; 1390 1391 /* 1392 * Update loopback bits in TXCON to reflect duplex mode. 1393 */ 1394 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1395 if (sc->sc_mii.mii_media_active & IFM_FDX) 1396 txcon |= (TXCON_LOOPBACK_D1 | TXCON_LOOPBACK_D2); 1397 else 1398 txcon &= ~(TXCON_LOOPBACK_D1 | TXCON_LOOPBACK_D2); 1399 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1400 1401 /* On some cards we need manualy set fullduplex led */ 1402 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1403 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1404 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1405 miicfg |= MIICFG_ENABLE; 1406 else 1407 miicfg &= ~MIICFG_ENABLE; 1408 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1409 } 1410 1411 /* 1412 * There is a multicast filter bug in 10Mbps mode. Kick the 1413 * multicast filter in case the speed changed. 1414 */ 1415 epic_set_mchash(sc); 1416 } 1417 1418 /* 1419 * Callback from ifmedia to request new media setting. 1420 * 1421 * XXX Looks to me like some of this complexity should move into 1422 * XXX one or two custom PHY drivers. --dyoung 1423 */ 1424 int 1425 epic_mediachange(struct ifnet *ifp) 1426 { 1427 struct epic_softc *sc = ifp->if_softc; 1428 struct mii_data *mii = &sc->sc_mii; 1429 struct ifmedia *ifm = &mii->mii_media; 1430 int media = ifm->ifm_cur->ifm_media; 1431 uint32_t miicfg; 1432 struct mii_softc *miisc; 1433 int rc; 1434 uint16_t cfg; 1435 1436 if ((ifp->if_flags & IFF_UP) == 0) 1437 return 0; 1438 1439 if (IFM_INST(media) != sc->sc_serinst) { 1440 /* If we're not selecting serial interface, select MII mode */ 1441 #ifdef EPICMEDIADEBUG 1442 printf("%s: parallel mode\n", ifp->if_xname); 1443 #endif 1444 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1445 miicfg &= ~MIICFG_SERMODEENA; 1446 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1447 } 1448 1449 if ((rc = mii_mediachg(mii)) == ENXIO) 1450 rc = 0; 1451 1452 if (IFM_INST(media) == sc->sc_serinst) { 1453 /* select serial interface */ 1454 #ifdef EPICMEDIADEBUG 1455 printf("%s: serial mode\n", ifp->if_xname); 1456 #endif 1457 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1458 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1459 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1460 1461 /* There is no driver to fill this */ 1462 mii->mii_media_active = media; 1463 mii->mii_media_status = 0; 1464 1465 epic_statchg(mii->mii_ifp); 1466 return 0; 1467 } 1468 1469 /* Lookup selected PHY */ 1470 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1471 if (IFM_INST(media) == miisc->mii_inst) 1472 break; 1473 } 1474 if (!miisc) { 1475 printf("%s: can't happen\n", __func__); /* ??? panic */ 1476 return 0; 1477 } 1478 #ifdef EPICMEDIADEBUG 1479 printf("%s: using phy %s\n", ifp->if_xname, 1480 device_xname(miisc->mii_dev)); 1481 #endif 1482 1483 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1484 /* XXX XXX assume it's a Level1 - should check */ 1485 1486 /* We have to powerup fiber transceivers */ 1487 PHY_READ(miisc, MII_LXTPHY_CONFIG, &cfg); 1488 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1489 #ifdef EPICMEDIADEBUG 1490 printf("%s: power up fiber\n", ifp->if_xname); 1491 #endif 1492 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1493 } else { 1494 #ifdef EPICMEDIADEBUG 1495 printf("%s: power down fiber\n", ifp->if_xname); 1496 #endif 1497 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1498 } 1499 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1500 } 1501 1502 return rc; 1503 } 1504
Indexes created Fri Sep 26 08:10:20 GMT 2025