smc83c170.c revision 1.9.4.1
1 /* $NetBSD: smc83c170.c,v 1.9.4.1 1998/12/11 04:53:00 kenh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Device driver for the Standard Microsystems Corp. 83C170 42 * Ethernet PCI Integrated Controller (EPIC/100). 43 */ 44 45 #include "opt_inet.h" 46 #include "opt_ns.h" 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #endif 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 73 #ifdef NS 74 #include <netns/ns.h> 75 #include <netns/ns_if.h> 76 #endif 77 78 #include <machine/bus.h> 79 #include <machine/intr.h> 80 81 #include <dev/mii/miivar.h> 82 83 #include <dev/ic/smc83c170reg.h> 84 #include <dev/ic/smc83c170var.h> 85 86 void epic_start __P((struct ifnet *)); 87 void epic_watchdog __P((struct ifnet *)); 88 int epic_ioctl __P((struct ifnet *, u_long, caddr_t)); 89 90 void epic_shutdown __P((void *)); 91 92 void epic_reset __P((struct epic_softc *)); 93 void epic_init __P((struct epic_softc *)); 94 void epic_stop __P((struct epic_softc *)); 95 int epic_add_rxbuf __P((struct epic_softc *, int)); 96 void epic_read_eeprom __P((struct epic_softc *, int, int, u_int16_t *)); 97 void epic_set_mchash __P((struct epic_softc *)); 98 void epic_fixup_clock_source __P((struct epic_softc *)); 99 int epic_mii_read __P((struct device *, int, int)); 100 void epic_mii_write __P((struct device *, int, int, int)); 101 int epic_mii_wait __P((struct epic_softc *, u_int32_t)); 102 void epic_tick __P((void *)); 103 104 void epic_statchg __P((struct device *)); 105 int epic_mediachange __P((struct ifnet *)); 106 void epic_mediastatus __P((struct ifnet *, struct ifmediareq *)); 107 108 /* 109 * Fudge the incoming packets by this much, to ensure the data after 110 * the Ethernet header is aligned. 111 */ 112 #define RX_ALIGNMENT_FUDGE 2 113 114 /* XXX Should be somewhere else. */ 115 #define ETHER_MIN_LEN 60 116 117 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 118 INTSTAT_TXC | INTSTAT_RQE | INTSTAT_RCC) 119 120 /* 121 * Attach an EPIC interface to the system. 122 */ 123 void 124 epic_attach(sc) 125 struct epic_softc *sc; 126 { 127 bus_space_tag_t st = sc->sc_st; 128 bus_space_handle_t sh = sc->sc_sh; 129 struct ifnet *ifp; 130 int i, rseg, error, attach_stage; 131 bus_dma_segment_t seg; 132 u_int8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 133 u_int16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 134 135 attach_stage = 0; 136 137 /* 138 * Allocate the control data structures, and create and load the 139 * DMA map for it. 140 */ 141 if ((error = bus_dmamem_alloc(sc->sc_dmat, 142 sizeof(struct epic_control_data), NBPG, 0, &seg, 1, &rseg, 143 BUS_DMA_NOWAIT)) != 0) { 144 printf("%s: unable to allocate control data, error = %d\n", 145 sc->sc_dev.dv_xname, error); 146 goto fail; 147 } 148 149 attach_stage = 1; 150 151 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 152 sizeof(struct epic_control_data), (caddr_t *)&sc->sc_control_data, 153 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 154 printf("%s: unable to map control data, error = %d\n", 155 sc->sc_dev.dv_xname, error); 156 goto fail; 157 } 158 159 attach_stage = 2; 160 161 if ((error = bus_dmamap_create(sc->sc_dmat, 162 sizeof(struct epic_control_data), 1, 163 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 164 &sc->sc_cddmamap)) != 0) { 165 printf("%s: unable to create control data DMA map, " 166 "error = %d\n", sc->sc_dev.dv_xname, error); 167 goto fail; 168 } 169 170 attach_stage = 3; 171 172 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 173 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 174 BUS_DMA_NOWAIT)) != 0) { 175 printf("%s: unable to load control data DMA map, error = %d\n", 176 sc->sc_dev.dv_xname, error); 177 goto fail; 178 } 179 180 attach_stage = 4; 181 182 /* 183 * Create the transmit buffer DMA maps. 184 */ 185 for (i = 0; i < EPIC_NTXDESC; i++) { 186 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 187 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 188 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 189 printf("%s: unable to create tx DMA map %d, " 190 "error = %d\n", sc->sc_dev.dv_xname, i, error); 191 goto fail; 192 } 193 } 194 195 attach_stage = 5; 196 197 /* 198 * Create the recieve buffer DMA maps. 199 */ 200 for (i = 0; i < EPIC_NRXDESC; i++) { 201 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 202 MCLBYTES, 0, BUS_DMA_NOWAIT, 203 &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 204 printf("%s: unable to create rx DMA map %d, " 205 "error = %d\n", sc->sc_dev.dv_xname, i, error); 206 goto fail; 207 } 208 } 209 210 attach_stage = 6; 211 212 /* 213 * Pre-allocate the receive buffers. 214 */ 215 for (i = 0; i < EPIC_NRXDESC; i++) { 216 if ((error = epic_add_rxbuf(sc, i)) != 0) { 217 printf("%s: unable to allocate or map rx buffer %d\n," 218 " error = %d\n", sc->sc_dev.dv_xname, i, error); 219 goto fail; 220 } 221 } 222 223 attach_stage = 7; 224 225 /* 226 * Bring the chip out of low-power mode and reset it to a known state. 227 */ 228 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 229 epic_reset(sc); 230 231 /* 232 * Read the Ethernet address from the EEPROM. 233 */ 234 epic_read_eeprom(sc, 0, (sizeof(myea) / sizeof(myea[0])), myea); 235 bcopy(myea, enaddr, sizeof(myea)); 236 237 /* 238 * ...and the device name. 239 */ 240 epic_read_eeprom(sc, 0x2c, (sizeof(mydevname) / sizeof(mydevname[0])), 241 mydevname); 242 bcopy(mydevname, devname, sizeof(mydevname)); 243 devname[sizeof(mydevname)] = '\0'; 244 for (i = sizeof(mydevname) - 1; i >= 0; i--) { 245 if (devname[i] == ' ') 246 devname[i] = '\0'; 247 else 248 break; 249 } 250 251 printf("%s: %s, Ethernet address %s\n", sc->sc_dev.dv_xname, 252 devname, ether_sprintf(enaddr)); 253 254 ifp = if_alloc(); 255 sc->sc_ethercom.ec_if = ifp; 256 ifp->if_ifcom = &sc->sc_ethercom; 257 /* 258 * Initialize our media structures and probe the MII. 259 */ 260 sc->sc_mii.mii_ifp = ifp; 261 sc->sc_mii.mii_readreg = epic_mii_read; 262 sc->sc_mii.mii_writereg = epic_mii_write; 263 sc->sc_mii.mii_statchg = epic_statchg; 264 ifmedia_init(&sc->sc_mii.mii_media, 0, epic_mediachange, 265 epic_mediastatus); 266 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 267 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 268 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 269 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 270 } else 271 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 272 273 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 274 ifp->if_softc = sc; 275 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 276 ifp->if_ioctl = epic_ioctl; 277 ifp->if_start = epic_start; 278 ifp->if_watchdog = epic_watchdog; 279 280 /* 281 * Attach the interface. 282 */ 283 if_attach(ifp); 284 ether_ifattach(ifp, enaddr); 285 #if NBPFILTER > 0 286 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, 287 sizeof(struct ether_header)); 288 #endif 289 290 /* 291 * Make sure the interface is shutdown during reboot. 292 */ 293 sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc); 294 if (sc->sc_sdhook == NULL) 295 printf("%s: WARNING: unable to establish shutdown hook\n", 296 sc->sc_dev.dv_xname); 297 return; 298 299 fail: 300 /* 301 * Free any resources we've allocated during the failed attach 302 * attempt. Do this in reverse order and fall through. 303 */ 304 switch (attach_stage) { 305 case 7: 306 for (i = 0; i < EPIC_NRXDESC; i++) { 307 if (sc->sc_rxsoft[i].ds_mbuf != NULL) { 308 bus_dmamap_unload(sc->sc_dmat, 309 sc->sc_rxsoft[i].ds_dmamap); 310 m_freem(sc->sc_rxsoft[i].ds_mbuf); 311 } 312 } 313 /* FALLTHROUGH */ 314 315 case 6: 316 for (i = 0; i < EPIC_NRXDESC; i++) 317 bus_dmamap_destroy(sc->sc_dmat, 318 sc->sc_rxsoft[i].ds_dmamap); 319 /* FALLTHROUGH */ 320 321 case 5: 322 for (i = 0; i < EPIC_NTXDESC; i++) 323 bus_dmamap_destroy(sc->sc_dmat, 324 sc->sc_txsoft[i].ds_dmamap); 325 /* FALLTHROUGH */ 326 327 case 4: 328 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 329 /* FALLTHROUGH */ 330 331 case 3: 332 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 333 /* FALLTHROUGH */ 334 335 case 2: 336 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 337 sizeof(struct epic_control_data)); 338 /* FALLTHROUGH */ 339 340 case 1: 341 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 342 break; 343 } 344 } 345 346 /* 347 * Shutdown hook. Make sure the interface is stopped at reboot. 348 */ 349 void 350 epic_shutdown(arg) 351 void *arg; 352 { 353 struct epic_softc *sc = arg; 354 355 epic_stop(sc); 356 } 357 358 /* 359 * Start packet transmission on the interface. 360 * [ifnet interface function] 361 */ 362 void 363 epic_start(ifp) 364 struct ifnet *ifp; 365 { 366 struct epic_softc *sc = ifp->if_softc; 367 struct epic_txdesc *txd; 368 struct epic_descsoft *ds; 369 struct epic_fraglist *fr; 370 bus_dmamap_t dmamap; 371 struct mbuf *m0; 372 int nexttx, seg, error, txqueued; 373 374 txqueued = 0; 375 376 /* 377 * Loop through the send queue, setting up transmit descriptors 378 * until we drain the queue, or use up all available transmit 379 * descriptors. 380 */ 381 while (ifp->if_snd.ifq_head != NULL && 382 sc->sc_txpending < EPIC_NTXDESC) { 383 /* 384 * Grab a packet off the queue. 385 */ 386 IF_DEQUEUE(&ifp->if_snd, m0); 387 388 /* 389 * Get the last and next available transmit descriptor. 390 */ 391 nexttx = EPIC_NEXTTX(sc->sc_txlast); 392 txd = &sc->sc_control_data->ecd_txdescs[nexttx]; 393 fr = &sc->sc_control_data->ecd_txfrags[nexttx]; 394 ds = &sc->sc_txsoft[nexttx]; 395 dmamap = ds->ds_dmamap; 396 397 loadmap: 398 /* 399 * Load the DMA map with the packet. 400 */ 401 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 402 BUS_DMA_NOWAIT); 403 switch (error) { 404 case 0: 405 /* Success. */ 406 break; 407 408 case EFBIG: 409 { 410 struct mbuf *mn; 411 412 /* 413 * We ran out of segments. We have to recopy this 414 * mbuf chain first. Bail out if we can't get the 415 * new buffers. 416 */ 417 printf("%s: too many segments, ", sc->sc_dev.dv_xname); 418 419 MGETHDR(mn, M_DONTWAIT, MT_DATA); 420 if (mn == NULL) { 421 m_freem(m0); 422 printf("aborting\n"); 423 goto out; 424 } 425 if (m0->m_pkthdr.len > MHLEN) { 426 MCLGET(mn, M_DONTWAIT); 427 if ((mn->m_flags & M_EXT) == 0) { 428 m_freem(mn); 429 m_freem(m0); 430 printf("aborting\n"); 431 goto out; 432 } 433 } 434 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mn, caddr_t)); 435 mn->m_pkthdr.len = mn->m_len = m0->m_pkthdr.len; 436 m_freem(m0); 437 m0 = mn; 438 printf("retrying\n"); 439 goto loadmap; 440 } 441 442 default: 443 /* 444 * Some other problem; report it. 445 */ 446 printf("%s: can't load mbuf chain, error = %d\n", 447 sc->sc_dev.dv_xname, error); 448 m_freem(m0); 449 goto out; 450 } 451 452 /* 453 * Initialize the fraglist. 454 */ 455 fr->ef_nfrags = dmamap->dm_nsegs; 456 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 457 fr->ef_frags[seg].ef_addr = 458 dmamap->dm_segs[seg].ds_addr; 459 fr->ef_frags[seg].ef_length = 460 dmamap->dm_segs[seg].ds_len; 461 } 462 463 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 464 BUS_DMASYNC_PREWRITE); 465 466 /* 467 * Store a pointer to the packet so we can free it later. 468 */ 469 ds->ds_mbuf = m0; 470 471 /* 472 * Finish setting up the new transmit descriptor: set the 473 * packet length and give it to the EPIC. 474 */ 475 txd->et_txlength = max(m0->m_pkthdr.len, ETHER_MIN_LEN); 476 txd->et_txstatus = ET_TXSTAT_OWNER; 477 478 /* 479 * Committed; advance the lasttx pointer. If nothing was 480 * previously queued, reset the dirty pointer. 481 */ 482 sc->sc_txlast = nexttx; 483 if (sc->sc_txpending == 0) 484 sc->sc_txdirty = nexttx; 485 486 sc->sc_txpending++; 487 488 txqueued = 1; 489 490 #if NBPFILTER > 0 491 /* 492 * Pass the packet to any BPF listeners. 493 */ 494 if (ifp->if_bpf) 495 bpf_mtap(ifp->if_bpf, m0); 496 #endif 497 } 498 499 out: 500 /* 501 * We're finished. If we added more packets, make sure the 502 * transmit DMA engine is running. 503 */ 504 if (txqueued) { 505 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 506 COMMAND_TXQUEUED); 507 508 /* 509 * Set a 5 second watchdog timer. 510 */ 511 ifp->if_timer = 5; 512 } 513 } 514 515 /* 516 * Watchdog timer handler. 517 * [ifnet interface function] 518 */ 519 void 520 epic_watchdog(ifp) 521 struct ifnet *ifp; 522 { 523 struct epic_softc *sc = ifp->if_softc; 524 525 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 526 ifp->if_oerrors++; 527 528 epic_init(sc); 529 } 530 531 /* 532 * Handle control requests from the operator. 533 * [ifnet interface function] 534 */ 535 int 536 epic_ioctl(ifp, cmd, data) 537 struct ifnet *ifp; 538 u_long cmd; 539 caddr_t data; 540 { 541 struct epic_softc *sc = ifp->if_softc; 542 struct ifreq *ifr = (struct ifreq *)data; 543 struct ifaddr *ifa = (struct ifaddr *)data; 544 int s, error = 0; 545 546 s = splnet(); 547 548 switch (cmd) { 549 case SIOCSIFADDR: 550 ifp->if_flags |= IFF_UP; 551 552 switch (ifa->ifa_addr->sa_family) { 553 #ifdef INET 554 case AF_INET: 555 epic_init(sc); 556 arp_ifinit(ifp, ifa); 557 break; 558 #endif /* INET */ 559 #ifdef NS 560 case AF_NS: 561 { 562 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 563 564 if (ns_nullhost(*ina)) 565 ina->x_host = *(union ns_host *) 566 LLADDR(ifp->if_sadl); 567 else 568 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 569 ifp->if_addrlen); 570 /* Set new address. */ 571 epic_init(sc); 572 break; 573 } 574 #endif /* NS */ 575 default: 576 epic_init(sc); 577 break; 578 } 579 break; 580 581 case SIOCSIFMTU: 582 if (ifr->ifr_mtu > ETHERMTU) 583 error = EINVAL; 584 else 585 ifp->if_mtu = ifr->ifr_mtu; 586 break; 587 588 case SIOCSIFFLAGS: 589 if ((ifp->if_flags & IFF_UP) == 0 && 590 (ifp->if_flags & IFF_RUNNING) != 0) { 591 /* 592 * If interface is marked down and it is running, then 593 * stop it. 594 */ 595 epic_stop(sc); 596 ifp->if_flags &= ~IFF_RUNNING; 597 } else if ((ifp->if_flags & IFF_UP) != 0 && 598 (ifp->if_flags & IFF_RUNNING) == 0) { 599 /* 600 * If interfase it marked up and it is stopped, then 601 * start it. 602 */ 603 epic_init(sc); 604 } else { 605 /* 606 * Reset the interface to pick up changes in any other 607 * flags that affect the hardware state. 608 */ 609 epic_init(sc); 610 } 611 break; 612 613 case SIOCADDMULTI: 614 case SIOCDELMULTI: 615 error = (cmd == SIOCADDMULTI) ? 616 ether_addmulti(ifr, &sc->sc_ethercom) : 617 ether_delmulti(ifr, &sc->sc_ethercom); 618 619 if (error == ENETRESET) { 620 /* 621 * Multicast list has changed; set the hardware filter 622 * accordingly. 623 */ 624 epic_init(sc); 625 error = 0; 626 } 627 break; 628 629 case SIOCSIFMEDIA: 630 case SIOCGIFMEDIA: 631 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 632 break; 633 634 default: 635 error = EINVAL; 636 break; 637 } 638 639 splx(s); 640 return (error); 641 } 642 643 /* 644 * Interrupt handler. 645 */ 646 int 647 epic_intr(arg) 648 void *arg; 649 { 650 struct epic_softc *sc = arg; 651 struct ifnet *ifp = sc->sc_ethercom.ec_if; 652 struct ether_header *eh; 653 struct epic_rxdesc *rxd; 654 struct epic_txdesc *txd; 655 struct epic_descsoft *ds; 656 struct mbuf *m; 657 u_int32_t intstat; 658 int i, len, claimed = 0, error; 659 660 top: 661 /* 662 * Get the interrupt status from the EPIC. 663 */ 664 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 665 if ((intstat & INTSTAT_INT_ACTV) == 0) 666 return (claimed); 667 668 claimed = 1; 669 670 /* 671 * Acknowledge the interrupt. 672 */ 673 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 674 intstat & INTMASK); 675 676 /* 677 * Check for receive interrupts. 678 */ 679 if (intstat & (INTSTAT_RCC | INTSTAT_RQE)) { 680 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 681 rxd = &sc->sc_control_data->ecd_rxdescs[i]; 682 ds = &sc->sc_rxsoft[i]; 683 m = ds->ds_mbuf; 684 error = 0; 685 686 if (rxd->er_rxstatus & ER_RXSTAT_OWNER) { 687 /* 688 * We have processed all of the 689 * receive buffers. 690 */ 691 break; 692 } 693 694 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 695 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 696 697 /* 698 * Make sure the packet arrived intact. 699 */ 700 if ((rxd->er_rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 701 #if 1 702 if (rxd->er_rxstatus & ER_RXSTAT_CRCERROR) 703 printf("%s: CRC error\n", 704 sc->sc_dev.dv_xname); 705 if (rxd->er_rxstatus & ER_RXSTAT_ALIGNERROR) 706 printf("%s: alignment error\n", 707 sc->sc_dev.dv_xname); 708 #endif 709 ifp->if_ierrors++; 710 error = 1; 711 } 712 713 /* 714 * Add a new buffer to the receive chain. If this 715 * fails, the old buffer is recycled. 716 */ 717 if (epic_add_rxbuf(sc, i) == 0) { 718 /* 719 * We wanted to reset the buffer, but 720 * didn't want to pass it on up. 721 */ 722 if (error) { 723 m_freem(m); 724 continue; 725 } 726 727 len = rxd->er_buflength; 728 if (len < sizeof(struct ether_header)) { 729 m_freem(m); 730 continue; 731 } 732 733 m->m_pkthdr.rcvif = ifp; 734 if_addref(ifp); 735 m->m_pkthdr.len = m->m_len = len; 736 eh = mtod(m, struct ether_header *); 737 #if NBPFILTER > 0 738 /* 739 * Pass this up to any BPF listeners. 740 */ 741 if (ifp->if_bpf) { 742 bpf_mtap(ifp->if_bpf, m); 743 744 /* 745 * Only pass this up the stack 746 * if it's for us. 747 */ 748 if ((ifp->if_flags & IFF_PROMISC) && 749 bcmp(LLADDR(ifp->if_sadl), 750 eh->ether_dhost, 751 ETHER_ADDR_LEN) != 0 && 752 (rxd->er_rxstatus & 753 (ER_RXSTAT_BCAST|ER_RXSTAT_MCAST)) 754 == 0) { 755 m_freem(m); 756 continue; 757 } 758 } 759 #endif /* NPBFILTER > 0 */ 760 m->m_data += sizeof(struct ether_header); 761 m->m_len -= sizeof(struct ether_header); 762 m->m_pkthdr.len = m->m_len; 763 ether_input(ifp, eh, m); 764 } 765 } 766 767 /* 768 * Update the recieve pointer. 769 */ 770 sc->sc_rxptr = i; 771 772 /* 773 * Check for receive queue underflow. 774 */ 775 if (intstat & INTSTAT_RQE) { 776 printf("%s: receiver queue empty\n", 777 sc->sc_dev.dv_xname); 778 /* 779 * Ring is already built; just restart the 780 * receiver. 781 */ 782 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 783 sc->sc_cddma + EPIC_CDOFF(ecd_rxdescs[0])); 784 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 785 COMMAND_RXQUEUED | COMMAND_START_RX); 786 } 787 } 788 789 /* 790 * Check for transmission complete interrupts. 791 */ 792 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 793 for (i = sc->sc_txdirty;; i = EPIC_NEXTTX(i)) { 794 txd = &sc->sc_control_data->ecd_txdescs[i]; 795 ds = &sc->sc_txsoft[i]; 796 797 if (sc->sc_txpending == 0 || 798 (txd->et_txstatus & ET_TXSTAT_OWNER) != 0) 799 break; 800 801 if (ds->ds_mbuf != NULL) { 802 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 803 0, ds->ds_dmamap->dm_mapsize, 804 BUS_DMASYNC_POSTWRITE); 805 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 806 m_freem(ds->ds_mbuf); 807 ds->ds_mbuf = NULL; 808 } 809 sc->sc_txpending--; 810 811 /* 812 * Check for errors and collisions. 813 */ 814 if ((txd->et_txstatus & ET_TXSTAT_PACKETTX) == 0) 815 ifp->if_oerrors++; 816 ifp->if_collisions += 817 TXSTAT_COLLISIONS(txd->et_txstatus); 818 if (txd->et_txstatus & ET_TXSTAT_CARSENSELOST) { 819 #if 1 820 printf("%s: lost carrier\n", 821 sc->sc_dev.dv_xname); 822 #endif 823 /* XXX clear "active" but in media data */ 824 } 825 } 826 827 /* 828 * Update the dirty transmit buffer pointer. 829 */ 830 sc->sc_txdirty = i; 831 832 /* 833 * Cancel the watchdog timer if there are no pending 834 * transmissions. 835 */ 836 if (sc->sc_txpending == 0) 837 ifp->if_timer = 0; 838 839 /* 840 * Kick the transmitter after a DMA underrun. 841 */ 842 if (intstat & INTSTAT_TXU) { 843 printf("%s: transmit underrun\n", sc->sc_dev.dv_xname); 844 bus_space_write_4(sc->sc_st, sc->sc_sh, 845 EPIC_COMMAND, COMMAND_TXUGO); 846 if (sc->sc_txpending) 847 bus_space_write_4(sc->sc_st, sc->sc_sh, 848 EPIC_COMMAND, COMMAND_TXQUEUED); 849 } 850 851 /* 852 * Try to get more packets going. 853 */ 854 epic_start(ifp); 855 } 856 857 /* 858 * Check for fatal interrupts. 859 */ 860 if (intstat & INTSTAT_FATAL_INT) { 861 printf("%s: fatal error, resetting\n", sc->sc_dev.dv_xname); 862 epic_init(sc); 863 } 864 865 /* 866 * Check for more interrupts. 867 */ 868 goto top; 869 } 870 871 /* 872 * One second timer, used to tick the MII. 873 */ 874 void 875 epic_tick(arg) 876 void *arg; 877 { 878 struct epic_softc *sc = arg; 879 int s; 880 881 s = splimp(); 882 mii_tick(&sc->sc_mii); 883 splx(s); 884 885 timeout(epic_tick, sc, hz); 886 } 887 888 /* 889 * Fixup the clock source on the EPIC. 890 */ 891 void 892 epic_fixup_clock_source(sc) 893 struct epic_softc *sc; 894 { 895 int i; 896 897 /* 898 * According to SMC Application Note 7-15, the EPIC's clock 899 * source is incorrect following a reset. This manifests itself 900 * as failure to recognize when host software has written to 901 * a register on the EPIC. The appnote recommends issuing at 902 * least 16 consecutive writes to the CLOCK TEST bit to correctly 903 * configure the clock source. 904 */ 905 for (i = 0; i < 16; i++) 906 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 907 TEST_CLOCKTEST); 908 } 909 910 /* 911 * Perform a soft reset on the EPIC. 912 */ 913 void 914 epic_reset(sc) 915 struct epic_softc *sc; 916 { 917 918 epic_fixup_clock_source(sc); 919 920 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 921 delay(100); 922 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 923 delay(100); 924 925 epic_fixup_clock_source(sc); 926 } 927 928 /* 929 * Initialize the interface. Must be called at splnet(). 930 */ 931 void 932 epic_init(sc) 933 struct epic_softc *sc; 934 { 935 bus_space_tag_t st = sc->sc_st; 936 bus_space_handle_t sh = sc->sc_sh; 937 struct ifnet *ifp = sc->sc_ethercom.ec_if; 938 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 939 struct epic_txdesc *txd; 940 struct epic_rxdesc *rxd; 941 u_int32_t genctl, reg0; 942 int i; 943 944 /* 945 * Cancel any pending I/O. 946 */ 947 epic_stop(sc); 948 949 /* 950 * Reset the EPIC to a known state. 951 */ 952 epic_reset(sc); 953 954 /* 955 * Magical mystery initialization. 956 */ 957 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 958 959 /* 960 * Initialize the EPIC genctl register: 961 * 962 * - 64 byte receive FIFO threshold 963 * - automatic advance to next receive frame 964 */ 965 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 966 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 967 968 /* 969 * Reset the MII bus and PHY. 970 */ 971 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 972 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 973 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 974 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 975 delay(100); 976 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 977 delay(100); 978 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 979 980 /* 981 * Initialize Ethernet address. 982 */ 983 reg0 = enaddr[1] << 8 | enaddr[0]; 984 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 985 reg0 = enaddr[3] << 8 | enaddr[2]; 986 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 987 reg0 = enaddr[5] << 8 | enaddr[4]; 988 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 989 990 /* 991 * Set up the multicast hash table. 992 */ 993 epic_set_mchash(sc); 994 995 /* 996 * Initialize receive control. Remember the external buffer 997 * size setting. 998 */ 999 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 1000 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 1001 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 1002 if (ifp->if_flags & IFF_PROMISC) 1003 reg0 |= RXCON_PROMISCMODE; 1004 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 1005 1006 /* Set the media. (XXX full-duplex in TXCON?) */ 1007 mii_mediachg(&sc->sc_mii); 1008 1009 /* 1010 * Initialize the transmit descriptors. 1011 */ 1012 txd = sc->sc_control_data->ecd_txdescs; 1013 bzero(txd, sizeof(sc->sc_control_data->ecd_txdescs)); 1014 for (i = 0; i < EPIC_NTXDESC; i++) { 1015 txd[i].et_control = ET_TXCTL_LASTDESC | ET_TXCTL_IAF | 1016 ET_TXCTL_FRAGLIST; 1017 txd[i].et_bufaddr = sc->sc_cddma + EPIC_CDOFF(ecd_txfrags[i]); 1018 txd[i].et_nextdesc = sc->sc_cddma + 1019 EPIC_CDOFF(ecd_txdescs[(i + 1) & EPIC_NTXDESC_MASK]); 1020 } 1021 1022 /* 1023 * Initialize the receive descriptors. Note the buffers 1024 * and control word have already been initialized; we only 1025 * need to initialize the ring. 1026 */ 1027 rxd = sc->sc_control_data->ecd_rxdescs; 1028 for (i = 0; i < EPIC_NRXDESC; i++) { 1029 rxd[i].er_nextdesc = sc->sc_cddma + 1030 EPIC_CDOFF(ecd_rxdescs[(i + 1) & EPIC_NRXDESC_MASK]); 1031 } 1032 1033 /* 1034 * Initialize the interrupt mask and enable interrupts. 1035 */ 1036 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1037 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1038 1039 /* 1040 * Give the transmit and receive rings to the EPIC. 1041 */ 1042 bus_space_write_4(st, sh, EPIC_PTCDAR, 1043 sc->sc_cddma + EPIC_CDOFF(ecd_txdescs[0])); 1044 bus_space_write_4(st, sh, EPIC_PRCDAR, 1045 sc->sc_cddma + EPIC_CDOFF(ecd_rxdescs[0])); 1046 1047 /* 1048 * Initialize our ring pointers. txlast it initialized to 1049 * the end of the list so that it will wrap around to the 1050 * first descriptor when the first packet is transmitted. 1051 */ 1052 sc->sc_txpending = 0; 1053 sc->sc_txdirty = 0; 1054 sc->sc_txlast = EPIC_NTXDESC - 1; 1055 1056 sc->sc_rxptr = 0; 1057 1058 /* 1059 * Set the EPIC in motion. 1060 */ 1061 bus_space_write_4(st, sh, EPIC_COMMAND, 1062 COMMAND_RXQUEUED | COMMAND_START_RX); 1063 1064 /* 1065 * ...all done! 1066 */ 1067 ifp->if_flags |= IFF_RUNNING; 1068 ifp->if_flags &= ~IFF_OACTIVE; 1069 1070 /* 1071 * Start the one second clock. 1072 */ 1073 timeout(epic_tick, sc, hz); 1074 1075 /* 1076 * Attempt to start output on the interface. 1077 */ 1078 epic_start(ifp); 1079 } 1080 1081 /* 1082 * Stop transmission on the interface. 1083 */ 1084 void 1085 epic_stop(sc) 1086 struct epic_softc *sc; 1087 { 1088 bus_space_tag_t st = sc->sc_st; 1089 bus_space_handle_t sh = sc->sc_sh; 1090 struct ifnet *ifp = sc->sc_ethercom.ec_if; 1091 struct epic_descsoft *ds; 1092 u_int32_t reg; 1093 int i; 1094 1095 /* 1096 * Stop the one second clock. 1097 */ 1098 untimeout(epic_tick, sc); 1099 1100 /* Paranoia... */ 1101 epic_fixup_clock_source(sc); 1102 1103 /* 1104 * Disable interrupts. 1105 */ 1106 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1107 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1108 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1109 1110 /* 1111 * Stop the DMA engine and take the receiver off-line. 1112 */ 1113 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1114 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1115 1116 /* 1117 * Release any queued transmit buffers. 1118 */ 1119 for (i = 0; i < EPIC_NTXDESC; i++) { 1120 ds = &sc->sc_txsoft[i]; 1121 if (ds->ds_mbuf != NULL) { 1122 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1123 m_freem(ds->ds_mbuf); 1124 ds->ds_mbuf = NULL; 1125 } 1126 } 1127 sc->sc_txpending = 0; 1128 1129 /* 1130 * Release the receive buffers, then reallocate/reinitialize. 1131 */ 1132 for (i = 0; i < EPIC_NRXDESC; i++) { 1133 ds = &sc->sc_rxsoft[i]; 1134 if (ds->ds_mbuf != NULL) { 1135 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1136 m_freem(ds->ds_mbuf); 1137 ds->ds_mbuf = NULL; 1138 } 1139 if (epic_add_rxbuf(sc, i) != 0) { 1140 /* 1141 * This "can't happen" - we're at splnet() 1142 * and we just freed the buffer we need 1143 * above. 1144 */ 1145 panic("epic_stop: no buffers!"); 1146 } 1147 } 1148 1149 /* 1150 * Mark the interface down and cancel the watchdog timer. 1151 */ 1152 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1153 ifp->if_timer = 0; 1154 } 1155 1156 /* 1157 * Read the EPIC Serial EEPROM. 1158 */ 1159 void 1160 epic_read_eeprom(sc, word, wordcnt, data) 1161 struct epic_softc *sc; 1162 int word, wordcnt; 1163 u_int16_t *data; 1164 { 1165 bus_space_tag_t st = sc->sc_st; 1166 bus_space_handle_t sh = sc->sc_sh; 1167 u_int16_t reg; 1168 int i, x; 1169 1170 #define EEPROM_WAIT_READY(st, sh) \ 1171 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1172 /* nothing */ 1173 1174 /* 1175 * Enable the EEPROM. 1176 */ 1177 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1178 EEPROM_WAIT_READY(st, sh); 1179 1180 for (i = 0; i < wordcnt; i++) { 1181 /* Send CHIP SELECT for one clock tick. */ 1182 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1183 EEPROM_WAIT_READY(st, sh); 1184 1185 /* Shift in the READ opcode. */ 1186 for (x = 3; x > 0; x--) { 1187 reg = EECTL_ENABLE|EECTL_EECS; 1188 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1189 reg |= EECTL_EEDI; 1190 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1191 EEPROM_WAIT_READY(st, sh); 1192 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1193 EEPROM_WAIT_READY(st, sh); 1194 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1195 EEPROM_WAIT_READY(st, sh); 1196 } 1197 1198 /* Shift in address. */ 1199 for (x = 6; x > 0; x--) { 1200 reg = EECTL_ENABLE|EECTL_EECS; 1201 if ((word + i) & (1 << (x - 1))) 1202 reg |= EECTL_EEDI; 1203 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1204 EEPROM_WAIT_READY(st, sh); 1205 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1206 EEPROM_WAIT_READY(st, sh); 1207 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1208 EEPROM_WAIT_READY(st, sh); 1209 } 1210 1211 /* Shift out data. */ 1212 reg = EECTL_ENABLE|EECTL_EECS; 1213 data[i] = 0; 1214 for (x = 16; x > 0; x--) { 1215 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1216 EEPROM_WAIT_READY(st, sh); 1217 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1218 data[i] |= (1 << (x - 1)); 1219 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1220 EEPROM_WAIT_READY(st, sh); 1221 } 1222 1223 /* Clear CHIP SELECT. */ 1224 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1225 EEPROM_WAIT_READY(st, sh); 1226 } 1227 1228 /* 1229 * Disable the EEPROM. 1230 */ 1231 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1232 1233 #undef EEPROM_WAIT_READY 1234 } 1235 1236 /* 1237 * Add a receive buffer to the indicated descriptor. 1238 */ 1239 int 1240 epic_add_rxbuf(sc, idx) 1241 struct epic_softc *sc; 1242 int idx; 1243 { 1244 struct epic_rxdesc *rxd = &sc->sc_control_data->ecd_rxdescs[idx]; 1245 struct epic_descsoft *ds = &sc->sc_rxsoft[idx]; 1246 struct mbuf *m, *oldm; 1247 int error = 0; 1248 1249 oldm = ds->ds_mbuf; 1250 1251 MGETHDR(m, M_DONTWAIT, MT_DATA); 1252 if (m != NULL) { 1253 MCLGET(m, M_DONTWAIT); 1254 if ((m->m_flags & M_EXT) == 0) { 1255 error = ENOMEM; 1256 m_freem(m); 1257 if (oldm == NULL) 1258 return (error); 1259 m = oldm; 1260 m->m_data = m->m_ext.ext_buf; 1261 } 1262 } else { 1263 error = ENOMEM; 1264 if (oldm == NULL) 1265 return (error); 1266 m = oldm; 1267 m->m_data = m->m_ext.ext_buf; 1268 } 1269 1270 ds->ds_mbuf = m; 1271 1272 /* 1273 * Set up the DMA map for this receive buffer. 1274 */ 1275 if (m != oldm) { 1276 if (oldm != NULL) 1277 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1278 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1279 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1280 if (error) { 1281 printf("%s: can't load rx buffer, error = %d\n", 1282 sc->sc_dev.dv_xname, error); 1283 panic("epic_add_rxbuf"); /* XXX */ 1284 } 1285 } 1286 1287 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1288 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1289 1290 /* 1291 * Move the data pointer up so that the incoming packet 1292 * will be 32-bit aligned. 1293 */ 1294 m->m_data += RX_ALIGNMENT_FUDGE; 1295 1296 /* 1297 * Initialize the receive descriptor. 1298 */ 1299 rxd->er_bufaddr = ds->ds_dmamap->dm_segs[0].ds_addr + 1300 RX_ALIGNMENT_FUDGE; 1301 rxd->er_buflength = m->m_ext.ext_size - RX_ALIGNMENT_FUDGE; 1302 rxd->er_control = 0; 1303 rxd->er_rxstatus = ER_RXSTAT_OWNER; 1304 1305 return (error); 1306 } 1307 1308 /* 1309 * Set the EPIC multicast hash table. 1310 */ 1311 void 1312 epic_set_mchash(sc) 1313 struct epic_softc *sc; 1314 { 1315 struct ethercom *ec = &sc->sc_ethercom; 1316 struct ifnet *ifp = sc->sc_ethercom.ec_if; 1317 struct ether_multi *enm; 1318 struct ether_multistep step; 1319 u_int8_t *cp; 1320 u_int32_t crc, mchash[4]; 1321 int len; 1322 static const u_int32_t crctab[] = { 1323 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, 1324 0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c, 1325 0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c, 1326 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c 1327 }; 1328 1329 /* 1330 * Set up the multicast address filter by passing all multicast 1331 * addresses through a CRC generator, and then using the high-order 1332 * 6 bits as an index into the 64 bit multicast hash table (only 1333 * the lower 16 bits of each 32 bit multicast hash register are 1334 * valid). The high order bit selects the register, while the 1335 * rest of the bits select the bit within the register. 1336 */ 1337 1338 if (ifp->if_flags & IFF_PROMISC) 1339 goto allmulti; 1340 1341 #if 1 /* XXX thorpej - hardware bug in 10Mb mode */ 1342 goto allmulti; 1343 #endif 1344 1345 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1346 1347 ETHER_FIRST_MULTI(step, ec, enm); 1348 while (enm != NULL) { 1349 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1350 /* 1351 * We must listen to a range of multicast addresses. 1352 * For now, just accept all multicasts, rather than 1353 * trying to set only those filter bits needed to match 1354 * the range. (At this time, the only use of address 1355 * ranges is for IP multicast routing, for which the 1356 * range is big enough to require all bits set.) 1357 */ 1358 goto allmulti; 1359 } 1360 1361 cp = enm->enm_addrlo; 1362 crc = 0xffffffff; 1363 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1364 crc ^= *cp++; 1365 crc = (crc >> 4) ^ crctab[crc & 0xf]; 1366 crc = (crc >> 4) ^ crctab[crc & 0xf]; 1367 } 1368 /* Just want the 6 most significant bits. */ 1369 crc >>= 26; 1370 1371 /* Set the corresponding bit in the hash table. */ 1372 mchash[crc >> 4] |= 1 << (crc & 0xf); 1373 1374 ETHER_NEXT_MULTI(step, enm); 1375 } 1376 1377 ifp->if_flags &= ~IFF_ALLMULTI; 1378 goto sethash; 1379 1380 allmulti: 1381 ifp->if_flags |= IFF_ALLMULTI; 1382 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1383 1384 sethash: 1385 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1386 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1387 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1388 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1389 } 1390 1391 /* 1392 * Wait for the MII to become ready. 1393 */ 1394 int 1395 epic_mii_wait(sc, rw) 1396 struct epic_softc *sc; 1397 u_int32_t rw; 1398 { 1399 int i; 1400 1401 for (i = 0; i < 50; i++) { 1402 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1403 == 0) 1404 break; 1405 delay(2); 1406 } 1407 if (i == 50) { 1408 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1409 return (1); 1410 } 1411 1412 return (0); 1413 } 1414 1415 /* 1416 * Read from the MII. 1417 */ 1418 int 1419 epic_mii_read(self, phy, reg) 1420 struct device *self; 1421 int phy, reg; 1422 { 1423 struct epic_softc *sc = (struct epic_softc *)self; 1424 1425 if (epic_mii_wait(sc, MMCTL_WRITE)) 1426 return (0); 1427 1428 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1429 MMCTL_ARG(phy, reg, MMCTL_READ)); 1430 1431 if (epic_mii_wait(sc, MMCTL_READ)) 1432 return (0); 1433 1434 return (bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) & 1435 MMDATA_MASK); 1436 } 1437 1438 /* 1439 * Write to the MII. 1440 */ 1441 void 1442 epic_mii_write(self, phy, reg, val) 1443 struct device *self; 1444 int phy, reg, val; 1445 { 1446 struct epic_softc *sc = (struct epic_softc *)self; 1447 1448 if (epic_mii_wait(sc, MMCTL_WRITE)) 1449 return; 1450 1451 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1452 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1453 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1454 } 1455 1456 /* 1457 * Callback from PHY when media changes. 1458 */ 1459 void 1460 epic_statchg(self) 1461 struct device *self; 1462 { 1463 1464 /* XXX Update ifp->if_baudrate */ 1465 } 1466 1467 /* 1468 * Callback from ifmedia to request current media status. 1469 */ 1470 void 1471 epic_mediastatus(ifp, ifmr) 1472 struct ifnet *ifp; 1473 struct ifmediareq *ifmr; 1474 { 1475 struct epic_softc *sc = ifp->if_softc; 1476 1477 mii_pollstat(&sc->sc_mii); 1478 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1479 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1480 } 1481 1482 /* 1483 * Callback from ifmedia to request new media setting. 1484 */ 1485 int 1486 epic_mediachange(ifp) 1487 struct ifnet *ifp; 1488 { 1489 1490 if (ifp->if_flags & IFF_UP) 1491 epic_init((struct epic_softc *)ifp->if_softc); 1492 return (0); 1493 } 1494
Indexes created Tue Oct 21 12:09:54 GMT 2025