smc83c170.c revision 1.93
1 /* $NetBSD: smc83c170.c,v 1.93 2020/02/07 00:56:48 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the Standard Microsystems Corp. 83C170 35 * Ethernet PCI Integrated Controller (EPIC/100). 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.93 2020/02/07 00:56:48 thorpej Exp $"); 40 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/miivar.h> 64 #include <dev/mii/lxtphyreg.h> 65 66 #include <dev/ic/smc83c170reg.h> 67 #include <dev/ic/smc83c170var.h> 68 69 static void epic_start(struct ifnet *); 70 static void epic_watchdog(struct ifnet *); 71 static int epic_ioctl(struct ifnet *, u_long, void *); 72 static int epic_init(struct ifnet *); 73 static void epic_stop(struct ifnet *, int); 74 75 static bool epic_shutdown(device_t, int); 76 77 static void epic_reset(struct epic_softc *); 78 static void epic_rxdrain(struct epic_softc *); 79 static int epic_add_rxbuf(struct epic_softc *, int); 80 static void epic_read_eeprom(struct epic_softc *, int, int, uint16_t *); 81 static void epic_set_mchash(struct epic_softc *); 82 static void epic_fixup_clock_source(struct epic_softc *); 83 static int epic_mii_read(device_t, int, int, uint16_t *); 84 static int epic_mii_write(device_t, int, int, uint16_t); 85 static int epic_mii_wait(struct epic_softc *, uint32_t); 86 static void epic_tick(void *); 87 88 static void epic_statchg(struct ifnet *); 89 static int epic_mediachange(struct ifnet *); 90 91 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 92 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 93 94 int epic_copy_small = 0; 95 96 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 97 98 /* 99 * Attach an EPIC interface to the system. 100 */ 101 void 102 epic_attach(struct epic_softc *sc) 103 { 104 bus_space_tag_t st = sc->sc_st; 105 bus_space_handle_t sh = sc->sc_sh; 106 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 107 struct mii_data * const mii = &sc->sc_mii; 108 int rseg, error, miiflags; 109 u_int i; 110 bus_dma_segment_t seg; 111 uint8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 112 uint16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 113 char *nullbuf; 114 115 callout_init(&sc->sc_mii_callout, 0); 116 callout_setfunc(&sc->sc_mii_callout, epic_tick, sc); 117 118 /* 119 * Allocate the control data structures, and create and load the 120 * DMA map for it. 121 */ 122 if ((error = bus_dmamem_alloc(sc->sc_dmat, 123 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0, 124 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 125 aprint_error_dev(sc->sc_dev, 126 "unable to allocate control data, error = %d\n", error); 127 goto fail_0; 128 } 129 130 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 131 sizeof(struct epic_control_data) + ETHER_PAD_LEN, 132 (void **)&sc->sc_control_data, 133 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 134 aprint_error_dev(sc->sc_dev, 135 "unable to map control data, error = %d\n", error); 136 goto fail_1; 137 } 138 nullbuf = 139 (char *)sc->sc_control_data + sizeof(struct epic_control_data); 140 memset(nullbuf, 0, ETHER_PAD_LEN); 141 142 if ((error = bus_dmamap_create(sc->sc_dmat, 143 sizeof(struct epic_control_data), 1, 144 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 145 &sc->sc_cddmamap)) != 0) { 146 aprint_error_dev(sc->sc_dev, 147 "unable to create control data DMA map, error = %d\n", 148 error); 149 goto fail_2; 150 } 151 152 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 153 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 154 BUS_DMA_NOWAIT)) != 0) { 155 aprint_error_dev(sc->sc_dev, 156 "unable to load control data DMA map, error = %d\n", 157 error); 158 goto fail_3; 159 } 160 161 /* 162 * Create the transmit buffer DMA maps. 163 */ 164 for (i = 0; i < EPIC_NTXDESC; i++) { 165 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 166 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 167 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 168 aprint_error_dev(sc->sc_dev, 169 "unable to create tx DMA map %d, error = %d\n", 170 i, error); 171 goto fail_4; 172 } 173 } 174 175 /* 176 * Create the receive buffer DMA maps. 177 */ 178 for (i = 0; i < EPIC_NRXDESC; i++) { 179 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 180 MCLBYTES, 0, BUS_DMA_NOWAIT, 181 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 182 aprint_error_dev(sc->sc_dev, 183 "unable to create rx DMA map %d, error = %d\n", 184 i, error); 185 goto fail_5; 186 } 187 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 188 } 189 190 /* 191 * create and map the pad buffer 192 */ 193 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 194 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) { 195 aprint_error_dev(sc->sc_dev, 196 "unable to create pad buffer DMA map, error = %d\n", error); 197 goto fail_5; 198 } 199 200 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 201 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "unable to load pad buffer DMA map, error = %d\n", error); 204 goto fail_6; 205 } 206 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 207 BUS_DMASYNC_PREWRITE); 208 209 /* 210 * Bring the chip out of low-power mode and reset it to a known state. 211 */ 212 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 213 epic_reset(sc); 214 215 /* 216 * Read the Ethernet address from the EEPROM. 217 */ 218 epic_read_eeprom(sc, 0, __arraycount(myea), myea); 219 for (i = 0; i < __arraycount(myea); i++) { 220 enaddr[i * 2] = myea[i] & 0xff; 221 enaddr[i * 2 + 1] = myea[i] >> 8; 222 } 223 224 /* 225 * ...and the device name. 226 */ 227 epic_read_eeprom(sc, 0x2c, __arraycount(mydevname), mydevname); 228 for (i = 0; i < __arraycount(mydevname); i++) { 229 devname[i * 2] = mydevname[i] & 0xff; 230 devname[i * 2 + 1] = mydevname[i] >> 8; 231 } 232 233 devname[sizeof(mydevname)] = '\0'; 234 for (i = sizeof(mydevname) ; i > 0; i--) { 235 if (devname[i - 1] == ' ') 236 devname[i - 1] = '\0'; 237 else 238 break; 239 } 240 241 aprint_normal_dev(sc->sc_dev, "%s, Ethernet address %s\n", 242 devname, ether_sprintf(enaddr)); 243 244 miiflags = 0; 245 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 246 miiflags |= MIIF_HAVEFIBER; 247 248 /* 249 * Initialize our media structures and probe the MII. 250 */ 251 mii->mii_ifp = ifp; 252 mii->mii_readreg = epic_mii_read; 253 mii->mii_writereg = epic_mii_write; 254 mii->mii_statchg = epic_statchg; 255 256 sc->sc_ethercom.ec_mii = mii; 257 ifmedia_init(&mii->mii_media, IFM_IMASK, epic_mediachange, 258 ether_mediastatus); 259 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 260 MII_OFFSET_ANY, miiflags); 261 if (LIST_EMPTY(&mii->mii_phys)) { 262 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 263 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 264 } else 265 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 266 267 if (sc->sc_hwflags & EPIC_HAS_BNC) { 268 /* use the next free media instance */ 269 sc->sc_serinst = mii->mii_instance++; 270 ifmedia_add(&mii->mii_media, 271 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->sc_serinst), 272 0, NULL); 273 aprint_normal_dev(sc->sc_dev, "10base2/BNC\n"); 274 } else 275 sc->sc_serinst = -1; 276 277 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 278 ifp->if_softc = sc; 279 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 280 ifp->if_ioctl = epic_ioctl; 281 ifp->if_start = epic_start; 282 ifp->if_watchdog = epic_watchdog; 283 ifp->if_init = epic_init; 284 ifp->if_stop = epic_stop; 285 IFQ_SET_READY(&ifp->if_snd); 286 287 /* 288 * We can support 802.1Q VLAN-sized frames. 289 */ 290 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 291 292 /* 293 * Attach the interface. 294 */ 295 if_attach(ifp); 296 if_deferred_start_init(ifp, NULL); 297 ether_ifattach(ifp, enaddr); 298 299 /* 300 * Make sure the interface is shutdown during reboot. 301 */ 302 if (pmf_device_register1(sc->sc_dev, NULL, NULL, epic_shutdown)) 303 pmf_class_network_register(sc->sc_dev, ifp); 304 else 305 aprint_error_dev(sc->sc_dev, 306 "couldn't establish power handler\n"); 307 308 return; 309 310 /* 311 * Free any resources we've allocated during the failed attach 312 * attempt. Do this in reverse order and fall through. 313 */ 314 fail_6: 315 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 316 fail_5: 317 for (i = 0; i < EPIC_NRXDESC; i++) { 318 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 319 bus_dmamap_destroy(sc->sc_dmat, 320 EPIC_DSRX(sc, i)->ds_dmamap); 321 } 322 fail_4: 323 for (i = 0; i < EPIC_NTXDESC; i++) { 324 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 325 bus_dmamap_destroy(sc->sc_dmat, 326 EPIC_DSTX(sc, i)->ds_dmamap); 327 } 328 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 329 fail_3: 330 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 331 fail_2: 332 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 333 sizeof(struct epic_control_data)); 334 fail_1: 335 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 336 fail_0: 337 return; 338 } 339 340 /* 341 * Shutdown hook. Make sure the interface is stopped at reboot. 342 */ 343 static bool 344 epic_shutdown(device_t self, int howto) 345 { 346 struct epic_softc *sc = device_private(self); 347 348 epic_stop(&sc->sc_ethercom.ec_if, 1); 349 350 return true; 351 } 352 353 /* 354 * Start packet transmission on the interface. 355 * [ifnet interface function] 356 */ 357 static void 358 epic_start(struct ifnet *ifp) 359 { 360 struct epic_softc *sc = ifp->if_softc; 361 struct mbuf *m0, *m; 362 struct epic_txdesc *txd; 363 struct epic_descsoft *ds; 364 struct epic_fraglist *fr; 365 bus_dmamap_t dmamap; 366 int error, firsttx, nexttx, opending, seg; 367 u_int len; 368 369 /* 370 * Remember the previous txpending and the first transmit 371 * descriptor we use. 372 */ 373 opending = sc->sc_txpending; 374 firsttx = EPIC_NEXTTX(sc->sc_txlast); 375 376 /* 377 * Loop through the send queue, setting up transmit descriptors 378 * until we drain the queue, or use up all available transmit 379 * descriptors. 380 */ 381 while (sc->sc_txpending < EPIC_NTXDESC) { 382 /* 383 * Grab a packet off the queue. 384 */ 385 IFQ_POLL(&ifp->if_snd, m0); 386 if (m0 == NULL) 387 break; 388 m = NULL; 389 390 /* 391 * Get the last and next available transmit descriptor. 392 */ 393 nexttx = EPIC_NEXTTX(sc->sc_txlast); 394 txd = EPIC_CDTX(sc, nexttx); 395 fr = EPIC_CDFL(sc, nexttx); 396 ds = EPIC_DSTX(sc, nexttx); 397 dmamap = ds->ds_dmamap; 398 399 /* 400 * Load the DMA map. If this fails, the packet either 401 * didn't fit in the alloted number of frags, or we were 402 * short on resources. In this case, we'll copy and try 403 * again. 404 */ 405 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 406 BUS_DMA_WRITE | BUS_DMA_NOWAIT)) != 0 || 407 (m0->m_pkthdr.len < ETHER_PAD_LEN && 408 dmamap-> dm_nsegs == EPIC_NFRAGS)) { 409 if (error == 0) 410 bus_dmamap_unload(sc->sc_dmat, dmamap); 411 412 MGETHDR(m, M_DONTWAIT, MT_DATA); 413 if (m == NULL) { 414 printf("%s: unable to allocate Tx mbuf\n", 415 device_xname(sc->sc_dev)); 416 break; 417 } 418 if (m0->m_pkthdr.len > MHLEN) { 419 MCLGET(m, M_DONTWAIT); 420 if ((m->m_flags & M_EXT) == 0) { 421 printf("%s: unable to allocate Tx " 422 "cluster\n", 423 device_xname(sc->sc_dev)); 424 m_freem(m); 425 break; 426 } 427 } 428 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 429 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 430 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 431 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 432 if (error) { 433 printf("%s: unable to load Tx buffer, " 434 "error = %d\n", device_xname(sc->sc_dev), 435 error); 436 break; 437 } 438 } 439 IFQ_DEQUEUE(&ifp->if_snd, m0); 440 if (m != NULL) { 441 m_freem(m0); 442 m0 = m; 443 } 444 445 /* Initialize the fraglist. */ 446 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 447 fr->ef_frags[seg].ef_addr = 448 dmamap->dm_segs[seg].ds_addr; 449 fr->ef_frags[seg].ef_length = 450 dmamap->dm_segs[seg].ds_len; 451 } 452 len = m0->m_pkthdr.len; 453 if (len < ETHER_PAD_LEN) { 454 fr->ef_frags[seg].ef_addr = sc->sc_nulldma; 455 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len; 456 len = ETHER_PAD_LEN; 457 seg++; 458 } 459 fr->ef_nfrags = seg; 460 461 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 462 463 /* Sync the DMA map. */ 464 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 465 BUS_DMASYNC_PREWRITE); 466 467 /* 468 * Store a pointer to the packet so we can free it later. 469 */ 470 ds->ds_mbuf = m0; 471 472 /* 473 * Fill in the transmit descriptor. 474 */ 475 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 476 477 /* 478 * If this is the first descriptor we're enqueueing, 479 * don't give it to the EPIC yet. That could cause 480 * a race condition. We'll do it below. 481 */ 482 if (nexttx == firsttx) 483 txd->et_txstatus = TXSTAT_TXLENGTH(len); 484 else 485 txd->et_txstatus = 486 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER; 487 488 EPIC_CDTXSYNC(sc, nexttx, 489 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 490 491 /* Advance the tx pointer. */ 492 sc->sc_txpending++; 493 sc->sc_txlast = nexttx; 494 495 /* 496 * Pass the packet to any BPF listeners. 497 */ 498 bpf_mtap(ifp, m0, BPF_D_OUT); 499 } 500 501 if (sc->sc_txpending == EPIC_NTXDESC) { 502 /* No more slots left; notify upper layer. */ 503 ifp->if_flags |= IFF_OACTIVE; 504 } 505 506 if (sc->sc_txpending != opending) { 507 /* 508 * We enqueued packets. If the transmitter was idle, 509 * reset the txdirty pointer. 510 */ 511 if (opending == 0) 512 sc->sc_txdirty = firsttx; 513 514 /* 515 * Cause a transmit interrupt to happen on the 516 * last packet we enqueued. 517 */ 518 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 519 EPIC_CDTXSYNC(sc, sc->sc_txlast, 520 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 521 522 /* 523 * The entire packet chain is set up. Give the 524 * first descriptor to the EPIC now. 525 */ 526 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER; 527 EPIC_CDTXSYNC(sc, firsttx, 528 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 529 530 /* Start the transmitter. */ 531 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 532 COMMAND_TXQUEUED); 533 534 /* Set a watchdog timer in case the chip flakes out. */ 535 ifp->if_timer = 5; 536 } 537 } 538 539 /* 540 * Watchdog timer handler. 541 * [ifnet interface function] 542 */ 543 static void 544 epic_watchdog(struct ifnet *ifp) 545 { 546 struct epic_softc *sc = ifp->if_softc; 547 548 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 549 if_statinc(ifp, if_oerrors); 550 551 (void)epic_init(ifp); 552 } 553 554 /* 555 * Handle control requests from the operator. 556 * [ifnet interface function] 557 */ 558 static int 559 epic_ioctl(struct ifnet *ifp, u_long cmd, void *data) 560 { 561 struct epic_softc *sc = ifp->if_softc; 562 int s, error; 563 564 s = splnet(); 565 566 error = ether_ioctl(ifp, cmd, data); 567 if (error == ENETRESET) { 568 /* 569 * Multicast list has changed; set the hardware filter 570 * accordingly. Update our idea of the current media; 571 * epic_set_mchash() needs to know what it is. 572 */ 573 if (ifp->if_flags & IFF_RUNNING) { 574 mii_pollstat(&sc->sc_mii); 575 epic_set_mchash(sc); 576 } 577 error = 0; 578 } 579 580 splx(s); 581 return error; 582 } 583 584 /* 585 * Interrupt handler. 586 */ 587 int 588 epic_intr(void *arg) 589 { 590 struct epic_softc *sc = arg; 591 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 592 struct epic_rxdesc *rxd; 593 struct epic_txdesc *txd; 594 struct epic_descsoft *ds; 595 struct mbuf *m; 596 uint32_t intstat, rxstatus, txstatus; 597 int i, claimed = 0; 598 u_int len; 599 600 top: 601 /* 602 * Get the interrupt status from the EPIC. 603 */ 604 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 605 if ((intstat & INTSTAT_INT_ACTV) == 0) 606 return claimed; 607 608 claimed = 1; 609 610 /* 611 * Acknowledge the interrupt. 612 */ 613 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 614 intstat & INTMASK); 615 616 /* 617 * Check for receive interrupts. 618 */ 619 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 620 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 621 rxd = EPIC_CDRX(sc, i); 622 ds = EPIC_DSRX(sc, i); 623 624 EPIC_CDRXSYNC(sc, i, 625 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 626 627 rxstatus = rxd->er_rxstatus; 628 if (rxstatus & ER_RXSTAT_OWNER) { 629 /* 630 * We have processed all of the 631 * receive buffers. 632 */ 633 break; 634 } 635 636 /* 637 * Make sure the packet arrived intact. If an error 638 * occurred, update stats and reset the descriptor. 639 * The buffer will be reused the next time the 640 * descriptor comes up in the ring. 641 */ 642 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 643 if (rxstatus & ER_RXSTAT_CRCERROR) 644 printf("%s: CRC error\n", 645 device_xname(sc->sc_dev)); 646 if (rxstatus & ER_RXSTAT_ALIGNERROR) 647 printf("%s: alignment error\n", 648 device_xname(sc->sc_dev)); 649 if_statinc(ifp, if_ierrors); 650 EPIC_INIT_RXDESC(sc, i); 651 continue; 652 } 653 654 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 655 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 656 657 /* 658 * The EPIC includes the CRC with every packet; 659 * trim it. 660 */ 661 len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN; 662 663 if (len < sizeof(struct ether_header)) { 664 /* 665 * Runt packet; drop it now. 666 */ 667 if_statinc(ifp, if_ierrors); 668 EPIC_INIT_RXDESC(sc, i); 669 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 670 ds->ds_dmamap->dm_mapsize, 671 BUS_DMASYNC_PREREAD); 672 continue; 673 } 674 675 /* 676 * If the packet is small enough to fit in a 677 * single header mbuf, allocate one and copy 678 * the data into it. This greatly reduces 679 * memory consumption when we receive lots 680 * of small packets. 681 * 682 * Otherwise, we add a new buffer to the receive 683 * chain. If this fails, we drop the packet and 684 * recycle the old buffer. 685 */ 686 if (epic_copy_small != 0 && len <= MHLEN) { 687 MGETHDR(m, M_DONTWAIT, MT_DATA); 688 if (m == NULL) 689 goto dropit; 690 memcpy(mtod(m, void *), 691 mtod(ds->ds_mbuf, void *), len); 692 EPIC_INIT_RXDESC(sc, i); 693 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 694 ds->ds_dmamap->dm_mapsize, 695 BUS_DMASYNC_PREREAD); 696 } else { 697 m = ds->ds_mbuf; 698 if (epic_add_rxbuf(sc, i) != 0) { 699 dropit: 700 if_statinc(ifp, if_ierrors); 701 EPIC_INIT_RXDESC(sc, i); 702 bus_dmamap_sync(sc->sc_dmat, 703 ds->ds_dmamap, 0, 704 ds->ds_dmamap->dm_mapsize, 705 BUS_DMASYNC_PREREAD); 706 continue; 707 } 708 } 709 710 m_set_rcvif(m, ifp); 711 m->m_pkthdr.len = m->m_len = len; 712 713 /* Pass it on. */ 714 if_percpuq_enqueue(ifp->if_percpuq, m); 715 } 716 717 /* Update the receive pointer. */ 718 sc->sc_rxptr = i; 719 720 /* 721 * Check for receive queue underflow. 722 */ 723 if (intstat & INTSTAT_RQE) { 724 printf("%s: receiver queue empty\n", 725 device_xname(sc->sc_dev)); 726 /* 727 * Ring is already built; just restart the 728 * receiver. 729 */ 730 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 731 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 732 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 733 COMMAND_RXQUEUED | COMMAND_START_RX); 734 } 735 } 736 737 /* 738 * Check for transmission complete interrupts. 739 */ 740 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 741 ifp->if_flags &= ~IFF_OACTIVE; 742 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 743 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 744 txd = EPIC_CDTX(sc, i); 745 ds = EPIC_DSTX(sc, i); 746 747 EPIC_CDTXSYNC(sc, i, 748 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 749 750 txstatus = txd->et_txstatus; 751 if (txstatus & ET_TXSTAT_OWNER) 752 break; 753 754 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 755 756 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 757 0, ds->ds_dmamap->dm_mapsize, 758 BUS_DMASYNC_POSTWRITE); 759 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 760 m_freem(ds->ds_mbuf); 761 ds->ds_mbuf = NULL; 762 763 /* 764 * Check for errors and collisions. 765 */ 766 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 767 if ((txstatus & ET_TXSTAT_PACKETTX) == 0) 768 if_statinc_ref(nsr, if_oerrors); 769 else 770 if_statinc_ref(nsr, if_opackets); 771 if (TXSTAT_COLLISIONS(txstatus)) 772 if_statadd_ref(nsr, if_collisions, 773 TXSTAT_COLLISIONS(txstatus)); 774 if (txstatus & ET_TXSTAT_CARSENSELOST) 775 printf("%s: lost carrier\n", 776 device_xname(sc->sc_dev)); 777 IF_STAT_PUTREF(ifp); 778 } 779 780 /* Update the dirty transmit buffer pointer. */ 781 sc->sc_txdirty = i; 782 783 /* 784 * Cancel the watchdog timer if there are no pending 785 * transmissions. 786 */ 787 if (sc->sc_txpending == 0) 788 ifp->if_timer = 0; 789 790 /* 791 * Kick the transmitter after a DMA underrun. 792 */ 793 if (intstat & INTSTAT_TXU) { 794 printf("%s: transmit underrun\n", 795 device_xname(sc->sc_dev)); 796 bus_space_write_4(sc->sc_st, sc->sc_sh, 797 EPIC_COMMAND, COMMAND_TXUGO); 798 if (sc->sc_txpending) 799 bus_space_write_4(sc->sc_st, sc->sc_sh, 800 EPIC_COMMAND, COMMAND_TXQUEUED); 801 } 802 803 /* 804 * Try to get more packets going. 805 */ 806 if_schedule_deferred_start(ifp); 807 } 808 809 /* 810 * Check for fatal interrupts. 811 */ 812 if (intstat & INTSTAT_FATAL_INT) { 813 if (intstat & INTSTAT_PTA) 814 printf("%s: PCI target abort error\n", 815 device_xname(sc->sc_dev)); 816 else if (intstat & INTSTAT_PMA) 817 printf("%s: PCI master abort error\n", 818 device_xname(sc->sc_dev)); 819 else if (intstat & INTSTAT_APE) 820 printf("%s: PCI address parity error\n", 821 device_xname(sc->sc_dev)); 822 else if (intstat & INTSTAT_DPE) 823 printf("%s: PCI data parity error\n", 824 device_xname(sc->sc_dev)); 825 else 826 printf("%s: unknown fatal error\n", 827 device_xname(sc->sc_dev)); 828 (void)epic_init(ifp); 829 } 830 831 /* 832 * Check for more interrupts. 833 */ 834 goto top; 835 } 836 837 /* 838 * One second timer, used to tick the MII. 839 */ 840 static void 841 epic_tick(void *arg) 842 { 843 struct epic_softc *sc = arg; 844 int s; 845 846 s = splnet(); 847 mii_tick(&sc->sc_mii); 848 splx(s); 849 850 callout_schedule(&sc->sc_mii_callout, hz); 851 } 852 853 /* 854 * Fixup the clock source on the EPIC. 855 */ 856 static void 857 epic_fixup_clock_source(struct epic_softc *sc) 858 { 859 int i; 860 861 /* 862 * According to SMC Application Note 7-15, the EPIC's clock 863 * source is incorrect following a reset. This manifests itself 864 * as failure to recognize when host software has written to 865 * a register on the EPIC. The appnote recommends issuing at 866 * least 16 consecutive writes to the CLOCK TEST bit to correctly 867 * configure the clock source. 868 */ 869 for (i = 0; i < 16; i++) 870 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 871 TEST_CLOCKTEST); 872 } 873 874 /* 875 * Perform a soft reset on the EPIC. 876 */ 877 static void 878 epic_reset(struct epic_softc *sc) 879 { 880 881 epic_fixup_clock_source(sc); 882 883 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 884 delay(100); 885 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 886 delay(100); 887 888 epic_fixup_clock_source(sc); 889 } 890 891 /* 892 * Initialize the interface. Must be called at splnet(). 893 */ 894 static int 895 epic_init(struct ifnet *ifp) 896 { 897 struct epic_softc *sc = ifp->if_softc; 898 bus_space_tag_t st = sc->sc_st; 899 bus_space_handle_t sh = sc->sc_sh; 900 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 901 struct epic_txdesc *txd; 902 struct epic_descsoft *ds; 903 uint32_t genctl, reg0; 904 int i, error = 0; 905 906 /* 907 * Cancel any pending I/O. 908 */ 909 epic_stop(ifp, 0); 910 911 /* 912 * Reset the EPIC to a known state. 913 */ 914 epic_reset(sc); 915 916 /* 917 * Magical mystery initialization. 918 */ 919 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 920 921 /* 922 * Initialize the EPIC genctl register: 923 * 924 * - 64 byte receive FIFO threshold 925 * - automatic advance to next receive frame 926 */ 927 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 928 #if BYTE_ORDER == BIG_ENDIAN 929 genctl |= GENCTL_BIG_ENDIAN; 930 #endif 931 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 932 933 /* 934 * Reset the MII bus and PHY. 935 */ 936 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 937 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 938 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 939 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 940 delay(100); 941 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 942 delay(1000); 943 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 944 945 /* 946 * Initialize Ethernet address. 947 */ 948 reg0 = enaddr[1] << 8 | enaddr[0]; 949 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 950 reg0 = enaddr[3] << 8 | enaddr[2]; 951 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 952 reg0 = enaddr[5] << 8 | enaddr[4]; 953 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 954 955 /* 956 * Initialize receive control. Remember the external buffer 957 * size setting. 958 */ 959 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 960 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 961 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 962 if (ifp->if_flags & IFF_PROMISC) 963 reg0 |= RXCON_PROMISCMODE; 964 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 965 966 /* Set the current media. */ 967 if ((error = epic_mediachange(ifp)) != 0) 968 goto out; 969 970 /* Set up the multicast hash table. */ 971 epic_set_mchash(sc); 972 973 /* 974 * Initialize the transmit descriptor ring. txlast is initialized 975 * to the end of the list so that it will wrap around to the first 976 * descriptor when the first packet is transmitted. 977 */ 978 for (i = 0; i < EPIC_NTXDESC; i++) { 979 txd = EPIC_CDTX(sc, i); 980 memset(txd, 0, sizeof(struct epic_txdesc)); 981 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 982 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 983 EPIC_CDTXSYNC(sc, i, 984 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 985 } 986 sc->sc_txpending = 0; 987 sc->sc_txdirty = 0; 988 sc->sc_txlast = EPIC_NTXDESC - 1; 989 990 /* 991 * Initialize the receive descriptor ring. 992 */ 993 for (i = 0; i < EPIC_NRXDESC; i++) { 994 ds = EPIC_DSRX(sc, i); 995 if (ds->ds_mbuf == NULL) { 996 if ((error = epic_add_rxbuf(sc, i)) != 0) { 997 printf("%s: unable to allocate or map rx " 998 "buffer %d error = %d\n", 999 device_xname(sc->sc_dev), i, error); 1000 /* 1001 * XXX Should attempt to run with fewer receive 1002 * XXX buffers instead of just failing. 1003 */ 1004 epic_rxdrain(sc); 1005 goto out; 1006 } 1007 } else 1008 EPIC_INIT_RXDESC(sc, i); 1009 } 1010 sc->sc_rxptr = 0; 1011 1012 /* 1013 * Initialize the interrupt mask and enable interrupts. 1014 */ 1015 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1016 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1017 1018 /* 1019 * Give the transmit and receive rings to the EPIC. 1020 */ 1021 bus_space_write_4(st, sh, EPIC_PTCDAR, 1022 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1023 bus_space_write_4(st, sh, EPIC_PRCDAR, 1024 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1025 1026 /* 1027 * Set the EPIC in motion. 1028 */ 1029 bus_space_write_4(st, sh, EPIC_COMMAND, 1030 COMMAND_RXQUEUED | COMMAND_START_RX); 1031 1032 /* 1033 * ...all done! 1034 */ 1035 ifp->if_flags |= IFF_RUNNING; 1036 ifp->if_flags &= ~IFF_OACTIVE; 1037 1038 /* 1039 * Start the one second clock. 1040 */ 1041 callout_schedule(&sc->sc_mii_callout, hz); 1042 1043 /* 1044 * Attempt to start output on the interface. 1045 */ 1046 epic_start(ifp); 1047 1048 out: 1049 if (error) 1050 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1051 return error; 1052 } 1053 1054 /* 1055 * Drain the receive queue. 1056 */ 1057 static void 1058 epic_rxdrain(struct epic_softc *sc) 1059 { 1060 struct epic_descsoft *ds; 1061 int i; 1062 1063 for (i = 0; i < EPIC_NRXDESC; i++) { 1064 ds = EPIC_DSRX(sc, i); 1065 if (ds->ds_mbuf != NULL) { 1066 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1067 m_freem(ds->ds_mbuf); 1068 ds->ds_mbuf = NULL; 1069 } 1070 } 1071 } 1072 1073 /* 1074 * Stop transmission on the interface. 1075 */ 1076 static void 1077 epic_stop(struct ifnet *ifp, int disable) 1078 { 1079 struct epic_softc *sc = ifp->if_softc; 1080 bus_space_tag_t st = sc->sc_st; 1081 bus_space_handle_t sh = sc->sc_sh; 1082 struct epic_descsoft *ds; 1083 uint32_t reg; 1084 int i; 1085 1086 /* 1087 * Stop the one second clock. 1088 */ 1089 callout_stop(&sc->sc_mii_callout); 1090 1091 /* Down the MII. */ 1092 mii_down(&sc->sc_mii); 1093 1094 /* Paranoia... */ 1095 epic_fixup_clock_source(sc); 1096 1097 /* 1098 * Disable interrupts. 1099 */ 1100 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1101 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1102 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1103 1104 /* 1105 * Stop the DMA engine and take the receiver off-line. 1106 */ 1107 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1108 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1109 1110 /* 1111 * Release any queued transmit buffers. 1112 */ 1113 for (i = 0; i < EPIC_NTXDESC; i++) { 1114 ds = EPIC_DSTX(sc, i); 1115 if (ds->ds_mbuf != NULL) { 1116 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1117 m_freem(ds->ds_mbuf); 1118 ds->ds_mbuf = NULL; 1119 } 1120 } 1121 1122 /* 1123 * Mark the interface down and cancel the watchdog timer. 1124 */ 1125 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1126 ifp->if_timer = 0; 1127 1128 if (disable) 1129 epic_rxdrain(sc); 1130 } 1131 1132 /* 1133 * Read the EPIC Serial EEPROM. 1134 */ 1135 static void 1136 epic_read_eeprom(struct epic_softc *sc, int word, int wordcnt, uint16_t *data) 1137 { 1138 bus_space_tag_t st = sc->sc_st; 1139 bus_space_handle_t sh = sc->sc_sh; 1140 uint16_t reg; 1141 int i, x; 1142 1143 #define EEPROM_WAIT_READY(st, sh) \ 1144 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1145 /* nothing */ 1146 1147 /* 1148 * Enable the EEPROM. 1149 */ 1150 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1151 EEPROM_WAIT_READY(st, sh); 1152 1153 for (i = 0; i < wordcnt; i++) { 1154 /* Send CHIP SELECT for one clock tick. */ 1155 bus_space_write_4(st, sh, EPIC_EECTL, 1156 EECTL_ENABLE | EECTL_EECS); 1157 EEPROM_WAIT_READY(st, sh); 1158 1159 /* Shift in the READ opcode. */ 1160 for (x = 3; x > 0; x--) { 1161 reg = EECTL_ENABLE | EECTL_EECS; 1162 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1163 reg |= EECTL_EEDI; 1164 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1165 EEPROM_WAIT_READY(st, sh); 1166 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1167 EEPROM_WAIT_READY(st, sh); 1168 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1169 EEPROM_WAIT_READY(st, sh); 1170 } 1171 1172 /* Shift in address. */ 1173 for (x = 6; x > 0; x--) { 1174 reg = EECTL_ENABLE | EECTL_EECS; 1175 if ((word + i) & (1 << (x - 1))) 1176 reg |= EECTL_EEDI; 1177 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1178 EEPROM_WAIT_READY(st, sh); 1179 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1180 EEPROM_WAIT_READY(st, sh); 1181 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1182 EEPROM_WAIT_READY(st, sh); 1183 } 1184 1185 /* Shift out data. */ 1186 reg = EECTL_ENABLE | EECTL_EECS; 1187 data[i] = 0; 1188 for (x = 16; x > 0; x--) { 1189 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1190 EEPROM_WAIT_READY(st, sh); 1191 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1192 data[i] |= (1 << (x - 1)); 1193 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1194 EEPROM_WAIT_READY(st, sh); 1195 } 1196 1197 /* Clear CHIP SELECT. */ 1198 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1199 EEPROM_WAIT_READY(st, sh); 1200 } 1201 1202 /* 1203 * Disable the EEPROM. 1204 */ 1205 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1206 1207 #undef EEPROM_WAIT_READY 1208 } 1209 1210 /* 1211 * Add a receive buffer to the indicated descriptor. 1212 */ 1213 static int 1214 epic_add_rxbuf(struct epic_softc *sc, int idx) 1215 { 1216 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1217 struct mbuf *m; 1218 int error; 1219 1220 MGETHDR(m, M_DONTWAIT, MT_DATA); 1221 if (m == NULL) 1222 return ENOBUFS; 1223 1224 MCLGET(m, M_DONTWAIT); 1225 if ((m->m_flags & M_EXT) == 0) { 1226 m_freem(m); 1227 return ENOBUFS; 1228 } 1229 1230 if (ds->ds_mbuf != NULL) 1231 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1232 1233 ds->ds_mbuf = m; 1234 1235 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1236 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1237 BUS_DMA_READ | BUS_DMA_NOWAIT); 1238 if (error) { 1239 printf("%s: can't load rx DMA map %d, error = %d\n", 1240 device_xname(sc->sc_dev), idx, error); 1241 panic("%s", __func__); /* XXX */ 1242 } 1243 1244 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1245 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1246 1247 EPIC_INIT_RXDESC(sc, idx); 1248 1249 return 0; 1250 } 1251 1252 /* 1253 * Set the EPIC multicast hash table. 1254 * 1255 * NOTE: We rely on a recently-updated mii_media_active here! 1256 */ 1257 static void 1258 epic_set_mchash(struct epic_softc *sc) 1259 { 1260 struct ethercom *ec = &sc->sc_ethercom; 1261 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1262 struct ether_multi *enm; 1263 struct ether_multistep step; 1264 uint32_t hash, mchash[4]; 1265 1266 /* 1267 * Set up the multicast address filter by passing all multicast 1268 * addresses through a CRC generator, and then using the low-order 1269 * 6 bits as an index into the 64 bit multicast hash table (only 1270 * the lower 16 bits of each 32 bit multicast hash register are 1271 * valid). The high order bits select the register, while the 1272 * rest of the bits select the bit within the register. 1273 */ 1274 1275 if (ifp->if_flags & IFF_PROMISC) 1276 goto allmulti; 1277 1278 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1279 /* XXX hardware bug in 10Mbps mode. */ 1280 goto allmulti; 1281 } 1282 1283 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1284 1285 ETHER_LOCK(ec); 1286 ETHER_FIRST_MULTI(step, ec, enm); 1287 while (enm != NULL) { 1288 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1289 /* 1290 * We must listen to a range of multicast addresses. 1291 * For now, just accept all multicasts, rather than 1292 * trying to set only those filter bits needed to match 1293 * the range. (At this time, the only use of address 1294 * ranges is for IP multicast routing, for which the 1295 * range is big enough to require all bits set.) 1296 */ 1297 ETHER_UNLOCK(ec); 1298 goto allmulti; 1299 } 1300 1301 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1302 hash >>= 26; 1303 1304 /* Set the corresponding bit in the hash table. */ 1305 mchash[hash >> 4] |= 1 << (hash & 0xf); 1306 1307 ETHER_NEXT_MULTI(step, enm); 1308 } 1309 ETHER_UNLOCK(ec); 1310 1311 ifp->if_flags &= ~IFF_ALLMULTI; 1312 goto sethash; 1313 1314 allmulti: 1315 ifp->if_flags |= IFF_ALLMULTI; 1316 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1317 1318 sethash: 1319 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1320 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1321 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1322 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1323 } 1324 1325 /* 1326 * Wait for the MII to become ready. 1327 */ 1328 static int 1329 epic_mii_wait(struct epic_softc *sc, uint32_t rw) 1330 { 1331 int i; 1332 1333 for (i = 0; i < 50; i++) { 1334 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1335 == 0) 1336 break; 1337 delay(2); 1338 } 1339 if (i == 50) { 1340 printf("%s: MII timed out\n", device_xname(sc->sc_dev)); 1341 return ETIMEDOUT; 1342 } 1343 1344 return 0; 1345 } 1346 1347 /* 1348 * Read from the MII. 1349 */ 1350 static int 1351 epic_mii_read(device_t self, int phy, int reg, uint16_t *val) 1352 { 1353 struct epic_softc *sc = device_private(self); 1354 int rv; 1355 1356 if ((rv = epic_mii_wait(sc, MMCTL_WRITE)) != 0) 1357 return rv; 1358 1359 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1360 MMCTL_ARG(phy, reg, MMCTL_READ)); 1361 1362 if ((rv = epic_mii_wait(sc, MMCTL_READ)) != 0) 1363 return rv; 1364 1365 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) 1366 & MMDATA_MASK; 1367 return 0; 1368 } 1369 1370 /* 1371 * Write to the MII. 1372 */ 1373 static int 1374 epic_mii_write(device_t self, int phy, int reg, uint16_t val) 1375 { 1376 struct epic_softc *sc = device_private(self); 1377 int rv; 1378 1379 if ((rv = epic_mii_wait(sc, MMCTL_WRITE)) != 0) 1380 return rv; 1381 1382 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1383 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1384 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1385 1386 return 0; 1387 } 1388 1389 /* 1390 * Callback from PHY when media changes. 1391 */ 1392 static void 1393 epic_statchg(struct ifnet *ifp) 1394 { 1395 struct epic_softc *sc = ifp->if_softc; 1396 uint32_t txcon, miicfg; 1397 1398 /* 1399 * Update loopback bits in TXCON to reflect duplex mode. 1400 */ 1401 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1402 if (sc->sc_mii.mii_media_active & IFM_FDX) 1403 txcon |= (TXCON_LOOPBACK_D1 | TXCON_LOOPBACK_D2); 1404 else 1405 txcon &= ~(TXCON_LOOPBACK_D1 | TXCON_LOOPBACK_D2); 1406 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1407 1408 /* On some cards we need manualy set fullduplex led */ 1409 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1410 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1411 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1412 miicfg |= MIICFG_ENABLE; 1413 else 1414 miicfg &= ~MIICFG_ENABLE; 1415 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1416 } 1417 1418 /* 1419 * There is a multicast filter bug in 10Mbps mode. Kick the 1420 * multicast filter in case the speed changed. 1421 */ 1422 epic_set_mchash(sc); 1423 } 1424 1425 /* 1426 * Callback from ifmedia to request new media setting. 1427 * 1428 * XXX Looks to me like some of this complexity should move into 1429 * XXX one or two custom PHY drivers. --dyoung 1430 */ 1431 static int 1432 epic_mediachange(struct ifnet *ifp) 1433 { 1434 struct epic_softc *sc = ifp->if_softc; 1435 struct mii_data *mii = &sc->sc_mii; 1436 struct ifmedia *ifm = &mii->mii_media; 1437 int media = ifm->ifm_cur->ifm_media; 1438 uint32_t miicfg; 1439 struct mii_softc *miisc; 1440 int rc; 1441 uint16_t cfg; 1442 1443 if ((ifp->if_flags & IFF_UP) == 0) 1444 return 0; 1445 1446 if (IFM_INST(media) != sc->sc_serinst) { 1447 /* If we're not selecting serial interface, select MII mode */ 1448 #ifdef EPICMEDIADEBUG 1449 printf("%s: parallel mode\n", ifp->if_xname); 1450 #endif 1451 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1452 miicfg &= ~MIICFG_SERMODEENA; 1453 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1454 } 1455 1456 if ((rc = mii_mediachg(mii)) == ENXIO) 1457 rc = 0; 1458 1459 if (IFM_INST(media) == sc->sc_serinst) { 1460 /* select serial interface */ 1461 #ifdef EPICMEDIADEBUG 1462 printf("%s: serial mode\n", ifp->if_xname); 1463 #endif 1464 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1465 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1466 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1467 1468 /* There is no driver to fill this */ 1469 mii->mii_media_active = media; 1470 mii->mii_media_status = 0; 1471 1472 epic_statchg(mii->mii_ifp); 1473 return 0; 1474 } 1475 1476 /* Lookup selected PHY */ 1477 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1478 if (IFM_INST(media) == miisc->mii_inst) 1479 break; 1480 } 1481 if (!miisc) { 1482 printf("%s: can't happen\n", __func__); /* ??? panic */ 1483 return 0; 1484 } 1485 #ifdef EPICMEDIADEBUG 1486 printf("%s: using phy %s\n", ifp->if_xname, 1487 device_xname(miisc->mii_dev)); 1488 #endif 1489 1490 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1491 /* XXX XXX assume it's a Level1 - should check */ 1492 1493 /* We have to powerup fiber transceivers */ 1494 PHY_READ(miisc, MII_LXTPHY_CONFIG, &cfg); 1495 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1496 #ifdef EPICMEDIADEBUG 1497 printf("%s: power up fiber\n", ifp->if_xname); 1498 #endif 1499 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1500 } else { 1501 #ifdef EPICMEDIADEBUG 1502 printf("%s: power down fiber\n", ifp->if_xname); 1503 #endif 1504 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1505 } 1506 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1507 } 1508 1509 return rc; 1510 } 1511
Indexes created Wed Sep 24 05:09:52 GMT 2025