smc83c170.c revision 1.94
1 /* $NetBSD: smc83c170.c,v 1.94 2020/03/12 03:01:46 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the Standard Microsystems Corp. 83C170 35 * Ethernet PCI Integrated Controller (EPIC/100). 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.94 2020/03/12 03:01:46 thorpej Exp $"); 40 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/miivar.h> 64 #include <dev/mii/lxtphyreg.h> 65 66 #include <dev/ic/smc83c170reg.h> 67 #include <dev/ic/smc83c170var.h> 68 69 static void epic_start(struct ifnet *); 70 static void epic_watchdog(struct ifnet *); 71 static int epic_ioctl(struct ifnet *, u_long, void *); 72 static int epic_init(struct ifnet *); 73 static void epic_stop(struct ifnet *, int); 74 75 static bool epic_shutdown(device_t, int); 76 77 static void epic_reset(struct epic_softc *); 78 static void epic_rxdrain(struct epic_softc *); 79 static int epic_add_rxbuf(struct epic_softc *, int); 80 static void epic_read_eeprom(struct epic_softc *, int, int, uint16_t *); 81 static void epic_set_mchash(struct epic_softc *); 82 static void epic_fixup_clock_source(struct epic_softc *); 83 static int epic_mii_read(device_t, int, int, uint16_t *); 84 static int epic_mii_write(device_t, int, int, uint16_t); 85 static int epic_mii_wait(struct epic_softc *, uint32_t); 86 static void epic_tick(void *); 87 88 static void epic_statchg(struct ifnet *); 89 static int epic_mediachange(struct ifnet *); 90 91 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 92 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 93 94 int epic_copy_small = 0; 95 96 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 97 98 /* 99 * Attach an EPIC interface to the system. 100 */ 101 void 102 epic_attach(struct epic_softc *sc) 103 { 104 bus_space_tag_t st = sc->sc_st; 105 bus_space_handle_t sh = sc->sc_sh; 106 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 107 struct mii_data * const mii = &sc->sc_mii; 108 int rseg, error, miiflags; 109 u_int i; 110 bus_dma_segment_t seg; 111 uint8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 112 uint16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 113 char *nullbuf; 114 115 callout_init(&sc->sc_mii_callout, 0); 116 callout_setfunc(&sc->sc_mii_callout, epic_tick, sc); 117 118 /* 119 * Allocate the control data structures, and create and load the 120 * DMA map for it. 121 */ 122 if ((error = bus_dmamem_alloc(sc->sc_dmat, 123 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0, 124 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 125 aprint_error_dev(sc->sc_dev, 126 "unable to allocate control data, error = %d\n", error); 127 goto fail_0; 128 } 129 130 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 131 sizeof(struct epic_control_data) + ETHER_PAD_LEN, 132 (void **)&sc->sc_control_data, 133 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 134 aprint_error_dev(sc->sc_dev, 135 "unable to map control data, error = %d\n", error); 136 goto fail_1; 137 } 138 nullbuf = 139 (char *)sc->sc_control_data + sizeof(struct epic_control_data); 140 memset(nullbuf, 0, ETHER_PAD_LEN); 141 142 if ((error = bus_dmamap_create(sc->sc_dmat, 143 sizeof(struct epic_control_data), 1, 144 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 145 &sc->sc_cddmamap)) != 0) { 146 aprint_error_dev(sc->sc_dev, 147 "unable to create control data DMA map, error = %d\n", 148 error); 149 goto fail_2; 150 } 151 152 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 153 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 154 BUS_DMA_NOWAIT)) != 0) { 155 aprint_error_dev(sc->sc_dev, 156 "unable to load control data DMA map, error = %d\n", 157 error); 158 goto fail_3; 159 } 160 161 /* 162 * Create the transmit buffer DMA maps. 163 */ 164 for (i = 0; i < EPIC_NTXDESC; i++) { 165 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 166 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 167 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 168 aprint_error_dev(sc->sc_dev, 169 "unable to create tx DMA map %d, error = %d\n", 170 i, error); 171 goto fail_4; 172 } 173 } 174 175 /* 176 * Create the receive buffer DMA maps. 177 */ 178 for (i = 0; i < EPIC_NRXDESC; i++) { 179 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 180 MCLBYTES, 0, BUS_DMA_NOWAIT, 181 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 182 aprint_error_dev(sc->sc_dev, 183 "unable to create rx DMA map %d, error = %d\n", 184 i, error); 185 goto fail_5; 186 } 187 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 188 } 189 190 /* 191 * create and map the pad buffer 192 */ 193 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 194 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) { 195 aprint_error_dev(sc->sc_dev, 196 "unable to create pad buffer DMA map, error = %d\n", error); 197 goto fail_5; 198 } 199 200 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 201 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "unable to load pad buffer DMA map, error = %d\n", error); 204 goto fail_6; 205 } 206 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 207 BUS_DMASYNC_PREWRITE); 208 209 /* 210 * Bring the chip out of low-power mode and reset it to a known state. 211 */ 212 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 213 epic_reset(sc); 214 215 /* 216 * Read the Ethernet address from the EEPROM. 217 */ 218 epic_read_eeprom(sc, 0, __arraycount(myea), myea); 219 for (i = 0; i < __arraycount(myea); i++) { 220 enaddr[i * 2] = myea[i] & 0xff; 221 enaddr[i * 2 + 1] = myea[i] >> 8; 222 } 223 224 /* 225 * ...and the device name. 226 */ 227 epic_read_eeprom(sc, 0x2c, __arraycount(mydevname), mydevname); 228 for (i = 0; i < __arraycount(mydevname); i++) { 229 devname[i * 2] = mydevname[i] & 0xff; 230 devname[i * 2 + 1] = mydevname[i] >> 8; 231 } 232 233 devname[sizeof(mydevname)] = '\0'; 234 for (i = sizeof(mydevname) ; i > 0; i--) { 235 if (devname[i - 1] == ' ') 236 devname[i - 1] = '\0'; 237 else 238 break; 239 } 240 241 aprint_normal_dev(sc->sc_dev, "%s, Ethernet address %s\n", 242 devname, ether_sprintf(enaddr)); 243 244 miiflags = 0; 245 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 246 miiflags |= MIIF_HAVEFIBER; 247 248 /* 249 * Initialize our media structures and probe the MII. 250 */ 251 mii->mii_ifp = ifp; 252 mii->mii_readreg = epic_mii_read; 253 mii->mii_writereg = epic_mii_write; 254 mii->mii_statchg = epic_statchg; 255 256 sc->sc_ethercom.ec_mii = mii; 257 ifmedia_init(&mii->mii_media, IFM_IMASK, epic_mediachange, 258 ether_mediastatus); 259 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 260 MII_OFFSET_ANY, miiflags); 261 if (LIST_EMPTY(&mii->mii_phys)) { 262 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 263 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 264 } else 265 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 266 267 if (sc->sc_hwflags & EPIC_HAS_BNC) { 268 /* use the next free media instance */ 269 sc->sc_serinst = mii->mii_instance++; 270 ifmedia_add(&mii->mii_media, 271 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->sc_serinst), 272 0, NULL); 273 aprint_normal_dev(sc->sc_dev, "10base2/BNC\n"); 274 } else 275 sc->sc_serinst = -1; 276 277 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 278 ifp->if_softc = sc; 279 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 280 ifp->if_ioctl = epic_ioctl; 281 ifp->if_start = epic_start; 282 ifp->if_watchdog = epic_watchdog; 283 ifp->if_init = epic_init; 284 ifp->if_stop = epic_stop; 285 IFQ_SET_READY(&ifp->if_snd); 286 287 /* 288 * We can support 802.1Q VLAN-sized frames. 289 */ 290 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 291 292 /* 293 * Attach the interface. 294 */ 295 if_attach(ifp); 296 if_deferred_start_init(ifp, NULL); 297 ether_ifattach(ifp, enaddr); 298 299 /* 300 * Make sure the interface is shutdown during reboot. 301 */ 302 if (pmf_device_register1(sc->sc_dev, NULL, NULL, epic_shutdown)) 303 pmf_class_network_register(sc->sc_dev, ifp); 304 else 305 aprint_error_dev(sc->sc_dev, 306 "couldn't establish power handler\n"); 307 308 return; 309 310 /* 311 * Free any resources we've allocated during the failed attach 312 * attempt. Do this in reverse order and fall through. 313 */ 314 fail_6: 315 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 316 fail_5: 317 for (i = 0; i < EPIC_NRXDESC; i++) { 318 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 319 bus_dmamap_destroy(sc->sc_dmat, 320 EPIC_DSRX(sc, i)->ds_dmamap); 321 } 322 fail_4: 323 for (i = 0; i < EPIC_NTXDESC; i++) { 324 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 325 bus_dmamap_destroy(sc->sc_dmat, 326 EPIC_DSTX(sc, i)->ds_dmamap); 327 } 328 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 329 fail_3: 330 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 331 fail_2: 332 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 333 sizeof(struct epic_control_data)); 334 fail_1: 335 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 336 fail_0: 337 return; 338 } 339 340 /* 341 * Shutdown hook. Make sure the interface is stopped at reboot. 342 */ 343 static bool 344 epic_shutdown(device_t self, int howto) 345 { 346 struct epic_softc *sc = device_private(self); 347 348 epic_stop(&sc->sc_ethercom.ec_if, 1); 349 350 return true; 351 } 352 353 /* 354 * Start packet transmission on the interface. 355 * [ifnet interface function] 356 */ 357 static void 358 epic_start(struct ifnet *ifp) 359 { 360 struct epic_softc *sc = ifp->if_softc; 361 struct mbuf *m0, *m; 362 struct epic_txdesc *txd; 363 struct epic_descsoft *ds; 364 struct epic_fraglist *fr; 365 bus_dmamap_t dmamap; 366 int error, firsttx, nexttx, opending, seg; 367 u_int len; 368 369 /* 370 * Remember the previous txpending and the first transmit 371 * descriptor we use. 372 */ 373 opending = sc->sc_txpending; 374 firsttx = EPIC_NEXTTX(sc->sc_txlast); 375 376 /* 377 * Loop through the send queue, setting up transmit descriptors 378 * until we drain the queue, or use up all available transmit 379 * descriptors. 380 */ 381 while (sc->sc_txpending < EPIC_NTXDESC) { 382 /* 383 * Grab a packet off the queue. 384 */ 385 IFQ_POLL(&ifp->if_snd, m0); 386 if (m0 == NULL) 387 break; 388 m = NULL; 389 390 /* 391 * Get the last and next available transmit descriptor. 392 */ 393 nexttx = EPIC_NEXTTX(sc->sc_txlast); 394 txd = EPIC_CDTX(sc, nexttx); 395 fr = EPIC_CDFL(sc, nexttx); 396 ds = EPIC_DSTX(sc, nexttx); 397 dmamap = ds->ds_dmamap; 398 399 /* 400 * Load the DMA map. If this fails, the packet either 401 * didn't fit in the alloted number of frags, or we were 402 * short on resources. In this case, we'll copy and try 403 * again. 404 */ 405 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 406 BUS_DMA_WRITE | BUS_DMA_NOWAIT)) != 0 || 407 (m0->m_pkthdr.len < ETHER_PAD_LEN && 408 dmamap-> dm_nsegs == EPIC_NFRAGS)) { 409 if (error == 0) 410 bus_dmamap_unload(sc->sc_dmat, dmamap); 411 412 MGETHDR(m, M_DONTWAIT, MT_DATA); 413 if (m == NULL) { 414 printf("%s: unable to allocate Tx mbuf\n", 415 device_xname(sc->sc_dev)); 416 break; 417 } 418 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 419 if (m0->m_pkthdr.len > MHLEN) { 420 MCLGET(m, M_DONTWAIT); 421 if ((m->m_flags & M_EXT) == 0) { 422 printf("%s: unable to allocate Tx " 423 "cluster\n", 424 device_xname(sc->sc_dev)); 425 m_freem(m); 426 break; 427 } 428 } 429 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 430 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 431 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 432 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 433 if (error) { 434 printf("%s: unable to load Tx buffer, " 435 "error = %d\n", device_xname(sc->sc_dev), 436 error); 437 break; 438 } 439 } 440 IFQ_DEQUEUE(&ifp->if_snd, m0); 441 if (m != NULL) { 442 m_freem(m0); 443 m0 = m; 444 } 445 446 /* Initialize the fraglist. */ 447 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 448 fr->ef_frags[seg].ef_addr = 449 dmamap->dm_segs[seg].ds_addr; 450 fr->ef_frags[seg].ef_length = 451 dmamap->dm_segs[seg].ds_len; 452 } 453 len = m0->m_pkthdr.len; 454 if (len < ETHER_PAD_LEN) { 455 fr->ef_frags[seg].ef_addr = sc->sc_nulldma; 456 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len; 457 len = ETHER_PAD_LEN; 458 seg++; 459 } 460 fr->ef_nfrags = seg; 461 462 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 463 464 /* Sync the DMA map. */ 465 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 466 BUS_DMASYNC_PREWRITE); 467 468 /* 469 * Store a pointer to the packet so we can free it later. 470 */ 471 ds->ds_mbuf = m0; 472 473 /* 474 * Fill in the transmit descriptor. 475 */ 476 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 477 478 /* 479 * If this is the first descriptor we're enqueueing, 480 * don't give it to the EPIC yet. That could cause 481 * a race condition. We'll do it below. 482 */ 483 if (nexttx == firsttx) 484 txd->et_txstatus = TXSTAT_TXLENGTH(len); 485 else 486 txd->et_txstatus = 487 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER; 488 489 EPIC_CDTXSYNC(sc, nexttx, 490 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 491 492 /* Advance the tx pointer. */ 493 sc->sc_txpending++; 494 sc->sc_txlast = nexttx; 495 496 /* 497 * Pass the packet to any BPF listeners. 498 */ 499 bpf_mtap(ifp, m0, BPF_D_OUT); 500 } 501 502 if (sc->sc_txpending == EPIC_NTXDESC) { 503 /* No more slots left; notify upper layer. */ 504 ifp->if_flags |= IFF_OACTIVE; 505 } 506 507 if (sc->sc_txpending != opending) { 508 /* 509 * We enqueued packets. If the transmitter was idle, 510 * reset the txdirty pointer. 511 */ 512 if (opending == 0) 513 sc->sc_txdirty = firsttx; 514 515 /* 516 * Cause a transmit interrupt to happen on the 517 * last packet we enqueued. 518 */ 519 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 520 EPIC_CDTXSYNC(sc, sc->sc_txlast, 521 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 522 523 /* 524 * The entire packet chain is set up. Give the 525 * first descriptor to the EPIC now. 526 */ 527 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER; 528 EPIC_CDTXSYNC(sc, firsttx, 529 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 530 531 /* Start the transmitter. */ 532 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 533 COMMAND_TXQUEUED); 534 535 /* Set a watchdog timer in case the chip flakes out. */ 536 ifp->if_timer = 5; 537 } 538 } 539 540 /* 541 * Watchdog timer handler. 542 * [ifnet interface function] 543 */ 544 static void 545 epic_watchdog(struct ifnet *ifp) 546 { 547 struct epic_softc *sc = ifp->if_softc; 548 549 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 550 if_statinc(ifp, if_oerrors); 551 552 (void)epic_init(ifp); 553 } 554 555 /* 556 * Handle control requests from the operator. 557 * [ifnet interface function] 558 */ 559 static int 560 epic_ioctl(struct ifnet *ifp, u_long cmd, void *data) 561 { 562 struct epic_softc *sc = ifp->if_softc; 563 int s, error; 564 565 s = splnet(); 566 567 error = ether_ioctl(ifp, cmd, data); 568 if (error == ENETRESET) { 569 /* 570 * Multicast list has changed; set the hardware filter 571 * accordingly. Update our idea of the current media; 572 * epic_set_mchash() needs to know what it is. 573 */ 574 if (ifp->if_flags & IFF_RUNNING) { 575 mii_pollstat(&sc->sc_mii); 576 epic_set_mchash(sc); 577 } 578 error = 0; 579 } 580 581 splx(s); 582 return error; 583 } 584 585 /* 586 * Interrupt handler. 587 */ 588 int 589 epic_intr(void *arg) 590 { 591 struct epic_softc *sc = arg; 592 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 593 struct epic_rxdesc *rxd; 594 struct epic_txdesc *txd; 595 struct epic_descsoft *ds; 596 struct mbuf *m; 597 uint32_t intstat, rxstatus, txstatus; 598 int i, claimed = 0; 599 u_int len; 600 601 top: 602 /* 603 * Get the interrupt status from the EPIC. 604 */ 605 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 606 if ((intstat & INTSTAT_INT_ACTV) == 0) 607 return claimed; 608 609 claimed = 1; 610 611 /* 612 * Acknowledge the interrupt. 613 */ 614 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 615 intstat & INTMASK); 616 617 /* 618 * Check for receive interrupts. 619 */ 620 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 621 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 622 rxd = EPIC_CDRX(sc, i); 623 ds = EPIC_DSRX(sc, i); 624 625 EPIC_CDRXSYNC(sc, i, 626 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 627 628 rxstatus = rxd->er_rxstatus; 629 if (rxstatus & ER_RXSTAT_OWNER) { 630 /* 631 * We have processed all of the 632 * receive buffers. 633 */ 634 break; 635 } 636 637 /* 638 * Make sure the packet arrived intact. If an error 639 * occurred, update stats and reset the descriptor. 640 * The buffer will be reused the next time the 641 * descriptor comes up in the ring. 642 */ 643 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 644 if (rxstatus & ER_RXSTAT_CRCERROR) 645 printf("%s: CRC error\n", 646 device_xname(sc->sc_dev)); 647 if (rxstatus & ER_RXSTAT_ALIGNERROR) 648 printf("%s: alignment error\n", 649 device_xname(sc->sc_dev)); 650 if_statinc(ifp, if_ierrors); 651 EPIC_INIT_RXDESC(sc, i); 652 continue; 653 } 654 655 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 656 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 657 658 /* 659 * The EPIC includes the CRC with every packet; 660 * trim it. 661 */ 662 len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN; 663 664 if (len < sizeof(struct ether_header)) { 665 /* 666 * Runt packet; drop it now. 667 */ 668 if_statinc(ifp, if_ierrors); 669 EPIC_INIT_RXDESC(sc, i); 670 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 671 ds->ds_dmamap->dm_mapsize, 672 BUS_DMASYNC_PREREAD); 673 continue; 674 } 675 676 /* 677 * If the packet is small enough to fit in a 678 * single header mbuf, allocate one and copy 679 * the data into it. This greatly reduces 680 * memory consumption when we receive lots 681 * of small packets. 682 * 683 * Otherwise, we add a new buffer to the receive 684 * chain. If this fails, we drop the packet and 685 * recycle the old buffer. 686 */ 687 if (epic_copy_small != 0 && len <= MHLEN) { 688 MGETHDR(m, M_DONTWAIT, MT_DATA); 689 if (m == NULL) 690 goto dropit; 691 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 692 memcpy(mtod(m, void *), 693 mtod(ds->ds_mbuf, void *), len); 694 EPIC_INIT_RXDESC(sc, i); 695 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 696 ds->ds_dmamap->dm_mapsize, 697 BUS_DMASYNC_PREREAD); 698 } else { 699 m = ds->ds_mbuf; 700 if (epic_add_rxbuf(sc, i) != 0) { 701 dropit: 702 if_statinc(ifp, if_ierrors); 703 EPIC_INIT_RXDESC(sc, i); 704 bus_dmamap_sync(sc->sc_dmat, 705 ds->ds_dmamap, 0, 706 ds->ds_dmamap->dm_mapsize, 707 BUS_DMASYNC_PREREAD); 708 continue; 709 } 710 } 711 712 m_set_rcvif(m, ifp); 713 m->m_pkthdr.len = m->m_len = len; 714 715 /* Pass it on. */ 716 if_percpuq_enqueue(ifp->if_percpuq, m); 717 } 718 719 /* Update the receive pointer. */ 720 sc->sc_rxptr = i; 721 722 /* 723 * Check for receive queue underflow. 724 */ 725 if (intstat & INTSTAT_RQE) { 726 printf("%s: receiver queue empty\n", 727 device_xname(sc->sc_dev)); 728 /* 729 * Ring is already built; just restart the 730 * receiver. 731 */ 732 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 733 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 734 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 735 COMMAND_RXQUEUED | COMMAND_START_RX); 736 } 737 } 738 739 /* 740 * Check for transmission complete interrupts. 741 */ 742 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 743 ifp->if_flags &= ~IFF_OACTIVE; 744 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 745 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 746 txd = EPIC_CDTX(sc, i); 747 ds = EPIC_DSTX(sc, i); 748 749 EPIC_CDTXSYNC(sc, i, 750 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 751 752 txstatus = txd->et_txstatus; 753 if (txstatus & ET_TXSTAT_OWNER) 754 break; 755 756 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 757 758 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 759 0, ds->ds_dmamap->dm_mapsize, 760 BUS_DMASYNC_POSTWRITE); 761 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 762 m_freem(ds->ds_mbuf); 763 ds->ds_mbuf = NULL; 764 765 /* 766 * Check for errors and collisions. 767 */ 768 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 769 if ((txstatus & ET_TXSTAT_PACKETTX) == 0) 770 if_statinc_ref(nsr, if_oerrors); 771 else 772 if_statinc_ref(nsr, if_opackets); 773 if (TXSTAT_COLLISIONS(txstatus)) 774 if_statadd_ref(nsr, if_collisions, 775 TXSTAT_COLLISIONS(txstatus)); 776 if (txstatus & ET_TXSTAT_CARSENSELOST) 777 printf("%s: lost carrier\n", 778 device_xname(sc->sc_dev)); 779 IF_STAT_PUTREF(ifp); 780 } 781 782 /* Update the dirty transmit buffer pointer. */ 783 sc->sc_txdirty = i; 784 785 /* 786 * Cancel the watchdog timer if there are no pending 787 * transmissions. 788 */ 789 if (sc->sc_txpending == 0) 790 ifp->if_timer = 0; 791 792 /* 793 * Kick the transmitter after a DMA underrun. 794 */ 795 if (intstat & INTSTAT_TXU) { 796 printf("%s: transmit underrun\n", 797 device_xname(sc->sc_dev)); 798 bus_space_write_4(sc->sc_st, sc->sc_sh, 799 EPIC_COMMAND, COMMAND_TXUGO); 800 if (sc->sc_txpending) 801 bus_space_write_4(sc->sc_st, sc->sc_sh, 802 EPIC_COMMAND, COMMAND_TXQUEUED); 803 } 804 805 /* 806 * Try to get more packets going. 807 */ 808 if_schedule_deferred_start(ifp); 809 } 810 811 /* 812 * Check for fatal interrupts. 813 */ 814 if (intstat & INTSTAT_FATAL_INT) { 815 if (intstat & INTSTAT_PTA) 816 printf("%s: PCI target abort error\n", 817 device_xname(sc->sc_dev)); 818 else if (intstat & INTSTAT_PMA) 819 printf("%s: PCI master abort error\n", 820 device_xname(sc->sc_dev)); 821 else if (intstat & INTSTAT_APE) 822 printf("%s: PCI address parity error\n", 823 device_xname(sc->sc_dev)); 824 else if (intstat & INTSTAT_DPE) 825 printf("%s: PCI data parity error\n", 826 device_xname(sc->sc_dev)); 827 else 828 printf("%s: unknown fatal error\n", 829 device_xname(sc->sc_dev)); 830 (void)epic_init(ifp); 831 } 832 833 /* 834 * Check for more interrupts. 835 */ 836 goto top; 837 } 838 839 /* 840 * One second timer, used to tick the MII. 841 */ 842 static void 843 epic_tick(void *arg) 844 { 845 struct epic_softc *sc = arg; 846 int s; 847 848 s = splnet(); 849 mii_tick(&sc->sc_mii); 850 splx(s); 851 852 callout_schedule(&sc->sc_mii_callout, hz); 853 } 854 855 /* 856 * Fixup the clock source on the EPIC. 857 */ 858 static void 859 epic_fixup_clock_source(struct epic_softc *sc) 860 { 861 int i; 862 863 /* 864 * According to SMC Application Note 7-15, the EPIC's clock 865 * source is incorrect following a reset. This manifests itself 866 * as failure to recognize when host software has written to 867 * a register on the EPIC. The appnote recommends issuing at 868 * least 16 consecutive writes to the CLOCK TEST bit to correctly 869 * configure the clock source. 870 */ 871 for (i = 0; i < 16; i++) 872 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 873 TEST_CLOCKTEST); 874 } 875 876 /* 877 * Perform a soft reset on the EPIC. 878 */ 879 static void 880 epic_reset(struct epic_softc *sc) 881 { 882 883 epic_fixup_clock_source(sc); 884 885 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 886 delay(100); 887 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 888 delay(100); 889 890 epic_fixup_clock_source(sc); 891 } 892 893 /* 894 * Initialize the interface. Must be called at splnet(). 895 */ 896 static int 897 epic_init(struct ifnet *ifp) 898 { 899 struct epic_softc *sc = ifp->if_softc; 900 bus_space_tag_t st = sc->sc_st; 901 bus_space_handle_t sh = sc->sc_sh; 902 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 903 struct epic_txdesc *txd; 904 struct epic_descsoft *ds; 905 uint32_t genctl, reg0; 906 int i, error = 0; 907 908 /* 909 * Cancel any pending I/O. 910 */ 911 epic_stop(ifp, 0); 912 913 /* 914 * Reset the EPIC to a known state. 915 */ 916 epic_reset(sc); 917 918 /* 919 * Magical mystery initialization. 920 */ 921 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 922 923 /* 924 * Initialize the EPIC genctl register: 925 * 926 * - 64 byte receive FIFO threshold 927 * - automatic advance to next receive frame 928 */ 929 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 930 #if BYTE_ORDER == BIG_ENDIAN 931 genctl |= GENCTL_BIG_ENDIAN; 932 #endif 933 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 934 935 /* 936 * Reset the MII bus and PHY. 937 */ 938 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 939 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 940 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 941 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 942 delay(100); 943 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 944 delay(1000); 945 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 946 947 /* 948 * Initialize Ethernet address. 949 */ 950 reg0 = enaddr[1] << 8 | enaddr[0]; 951 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 952 reg0 = enaddr[3] << 8 | enaddr[2]; 953 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 954 reg0 = enaddr[5] << 8 | enaddr[4]; 955 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 956 957 /* 958 * Initialize receive control. Remember the external buffer 959 * size setting. 960 */ 961 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 962 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 963 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 964 if (ifp->if_flags & IFF_PROMISC) 965 reg0 |= RXCON_PROMISCMODE; 966 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 967 968 /* Set the current media. */ 969 if ((error = epic_mediachange(ifp)) != 0) 970 goto out; 971 972 /* Set up the multicast hash table. */ 973 epic_set_mchash(sc); 974 975 /* 976 * Initialize the transmit descriptor ring. txlast is initialized 977 * to the end of the list so that it will wrap around to the first 978 * descriptor when the first packet is transmitted. 979 */ 980 for (i = 0; i < EPIC_NTXDESC; i++) { 981 txd = EPIC_CDTX(sc, i); 982 memset(txd, 0, sizeof(struct epic_txdesc)); 983 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 984 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 985 EPIC_CDTXSYNC(sc, i, 986 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 987 } 988 sc->sc_txpending = 0; 989 sc->sc_txdirty = 0; 990 sc->sc_txlast = EPIC_NTXDESC - 1; 991 992 /* 993 * Initialize the receive descriptor ring. 994 */ 995 for (i = 0; i < EPIC_NRXDESC; i++) { 996 ds = EPIC_DSRX(sc, i); 997 if (ds->ds_mbuf == NULL) { 998 if ((error = epic_add_rxbuf(sc, i)) != 0) { 999 printf("%s: unable to allocate or map rx " 1000 "buffer %d error = %d\n", 1001 device_xname(sc->sc_dev), i, error); 1002 /* 1003 * XXX Should attempt to run with fewer receive 1004 * XXX buffers instead of just failing. 1005 */ 1006 epic_rxdrain(sc); 1007 goto out; 1008 } 1009 } else 1010 EPIC_INIT_RXDESC(sc, i); 1011 } 1012 sc->sc_rxptr = 0; 1013 1014 /* 1015 * Initialize the interrupt mask and enable interrupts. 1016 */ 1017 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1018 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1019 1020 /* 1021 * Give the transmit and receive rings to the EPIC. 1022 */ 1023 bus_space_write_4(st, sh, EPIC_PTCDAR, 1024 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1025 bus_space_write_4(st, sh, EPIC_PRCDAR, 1026 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1027 1028 /* 1029 * Set the EPIC in motion. 1030 */ 1031 bus_space_write_4(st, sh, EPIC_COMMAND, 1032 COMMAND_RXQUEUED | COMMAND_START_RX); 1033 1034 /* 1035 * ...all done! 1036 */ 1037 ifp->if_flags |= IFF_RUNNING; 1038 ifp->if_flags &= ~IFF_OACTIVE; 1039 1040 /* 1041 * Start the one second clock. 1042 */ 1043 callout_schedule(&sc->sc_mii_callout, hz); 1044 1045 /* 1046 * Attempt to start output on the interface. 1047 */ 1048 epic_start(ifp); 1049 1050 out: 1051 if (error) 1052 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1053 return error; 1054 } 1055 1056 /* 1057 * Drain the receive queue. 1058 */ 1059 static void 1060 epic_rxdrain(struct epic_softc *sc) 1061 { 1062 struct epic_descsoft *ds; 1063 int i; 1064 1065 for (i = 0; i < EPIC_NRXDESC; i++) { 1066 ds = EPIC_DSRX(sc, i); 1067 if (ds->ds_mbuf != NULL) { 1068 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1069 m_freem(ds->ds_mbuf); 1070 ds->ds_mbuf = NULL; 1071 } 1072 } 1073 } 1074 1075 /* 1076 * Stop transmission on the interface. 1077 */ 1078 static void 1079 epic_stop(struct ifnet *ifp, int disable) 1080 { 1081 struct epic_softc *sc = ifp->if_softc; 1082 bus_space_tag_t st = sc->sc_st; 1083 bus_space_handle_t sh = sc->sc_sh; 1084 struct epic_descsoft *ds; 1085 uint32_t reg; 1086 int i; 1087 1088 /* 1089 * Stop the one second clock. 1090 */ 1091 callout_stop(&sc->sc_mii_callout); 1092 1093 /* Down the MII. */ 1094 mii_down(&sc->sc_mii); 1095 1096 /* Paranoia... */ 1097 epic_fixup_clock_source(sc); 1098 1099 /* 1100 * Disable interrupts. 1101 */ 1102 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1103 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1104 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1105 1106 /* 1107 * Stop the DMA engine and take the receiver off-line. 1108 */ 1109 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1110 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1111 1112 /* 1113 * Release any queued transmit buffers. 1114 */ 1115 for (i = 0; i < EPIC_NTXDESC; i++) { 1116 ds = EPIC_DSTX(sc, i); 1117 if (ds->ds_mbuf != NULL) { 1118 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1119 m_freem(ds->ds_mbuf); 1120 ds->ds_mbuf = NULL; 1121 } 1122 } 1123 1124 /* 1125 * Mark the interface down and cancel the watchdog timer. 1126 */ 1127 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1128 ifp->if_timer = 0; 1129 1130 if (disable) 1131 epic_rxdrain(sc); 1132 } 1133 1134 /* 1135 * Read the EPIC Serial EEPROM. 1136 */ 1137 static void 1138 epic_read_eeprom(struct epic_softc *sc, int word, int wordcnt, uint16_t *data) 1139 { 1140 bus_space_tag_t st = sc->sc_st; 1141 bus_space_handle_t sh = sc->sc_sh; 1142 uint16_t reg; 1143 int i, x; 1144 1145 #define EEPROM_WAIT_READY(st, sh) \ 1146 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1147 /* nothing */ 1148 1149 /* 1150 * Enable the EEPROM. 1151 */ 1152 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1153 EEPROM_WAIT_READY(st, sh); 1154 1155 for (i = 0; i < wordcnt; i++) { 1156 /* Send CHIP SELECT for one clock tick. */ 1157 bus_space_write_4(st, sh, EPIC_EECTL, 1158 EECTL_ENABLE | EECTL_EECS); 1159 EEPROM_WAIT_READY(st, sh); 1160 1161 /* Shift in the READ opcode. */ 1162 for (x = 3; x > 0; x--) { 1163 reg = EECTL_ENABLE | EECTL_EECS; 1164 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1165 reg |= EECTL_EEDI; 1166 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1167 EEPROM_WAIT_READY(st, sh); 1168 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1169 EEPROM_WAIT_READY(st, sh); 1170 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1171 EEPROM_WAIT_READY(st, sh); 1172 } 1173 1174 /* Shift in address. */ 1175 for (x = 6; x > 0; x--) { 1176 reg = EECTL_ENABLE | EECTL_EECS; 1177 if ((word + i) & (1 << (x - 1))) 1178 reg |= EECTL_EEDI; 1179 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1180 EEPROM_WAIT_READY(st, sh); 1181 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1182 EEPROM_WAIT_READY(st, sh); 1183 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1184 EEPROM_WAIT_READY(st, sh); 1185 } 1186 1187 /* Shift out data. */ 1188 reg = EECTL_ENABLE | EECTL_EECS; 1189 data[i] = 0; 1190 for (x = 16; x > 0; x--) { 1191 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1192 EEPROM_WAIT_READY(st, sh); 1193 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1194 data[i] |= (1 << (x - 1)); 1195 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1196 EEPROM_WAIT_READY(st, sh); 1197 } 1198 1199 /* Clear CHIP SELECT. */ 1200 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1201 EEPROM_WAIT_READY(st, sh); 1202 } 1203 1204 /* 1205 * Disable the EEPROM. 1206 */ 1207 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1208 1209 #undef EEPROM_WAIT_READY 1210 } 1211 1212 /* 1213 * Add a receive buffer to the indicated descriptor. 1214 */ 1215 static int 1216 epic_add_rxbuf(struct epic_softc *sc, int idx) 1217 { 1218 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1219 struct mbuf *m; 1220 int error; 1221 1222 MGETHDR(m, M_DONTWAIT, MT_DATA); 1223 if (m == NULL) 1224 return ENOBUFS; 1225 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1226 1227 MCLGET(m, M_DONTWAIT); 1228 if ((m->m_flags & M_EXT) == 0) { 1229 m_freem(m); 1230 return ENOBUFS; 1231 } 1232 1233 if (ds->ds_mbuf != NULL) 1234 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1235 1236 ds->ds_mbuf = m; 1237 1238 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1239 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1240 BUS_DMA_READ | BUS_DMA_NOWAIT); 1241 if (error) { 1242 printf("%s: can't load rx DMA map %d, error = %d\n", 1243 device_xname(sc->sc_dev), idx, error); 1244 panic("%s", __func__); /* XXX */ 1245 } 1246 1247 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1248 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1249 1250 EPIC_INIT_RXDESC(sc, idx); 1251 1252 return 0; 1253 } 1254 1255 /* 1256 * Set the EPIC multicast hash table. 1257 * 1258 * NOTE: We rely on a recently-updated mii_media_active here! 1259 */ 1260 static void 1261 epic_set_mchash(struct epic_softc *sc) 1262 { 1263 struct ethercom *ec = &sc->sc_ethercom; 1264 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1265 struct ether_multi *enm; 1266 struct ether_multistep step; 1267 uint32_t hash, mchash[4]; 1268 1269 /* 1270 * Set up the multicast address filter by passing all multicast 1271 * addresses through a CRC generator, and then using the low-order 1272 * 6 bits as an index into the 64 bit multicast hash table (only 1273 * the lower 16 bits of each 32 bit multicast hash register are 1274 * valid). The high order bits select the register, while the 1275 * rest of the bits select the bit within the register. 1276 */ 1277 1278 if (ifp->if_flags & IFF_PROMISC) 1279 goto allmulti; 1280 1281 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1282 /* XXX hardware bug in 10Mbps mode. */ 1283 goto allmulti; 1284 } 1285 1286 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1287 1288 ETHER_LOCK(ec); 1289 ETHER_FIRST_MULTI(step, ec, enm); 1290 while (enm != NULL) { 1291 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1292 /* 1293 * We must listen to a range of multicast addresses. 1294 * For now, just accept all multicasts, rather than 1295 * trying to set only those filter bits needed to match 1296 * the range. (At this time, the only use of address 1297 * ranges is for IP multicast routing, for which the 1298 * range is big enough to require all bits set.) 1299 */ 1300 ETHER_UNLOCK(ec); 1301 goto allmulti; 1302 } 1303 1304 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1305 hash >>= 26; 1306 1307 /* Set the corresponding bit in the hash table. */ 1308 mchash[hash >> 4] |= 1 << (hash & 0xf); 1309 1310 ETHER_NEXT_MULTI(step, enm); 1311 } 1312 ETHER_UNLOCK(ec); 1313 1314 ifp->if_flags &= ~IFF_ALLMULTI; 1315 goto sethash; 1316 1317 allmulti: 1318 ifp->if_flags |= IFF_ALLMULTI; 1319 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1320 1321 sethash: 1322 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1323 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1324 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1325 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1326 } 1327 1328 /* 1329 * Wait for the MII to become ready. 1330 */ 1331 static int 1332 epic_mii_wait(struct epic_softc *sc, uint32_t rw) 1333 { 1334 int i; 1335 1336 for (i = 0; i < 50; i++) { 1337 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1338 == 0) 1339 break; 1340 delay(2); 1341 } 1342 if (i == 50) { 1343 printf("%s: MII timed out\n", device_xname(sc->sc_dev)); 1344 return ETIMEDOUT; 1345 } 1346 1347 return 0; 1348 } 1349 1350 /* 1351 * Read from the MII. 1352 */ 1353 static int 1354 epic_mii_read(device_t self, int phy, int reg, uint16_t *val) 1355 { 1356 struct epic_softc *sc = device_private(self); 1357 int rv; 1358 1359 if ((rv = epic_mii_wait(sc, MMCTL_WRITE)) != 0) 1360 return rv; 1361 1362 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1363 MMCTL_ARG(phy, reg, MMCTL_READ)); 1364 1365 if ((rv = epic_mii_wait(sc, MMCTL_READ)) != 0) 1366 return rv; 1367 1368 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) 1369 & MMDATA_MASK; 1370 return 0; 1371 } 1372 1373 /* 1374 * Write to the MII. 1375 */ 1376 static int 1377 epic_mii_write(device_t self, int phy, int reg, uint16_t val) 1378 { 1379 struct epic_softc *sc = device_private(self); 1380 int rv; 1381 1382 if ((rv = epic_mii_wait(sc, MMCTL_WRITE)) != 0) 1383 return rv; 1384 1385 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1386 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1387 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1388 1389 return 0; 1390 } 1391 1392 /* 1393 * Callback from PHY when media changes. 1394 */ 1395 static void 1396 epic_statchg(struct ifnet *ifp) 1397 { 1398 struct epic_softc *sc = ifp->if_softc; 1399 uint32_t txcon, miicfg; 1400 1401 /* 1402 * Update loopback bits in TXCON to reflect duplex mode. 1403 */ 1404 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1405 if (sc->sc_mii.mii_media_active & IFM_FDX) 1406 txcon |= (TXCON_LOOPBACK_D1 | TXCON_LOOPBACK_D2); 1407 else 1408 txcon &= ~(TXCON_LOOPBACK_D1 | TXCON_LOOPBACK_D2); 1409 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1410 1411 /* On some cards we need manualy set fullduplex led */ 1412 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1413 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1414 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1415 miicfg |= MIICFG_ENABLE; 1416 else 1417 miicfg &= ~MIICFG_ENABLE; 1418 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1419 } 1420 1421 /* 1422 * There is a multicast filter bug in 10Mbps mode. Kick the 1423 * multicast filter in case the speed changed. 1424 */ 1425 epic_set_mchash(sc); 1426 } 1427 1428 /* 1429 * Callback from ifmedia to request new media setting. 1430 * 1431 * XXX Looks to me like some of this complexity should move into 1432 * XXX one or two custom PHY drivers. --dyoung 1433 */ 1434 static int 1435 epic_mediachange(struct ifnet *ifp) 1436 { 1437 struct epic_softc *sc = ifp->if_softc; 1438 struct mii_data *mii = &sc->sc_mii; 1439 struct ifmedia *ifm = &mii->mii_media; 1440 int media = ifm->ifm_cur->ifm_media; 1441 uint32_t miicfg; 1442 struct mii_softc *miisc; 1443 int rc; 1444 uint16_t cfg; 1445 1446 if ((ifp->if_flags & IFF_UP) == 0) 1447 return 0; 1448 1449 if (IFM_INST(media) != sc->sc_serinst) { 1450 /* If we're not selecting serial interface, select MII mode */ 1451 #ifdef EPICMEDIADEBUG 1452 printf("%s: parallel mode\n", ifp->if_xname); 1453 #endif 1454 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1455 miicfg &= ~MIICFG_SERMODEENA; 1456 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1457 } 1458 1459 if ((rc = mii_mediachg(mii)) == ENXIO) 1460 rc = 0; 1461 1462 if (IFM_INST(media) == sc->sc_serinst) { 1463 /* select serial interface */ 1464 #ifdef EPICMEDIADEBUG 1465 printf("%s: serial mode\n", ifp->if_xname); 1466 #endif 1467 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1468 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1469 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1470 1471 /* There is no driver to fill this */ 1472 mii->mii_media_active = media; 1473 mii->mii_media_status = 0; 1474 1475 epic_statchg(mii->mii_ifp); 1476 return 0; 1477 } 1478 1479 /* Lookup selected PHY */ 1480 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1481 if (IFM_INST(media) == miisc->mii_inst) 1482 break; 1483 } 1484 if (!miisc) { 1485 printf("%s: can't happen\n", __func__); /* ??? panic */ 1486 return 0; 1487 } 1488 #ifdef EPICMEDIADEBUG 1489 printf("%s: using phy %s\n", ifp->if_xname, 1490 device_xname(miisc->mii_dev)); 1491 #endif 1492 1493 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1494 /* XXX XXX assume it's a Level1 - should check */ 1495 1496 /* We have to powerup fiber transceivers */ 1497 PHY_READ(miisc, MII_LXTPHY_CONFIG, &cfg); 1498 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1499 #ifdef EPICMEDIADEBUG 1500 printf("%s: power up fiber\n", ifp->if_xname); 1501 #endif 1502 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1503 } else { 1504 #ifdef EPICMEDIADEBUG 1505 printf("%s: power down fiber\n", ifp->if_xname); 1506 #endif 1507 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1508 } 1509 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1510 } 1511 1512 return rc; 1513 } 1514
Indexes created Thu Sep 25 16:09:42 GMT 2025