smc83c170.c revision 1.95
1 /* $NetBSD: smc83c170.c,v 1.95 2020/03/15 22:19:00 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the Standard Microsystems Corp. 83C170 35 * Ethernet PCI Integrated Controller (EPIC/100). 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.95 2020/03/15 22:19:00 thorpej Exp $"); 40 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/miivar.h> 64 #include <dev/mii/lxtphyreg.h> 65 66 #include <dev/ic/smc83c170reg.h> 67 #include <dev/ic/smc83c170var.h> 68 69 static void epic_start(struct ifnet *); 70 static void epic_watchdog(struct ifnet *); 71 static int epic_ioctl(struct ifnet *, u_long, void *); 72 static int epic_init(struct ifnet *); 73 static void epic_stop(struct ifnet *, int); 74 75 static bool epic_shutdown(device_t, int); 76 77 static void epic_reset(struct epic_softc *); 78 static void epic_rxdrain(struct epic_softc *); 79 static int epic_add_rxbuf(struct epic_softc *, int); 80 static void epic_read_eeprom(struct epic_softc *, int, int, uint16_t *); 81 static void epic_set_mchash(struct epic_softc *); 82 static void epic_fixup_clock_source(struct epic_softc *); 83 static int epic_mii_read(device_t, int, int, uint16_t *); 84 static int epic_mii_write(device_t, int, int, uint16_t); 85 static int epic_mii_wait(struct epic_softc *, uint32_t); 86 static void epic_tick(void *); 87 88 static void epic_statchg(struct ifnet *); 89 static int epic_mediachange(struct ifnet *); 90 91 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 92 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 93 94 int epic_copy_small = 0; 95 96 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 97 98 /* 99 * Attach an EPIC interface to the system. 100 */ 101 void 102 epic_attach(struct epic_softc *sc) 103 { 104 bus_space_tag_t st = sc->sc_st; 105 bus_space_handle_t sh = sc->sc_sh; 106 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 107 struct mii_data * const mii = &sc->sc_mii; 108 int rseg, error, miiflags; 109 u_int i; 110 bus_dma_segment_t seg; 111 uint8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 112 uint16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 113 char *nullbuf; 114 115 callout_init(&sc->sc_mii_callout, 0); 116 callout_setfunc(&sc->sc_mii_callout, epic_tick, sc); 117 118 /* 119 * Allocate the control data structures, and create and load the 120 * DMA map for it. 121 */ 122 if ((error = bus_dmamem_alloc(sc->sc_dmat, 123 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0, 124 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 125 aprint_error_dev(sc->sc_dev, 126 "unable to allocate control data, error = %d\n", error); 127 goto fail_0; 128 } 129 130 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 131 sizeof(struct epic_control_data) + ETHER_PAD_LEN, 132 (void **)&sc->sc_control_data, 133 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 134 aprint_error_dev(sc->sc_dev, 135 "unable to map control data, error = %d\n", error); 136 goto fail_1; 137 } 138 nullbuf = 139 (char *)sc->sc_control_data + sizeof(struct epic_control_data); 140 memset(nullbuf, 0, ETHER_PAD_LEN); 141 142 if ((error = bus_dmamap_create(sc->sc_dmat, 143 sizeof(struct epic_control_data), 1, 144 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 145 &sc->sc_cddmamap)) != 0) { 146 aprint_error_dev(sc->sc_dev, 147 "unable to create control data DMA map, error = %d\n", 148 error); 149 goto fail_2; 150 } 151 152 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 153 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 154 BUS_DMA_NOWAIT)) != 0) { 155 aprint_error_dev(sc->sc_dev, 156 "unable to load control data DMA map, error = %d\n", 157 error); 158 goto fail_3; 159 } 160 161 /* 162 * Create the transmit buffer DMA maps. 163 */ 164 for (i = 0; i < EPIC_NTXDESC; i++) { 165 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 166 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 167 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 168 aprint_error_dev(sc->sc_dev, 169 "unable to create tx DMA map %d, error = %d\n", 170 i, error); 171 goto fail_4; 172 } 173 } 174 175 /* 176 * Create the receive buffer DMA maps. 177 */ 178 for (i = 0; i < EPIC_NRXDESC; i++) { 179 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 180 MCLBYTES, 0, BUS_DMA_NOWAIT, 181 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 182 aprint_error_dev(sc->sc_dev, 183 "unable to create rx DMA map %d, error = %d\n", 184 i, error); 185 goto fail_5; 186 } 187 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 188 } 189 190 /* 191 * create and map the pad buffer 192 */ 193 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 194 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) { 195 aprint_error_dev(sc->sc_dev, 196 "unable to create pad buffer DMA map, error = %d\n", error); 197 goto fail_5; 198 } 199 200 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 201 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "unable to load pad buffer DMA map, error = %d\n", error); 204 goto fail_6; 205 } 206 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 207 BUS_DMASYNC_PREWRITE); 208 209 /* 210 * Bring the chip out of low-power mode and reset it to a known state. 211 */ 212 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 213 epic_reset(sc); 214 215 /* 216 * Read the Ethernet address from the EEPROM. 217 */ 218 epic_read_eeprom(sc, 0, __arraycount(myea), myea); 219 for (i = 0; i < __arraycount(myea); i++) { 220 enaddr[i * 2] = myea[i] & 0xff; 221 enaddr[i * 2 + 1] = myea[i] >> 8; 222 } 223 224 /* 225 * ...and the device name. 226 */ 227 epic_read_eeprom(sc, 0x2c, __arraycount(mydevname), mydevname); 228 for (i = 0; i < __arraycount(mydevname); i++) { 229 devname[i * 2] = mydevname[i] & 0xff; 230 devname[i * 2 + 1] = mydevname[i] >> 8; 231 } 232 233 devname[sizeof(mydevname)] = '\0'; 234 for (i = sizeof(mydevname) ; i > 0; i--) { 235 if (devname[i - 1] == ' ') 236 devname[i - 1] = '\0'; 237 else 238 break; 239 } 240 241 aprint_normal_dev(sc->sc_dev, "%s, Ethernet address %s\n", 242 devname, ether_sprintf(enaddr)); 243 244 miiflags = 0; 245 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 246 miiflags |= MIIF_HAVEFIBER; 247 248 /* 249 * Initialize our media structures and probe the MII. 250 */ 251 mii->mii_ifp = ifp; 252 mii->mii_readreg = epic_mii_read; 253 mii->mii_writereg = epic_mii_write; 254 mii->mii_statchg = epic_statchg; 255 256 sc->sc_ethercom.ec_mii = mii; 257 ifmedia_init(&mii->mii_media, IFM_IMASK, epic_mediachange, 258 ether_mediastatus); 259 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 260 MII_OFFSET_ANY, miiflags); 261 if (LIST_EMPTY(&mii->mii_phys)) { 262 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 263 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 264 } else 265 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 266 267 if (sc->sc_hwflags & EPIC_HAS_BNC) { 268 /* use the next free media instance */ 269 sc->sc_serinst = mii->mii_instance++; 270 ifmedia_add(&mii->mii_media, 271 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->sc_serinst), 272 0, NULL); 273 aprint_normal_dev(sc->sc_dev, "10base2/BNC\n"); 274 } else 275 sc->sc_serinst = -1; 276 277 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 278 ifp->if_softc = sc; 279 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 280 ifp->if_ioctl = epic_ioctl; 281 ifp->if_start = epic_start; 282 ifp->if_watchdog = epic_watchdog; 283 ifp->if_init = epic_init; 284 ifp->if_stop = epic_stop; 285 IFQ_SET_READY(&ifp->if_snd); 286 287 /* 288 * We can support 802.1Q VLAN-sized frames. 289 */ 290 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 291 292 /* 293 * Attach the interface. 294 */ 295 if_attach(ifp); 296 if_deferred_start_init(ifp, NULL); 297 ether_ifattach(ifp, enaddr); 298 299 /* 300 * Make sure the interface is shutdown during reboot. 301 */ 302 if (pmf_device_register1(sc->sc_dev, NULL, NULL, epic_shutdown)) 303 pmf_class_network_register(sc->sc_dev, ifp); 304 else 305 aprint_error_dev(sc->sc_dev, 306 "couldn't establish power handler\n"); 307 308 return; 309 310 /* 311 * Free any resources we've allocated during the failed attach 312 * attempt. Do this in reverse order and fall through. 313 */ 314 fail_6: 315 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 316 fail_5: 317 for (i = 0; i < EPIC_NRXDESC; i++) { 318 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 319 bus_dmamap_destroy(sc->sc_dmat, 320 EPIC_DSRX(sc, i)->ds_dmamap); 321 } 322 fail_4: 323 for (i = 0; i < EPIC_NTXDESC; i++) { 324 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 325 bus_dmamap_destroy(sc->sc_dmat, 326 EPIC_DSTX(sc, i)->ds_dmamap); 327 } 328 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 329 fail_3: 330 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 331 fail_2: 332 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 333 sizeof(struct epic_control_data)); 334 fail_1: 335 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 336 fail_0: 337 return; 338 } 339 340 /* 341 * Shutdown hook. Make sure the interface is stopped at reboot. 342 */ 343 static bool 344 epic_shutdown(device_t self, int howto) 345 { 346 struct epic_softc *sc = device_private(self); 347 348 epic_stop(&sc->sc_ethercom.ec_if, 1); 349 350 return true; 351 } 352 353 /* 354 * Start packet transmission on the interface. 355 * [ifnet interface function] 356 */ 357 static void 358 epic_start(struct ifnet *ifp) 359 { 360 struct epic_softc *sc = ifp->if_softc; 361 struct mbuf *m0, *m; 362 struct epic_txdesc *txd; 363 struct epic_descsoft *ds; 364 struct epic_fraglist *fr; 365 bus_dmamap_t dmamap; 366 int error, firsttx, nexttx, opending, seg; 367 u_int len; 368 369 /* 370 * Remember the previous txpending and the first transmit 371 * descriptor we use. 372 */ 373 opending = sc->sc_txpending; 374 firsttx = EPIC_NEXTTX(sc->sc_txlast); 375 376 /* 377 * Loop through the send queue, setting up transmit descriptors 378 * until we drain the queue, or use up all available transmit 379 * descriptors. 380 */ 381 while (sc->sc_txpending < EPIC_NTXDESC) { 382 /* 383 * Grab a packet off the queue. 384 */ 385 IFQ_POLL(&ifp->if_snd, m0); 386 if (m0 == NULL) 387 break; 388 m = NULL; 389 390 /* 391 * Get the last and next available transmit descriptor. 392 */ 393 nexttx = EPIC_NEXTTX(sc->sc_txlast); 394 txd = EPIC_CDTX(sc, nexttx); 395 fr = EPIC_CDFL(sc, nexttx); 396 ds = EPIC_DSTX(sc, nexttx); 397 dmamap = ds->ds_dmamap; 398 399 /* 400 * Load the DMA map. If this fails, the packet either 401 * didn't fit in the alloted number of frags, or we were 402 * short on resources. In this case, we'll copy and try 403 * again. 404 */ 405 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 406 BUS_DMA_WRITE | BUS_DMA_NOWAIT)) != 0 || 407 (m0->m_pkthdr.len < ETHER_PAD_LEN && 408 dmamap-> dm_nsegs == EPIC_NFRAGS)) { 409 if (error == 0) 410 bus_dmamap_unload(sc->sc_dmat, dmamap); 411 412 MGETHDR(m, M_DONTWAIT, MT_DATA); 413 if (m == NULL) { 414 printf("%s: unable to allocate Tx mbuf\n", 415 device_xname(sc->sc_dev)); 416 break; 417 } 418 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 419 if (m0->m_pkthdr.len > MHLEN) { 420 MCLGET(m, M_DONTWAIT); 421 if ((m->m_flags & M_EXT) == 0) { 422 printf("%s: unable to allocate Tx " 423 "cluster\n", 424 device_xname(sc->sc_dev)); 425 m_freem(m); 426 break; 427 } 428 } 429 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 430 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 431 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 432 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 433 if (error) { 434 printf("%s: unable to load Tx buffer, " 435 "error = %d\n", device_xname(sc->sc_dev), 436 error); 437 break; 438 } 439 } 440 IFQ_DEQUEUE(&ifp->if_snd, m0); 441 if (m != NULL) { 442 m_freem(m0); 443 m0 = m; 444 } 445 446 /* Initialize the fraglist. */ 447 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 448 fr->ef_frags[seg].ef_addr = 449 dmamap->dm_segs[seg].ds_addr; 450 fr->ef_frags[seg].ef_length = 451 dmamap->dm_segs[seg].ds_len; 452 } 453 len = m0->m_pkthdr.len; 454 if (len < ETHER_PAD_LEN) { 455 fr->ef_frags[seg].ef_addr = sc->sc_nulldma; 456 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len; 457 len = ETHER_PAD_LEN; 458 seg++; 459 } 460 fr->ef_nfrags = seg; 461 462 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 463 464 /* Sync the DMA map. */ 465 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 466 BUS_DMASYNC_PREWRITE); 467 468 /* 469 * Store a pointer to the packet so we can free it later. 470 */ 471 ds->ds_mbuf = m0; 472 473 /* 474 * Fill in the transmit descriptor. 475 */ 476 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 477 478 /* 479 * If this is the first descriptor we're enqueueing, 480 * don't give it to the EPIC yet. That could cause 481 * a race condition. We'll do it below. 482 */ 483 if (nexttx == firsttx) 484 txd->et_txstatus = TXSTAT_TXLENGTH(len); 485 else 486 txd->et_txstatus = 487 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER; 488 489 EPIC_CDTXSYNC(sc, nexttx, 490 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 491 492 /* Advance the tx pointer. */ 493 sc->sc_txpending++; 494 sc->sc_txlast = nexttx; 495 496 /* 497 * Pass the packet to any BPF listeners. 498 */ 499 bpf_mtap(ifp, m0, BPF_D_OUT); 500 } 501 502 if (sc->sc_txpending != opending) { 503 /* 504 * We enqueued packets. If the transmitter was idle, 505 * reset the txdirty pointer. 506 */ 507 if (opending == 0) 508 sc->sc_txdirty = firsttx; 509 510 /* 511 * Cause a transmit interrupt to happen on the 512 * last packet we enqueued. 513 */ 514 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 515 EPIC_CDTXSYNC(sc, sc->sc_txlast, 516 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 517 518 /* 519 * The entire packet chain is set up. Give the 520 * first descriptor to the EPIC now. 521 */ 522 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER; 523 EPIC_CDTXSYNC(sc, firsttx, 524 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 525 526 /* Start the transmitter. */ 527 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 528 COMMAND_TXQUEUED); 529 530 /* Set a watchdog timer in case the chip flakes out. */ 531 ifp->if_timer = 5; 532 } 533 } 534 535 /* 536 * Watchdog timer handler. 537 * [ifnet interface function] 538 */ 539 static void 540 epic_watchdog(struct ifnet *ifp) 541 { 542 struct epic_softc *sc = ifp->if_softc; 543 544 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 545 if_statinc(ifp, if_oerrors); 546 547 (void)epic_init(ifp); 548 } 549 550 /* 551 * Handle control requests from the operator. 552 * [ifnet interface function] 553 */ 554 static int 555 epic_ioctl(struct ifnet *ifp, u_long cmd, void *data) 556 { 557 struct epic_softc *sc = ifp->if_softc; 558 int s, error; 559 560 s = splnet(); 561 562 error = ether_ioctl(ifp, cmd, data); 563 if (error == ENETRESET) { 564 /* 565 * Multicast list has changed; set the hardware filter 566 * accordingly. Update our idea of the current media; 567 * epic_set_mchash() needs to know what it is. 568 */ 569 if (ifp->if_flags & IFF_RUNNING) { 570 mii_pollstat(&sc->sc_mii); 571 epic_set_mchash(sc); 572 } 573 error = 0; 574 } 575 576 splx(s); 577 return error; 578 } 579 580 /* 581 * Interrupt handler. 582 */ 583 int 584 epic_intr(void *arg) 585 { 586 struct epic_softc *sc = arg; 587 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 588 struct epic_rxdesc *rxd; 589 struct epic_txdesc *txd; 590 struct epic_descsoft *ds; 591 struct mbuf *m; 592 uint32_t intstat, rxstatus, txstatus; 593 int i, claimed = 0; 594 u_int len; 595 596 top: 597 /* 598 * Get the interrupt status from the EPIC. 599 */ 600 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 601 if ((intstat & INTSTAT_INT_ACTV) == 0) 602 return claimed; 603 604 claimed = 1; 605 606 /* 607 * Acknowledge the interrupt. 608 */ 609 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 610 intstat & INTMASK); 611 612 /* 613 * Check for receive interrupts. 614 */ 615 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 616 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 617 rxd = EPIC_CDRX(sc, i); 618 ds = EPIC_DSRX(sc, i); 619 620 EPIC_CDRXSYNC(sc, i, 621 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 622 623 rxstatus = rxd->er_rxstatus; 624 if (rxstatus & ER_RXSTAT_OWNER) { 625 /* 626 * We have processed all of the 627 * receive buffers. 628 */ 629 break; 630 } 631 632 /* 633 * Make sure the packet arrived intact. If an error 634 * occurred, update stats and reset the descriptor. 635 * The buffer will be reused the next time the 636 * descriptor comes up in the ring. 637 */ 638 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 639 if (rxstatus & ER_RXSTAT_CRCERROR) 640 printf("%s: CRC error\n", 641 device_xname(sc->sc_dev)); 642 if (rxstatus & ER_RXSTAT_ALIGNERROR) 643 printf("%s: alignment error\n", 644 device_xname(sc->sc_dev)); 645 if_statinc(ifp, if_ierrors); 646 EPIC_INIT_RXDESC(sc, i); 647 continue; 648 } 649 650 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 651 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 652 653 /* 654 * The EPIC includes the CRC with every packet; 655 * trim it. 656 */ 657 len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN; 658 659 if (len < sizeof(struct ether_header)) { 660 /* 661 * Runt packet; drop it now. 662 */ 663 if_statinc(ifp, if_ierrors); 664 EPIC_INIT_RXDESC(sc, i); 665 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 666 ds->ds_dmamap->dm_mapsize, 667 BUS_DMASYNC_PREREAD); 668 continue; 669 } 670 671 /* 672 * If the packet is small enough to fit in a 673 * single header mbuf, allocate one and copy 674 * the data into it. This greatly reduces 675 * memory consumption when we receive lots 676 * of small packets. 677 * 678 * Otherwise, we add a new buffer to the receive 679 * chain. If this fails, we drop the packet and 680 * recycle the old buffer. 681 */ 682 if (epic_copy_small != 0 && len <= MHLEN) { 683 MGETHDR(m, M_DONTWAIT, MT_DATA); 684 if (m == NULL) 685 goto dropit; 686 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 687 memcpy(mtod(m, void *), 688 mtod(ds->ds_mbuf, void *), len); 689 EPIC_INIT_RXDESC(sc, i); 690 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 691 ds->ds_dmamap->dm_mapsize, 692 BUS_DMASYNC_PREREAD); 693 } else { 694 m = ds->ds_mbuf; 695 if (epic_add_rxbuf(sc, i) != 0) { 696 dropit: 697 if_statinc(ifp, if_ierrors); 698 EPIC_INIT_RXDESC(sc, i); 699 bus_dmamap_sync(sc->sc_dmat, 700 ds->ds_dmamap, 0, 701 ds->ds_dmamap->dm_mapsize, 702 BUS_DMASYNC_PREREAD); 703 continue; 704 } 705 } 706 707 m_set_rcvif(m, ifp); 708 m->m_pkthdr.len = m->m_len = len; 709 710 /* Pass it on. */ 711 if_percpuq_enqueue(ifp->if_percpuq, m); 712 } 713 714 /* Update the receive pointer. */ 715 sc->sc_rxptr = i; 716 717 /* 718 * Check for receive queue underflow. 719 */ 720 if (intstat & INTSTAT_RQE) { 721 printf("%s: receiver queue empty\n", 722 device_xname(sc->sc_dev)); 723 /* 724 * Ring is already built; just restart the 725 * receiver. 726 */ 727 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 728 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 729 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 730 COMMAND_RXQUEUED | COMMAND_START_RX); 731 } 732 } 733 734 /* 735 * Check for transmission complete interrupts. 736 */ 737 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 738 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 739 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 740 txd = EPIC_CDTX(sc, i); 741 ds = EPIC_DSTX(sc, i); 742 743 EPIC_CDTXSYNC(sc, i, 744 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 745 746 txstatus = txd->et_txstatus; 747 if (txstatus & ET_TXSTAT_OWNER) 748 break; 749 750 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 751 752 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 753 0, ds->ds_dmamap->dm_mapsize, 754 BUS_DMASYNC_POSTWRITE); 755 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 756 m_freem(ds->ds_mbuf); 757 ds->ds_mbuf = NULL; 758 759 /* 760 * Check for errors and collisions. 761 */ 762 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 763 if ((txstatus & ET_TXSTAT_PACKETTX) == 0) 764 if_statinc_ref(nsr, if_oerrors); 765 else 766 if_statinc_ref(nsr, if_opackets); 767 if (TXSTAT_COLLISIONS(txstatus)) 768 if_statadd_ref(nsr, if_collisions, 769 TXSTAT_COLLISIONS(txstatus)); 770 if (txstatus & ET_TXSTAT_CARSENSELOST) 771 printf("%s: lost carrier\n", 772 device_xname(sc->sc_dev)); 773 IF_STAT_PUTREF(ifp); 774 } 775 776 /* Update the dirty transmit buffer pointer. */ 777 sc->sc_txdirty = i; 778 779 /* 780 * Cancel the watchdog timer if there are no pending 781 * transmissions. 782 */ 783 if (sc->sc_txpending == 0) 784 ifp->if_timer = 0; 785 786 /* 787 * Kick the transmitter after a DMA underrun. 788 */ 789 if (intstat & INTSTAT_TXU) { 790 printf("%s: transmit underrun\n", 791 device_xname(sc->sc_dev)); 792 bus_space_write_4(sc->sc_st, sc->sc_sh, 793 EPIC_COMMAND, COMMAND_TXUGO); 794 if (sc->sc_txpending) 795 bus_space_write_4(sc->sc_st, sc->sc_sh, 796 EPIC_COMMAND, COMMAND_TXQUEUED); 797 } 798 799 /* 800 * Try to get more packets going. 801 */ 802 if_schedule_deferred_start(ifp); 803 } 804 805 /* 806 * Check for fatal interrupts. 807 */ 808 if (intstat & INTSTAT_FATAL_INT) { 809 if (intstat & INTSTAT_PTA) 810 printf("%s: PCI target abort error\n", 811 device_xname(sc->sc_dev)); 812 else if (intstat & INTSTAT_PMA) 813 printf("%s: PCI master abort error\n", 814 device_xname(sc->sc_dev)); 815 else if (intstat & INTSTAT_APE) 816 printf("%s: PCI address parity error\n", 817 device_xname(sc->sc_dev)); 818 else if (intstat & INTSTAT_DPE) 819 printf("%s: PCI data parity error\n", 820 device_xname(sc->sc_dev)); 821 else 822 printf("%s: unknown fatal error\n", 823 device_xname(sc->sc_dev)); 824 (void)epic_init(ifp); 825 } 826 827 /* 828 * Check for more interrupts. 829 */ 830 goto top; 831 } 832 833 /* 834 * One second timer, used to tick the MII. 835 */ 836 static void 837 epic_tick(void *arg) 838 { 839 struct epic_softc *sc = arg; 840 int s; 841 842 s = splnet(); 843 mii_tick(&sc->sc_mii); 844 splx(s); 845 846 callout_schedule(&sc->sc_mii_callout, hz); 847 } 848 849 /* 850 * Fixup the clock source on the EPIC. 851 */ 852 static void 853 epic_fixup_clock_source(struct epic_softc *sc) 854 { 855 int i; 856 857 /* 858 * According to SMC Application Note 7-15, the EPIC's clock 859 * source is incorrect following a reset. This manifests itself 860 * as failure to recognize when host software has written to 861 * a register on the EPIC. The appnote recommends issuing at 862 * least 16 consecutive writes to the CLOCK TEST bit to correctly 863 * configure the clock source. 864 */ 865 for (i = 0; i < 16; i++) 866 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 867 TEST_CLOCKTEST); 868 } 869 870 /* 871 * Perform a soft reset on the EPIC. 872 */ 873 static void 874 epic_reset(struct epic_softc *sc) 875 { 876 877 epic_fixup_clock_source(sc); 878 879 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 880 delay(100); 881 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 882 delay(100); 883 884 epic_fixup_clock_source(sc); 885 } 886 887 /* 888 * Initialize the interface. Must be called at splnet(). 889 */ 890 static int 891 epic_init(struct ifnet *ifp) 892 { 893 struct epic_softc *sc = ifp->if_softc; 894 bus_space_tag_t st = sc->sc_st; 895 bus_space_handle_t sh = sc->sc_sh; 896 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 897 struct epic_txdesc *txd; 898 struct epic_descsoft *ds; 899 uint32_t genctl, reg0; 900 int i, error = 0; 901 902 /* 903 * Cancel any pending I/O. 904 */ 905 epic_stop(ifp, 0); 906 907 /* 908 * Reset the EPIC to a known state. 909 */ 910 epic_reset(sc); 911 912 /* 913 * Magical mystery initialization. 914 */ 915 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 916 917 /* 918 * Initialize the EPIC genctl register: 919 * 920 * - 64 byte receive FIFO threshold 921 * - automatic advance to next receive frame 922 */ 923 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 924 #if BYTE_ORDER == BIG_ENDIAN 925 genctl |= GENCTL_BIG_ENDIAN; 926 #endif 927 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 928 929 /* 930 * Reset the MII bus and PHY. 931 */ 932 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 933 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 934 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 935 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 936 delay(100); 937 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 938 delay(1000); 939 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 940 941 /* 942 * Initialize Ethernet address. 943 */ 944 reg0 = enaddr[1] << 8 | enaddr[0]; 945 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 946 reg0 = enaddr[3] << 8 | enaddr[2]; 947 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 948 reg0 = enaddr[5] << 8 | enaddr[4]; 949 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 950 951 /* 952 * Initialize receive control. Remember the external buffer 953 * size setting. 954 */ 955 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 956 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 957 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 958 if (ifp->if_flags & IFF_PROMISC) 959 reg0 |= RXCON_PROMISCMODE; 960 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 961 962 /* Set the current media. */ 963 if ((error = epic_mediachange(ifp)) != 0) 964 goto out; 965 966 /* Set up the multicast hash table. */ 967 epic_set_mchash(sc); 968 969 /* 970 * Initialize the transmit descriptor ring. txlast is initialized 971 * to the end of the list so that it will wrap around to the first 972 * descriptor when the first packet is transmitted. 973 */ 974 for (i = 0; i < EPIC_NTXDESC; i++) { 975 txd = EPIC_CDTX(sc, i); 976 memset(txd, 0, sizeof(struct epic_txdesc)); 977 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 978 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 979 EPIC_CDTXSYNC(sc, i, 980 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 981 } 982 sc->sc_txpending = 0; 983 sc->sc_txdirty = 0; 984 sc->sc_txlast = EPIC_NTXDESC - 1; 985 986 /* 987 * Initialize the receive descriptor ring. 988 */ 989 for (i = 0; i < EPIC_NRXDESC; i++) { 990 ds = EPIC_DSRX(sc, i); 991 if (ds->ds_mbuf == NULL) { 992 if ((error = epic_add_rxbuf(sc, i)) != 0) { 993 printf("%s: unable to allocate or map rx " 994 "buffer %d error = %d\n", 995 device_xname(sc->sc_dev), i, error); 996 /* 997 * XXX Should attempt to run with fewer receive 998 * XXX buffers instead of just failing. 999 */ 1000 epic_rxdrain(sc); 1001 goto out; 1002 } 1003 } else 1004 EPIC_INIT_RXDESC(sc, i); 1005 } 1006 sc->sc_rxptr = 0; 1007 1008 /* 1009 * Initialize the interrupt mask and enable interrupts. 1010 */ 1011 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1012 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1013 1014 /* 1015 * Give the transmit and receive rings to the EPIC. 1016 */ 1017 bus_space_write_4(st, sh, EPIC_PTCDAR, 1018 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1019 bus_space_write_4(st, sh, EPIC_PRCDAR, 1020 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1021 1022 /* 1023 * Set the EPIC in motion. 1024 */ 1025 bus_space_write_4(st, sh, EPIC_COMMAND, 1026 COMMAND_RXQUEUED | COMMAND_START_RX); 1027 1028 /* 1029 * ...all done! 1030 */ 1031 ifp->if_flags |= IFF_RUNNING; 1032 1033 /* 1034 * Start the one second clock. 1035 */ 1036 callout_schedule(&sc->sc_mii_callout, hz); 1037 1038 /* 1039 * Attempt to start output on the interface. 1040 */ 1041 epic_start(ifp); 1042 1043 out: 1044 if (error) 1045 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1046 return error; 1047 } 1048 1049 /* 1050 * Drain the receive queue. 1051 */ 1052 static void 1053 epic_rxdrain(struct epic_softc *sc) 1054 { 1055 struct epic_descsoft *ds; 1056 int i; 1057 1058 for (i = 0; i < EPIC_NRXDESC; i++) { 1059 ds = EPIC_DSRX(sc, i); 1060 if (ds->ds_mbuf != NULL) { 1061 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1062 m_freem(ds->ds_mbuf); 1063 ds->ds_mbuf = NULL; 1064 } 1065 } 1066 } 1067 1068 /* 1069 * Stop transmission on the interface. 1070 */ 1071 static void 1072 epic_stop(struct ifnet *ifp, int disable) 1073 { 1074 struct epic_softc *sc = ifp->if_softc; 1075 bus_space_tag_t st = sc->sc_st; 1076 bus_space_handle_t sh = sc->sc_sh; 1077 struct epic_descsoft *ds; 1078 uint32_t reg; 1079 int i; 1080 1081 /* 1082 * Stop the one second clock. 1083 */ 1084 callout_stop(&sc->sc_mii_callout); 1085 1086 /* Down the MII. */ 1087 mii_down(&sc->sc_mii); 1088 1089 /* Paranoia... */ 1090 epic_fixup_clock_source(sc); 1091 1092 /* 1093 * Disable interrupts. 1094 */ 1095 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1096 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1097 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1098 1099 /* 1100 * Stop the DMA engine and take the receiver off-line. 1101 */ 1102 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1103 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1104 1105 /* 1106 * Release any queued transmit buffers. 1107 */ 1108 for (i = 0; i < EPIC_NTXDESC; i++) { 1109 ds = EPIC_DSTX(sc, i); 1110 if (ds->ds_mbuf != NULL) { 1111 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1112 m_freem(ds->ds_mbuf); 1113 ds->ds_mbuf = NULL; 1114 } 1115 } 1116 1117 /* 1118 * Mark the interface down and cancel the watchdog timer. 1119 */ 1120 ifp->if_flags &= ~IFF_RUNNING; 1121 ifp->if_timer = 0; 1122 1123 if (disable) 1124 epic_rxdrain(sc); 1125 } 1126 1127 /* 1128 * Read the EPIC Serial EEPROM. 1129 */ 1130 static void 1131 epic_read_eeprom(struct epic_softc *sc, int word, int wordcnt, uint16_t *data) 1132 { 1133 bus_space_tag_t st = sc->sc_st; 1134 bus_space_handle_t sh = sc->sc_sh; 1135 uint16_t reg; 1136 int i, x; 1137 1138 #define EEPROM_WAIT_READY(st, sh) \ 1139 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1140 /* nothing */ 1141 1142 /* 1143 * Enable the EEPROM. 1144 */ 1145 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1146 EEPROM_WAIT_READY(st, sh); 1147 1148 for (i = 0; i < wordcnt; i++) { 1149 /* Send CHIP SELECT for one clock tick. */ 1150 bus_space_write_4(st, sh, EPIC_EECTL, 1151 EECTL_ENABLE | EECTL_EECS); 1152 EEPROM_WAIT_READY(st, sh); 1153 1154 /* Shift in the READ opcode. */ 1155 for (x = 3; x > 0; x--) { 1156 reg = EECTL_ENABLE | EECTL_EECS; 1157 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1158 reg |= EECTL_EEDI; 1159 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1160 EEPROM_WAIT_READY(st, sh); 1161 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1162 EEPROM_WAIT_READY(st, sh); 1163 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1164 EEPROM_WAIT_READY(st, sh); 1165 } 1166 1167 /* Shift in address. */ 1168 for (x = 6; x > 0; x--) { 1169 reg = EECTL_ENABLE | EECTL_EECS; 1170 if ((word + i) & (1 << (x - 1))) 1171 reg |= EECTL_EEDI; 1172 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1173 EEPROM_WAIT_READY(st, sh); 1174 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1175 EEPROM_WAIT_READY(st, sh); 1176 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1177 EEPROM_WAIT_READY(st, sh); 1178 } 1179 1180 /* Shift out data. */ 1181 reg = EECTL_ENABLE | EECTL_EECS; 1182 data[i] = 0; 1183 for (x = 16; x > 0; x--) { 1184 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1185 EEPROM_WAIT_READY(st, sh); 1186 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1187 data[i] |= (1 << (x - 1)); 1188 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1189 EEPROM_WAIT_READY(st, sh); 1190 } 1191 1192 /* Clear CHIP SELECT. */ 1193 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1194 EEPROM_WAIT_READY(st, sh); 1195 } 1196 1197 /* 1198 * Disable the EEPROM. 1199 */ 1200 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1201 1202 #undef EEPROM_WAIT_READY 1203 } 1204 1205 /* 1206 * Add a receive buffer to the indicated descriptor. 1207 */ 1208 static int 1209 epic_add_rxbuf(struct epic_softc *sc, int idx) 1210 { 1211 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1212 struct mbuf *m; 1213 int error; 1214 1215 MGETHDR(m, M_DONTWAIT, MT_DATA); 1216 if (m == NULL) 1217 return ENOBUFS; 1218 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1219 1220 MCLGET(m, M_DONTWAIT); 1221 if ((m->m_flags & M_EXT) == 0) { 1222 m_freem(m); 1223 return ENOBUFS; 1224 } 1225 1226 if (ds->ds_mbuf != NULL) 1227 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1228 1229 ds->ds_mbuf = m; 1230 1231 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1232 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1233 BUS_DMA_READ | BUS_DMA_NOWAIT); 1234 if (error) { 1235 printf("%s: can't load rx DMA map %d, error = %d\n", 1236 device_xname(sc->sc_dev), idx, error); 1237 panic("%s", __func__); /* XXX */ 1238 } 1239 1240 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1241 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1242 1243 EPIC_INIT_RXDESC(sc, idx); 1244 1245 return 0; 1246 } 1247 1248 /* 1249 * Set the EPIC multicast hash table. 1250 * 1251 * NOTE: We rely on a recently-updated mii_media_active here! 1252 */ 1253 static void 1254 epic_set_mchash(struct epic_softc *sc) 1255 { 1256 struct ethercom *ec = &sc->sc_ethercom; 1257 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1258 struct ether_multi *enm; 1259 struct ether_multistep step; 1260 uint32_t hash, mchash[4]; 1261 1262 /* 1263 * Set up the multicast address filter by passing all multicast 1264 * addresses through a CRC generator, and then using the low-order 1265 * 6 bits as an index into the 64 bit multicast hash table (only 1266 * the lower 16 bits of each 32 bit multicast hash register are 1267 * valid). The high order bits select the register, while the 1268 * rest of the bits select the bit within the register. 1269 */ 1270 1271 if (ifp->if_flags & IFF_PROMISC) 1272 goto allmulti; 1273 1274 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1275 /* XXX hardware bug in 10Mbps mode. */ 1276 goto allmulti; 1277 } 1278 1279 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1280 1281 ETHER_LOCK(ec); 1282 ETHER_FIRST_MULTI(step, ec, enm); 1283 while (enm != NULL) { 1284 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1285 /* 1286 * We must listen to a range of multicast addresses. 1287 * For now, just accept all multicasts, rather than 1288 * trying to set only those filter bits needed to match 1289 * the range. (At this time, the only use of address 1290 * ranges is for IP multicast routing, for which the 1291 * range is big enough to require all bits set.) 1292 */ 1293 ETHER_UNLOCK(ec); 1294 goto allmulti; 1295 } 1296 1297 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1298 hash >>= 26; 1299 1300 /* Set the corresponding bit in the hash table. */ 1301 mchash[hash >> 4] |= 1 << (hash & 0xf); 1302 1303 ETHER_NEXT_MULTI(step, enm); 1304 } 1305 ETHER_UNLOCK(ec); 1306 1307 ifp->if_flags &= ~IFF_ALLMULTI; 1308 goto sethash; 1309 1310 allmulti: 1311 ifp->if_flags |= IFF_ALLMULTI; 1312 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1313 1314 sethash: 1315 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1316 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1317 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1318 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1319 } 1320 1321 /* 1322 * Wait for the MII to become ready. 1323 */ 1324 static int 1325 epic_mii_wait(struct epic_softc *sc, uint32_t rw) 1326 { 1327 int i; 1328 1329 for (i = 0; i < 50; i++) { 1330 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1331 == 0) 1332 break; 1333 delay(2); 1334 } 1335 if (i == 50) { 1336 printf("%s: MII timed out\n", device_xname(sc->sc_dev)); 1337 return ETIMEDOUT; 1338 } 1339 1340 return 0; 1341 } 1342 1343 /* 1344 * Read from the MII. 1345 */ 1346 static int 1347 epic_mii_read(device_t self, int phy, int reg, uint16_t *val) 1348 { 1349 struct epic_softc *sc = device_private(self); 1350 int rv; 1351 1352 if ((rv = epic_mii_wait(sc, MMCTL_WRITE)) != 0) 1353 return rv; 1354 1355 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1356 MMCTL_ARG(phy, reg, MMCTL_READ)); 1357 1358 if ((rv = epic_mii_wait(sc, MMCTL_READ)) != 0) 1359 return rv; 1360 1361 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) 1362 & MMDATA_MASK; 1363 return 0; 1364 } 1365 1366 /* 1367 * Write to the MII. 1368 */ 1369 static int 1370 epic_mii_write(device_t self, int phy, int reg, uint16_t val) 1371 { 1372 struct epic_softc *sc = device_private(self); 1373 int rv; 1374 1375 if ((rv = epic_mii_wait(sc, MMCTL_WRITE)) != 0) 1376 return rv; 1377 1378 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1379 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1380 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1381 1382 return 0; 1383 } 1384 1385 /* 1386 * Callback from PHY when media changes. 1387 */ 1388 static void 1389 epic_statchg(struct ifnet *ifp) 1390 { 1391 struct epic_softc *sc = ifp->if_softc; 1392 uint32_t txcon, miicfg; 1393 1394 /* 1395 * Update loopback bits in TXCON to reflect duplex mode. 1396 */ 1397 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1398 if (sc->sc_mii.mii_media_active & IFM_FDX) 1399 txcon |= (TXCON_LOOPBACK_D1 | TXCON_LOOPBACK_D2); 1400 else 1401 txcon &= ~(TXCON_LOOPBACK_D1 | TXCON_LOOPBACK_D2); 1402 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1403 1404 /* On some cards we need manualy set fullduplex led */ 1405 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1406 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1407 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1408 miicfg |= MIICFG_ENABLE; 1409 else 1410 miicfg &= ~MIICFG_ENABLE; 1411 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1412 } 1413 1414 /* 1415 * There is a multicast filter bug in 10Mbps mode. Kick the 1416 * multicast filter in case the speed changed. 1417 */ 1418 epic_set_mchash(sc); 1419 } 1420 1421 /* 1422 * Callback from ifmedia to request new media setting. 1423 * 1424 * XXX Looks to me like some of this complexity should move into 1425 * XXX one or two custom PHY drivers. --dyoung 1426 */ 1427 static int 1428 epic_mediachange(struct ifnet *ifp) 1429 { 1430 struct epic_softc *sc = ifp->if_softc; 1431 struct mii_data *mii = &sc->sc_mii; 1432 struct ifmedia *ifm = &mii->mii_media; 1433 int media = ifm->ifm_cur->ifm_media; 1434 uint32_t miicfg; 1435 struct mii_softc *miisc; 1436 int rc; 1437 uint16_t cfg; 1438 1439 if ((ifp->if_flags & IFF_UP) == 0) 1440 return 0; 1441 1442 if (IFM_INST(media) != sc->sc_serinst) { 1443 /* If we're not selecting serial interface, select MII mode */ 1444 #ifdef EPICMEDIADEBUG 1445 printf("%s: parallel mode\n", ifp->if_xname); 1446 #endif 1447 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1448 miicfg &= ~MIICFG_SERMODEENA; 1449 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1450 } 1451 1452 if ((rc = mii_mediachg(mii)) == ENXIO) 1453 rc = 0; 1454 1455 if (IFM_INST(media) == sc->sc_serinst) { 1456 /* select serial interface */ 1457 #ifdef EPICMEDIADEBUG 1458 printf("%s: serial mode\n", ifp->if_xname); 1459 #endif 1460 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1461 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1462 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1463 1464 /* There is no driver to fill this */ 1465 mii->mii_media_active = media; 1466 mii->mii_media_status = 0; 1467 1468 epic_statchg(mii->mii_ifp); 1469 return 0; 1470 } 1471 1472 /* Lookup selected PHY */ 1473 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1474 if (IFM_INST(media) == miisc->mii_inst) 1475 break; 1476 } 1477 if (!miisc) { 1478 printf("%s: can't happen\n", __func__); /* ??? panic */ 1479 return 0; 1480 } 1481 #ifdef EPICMEDIADEBUG 1482 printf("%s: using phy %s\n", ifp->if_xname, 1483 device_xname(miisc->mii_dev)); 1484 #endif 1485 1486 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1487 /* XXX XXX assume it's a Level1 - should check */ 1488 1489 /* We have to powerup fiber transceivers */ 1490 PHY_READ(miisc, MII_LXTPHY_CONFIG, &cfg); 1491 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1492 #ifdef EPICMEDIADEBUG 1493 printf("%s: power up fiber\n", ifp->if_xname); 1494 #endif 1495 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1496 } else { 1497 #ifdef EPICMEDIADEBUG 1498 printf("%s: power down fiber\n", ifp->if_xname); 1499 #endif 1500 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1501 } 1502 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1503 } 1504 1505 return rc; 1506 } 1507
Indexes created Thu Sep 25 16:09:42 GMT 2025