smc83c170reg.h revision 1.2
1 /* $NetBSD: smc83c170reg.h,v 1.2 1998/07/20 20:45:06 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_IC_SMC83C170REG_H_ 41 #define _DEV_IC_SMC83C170REG_H_ 42 43 /* 44 * Register description for the Standard Microsystems Corp. 83C170 45 * Ethernet PCI Integrated Controller (EPIC/100). 46 */ 47 48 /* 49 * EPIC transmit descriptor. Must be 4-byte aligned. 50 */ 51 struct epic_txdesc { 52 #if BYTE_ORDER == BIG_ENDIAN 53 u_int16_t et_txlength; /* transmit length */ 54 u_int16_t et_txstatus; /* transmit status; see below */ 55 #else 56 u_int16_t et_txstatus; /* transmit status; see below */ 57 u_int16_t et_txlength; /* transmit length */ 58 #endif 59 u_int32_t et_bufaddr; /* buffer address */ 60 #if BYTE_ORDER == BIG_ENDIAN 61 u_int16_t et_control; /* control word; see below */ 62 u_int16_t et_buflength; /* buffer length */ 63 #else 64 u_int16_t et_buflength; /* buffer length */ 65 u_int16_t et_control; /* control word; see below */ 66 #endif 67 u_int32_t et_nextdesc; /* next descriptor pointer */ 68 }; 69 70 /* et_txstatus */ 71 #define ET_TXSTAT_OWNER 0x8000 /* NIC owns descriptor */ 72 #define ET_TXSTAT_COLLMASK 0x1f00 /* collisions */ 73 #define ET_TXSTAT_DEFERRING 0x0080 /* deferring due to jabber */ 74 #define ET_TXSTAT_OOWCOLL 0x0040 /* out of window collision */ 75 #define ET_TXSTAT_CDHB 0x0020 /* collision detect heartbeat */ 76 #define ET_TXSTAT_UNDERRUN 0x0010 /* DMA underrun */ 77 #define ET_TXSTAT_CARSENSELOST 0x0008 /* carrier lost */ 78 #define ET_TXSTAT_TXWITHCOLL 0x0004 /* encountered collisions during tx */ 79 #define ET_TXSTAT_NONDEFERRED 0x0002 /* transmitted without deferring */ 80 #define ET_TXSTAT_PACKETTX 0x0001 /* packet transmitted successfully */ 81 82 #define TXSTAT_COLLISIONS(x) (((x) & ET_TXSTAT_COLLMASK) >> 8) 83 84 /* et_control */ 85 #define ET_TXCTL_LASTDESC 0x0010 /* last descriptor in frame */ 86 #define ET_TXCTL_NOCRC 0x0008 /* disable CRC generation */ 87 #define ET_TXCTL_IAF 0x0004 /* interrupt after frame */ 88 #define ET_TXCTL_LFFORM 0x0002 /* alternate fraglist format */ 89 #define ET_TXCTL_FRAGLIST 0x0001 /* descriptor points to fraglist */ 90 91 /* 92 * EPIC receive descriptor. Must be 4-byte aligned. 93 */ 94 struct epic_rxdesc { 95 #if BYTE_ORDER == BIG_ENDIAN 96 u_int16_t er_rxlength; /* receive frame length */ 97 u_int16_t er_rxstatus; /* receive status; see below */ 98 #else 99 u_int16_t er_rxstatus; /* receive status; see below */ 100 u_int16_t er_rxlength; /* receive frame length */ 101 #endif 102 u_int32_t er_bufaddr; /* buffer address */ 103 #if BYTE_ORDER == BIG_ENDIAN 104 u_int16_t er_control; /* control word; see below */ 105 u_int16_t er_buflength; /* buffer length */ 106 #else 107 u_int16_t er_buflength; /* buffer length */ 108 u_int16_t er_control; /* control word; see below */ 109 #endif 110 u_int32_t er_nextdesc; /* next descriptor pointer */ 111 }; 112 113 /* er_rxstatus */ 114 #define ER_RXSTAT_OWNER 0x8000 /* NIC owns descriptor */ 115 #define ER_RXSTAT_HDRCOPIED 0x4000 /* rx status posted after hdr copy */ 116 #define ER_RXSTAT_FRAGLISTERR 0x2000 /* ran out of frags to copy frame */ 117 #define ER_RXSTAT_NETSTATVALID 0x1000 /* length and status are valid */ 118 #define ER_RXSTAT_RCVRDIS 0x0040 /* receiver disabled */ 119 #define ER_RXSTAT_BCAST 0x0020 /* broadcast address recognized */ 120 #define ER_RXSTAT_MCAST 0x0010 /* multicast address recognized */ 121 #define ER_RXSTAT_MISSEDPKT 0x0008 /* missed packet */ 122 #define ER_RXSTAT_CRCERROR 0x0004 /* EPIC or MII asserted CRC error */ 123 #define ER_RXSTAT_ALIGNERROR 0x0002 /* frame not byte-aligned */ 124 #define ER_RXSTAT_PKTINTACT 0x0001 /* packet received without error */ 125 126 /* er_control */ 127 #define ER_RXCTL_HEADER 0x0004 /* descriptor is for hdr copy */ 128 #define ER_RXCTL_LFFORM 0x0002 /* alternate fraglist format */ 129 #define ER_RXCTL_FRAGLIST 0x0001 /* descriptor points to fraglist */ 130 131 #define EPIC_NFRAGS 63 /* maximum number of frags in list */ 132 133 /* 134 * EPIC fraglist descriptor. 135 */ 136 struct epic_fraglist { 137 u_int32_t ef_nfrags; /* number of frags in list */ 138 struct { 139 u_int32_t ef_addr; /* address of frag */ 140 u_int32_t ef_length; /* length of frag */ 141 } ef_frags[EPIC_NFRAGS]; 142 }; 143 144 /* 145 * EPIC control registers. 146 */ 147 148 #define EPIC_COMMAND 0x00 /* COMMAND */ 149 #define COMMAND_TXUGO 0x00000080 /* start tx after underrun */ 150 #define COMMAND_STOP_RDMA 0x00000040 /* stop rx dma */ 151 #define COMMAND_STOP_TDMA 0x00000020 /* stop tx dma */ 152 #define COMMAND_NEXTFRAME 0x00000010 /* move onto next rx frame */ 153 #define COMMAND_RXQUEUED 0x00000008 /* queue a rx descriptor */ 154 #define COMMAND_TXQUEUED 0x00000004 /* queue a tx descriptor */ 155 #define COMMAND_START_RX 0x00000002 /* start receiver */ 156 #define COMMAND_STOP_RX 0x00000001 /* stop receiver */ 157 158 #define EPIC_INTSTAT 0x04 /* INTERRUPT STATUS */ 159 #define INTSTAT_PTA 0x08000000 /* PCI target abort */ 160 #define INTSTAT_PMA 0x04000000 /* PCI master abort */ 161 #define INTSTAT_APE 0x02000000 /* PCI address parity error */ 162 #define INTSTAT_DPE 0x01000000 /* PCI data parity error */ 163 #define INTSTAT_RSV 0x00800000 /* rx status valid */ 164 #define INTSTAT_RCTS 0x00400000 /* rx copy threshold status */ 165 #define INTSTAT_RBE 0x00200000 /* rx buffers empty */ 166 #define INTSTAT_TCIP 0x00100000 /* tx copy in progress */ 167 #define INTSTAT_RCIP 0x00080000 /* rx copy in progress */ 168 #define INTSTAT_TXIDLE 0x00040000 /* transmit idle */ 169 #define INTSTAT_RXIDLE 0x00020000 /* receive idle */ 170 #define INTSTAT_INT_ACTV 0x00010000 /* interrupt active */ 171 #define INTSTAT_GP2_INT 0x00008000 /* gpio2 low (PHY event) */ 172 #define INTSTAT_FATAL_INT 0x00001000 /* fatal error occured */ 173 #define INTSTAT_RCT 0x00000800 /* rx copy threshold crossed */ 174 #define INTSTAT_PREI 0x00000400 /* preemptive interrupt */ 175 #define INTSTAT_CNT 0x00000200 /* counter overflow */ 176 #define INTSTAT_TXU 0x00000100 /* transmit underrun */ 177 #define INTSTAT_TQE 0x00000080 /* transmit queue empty */ 178 #define INTSTAT_TCC 0x00000040 /* transmit chain complete */ 179 #define INTSTAT_TXC 0x00000020 /* transmit complete */ 180 #define INTSTAT_RXE 0x00000010 /* receive error */ 181 #define INTSTAT_OVW 0x00000008 /* rx buffer overflow */ 182 #define INTSTAT_RQE 0x00000004 /* receive queue empty */ 183 #define INTSTAT_HCC 0x00000002 /* header copy complete */ 184 #define INTSTAT_RCC 0x00000001 /* receive copy complete */ 185 186 #define EPIC_INTMASK 0x08 /* INTERRUPT MASK */ 187 /* Bits 0-15 enable the corresponding interrupt in INTSTAT. */ 188 189 #define EPIC_GENCTL 0x0c /* GENERAL CONTROL */ 190 #define GENCTL_RESET_PHY 0x00004000 /* reset PHY */ 191 #define GENCTL_SOFT1 0x00002000 /* software use */ 192 #define GENCTL_SOFT0 0x00001000 /* software use */ 193 #define GENCTL_MEM_READ_CTL1 0x00000800 /* PCI memory control */ 194 #define GENCTL_MEM_READ_CTL0 0x00000400 /* (see below) */ 195 #define GENCTL_RX_FIFO_THRESH1 0x00000200 /* rx fifo thresh */ 196 #define GENCTL_RX_FIFO_THRESH0 0x00000100 /* (see below) */ 197 #define GENCTL_BIG_ENDIAN 0x00000020 /* big endian mode */ 198 #define GENCTL_ONECOPY 0x00000010 /* auto-NEXTFRAME */ 199 #define GENCTL_POWERDOWN 0x00000008 /* powersave sleep mode */ 200 #define GENCTL_SOFTINT 0x00000004 /* software-generated intr */ 201 #define GENCTL_INTENA 0x00000002 /* interrupt enable */ 202 #define GENCTL_SOFTRESET 0x00000001 /* initialize EPIC */ 203 204 /* 205 * Explanation of MEMORY READ CONTROL: 206 * 207 * These bits control which PCI command the transmit DMA will use when 208 * bursting data over the PCI bus. When CTL1 is set, the transmit DMA 209 * will use the PCI "memory read line" command. When CTL0 is set, the 210 * transmit DMA will use the PCI "memory read multiple" command. When 211 * neither bit is set, the transmit DMA will use the "memory read" command. 212 * Use of "memory read line" or "memory read multiple" may enhance 213 * performance on some systems. 214 */ 215 216 /* 217 * Explanation of RECEIVE FIFO THRESHOLD: 218 * 219 * Controls the level at which the PCI burst state machine begins to 220 * empty the receive FIFO. Default is "1/2 full" (0,1). 221 * 222 * 0,0 1/4 full 32 bytes 223 * 0,1 1/2 full 64 bytes 224 * 1,0 3/4 full 96 bytes 225 * 1,1 full 128 bytes 226 */ 227 228 #define EPIC_NVCTL 0x10 /* NON-VOLATILE CONTROL */ 229 #define NVCTL_IPG_DLY_MASK 0x00000780 /* interpacket delay gap */ 230 #define NVCTL_CB_MODE 0x00000040 /* CardBus mode */ 231 #define NVCTL_GPIO2 0x00000020 /* general purpose i/o */ 232 #define NVCTL_GPIO1 0x00000010 /* ... */ 233 #define NVCTL_GPOE2 0x00000008 /* general purpose output ena */ 234 #define NVCTL_GPOE1 0x00000004 /* ... */ 235 #define NVCTL_CLKRUNSUPP 0x00000002 /* clock run supported */ 236 #define NVCTL_ENAMEMMAP 0x00000001 /* enable memory map */ 237 238 #define NVCTL_IPG_DLY(x) (((x) & NVCTL_IPG_DLY_MASK) >> 7) 239 240 #define EPIC_EECTL 0x14 /* EEPROM CONTROL */ 241 #define EECTL_EEPROMSIZE 0x00000040 /* eeprom size; see below */ 242 #define EECTL_EERDY 0x00000020 /* eeprom ready */ 243 #define EECTL_EEDO 0x00000010 /* eeprom data out (from) */ 244 #define EECTL_EEDI 0x00000008 /* eeprom data in (to) */ 245 #define EECTL_EESK 0x00000004 /* eeprom clock */ 246 #define EECTL_EECS 0x00000002 /* eeprom chip select */ 247 #define EECTL_ENABLE 0x00000001 /* eeprom enable */ 248 249 /* 250 * Explanation of EEPROM SIZE: 251 * 252 * Indicates the size of the serial EEPROM: 253 * 254 * 1 16x16 or 64x16 255 * 0 128x16 or 256x16 256 */ 257 258 /* 259 * Serial EEPROM opcodes, including start bit: 260 */ 261 #define EPIC_EEPROM_OPC_WRITE 0x05 262 #define EPIC_EEPROM_OPC_READ 0x06 263 264 #define EPIC_PBLCNT 0x18 /* PBLCNT */ 265 #define PBLCNT_MASK 0x0000003f /* programmable burst length */ 266 267 #define EPIC_TEST 0x1c /* TEST */ 268 #define TEST_CLOCKTEST 0x00000008 269 270 #define EPIC_CRCCNT 0x20 /* CRC ERROR COUNTER */ 271 #define CRCCNT_MASK 0x0000000f /* crc errs since last read */ 272 273 #define EPIC_ALICNT 0x24 /* FRAME ALIGNMENT ERROR COUNTER */ 274 #define ALICNT_MASK 0x0000000f /* align errs since last read */ 275 276 #define EPIC_MPCNT 0x28 /* MISSED PACKET COUNTER */ 277 #define MPCNT_MASK 0x0000000f /* miss. pkts since last read */ 278 279 #define EPIC_RXFIFO 0x2c 280 281 #define EPIC_MMCTL 0x30 /* MII MANAGEMENT INTERFACE CONTROL */ 282 #define MMCTL_PHY_ADDR_MASK 0x00003e00 /* phy address field */ 283 #define MMCTL_PHY_REG_ADDR_MASK 0x000001f0 /* phy register address field */ 284 #define MMCTL_RESPONDER 0x00000008 /* phy responder */ 285 #define MMCTL_WRITE 0x00000002 /* write to phy */ 286 #define MMCTL_READ 0x00000001 /* read from phy */ 287 288 #define EPIC_MMDATA 0x34 /* MII MANAGEMENT INTERFACE DATA */ 289 #define MMDATA_MASK 0x0000ffff /* MII frame data */ 290 291 #define EPIC_MIICFG 0x38 /* MII CONFIGURATION */ 292 #define MIICFG_ALTDIR 0x00000080 /* alternate direction */ 293 #define MIICFG_ALTDATA 0x00000040 /* alternate data */ 294 #define MIICFG_ALTCLOCK 0x00000020 /* alternate clock source */ 295 #define MIICFG_ENASER 0x00000010 /* enable serial manag intf */ 296 #define MIICFG_PHYPRESENT 0x00000008 /* phy present on MII */ 297 #define MIICFG_LINKSTATUS 0x00000004 /* 694 link status */ 298 #define MIICFG_ENABLE 0x00000002 /* enable 694 */ 299 #define MIICFG_SERMODEENA 0x00000001 /* serial mode enable */ 300 301 #define EPIC_IPG 0x3c /* INTERPACKET GAP */ 302 #define IPG_INTERFRAME_MASK 0x00007f00 /* interframe gap time */ 303 #define IPG_INTERPKT_MASK 0x000000ff /* interpacket gap time */ 304 305 #define EPIC_LAN0 0x40 /* LAN ADDRESS */ 306 307 #define EPIC_LAN1 0x44 308 309 #define EPIC_LAN2 0x48 310 311 #define LANn_MASK 0x0000ffff 312 313 /* 314 * Explanation of LAN ADDRESS registers: 315 * 316 * LAN address is described as: 317 * 318 * 0000 [n1][n0][n3][n2] | 0000 [n5][n4][n7][n6] | 0000 [n9][n8][n11][n10] 319 * 320 * n == one nibble, mapped as follows: 321 * 322 * LAN0 [15-12] n3 323 * LAN0 [11-8] n2 324 * LAN0 [7-4] n1 325 * LAN0 [3-0] n0 326 * LAN1 [15-12] n7 327 * LAN1 [11-8] n6 328 * LAN1 [7-4] n5 329 * LAN1 [3-0] n4 330 * LAN2 [15-12] n11 331 * LAN2 [11-8] n10 332 * LAN2 [7-4] n9 333 * LAN2 [3-0] n8 334 * 335 * The LAN address is automatically recalled from the EEPROM after a 336 * hard reseet. 337 */ 338 339 #define EPIC_IDCHK 0x4c /* BOARD ID/CHECKSUM */ 340 #define IDCHK_ID_MASK 0x0000ff00 /* board ID */ 341 #define IDCHK_CKSUM_MASK 0x000000ff /* checksum (should be 0xff) */ 342 343 #define EPIC_MC0 0x50 /* MULTICAST ADDDRESS HASH TABLE */ 344 345 #define EPIC_MC1 0x54 346 347 #define EPIC_MC2 0x58 348 349 #define EPIC_MC3 0x5c 350 351 /* 352 * Explanation of MULTICAST ADDRESS HASH TABLE registers: 353 * 354 * Bits in the hash table are encoded as follows: 355 * 356 * MC0 [15-0] 357 * MC1 [31-16] 358 * MC2 [47-32] 359 * MC3 [53-48] 360 */ 361 362 #define EPIC_RXCON 0x60 /* RECEIVE CONTROL */ 363 #define RXCON_EXTBUFSIZESEL1 0x00000200 /* ext buf size; see below */ 364 #define RXCON_EXTBUFSIZESEL0 0x00000100 /* ... */ 365 #define RXCON_EARLYRXENABLE 0x00000080 /* early receive enable */ 366 #define RXCON_MONITORMODE 0x00000040 /* monitor mode */ 367 #define RXCON_PROMISCMODE 0x00000020 /* promiscuous mode */ 368 #define RXCON_RXINVADDR 0x00000010 /* rx inv individual addr */ 369 #define RXCON_RXMULTICAST 0x00000008 /* receive multicast */ 370 #define RXCON_RXBROADCAST 0x00000004 /* receive broadcast */ 371 #define RXCON_RXRUNT 0x00000002 /* receive runt frames */ 372 #define RXCON_SAVEERRPKTS 0x00000001 /* save errored packets */ 373 374 /* 375 * Explanation of EXTERNAL BUFFER SIZE SELECT: 376 * 377 * 0,0 external buffer access is disabled 378 * 0,1 16k 379 * 1,0 32k 380 * 1,1 128k 381 */ 382 383 #define EPIC_RXSTAT 0x64 /* RECEIVE STATUS */ 384 385 #define EPIC_RXCNT 0x68 386 387 #define EPIC_RXTEST 0x6c 388 389 #define EPIC_TXCON 0x70 /* TRANSMIT CONTROL */ 390 #define TXCON_SLOTTIME_MASK 0x000000f8 /* slot time */ 391 #define TXCON_LOOPBACK_D2 0x00000004 /* loopback mode bit 2 */ 392 #define TXCON_LOOPBACK_D1 0x00000002 /* loopback mode bit 1 */ 393 #define TXCON_EARLYTX_ENABLE 0x00000001 /* early transmit enable */ 394 395 /* 396 * Explanation of LOOPBACK MODE BIT: 397 * 398 * 0,0 normal operation 399 * 0,1 internal loopback (before PHY) 400 * 1,0 external loopback (after PHY) 401 * 1,1 full duplex - decouples transmit and receive blocks 402 */ 403 404 #define EPIC_TXSTAT 0x74 /* TRANSMIT STATUS */ 405 406 #define EPIC_TDPAR 0x78 407 408 #define EPIC_TXTEST 0x7c 409 410 #define EPIC_PRFDAR 0x80 411 412 #define EPIC_PRCDAR 0x84 /* PCI RECEIVE CURRENT DESCRIPTOR ADDR */ 413 414 #define EPIC_PRHDAR 0x88 415 416 #define EPIC_PRFLAR 0x8c 417 418 #define EPIC_PRDLGTH 0x90 419 420 #define EPIC_PRFCNT 0x94 421 422 #define EPIC_PRLCAR 0x98 423 424 #define EPIC_PRLPAR 0x9c 425 426 #define EPIC_PREFAR 0xa0 427 428 #define EPIC_PRSTAT 0xa4 /* PCI RECEIVE DMA STATUS */ 429 430 #define EPIC_PRBUF 0xa8 431 432 #define EPIC_RDNCAR 0xac 433 434 #define EPIC_PRCPTHR 0xb0 /* PCI RECEIVE COPY THRESHOLD */ 435 436 #define EPIC_ROMDATA 0xb4 437 438 #define EPIC_PREEMPR 0xbc 439 440 #define EPIC_PTFDAR 0xc0 441 442 #define EPIC_PTCDAR 0xc4 /* PCI TRANSMIT CURRENT DESCRIPTOR ADDR */ 443 444 #define EPIC_PTHDAR 0xc8 445 446 #define EPIC_PTFLAR 0xcc 447 448 #define EPIC_PTDLGTH 0xd0 449 450 #define EPIC_PTFCNT 0xd4 451 452 #define EPIC_PTLCAR 0xd8 453 454 #define EPIC_ETXTHR 0xdc /* EARLY TRANSMIT THRESHOLD */ 455 456 #define EPIC_PTETXC 0xe0 457 458 #define EPIC_PTSTAT 0xe4 459 460 #define EPIC_PTBUF 0xe8 461 462 #define EPIC_PTFDAR2 0xec 463 464 #define EPIC_FEVTR 0xf0 /* FEVTR (CardBus) */ 465 466 #define EPIC_FEVTRMSKR 0xf4 /* FEVTRMSKR (CardBus) */ 467 468 #define EPIC_FPRSTSTR 0xf8 /* FPRSTR (CardBus) */ 469 470 #define EPIC_FFRCEVTR 0xfc /* PPRCEVTR (CardBus) */ 471 472 /* 473 * EEPROM format: 474 * 475 * Word Bits Description 476 * ---- ---- ----------- 477 * 0 7-0 LAN Address Byte 0 478 * 0 15-8 LAN Address Byte 1 479 * 1 7-0 LAN Address Byte 2 480 * 1 15-8 LAN Address Byte 3 481 * 2 7-0 LAN Address Byte 4 482 * 2 15-8 LAN Address Byte 5 483 * 3 7-0 Board ID 484 * 3 15-8 Checksum 485 * 4 5-0 Non-Volatile Control Register Contents 486 * 5 7-0 PCI Minimum Grant Desired Setting 487 * 5 15-8 PCI Maximum Latency Desired Setting 488 * 6 15-0 Subsystem Vendor ID 489 * 7 14-0 Subsystem ID 490 */ 491 492 #endif /* _DEV_IC_SMC83C170REG_H_ */ 493
Indexes created Sat Sep 27 14:09:57 GMT 2025