smc83c170reg.h revision 1.3.8.1
1 /* $NetBSD: smc83c170reg.h,v 1.3.8.1 1999/08/02 21:59:06 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_IC_SMC83C170REG_H_ 41 #define _DEV_IC_SMC83C170REG_H_ 42 43 /* 44 * Register description for the Standard Microsystems Corp. 83C170 45 * Ethernet PCI Integrated Controller (EPIC/100). 46 */ 47 48 /* 49 * EPIC transmit descriptor. Must be 4-byte aligned. 50 */ 51 struct epic_txdesc { 52 u_int16_t et_txstatus; /* transmit status; see below */ 53 u_int16_t et_txlength; /* transmit length */ 54 u_int32_t et_bufaddr; /* buffer address */ 55 u_int16_t et_buflength; /* buffer length */ 56 u_int16_t et_control; /* control word; see below */ 57 u_int32_t et_nextdesc; /* next descriptor pointer */ 58 }; 59 60 /* et_txstatus */ 61 #define ET_TXSTAT_OWNER 0x8000 /* NIC owns descriptor */ 62 #define ET_TXSTAT_COLLMASK 0x1f00 /* collisions */ 63 #define ET_TXSTAT_DEFERRING 0x0080 /* deferring due to jabber */ 64 #define ET_TXSTAT_OOWCOLL 0x0040 /* out of window collision */ 65 #define ET_TXSTAT_CDHB 0x0020 /* collision detect heartbeat */ 66 #define ET_TXSTAT_UNDERRUN 0x0010 /* DMA underrun */ 67 #define ET_TXSTAT_CARSENSELOST 0x0008 /* carrier lost */ 68 #define ET_TXSTAT_TXWITHCOLL 0x0004 /* encountered collisions during tx */ 69 #define ET_TXSTAT_NONDEFERRED 0x0002 /* transmitted without deferring */ 70 #define ET_TXSTAT_PACKETTX 0x0001 /* packet transmitted successfully */ 71 72 #define TXSTAT_COLLISIONS(x) (((x) & ET_TXSTAT_COLLMASK) >> 8) 73 74 /* et_control */ 75 #define ET_TXCTL_LASTDESC 0x0010 /* last descriptor in frame */ 76 #define ET_TXCTL_NOCRC 0x0008 /* disable CRC generation */ 77 #define ET_TXCTL_IAF 0x0004 /* interrupt after frame */ 78 #define ET_TXCTL_LFFORM 0x0002 /* alternate fraglist format */ 79 #define ET_TXCTL_FRAGLIST 0x0001 /* descriptor points to fraglist */ 80 81 /* 82 * EPIC receive descriptor. Must be 4-byte aligned. 83 */ 84 struct epic_rxdesc { 85 u_int16_t er_rxstatus; /* receive status; see below */ 86 u_int16_t er_rxlength; /* receive frame length */ 87 u_int32_t er_bufaddr; /* buffer address */ 88 u_int16_t er_buflength; /* buffer length */ 89 u_int16_t er_control; /* control word; see below */ 90 u_int32_t er_nextdesc; /* next descriptor pointer */ 91 }; 92 93 /* er_rxstatus */ 94 #define ER_RXSTAT_OWNER 0x8000 /* NIC owns descriptor */ 95 #define ER_RXSTAT_HDRCOPIED 0x4000 /* rx status posted after hdr copy */ 96 #define ER_RXSTAT_FRAGLISTERR 0x2000 /* ran out of frags to copy frame */ 97 #define ER_RXSTAT_NETSTATVALID 0x1000 /* length and status are valid */ 98 #define ER_RXSTAT_RCVRDIS 0x0040 /* receiver disabled */ 99 #define ER_RXSTAT_BCAST 0x0020 /* broadcast address recognized */ 100 #define ER_RXSTAT_MCAST 0x0010 /* multicast address recognized */ 101 #define ER_RXSTAT_MISSEDPKT 0x0008 /* missed packet */ 102 #define ER_RXSTAT_CRCERROR 0x0004 /* EPIC or MII asserted CRC error */ 103 #define ER_RXSTAT_ALIGNERROR 0x0002 /* frame not byte-aligned */ 104 #define ER_RXSTAT_PKTINTACT 0x0001 /* packet received without error */ 105 106 /* er_control */ 107 #define ER_RXCTL_HEADER 0x0004 /* descriptor is for hdr copy */ 108 #define ER_RXCTL_LFFORM 0x0002 /* alternate fraglist format */ 109 #define ER_RXCTL_FRAGLIST 0x0001 /* descriptor points to fraglist */ 110 111 #define EPIC_NFRAGS 63 /* maximum number of frags in list */ 112 113 /* 114 * EPIC fraglist descriptor. 115 */ 116 struct epic_fraglist { 117 u_int32_t ef_nfrags; /* number of frags in list */ 118 struct { 119 u_int32_t ef_addr; /* address of frag */ 120 u_int32_t ef_length; /* length of frag */ 121 } ef_frags[EPIC_NFRAGS]; 122 }; 123 124 /* 125 * EPIC control registers. 126 */ 127 128 #define EPIC_COMMAND 0x00 /* COMMAND */ 129 #define COMMAND_TXUGO 0x00000080 /* start tx after underrun */ 130 #define COMMAND_STOP_RDMA 0x00000040 /* stop rx dma */ 131 #define COMMAND_STOP_TDMA 0x00000020 /* stop tx dma */ 132 #define COMMAND_NEXTFRAME 0x00000010 /* move onto next rx frame */ 133 #define COMMAND_RXQUEUED 0x00000008 /* queue a rx descriptor */ 134 #define COMMAND_TXQUEUED 0x00000004 /* queue a tx descriptor */ 135 #define COMMAND_START_RX 0x00000002 /* start receiver */ 136 #define COMMAND_STOP_RX 0x00000001 /* stop receiver */ 137 138 #define EPIC_INTSTAT 0x04 /* INTERRUPT STATUS */ 139 #define INTSTAT_PTA 0x08000000 /* PCI target abort */ 140 #define INTSTAT_PMA 0x04000000 /* PCI master abort */ 141 #define INTSTAT_APE 0x02000000 /* PCI address parity error */ 142 #define INTSTAT_DPE 0x01000000 /* PCI data parity error */ 143 #define INTSTAT_RSV 0x00800000 /* rx status valid */ 144 #define INTSTAT_RCTS 0x00400000 /* rx copy threshold status */ 145 #define INTSTAT_RBE 0x00200000 /* rx buffers empty */ 146 #define INTSTAT_TCIP 0x00100000 /* tx copy in progress */ 147 #define INTSTAT_RCIP 0x00080000 /* rx copy in progress */ 148 #define INTSTAT_TXIDLE 0x00040000 /* transmit idle */ 149 #define INTSTAT_RXIDLE 0x00020000 /* receive idle */ 150 #define INTSTAT_INT_ACTV 0x00010000 /* interrupt active */ 151 #define INTSTAT_GP2_INT 0x00008000 /* gpio2 low (PHY event) */ 152 #define INTSTAT_FATAL_INT 0x00001000 /* fatal error occured */ 153 #define INTSTAT_RCT 0x00000800 /* rx copy threshold crossed */ 154 #define INTSTAT_PREI 0x00000400 /* preemptive interrupt */ 155 #define INTSTAT_CNT 0x00000200 /* counter overflow */ 156 #define INTSTAT_TXU 0x00000100 /* transmit underrun */ 157 #define INTSTAT_TQE 0x00000080 /* transmit queue empty */ 158 #define INTSTAT_TCC 0x00000040 /* transmit chain complete */ 159 #define INTSTAT_TXC 0x00000020 /* transmit complete */ 160 #define INTSTAT_RXE 0x00000010 /* receive error */ 161 #define INTSTAT_OVW 0x00000008 /* rx buffer overflow */ 162 #define INTSTAT_RQE 0x00000004 /* receive queue empty */ 163 #define INTSTAT_HCC 0x00000002 /* header copy complete */ 164 #define INTSTAT_RCC 0x00000001 /* receive copy complete */ 165 166 #define EPIC_INTMASK 0x08 /* INTERRUPT MASK */ 167 /* Bits 0-15 enable the corresponding interrupt in INTSTAT. */ 168 169 #define EPIC_GENCTL 0x0c /* GENERAL CONTROL */ 170 #define GENCTL_RESET_PHY 0x00004000 /* reset PHY */ 171 #define GENCTL_SOFT1 0x00002000 /* software use */ 172 #define GENCTL_SOFT0 0x00001000 /* software use */ 173 #define GENCTL_MEM_READ_CTL1 0x00000800 /* PCI memory control */ 174 #define GENCTL_MEM_READ_CTL0 0x00000400 /* (see below) */ 175 #define GENCTL_RX_FIFO_THRESH1 0x00000200 /* rx fifo thresh */ 176 #define GENCTL_RX_FIFO_THRESH0 0x00000100 /* (see below) */ 177 #define GENCTL_BIG_ENDIAN 0x00000020 /* big endian mode */ 178 #define GENCTL_ONECOPY 0x00000010 /* auto-NEXTFRAME */ 179 #define GENCTL_POWERDOWN 0x00000008 /* powersave sleep mode */ 180 #define GENCTL_SOFTINT 0x00000004 /* software-generated intr */ 181 #define GENCTL_INTENA 0x00000002 /* interrupt enable */ 182 #define GENCTL_SOFTRESET 0x00000001 /* initialize EPIC */ 183 184 /* 185 * Explanation of MEMORY READ CONTROL: 186 * 187 * These bits control which PCI command the transmit DMA will use when 188 * bursting data over the PCI bus. When CTL1 is set, the transmit DMA 189 * will use the PCI "memory read line" command. When CTL0 is set, the 190 * transmit DMA will use the PCI "memory read multiple" command. When 191 * neither bit is set, the transmit DMA will use the "memory read" command. 192 * Use of "memory read line" or "memory read multiple" may enhance 193 * performance on some systems. 194 */ 195 196 /* 197 * Explanation of RECEIVE FIFO THRESHOLD: 198 * 199 * Controls the level at which the PCI burst state machine begins to 200 * empty the receive FIFO. Default is "1/2 full" (0,1). 201 * 202 * 0,0 1/4 full 32 bytes 203 * 0,1 1/2 full 64 bytes 204 * 1,0 3/4 full 96 bytes 205 * 1,1 full 128 bytes 206 */ 207 208 #define EPIC_NVCTL 0x10 /* NON-VOLATILE CONTROL */ 209 #define NVCTL_IPG_DLY_MASK 0x00000780 /* interpacket delay gap */ 210 #define NVCTL_CB_MODE 0x00000040 /* CardBus mode */ 211 #define NVCTL_GPIO2 0x00000020 /* general purpose i/o */ 212 #define NVCTL_GPIO1 0x00000010 /* ... */ 213 #define NVCTL_GPOE2 0x00000008 /* general purpose output ena */ 214 #define NVCTL_GPOE1 0x00000004 /* ... */ 215 #define NVCTL_CLKRUNSUPP 0x00000002 /* clock run supported */ 216 #define NVCTL_ENAMEMMAP 0x00000001 /* enable memory map */ 217 218 #define NVCTL_IPG_DLY(x) (((x) & NVCTL_IPG_DLY_MASK) >> 7) 219 220 #define EPIC_EECTL 0x14 /* EEPROM CONTROL */ 221 #define EECTL_EEPROMSIZE 0x00000040 /* eeprom size; see below */ 222 #define EECTL_EERDY 0x00000020 /* eeprom ready */ 223 #define EECTL_EEDO 0x00000010 /* eeprom data out (from) */ 224 #define EECTL_EEDI 0x00000008 /* eeprom data in (to) */ 225 #define EECTL_EESK 0x00000004 /* eeprom clock */ 226 #define EECTL_EECS 0x00000002 /* eeprom chip select */ 227 #define EECTL_ENABLE 0x00000001 /* eeprom enable */ 228 229 /* 230 * Explanation of EEPROM SIZE: 231 * 232 * Indicates the size of the serial EEPROM: 233 * 234 * 1 16x16 or 64x16 235 * 0 128x16 or 256x16 236 */ 237 238 /* 239 * Serial EEPROM opcodes, including start bit: 240 */ 241 #define EPIC_EEPROM_OPC_WRITE 0x05 242 #define EPIC_EEPROM_OPC_READ 0x06 243 244 #define EPIC_PBLCNT 0x18 /* PBLCNT */ 245 #define PBLCNT_MASK 0x0000003f /* programmable burst length */ 246 247 #define EPIC_TEST 0x1c /* TEST */ 248 #define TEST_CLOCKTEST 0x00000008 249 250 #define EPIC_CRCCNT 0x20 /* CRC ERROR COUNTER */ 251 #define CRCCNT_MASK 0x0000000f /* crc errs since last read */ 252 253 #define EPIC_ALICNT 0x24 /* FRAME ALIGNMENT ERROR COUNTER */ 254 #define ALICNT_MASK 0x0000000f /* align errs since last read */ 255 256 #define EPIC_MPCNT 0x28 /* MISSED PACKET COUNTER */ 257 #define MPCNT_MASK 0x0000000f /* miss. pkts since last read */ 258 259 #define EPIC_RXFIFO 0x2c 260 261 #define EPIC_MMCTL 0x30 /* MII MANAGEMENT INTERFACE CONTROL */ 262 #define MMCTL_PHY_ADDR_MASK 0x00003e00 /* phy address field */ 263 #define MMCTL_PHY_REG_ADDR_MASK 0x000001f0 /* phy register address field */ 264 #define MMCTL_RESPONDER 0x00000008 /* phy responder */ 265 #define MMCTL_WRITE 0x00000002 /* write to phy */ 266 #define MMCTL_READ 0x00000001 /* read from phy */ 267 268 #define MMCTL_ARG(phy, reg, cmd) (((phy) << 9) | ((reg) << 4) | (cmd)) 269 270 #define EPIC_MMDATA 0x34 /* MII MANAGEMENT INTERFACE DATA */ 271 #define MMDATA_MASK 0x0000ffff /* MII frame data */ 272 273 #define EPIC_MIICFG 0x38 /* MII CONFIGURATION */ 274 #define MIICFG_ALTDIR 0x00000080 /* alternate direction */ 275 #define MIICFG_ALTDATA 0x00000040 /* alternate data */ 276 #define MIICFG_ALTCLOCK 0x00000020 /* alternate clock source */ 277 #define MIICFG_ENASER 0x00000010 /* enable serial manag intf */ 278 #define MIICFG_PHYPRESENT 0x00000008 /* phy present on MII */ 279 #define MIICFG_LINKSTATUS 0x00000004 /* 694 link status */ 280 #define MIICFG_ENABLE 0x00000002 /* enable 694 */ 281 #define MIICFG_SERMODEENA 0x00000001 /* serial mode enable */ 282 283 #define EPIC_IPG 0x3c /* INTERPACKET GAP */ 284 #define IPG_INTERFRAME_MASK 0x00007f00 /* interframe gap time */ 285 #define IPG_INTERPKT_MASK 0x000000ff /* interpacket gap time */ 286 287 #define EPIC_LAN0 0x40 /* LAN ADDRESS */ 288 289 #define EPIC_LAN1 0x44 290 291 #define EPIC_LAN2 0x48 292 293 #define LANn_MASK 0x0000ffff 294 295 /* 296 * Explanation of LAN ADDRESS registers: 297 * 298 * LAN address is described as: 299 * 300 * 0000 [n1][n0][n3][n2] | 0000 [n5][n4][n7][n6] | 0000 [n9][n8][n11][n10] 301 * 302 * n == one nibble, mapped as follows: 303 * 304 * LAN0 [15-12] n3 305 * LAN0 [11-8] n2 306 * LAN0 [7-4] n1 307 * LAN0 [3-0] n0 308 * LAN1 [15-12] n7 309 * LAN1 [11-8] n6 310 * LAN1 [7-4] n5 311 * LAN1 [3-0] n4 312 * LAN2 [15-12] n11 313 * LAN2 [11-8] n10 314 * LAN2 [7-4] n9 315 * LAN2 [3-0] n8 316 * 317 * The LAN address is automatically recalled from the EEPROM after a 318 * hard reseet. 319 */ 320 321 #define EPIC_IDCHK 0x4c /* BOARD ID/CHECKSUM */ 322 #define IDCHK_ID_MASK 0x0000ff00 /* board ID */ 323 #define IDCHK_CKSUM_MASK 0x000000ff /* checksum (should be 0xff) */ 324 325 #define EPIC_MC0 0x50 /* MULTICAST ADDDRESS HASH TABLE */ 326 327 #define EPIC_MC1 0x54 328 329 #define EPIC_MC2 0x58 330 331 #define EPIC_MC3 0x5c 332 333 /* 334 * Explanation of MULTICAST ADDRESS HASH TABLE registers: 335 * 336 * Bits in the hash table are encoded as follows: 337 * 338 * MC0 [15-0] 339 * MC1 [31-16] 340 * MC2 [47-32] 341 * MC3 [53-48] 342 */ 343 344 #define EPIC_RXCON 0x60 /* RECEIVE CONTROL */ 345 #define RXCON_EXTBUFSIZESEL1 0x00000200 /* ext buf size; see below */ 346 #define RXCON_EXTBUFSIZESEL0 0x00000100 /* ... */ 347 #define RXCON_EARLYRXENABLE 0x00000080 /* early receive enable */ 348 #define RXCON_MONITORMODE 0x00000040 /* monitor mode */ 349 #define RXCON_PROMISCMODE 0x00000020 /* promiscuous mode */ 350 #define RXCON_RXINVADDR 0x00000010 /* rx inv individual addr */ 351 #define RXCON_RXMULTICAST 0x00000008 /* receive multicast */ 352 #define RXCON_RXBROADCAST 0x00000004 /* receive broadcast */ 353 #define RXCON_RXRUNT 0x00000002 /* receive runt frames */ 354 #define RXCON_SAVEERRPKTS 0x00000001 /* save errored packets */ 355 356 /* 357 * Explanation of EXTERNAL BUFFER SIZE SELECT: 358 * 359 * 0,0 external buffer access is disabled 360 * 0,1 16k 361 * 1,0 32k 362 * 1,1 128k 363 */ 364 365 #define EPIC_RXSTAT 0x64 /* RECEIVE STATUS */ 366 367 #define EPIC_RXCNT 0x68 368 369 #define EPIC_RXTEST 0x6c 370 371 #define EPIC_TXCON 0x70 /* TRANSMIT CONTROL */ 372 #define TXCON_SLOTTIME_MASK 0x000000f8 /* slot time */ 373 #define TXCON_LOOPBACK_D2 0x00000004 /* loopback mode bit 2 */ 374 #define TXCON_LOOPBACK_D1 0x00000002 /* loopback mode bit 1 */ 375 #define TXCON_EARLYTX_ENABLE 0x00000001 /* early transmit enable */ 376 377 /* 378 * Explanation of LOOPBACK MODE BIT: 379 * 380 * 0,0 normal operation 381 * 0,1 internal loopback (before PHY) 382 * 1,0 external loopback (after PHY) 383 * 1,1 full duplex - decouples transmit and receive blocks 384 */ 385 386 #define EPIC_TXSTAT 0x74 /* TRANSMIT STATUS */ 387 388 #define EPIC_TDPAR 0x78 389 390 #define EPIC_TXTEST 0x7c 391 392 #define EPIC_PRFDAR 0x80 393 394 #define EPIC_PRCDAR 0x84 /* PCI RECEIVE CURRENT DESCRIPTOR ADDR */ 395 396 #define EPIC_PRHDAR 0x88 397 398 #define EPIC_PRFLAR 0x8c 399 400 #define EPIC_PRDLGTH 0x90 401 402 #define EPIC_PRFCNT 0x94 403 404 #define EPIC_PRLCAR 0x98 405 406 #define EPIC_PRLPAR 0x9c 407 408 #define EPIC_PREFAR 0xa0 409 410 #define EPIC_PRSTAT 0xa4 /* PCI RECEIVE DMA STATUS */ 411 412 #define EPIC_PRBUF 0xa8 413 414 #define EPIC_RDNCAR 0xac 415 416 #define EPIC_PRCPTHR 0xb0 /* PCI RECEIVE COPY THRESHOLD */ 417 418 #define EPIC_ROMDATA 0xb4 419 420 #define EPIC_PREEMPR 0xbc 421 422 #define EPIC_PTFDAR 0xc0 423 424 #define EPIC_PTCDAR 0xc4 /* PCI TRANSMIT CURRENT DESCRIPTOR ADDR */ 425 426 #define EPIC_PTHDAR 0xc8 427 428 #define EPIC_PTFLAR 0xcc 429 430 #define EPIC_PTDLGTH 0xd0 431 432 #define EPIC_PTFCNT 0xd4 433 434 #define EPIC_PTLCAR 0xd8 435 436 #define EPIC_ETXTHR 0xdc /* EARLY TRANSMIT THRESHOLD */ 437 438 #define EPIC_PTETXC 0xe0 439 440 #define EPIC_PTSTAT 0xe4 441 442 #define EPIC_PTBUF 0xe8 443 444 #define EPIC_PTFDAR2 0xec 445 446 #define EPIC_FEVTR 0xf0 /* FEVTR (CardBus) */ 447 448 #define EPIC_FEVTRMSKR 0xf4 /* FEVTRMSKR (CardBus) */ 449 450 #define EPIC_FPRSTSTR 0xf8 /* FPRSTR (CardBus) */ 451 452 #define EPIC_FFRCEVTR 0xfc /* PPRCEVTR (CardBus) */ 453 454 /* 455 * EEPROM format: 456 * 457 * Word Bits Description 458 * ---- ---- ----------- 459 * 0 7-0 LAN Address Byte 0 460 * 0 15-8 LAN Address Byte 1 461 * 1 7-0 LAN Address Byte 2 462 * 1 15-8 LAN Address Byte 3 463 * 2 7-0 LAN Address Byte 4 464 * 2 15-8 LAN Address Byte 5 465 * 3 7-0 Board ID 466 * 3 15-8 Checksum 467 * 4 5-0 Non-Volatile Control Register Contents 468 * 5 7-0 PCI Minimum Grant Desired Setting 469 * 5 15-8 PCI Maximum Latency Desired Setting 470 * 6 15-0 Subsystem Vendor ID 471 * 7 14-0 Subsystem ID 472 */ 473 474 #endif /* _DEV_IC_SMC83C170REG_H_ */ 475
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