smc83c170var.h revision 1.3
1 /* $NetBSD: smc83c170var.h,v 1.3 1999/02/12 05:55:27 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_IC_SMC83C170VAR_H_ 41 #define _DEV_IC_SMC83C170VAR_H_ 42 43 /* 44 * Misc. definitions for the Standard Microsystems Corp. 83C170 45 * Ethernet PCI Integrated Controller (EPIC/100) driver. 46 */ 47 48 /* 49 * Transmit descriptor list size. 50 */ 51 #define EPIC_NTXDESC 128 52 #define EPIC_NTXDESC_MASK (EPIC_NTXDESC - 1) 53 #define EPIC_NEXTTX(x) ((x + 1) & EPIC_NTXDESC_MASK) 54 55 /* 56 * Receive descriptor list size. 57 */ 58 #define EPIC_NRXDESC 64 59 #define EPIC_NRXDESC_MASK (EPIC_NRXDESC - 1) 60 #define EPIC_NEXTRX(x) ((x + 1) & EPIC_NRXDESC_MASK) 61 62 /* 63 * Control structures are DMA'd to the EPIC chip. We allocate them in 64 * a single clump that maps to a single DMA segment to make several things 65 * easier. 66 */ 67 struct epic_control_data { 68 /* 69 * The transmit descriptors. 70 */ 71 struct epic_txdesc ecd_txdescs[EPIC_NTXDESC]; 72 73 /* 74 * The receive descriptors. 75 */ 76 struct epic_rxdesc ecd_rxdescs[EPIC_NRXDESC]; 77 78 /* 79 * The transmit fraglists. 80 */ 81 struct epic_fraglist ecd_txfrags[EPIC_NTXDESC]; 82 }; 83 84 #define EPIC_CDOFF(x) offsetof(struct epic_control_data, x) 85 #define EPIC_CDTXOFF(x) EPIC_CDOFF(ecd_txdescs[(x)]) 86 #define EPIC_CDRXOFF(x) EPIC_CDOFF(ecd_rxdescs[(x)]) 87 #define EPIC_CDFLOFF(x) EPIC_CDOFF(ecd_txfrags[(x)]) 88 89 /* 90 * Software state for transmit and receive desciptors. 91 */ 92 struct epic_descsoft { 93 struct mbuf *ds_mbuf; /* head of mbuf chain */ 94 bus_dmamap_t ds_dmamap; /* our DMA map */ 95 }; 96 97 /* 98 * Software state per device. 99 */ 100 struct epic_softc { 101 struct device sc_dev; /* generic device information */ 102 bus_space_tag_t sc_st; /* bus space tag */ 103 bus_space_handle_t sc_sh; /* bus space handle */ 104 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 105 struct ethercom sc_ethercom; /* ethernet common data */ 106 void *sc_sdhook; /* shutdown hook */ 107 108 struct mii_data sc_mii; /* MII/media information */ 109 110 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 111 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 112 113 /* 114 * Software state for transmit and receive descriptors. 115 */ 116 struct epic_descsoft sc_txsoft[EPIC_NTXDESC]; 117 struct epic_descsoft sc_rxsoft[EPIC_NRXDESC]; 118 119 /* 120 * Control data structures. 121 */ 122 struct epic_control_data *sc_control_data; 123 124 int sc_txpending; /* number of TX requests pending */ 125 int sc_txdirty; /* first dirty TX descriptor */ 126 int sc_txlast; /* last used TX descriptor */ 127 128 int sc_rxptr; /* next ready RX descriptor */ 129 }; 130 131 #define EPIC_CDTXADDR(sc, x) ((sc)->sc_cddma + EPIC_CDTXOFF((x))) 132 #define EPIC_CDRXADDR(sc, x) ((sc)->sc_cddma + EPIC_CDRXOFF((x))) 133 #define EPIC_CDFLADDR(sc, x) ((sc)->sc_cddma + EPIC_CDFLOFF((x))) 134 135 #define EPIC_CDTX(sc, x) (&(sc)->sc_control_data->ecd_txdescs[(x)]) 136 #define EPIC_CDRX(sc, x) (&(sc)->sc_control_data->ecd_rxdescs[(x)]) 137 #define EPIC_CDFL(sc, x) (&(sc)->sc_control_data->ecd_txfrags[(x)]) 138 139 #define EPIC_DSTX(sc, x) (&(sc)->sc_txsoft[(x)]) 140 #define EPIC_DSRX(sc, x) (&(sc)->sc_rxsoft[(x)]) 141 142 #define EPIC_CDTXSYNC(sc, x, ops) \ 143 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 144 EPIC_CDTXOFF((x)), sizeof(struct epic_txdesc), (ops)) 145 146 #define EPIC_CDRXSYNC(sc, x, ops) \ 147 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 148 EPIC_CDRXOFF((x)), sizeof(struct epic_rxdesc), (ops)) 149 150 #define EPIC_CDFLSYNC(sc, x, ops) \ 151 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 152 EPIC_CDFLOFF((x)), sizeof(struct epic_fraglist), (ops)) 153 154 #define EPIC_INIT_RXDESC(sc, x) \ 155 do { \ 156 struct epic_descsoft *__ds = EPIC_DSRX((sc), (x)); \ 157 struct epic_rxdesc *__rxd = EPIC_CDRX((sc), (x)); \ 158 struct mbuf *__m = __ds->ds_mbuf; \ 159 \ 160 /* \ 161 * Note we scoot the packet forward 2 bytes in the buffer \ 162 * so that the payload after the Ethernet header is aligned \ 163 * to a 4 byte boundary. \ 164 */ \ 165 __m->m_data = __m->m_ext.ext_buf + 2; \ 166 __rxd->er_bufaddr = __ds->ds_dmamap->dm_segs[0].ds_addr + 2; \ 167 __rxd->er_buflength = __m->m_ext.ext_size - 2; \ 168 __rxd->er_control = 0; \ 169 __rxd->er_rxstatus = ER_RXSTAT_OWNER; \ 170 __rxd->er_nextdesc = EPIC_CDRXADDR((sc), EPIC_NEXTRX((x))); \ 171 EPIC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 172 } while (0) 173 174 #ifdef _KERNEL 175 void epic_attach __P((struct epic_softc *)); 176 int epic_intr __P((void *)); 177 #endif /* _KERNEL */ 178 179 #endif /* _DEV_IC_SMC83C170VAR_H_ */ 180
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