smc91cxx.c revision 1.68 1 1.68 nakayama /* $NetBSD: smc91cxx.c,v 1.68 2008/04/29 17:48:43 nakayama Exp $ */
2 1.2 thorpej
3 1.2 thorpej /*-
4 1.2 thorpej * Copyright (c) 1997 The NetBSD Foundation, Inc.
5 1.2 thorpej * All rights reserved.
6 1.2 thorpej *
7 1.2 thorpej * This code is derived from software contributed to The NetBSD Foundation
8 1.2 thorpej * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 1.2 thorpej * NASA Ames Research Center.
10 1.2 thorpej *
11 1.2 thorpej * Redistribution and use in source and binary forms, with or without
12 1.2 thorpej * modification, are permitted provided that the following conditions
13 1.2 thorpej * are met:
14 1.2 thorpej * 1. Redistributions of source code must retain the above copyright
15 1.2 thorpej * notice, this list of conditions and the following disclaimer.
16 1.2 thorpej * 2. Redistributions in binary form must reproduce the above copyright
17 1.2 thorpej * notice, this list of conditions and the following disclaimer in the
18 1.2 thorpej * documentation and/or other materials provided with the distribution.
19 1.2 thorpej *
20 1.2 thorpej * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 1.2 thorpej * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 1.2 thorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 1.3 jtc * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 1.3 jtc * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 1.2 thorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 1.2 thorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 1.2 thorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 1.2 thorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 1.2 thorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 1.2 thorpej * POSSIBILITY OF SUCH DAMAGE.
31 1.2 thorpej */
32 1.2 thorpej
33 1.51 perry /*
34 1.2 thorpej * Copyright (c) 1996 Gardner Buchanan <gbuchanan (at) shl.com>
35 1.2 thorpej * All rights reserved.
36 1.51 perry *
37 1.2 thorpej * Redistribution and use in source and binary forms, with or without
38 1.2 thorpej * modification, are permitted provided that the following conditions
39 1.2 thorpej * are met:
40 1.2 thorpej * 1. Redistributions of source code must retain the above copyright
41 1.2 thorpej * notice, this list of conditions and the following disclaimer.
42 1.2 thorpej * 2. Redistributions in binary form must reproduce the above copyright
43 1.2 thorpej * notice, this list of conditions and the following disclaimer in the
44 1.2 thorpej * documentation and/or other materials provided with the distribution.
45 1.2 thorpej * 3. All advertising materials mentioning features or use of this software
46 1.2 thorpej * must display the following acknowledgement:
47 1.2 thorpej * This product includes software developed by Gardner Buchanan.
48 1.2 thorpej * 4. The name of Gardner Buchanan may not be used to endorse or promote
49 1.2 thorpej * products derived from this software without specific prior written
50 1.2 thorpej * permission.
51 1.51 perry *
52 1.2 thorpej * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
53 1.2 thorpej * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
54 1.2 thorpej * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
55 1.2 thorpej * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
56 1.2 thorpej * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
57 1.2 thorpej * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 1.2 thorpej * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 1.2 thorpej * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 1.2 thorpej * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
61 1.2 thorpej * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 1.51 perry *
63 1.2 thorpej * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp
64 1.51 perry */
65 1.2 thorpej
66 1.2 thorpej /*
67 1.2 thorpej * Core driver for the SMC 91Cxx family of Ethernet chips.
68 1.2 thorpej *
69 1.2 thorpej * Memory allocation interrupt logic is drived from an SMC 91C90 driver
70 1.2 thorpej * written for NetBSD/amiga by Michael Hitch.
71 1.2 thorpej */
72 1.37 lukem
73 1.37 lukem #include <sys/cdefs.h>
74 1.68 nakayama __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.68 2008/04/29 17:48:43 nakayama Exp $");
75 1.2 thorpej
76 1.7 jonathan #include "opt_inet.h"
77 1.2 thorpej #include "bpfilter.h"
78 1.5 explorer #include "rnd.h"
79 1.2 thorpej
80 1.51 perry #include <sys/param.h>
81 1.2 thorpej #include <sys/systm.h>
82 1.2 thorpej #include <sys/mbuf.h>
83 1.2 thorpej #include <sys/syslog.h>
84 1.2 thorpej #include <sys/socket.h>
85 1.2 thorpej #include <sys/device.h>
86 1.26 briggs #include <sys/kernel.h>
87 1.2 thorpej #include <sys/malloc.h>
88 1.51 perry #include <sys/ioctl.h>
89 1.2 thorpej #include <sys/errno.h>
90 1.5 explorer #if NRND > 0
91 1.5 explorer #include <sys/rnd.h>
92 1.5 explorer #endif
93 1.2 thorpej
94 1.63 ad #include <sys/bus.h>
95 1.63 ad #include <sys/intr.h>
96 1.2 thorpej
97 1.2 thorpej #include <net/if.h>
98 1.2 thorpej #include <net/if_dl.h>
99 1.2 thorpej #include <net/if_ether.h>
100 1.51 perry #include <net/if_media.h>
101 1.2 thorpej
102 1.2 thorpej #ifdef INET
103 1.51 perry #include <netinet/in.h>
104 1.2 thorpej #include <netinet/if_inarp.h>
105 1.2 thorpej #include <netinet/in_systm.h>
106 1.2 thorpej #include <netinet/in_var.h>
107 1.2 thorpej #include <netinet/ip.h>
108 1.2 thorpej #endif
109 1.2 thorpej
110 1.2 thorpej
111 1.2 thorpej
112 1.2 thorpej #if NBPFILTER > 0
113 1.2 thorpej #include <net/bpf.h>
114 1.2 thorpej #include <net/bpfdesc.h>
115 1.2 thorpej #endif
116 1.2 thorpej
117 1.26 briggs #include <dev/mii/mii.h>
118 1.26 briggs #include <dev/mii/miivar.h>
119 1.26 briggs #include <dev/mii/mii_bitbang.h>
120 1.26 briggs
121 1.2 thorpej #include <dev/ic/smc91cxxreg.h>
122 1.2 thorpej #include <dev/ic/smc91cxxvar.h>
123 1.40 thorpej
124 1.40 thorpej #ifndef __BUS_SPACE_HAS_STREAM_METHODS
125 1.40 thorpej #define bus_space_write_multi_stream_2 bus_space_write_multi_2
126 1.42 bsh #define bus_space_write_multi_stream_4 bus_space_write_multi_4
127 1.40 thorpej #define bus_space_read_multi_stream_2 bus_space_read_multi_2
128 1.42 bsh #define bus_space_read_multi_stream_4 bus_space_read_multi_4
129 1.42 bsh
130 1.42 bsh #define bus_space_write_stream_4 bus_space_write_4
131 1.42 bsh #define bus_space_read_stream_4 bus_space_read_4
132 1.40 thorpej #endif /* __BUS_SPACE_HAS_STREAM_METHODS */
133 1.2 thorpej
134 1.2 thorpej /* XXX Hardware padding doesn't work yet(?) */
135 1.2 thorpej #define SMC91CXX_SW_PAD
136 1.67 matt #define SMC91CXX_NO_BYTE_WRITE
137 1.2 thorpej
138 1.2 thorpej const char *smc91cxx_idstrs[] = {
139 1.2 thorpej NULL, /* 0 */
140 1.2 thorpej NULL, /* 1 */
141 1.2 thorpej NULL, /* 2 */
142 1.2 thorpej "SMC91C90/91C92", /* 3 */
143 1.39 chs "SMC91C94/91C96", /* 4 */
144 1.2 thorpej "SMC91C95", /* 5 */
145 1.2 thorpej NULL, /* 6 */
146 1.2 thorpej "SMC91C100", /* 7 */
147 1.26 briggs "SMC91C100FD", /* 8 */
148 1.45 scw "SMC91C111", /* 9 */
149 1.2 thorpej NULL, /* 10 */
150 1.2 thorpej NULL, /* 11 */
151 1.2 thorpej NULL, /* 12 */
152 1.2 thorpej NULL, /* 13 */
153 1.2 thorpej NULL, /* 14 */
154 1.2 thorpej NULL, /* 15 */
155 1.2 thorpej };
156 1.2 thorpej
157 1.2 thorpej /* Supported media types. */
158 1.2 thorpej const int smc91cxx_media[] = {
159 1.2 thorpej IFM_ETHER|IFM_10_T,
160 1.2 thorpej IFM_ETHER|IFM_10_5,
161 1.2 thorpej };
162 1.2 thorpej #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0]))
163 1.2 thorpej
164 1.26 briggs /*
165 1.26 briggs * MII bit-bang glue.
166 1.26 briggs */
167 1.50 perry u_int32_t smc91cxx_mii_bitbang_read(struct device *);
168 1.50 perry void smc91cxx_mii_bitbang_write(struct device *, u_int32_t);
169 1.26 briggs
170 1.26 briggs const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = {
171 1.26 briggs smc91cxx_mii_bitbang_read,
172 1.26 briggs smc91cxx_mii_bitbang_write,
173 1.26 briggs {
174 1.26 briggs MR_MDO, /* MII_BIT_MDO */
175 1.26 briggs MR_MDI, /* MII_BIT_MDI */
176 1.26 briggs MR_MCLK, /* MII_BIT_MDC */
177 1.26 briggs MR_MDOE, /* MII_BIT_DIR_HOST_PHY */
178 1.26 briggs 0, /* MII_BIT_DIR_PHY_HOST */
179 1.26 briggs }
180 1.26 briggs };
181 1.26 briggs
182 1.26 briggs /* MII callbacks */
183 1.50 perry int smc91cxx_mii_readreg(struct device *, int, int);
184 1.50 perry void smc91cxx_mii_writereg(struct device *, int, int, int);
185 1.50 perry void smc91cxx_statchg(struct device *);
186 1.50 perry void smc91cxx_tick(void *);
187 1.50 perry
188 1.50 perry int smc91cxx_mediachange(struct ifnet *);
189 1.50 perry void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *);
190 1.50 perry
191 1.50 perry int smc91cxx_set_media(struct smc91cxx_softc *, int);
192 1.50 perry
193 1.50 perry void smc91cxx_init(struct smc91cxx_softc *);
194 1.50 perry void smc91cxx_read(struct smc91cxx_softc *);
195 1.50 perry void smc91cxx_reset(struct smc91cxx_softc *);
196 1.50 perry void smc91cxx_start(struct ifnet *);
197 1.67 matt uint8_t smc91cxx_copy_tx_frame(struct smc91cxx_softc *, struct mbuf *);
198 1.50 perry void smc91cxx_resume(struct smc91cxx_softc *);
199 1.50 perry void smc91cxx_stop(struct smc91cxx_softc *);
200 1.50 perry void smc91cxx_watchdog(struct ifnet *);
201 1.59 christos int smc91cxx_ioctl(struct ifnet *, u_long, void *);
202 1.2 thorpej
203 1.61 dyoung static inline int ether_cmp(const void *, const void *);
204 1.54 perry static inline int
205 1.2 thorpej ether_cmp(va, vb)
206 1.61 dyoung const void *va, *vb;
207 1.2 thorpej {
208 1.61 dyoung const u_int8_t *a = va;
209 1.61 dyoung const u_int8_t *b = vb;
210 1.2 thorpej
211 1.2 thorpej return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) ||
212 1.2 thorpej (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0]));
213 1.2 thorpej }
214 1.2 thorpej
215 1.67 matt static inline void
216 1.67 matt smc91cxx_intr_mask_write(bus_space_tag_t bst, bus_space_handle_t bsh,
217 1.67 matt uint8_t mask)
218 1.67 matt {
219 1.67 matt KDASSERT((mask & IM_ERCV_INT) == 0);
220 1.67 matt #ifdef SMC91CXX_NO_BYTE_WRITE
221 1.67 matt #if BYTE_ORDER == LITTLE_ENDIAN
222 1.67 matt bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask << 8);
223 1.67 matt #else
224 1.68 nakayama bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask);
225 1.67 matt #endif
226 1.67 matt #else
227 1.67 matt bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask);
228 1.67 matt #endif
229 1.67 matt KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT));
230 1.67 matt }
231 1.67 matt
232 1.67 matt static inline void
233 1.67 matt smc91cxx_intr_ack_write(bus_space_tag_t bst, bus_space_handle_t bsh,
234 1.67 matt uint8_t mask)
235 1.67 matt {
236 1.67 matt #ifdef SMC91CXX_NO_BYTE_WRITE
237 1.67 matt #if BYTE_ORDER == LITTLE_ENDIAN
238 1.67 matt bus_space_write_2(bst, bsh, INTR_ACK_REG_B,
239 1.67 matt mask | (bus_space_read_2(bst, bsh, INTR_ACK_REG_B) & 0xff00));
240 1.67 matt #else
241 1.67 matt bus_space_write_2(bst, bsh, INTR_ACK_REG_B,
242 1.67 matt (mask << 8) | (bus_space_read_2(bst, bsh, INTR_ACK_REG_B) & 0xff));
243 1.67 matt #endif
244 1.67 matt #else
245 1.67 matt bus_space_write_1(bst, bsh, INTR_ACK_REG_B, mask);
246 1.67 matt #endif
247 1.67 matt KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT));
248 1.67 matt }
249 1.67 matt
250 1.2 thorpej void
251 1.2 thorpej smc91cxx_attach(sc, myea)
252 1.2 thorpej struct smc91cxx_softc *sc;
253 1.2 thorpej u_int8_t *myea;
254 1.2 thorpej {
255 1.2 thorpej struct ifnet *ifp = &sc->sc_ec.ec_if;
256 1.2 thorpej bus_space_tag_t bst = sc->sc_bst;
257 1.2 thorpej bus_space_handle_t bsh = sc->sc_bsh;
258 1.26 briggs struct ifmedia *ifm = &sc->sc_mii.mii_media;
259 1.2 thorpej const char *idstr;
260 1.26 briggs u_int32_t miicapabilities;
261 1.2 thorpej u_int16_t tmp;
262 1.2 thorpej u_int8_t enaddr[ETHER_ADDR_LEN];
263 1.45 scw int i, aui, mult, scale, memsize;
264 1.26 briggs char pbuf[9];
265 1.2 thorpej
266 1.47 mycroft tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W);
267 1.47 mycroft /* check magic number */
268 1.47 mycroft if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
269 1.65 cegger aprint_error_dev(&sc->sc_dev, "failed to detect chip, bsr=%04x\n", tmp);
270 1.47 mycroft return;
271 1.47 mycroft }
272 1.47 mycroft
273 1.2 thorpej /* Make sure the chip is stopped. */
274 1.2 thorpej smc91cxx_stop(sc);
275 1.2 thorpej
276 1.2 thorpej SMC_SELECT_BANK(sc, 3);
277 1.2 thorpej tmp = bus_space_read_2(bst, bsh, REVISION_REG_W);
278 1.26 briggs sc->sc_chipid = RR_ID(tmp);
279 1.47 mycroft idstr = smc91cxx_idstrs[sc->sc_chipid];
280 1.47 mycroft
281 1.65 cegger aprint_normal_dev(&sc->sc_dev, "");
282 1.2 thorpej if (idstr != NULL)
283 1.47 mycroft aprint_normal("%s, ", idstr);
284 1.2 thorpej else
285 1.47 mycroft aprint_normal("unknown chip id %d, ", sc->sc_chipid);
286 1.47 mycroft aprint_normal("revision %d, ", RR_REV(tmp));
287 1.26 briggs
288 1.26 briggs SMC_SELECT_BANK(sc, 0);
289 1.45 scw switch (sc->sc_chipid) {
290 1.45 scw default:
291 1.45 scw mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W));
292 1.45 scw scale = MIR_SCALE_91C9x;
293 1.45 scw break;
294 1.45 scw
295 1.45 scw case CHIP_91C111:
296 1.45 scw mult = MIR_MULT_91C111;
297 1.45 scw scale = MIR_SCALE_91C111;
298 1.45 scw }
299 1.26 briggs memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK;
300 1.26 briggs if (memsize == 255) memsize++;
301 1.45 scw memsize *= scale * mult;
302 1.26 briggs
303 1.26 briggs format_bytes(pbuf, sizeof(pbuf), memsize);
304 1.47 mycroft aprint_normal("buffer size: %s\n", pbuf);
305 1.2 thorpej
306 1.2 thorpej /* Read the station address from the chip. */
307 1.2 thorpej SMC_SELECT_BANK(sc, 1);
308 1.2 thorpej if (myea == NULL) {
309 1.2 thorpej myea = enaddr;
310 1.2 thorpej for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
311 1.2 thorpej tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i);
312 1.2 thorpej myea[i + 1] = (tmp >> 8) & 0xff;
313 1.2 thorpej myea[i] = tmp & 0xff;
314 1.2 thorpej }
315 1.2 thorpej }
316 1.65 cegger aprint_normal_dev(&sc->sc_dev, "MAC address %s, ",
317 1.2 thorpej ether_sprintf(myea));
318 1.2 thorpej
319 1.2 thorpej /* Initialize the ifnet structure. */
320 1.65 cegger strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ);
321 1.2 thorpej ifp->if_softc = sc;
322 1.2 thorpej ifp->if_start = smc91cxx_start;
323 1.2 thorpej ifp->if_ioctl = smc91cxx_ioctl;
324 1.2 thorpej ifp->if_watchdog = smc91cxx_watchdog;
325 1.2 thorpej ifp->if_flags =
326 1.2 thorpej IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
327 1.32 thorpej IFQ_SET_READY(&ifp->if_snd);
328 1.2 thorpej
329 1.2 thorpej /* Attach the interface. */
330 1.2 thorpej if_attach(ifp);
331 1.2 thorpej ether_ifattach(ifp, myea);
332 1.2 thorpej
333 1.26 briggs /*
334 1.26 briggs * Initialize our media structures and MII info. We will
335 1.26 briggs * probe the MII if we are on the SMC91Cxx
336 1.26 briggs */
337 1.26 briggs sc->sc_mii.mii_ifp = ifp;
338 1.26 briggs sc->sc_mii.mii_readreg = smc91cxx_mii_readreg;
339 1.26 briggs sc->sc_mii.mii_writereg = smc91cxx_mii_writereg;
340 1.26 briggs sc->sc_mii.mii_statchg = smc91cxx_statchg;
341 1.44 fair ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, smc91cxx_mediastatus);
342 1.26 briggs
343 1.26 briggs SMC_SELECT_BANK(sc, 1);
344 1.26 briggs tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
345 1.26 briggs
346 1.35 thorpej miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG;
347 1.26 briggs switch (sc->sc_chipid) {
348 1.26 briggs case CHIP_91100:
349 1.26 briggs /*
350 1.26 briggs * The 91100 does not have full-duplex capabilities,
351 1.26 briggs * even if the PHY does.
352 1.26 briggs */
353 1.26 briggs miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX);
354 1.26 briggs case CHIP_91100FD:
355 1.45 scw case CHIP_91C111:
356 1.26 briggs if (tmp & CR_MII_SELECT) {
357 1.47 mycroft aprint_normal("default media MII");
358 1.45 scw if (sc->sc_chipid == CHIP_91C111) {
359 1.47 mycroft aprint_normal(" (%s PHY)\n", (tmp & CR_AUI_SELECT) ?
360 1.45 scw "external" : "internal");
361 1.45 scw sc->sc_internal_phy = !(tmp & CR_AUI_SELECT);
362 1.45 scw } else
363 1.47 mycroft aprint_normal("\n");
364 1.26 briggs mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities,
365 1.26 briggs MII_PHY_ANY, MII_OFFSET_ANY, 0);
366 1.26 briggs if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
367 1.26 briggs ifmedia_add(&sc->sc_mii.mii_media,
368 1.26 briggs IFM_ETHER|IFM_NONE, 0, NULL);
369 1.26 briggs ifmedia_set(&sc->sc_mii.mii_media,
370 1.26 briggs IFM_ETHER|IFM_NONE);
371 1.26 briggs } else {
372 1.26 briggs ifmedia_set(&sc->sc_mii.mii_media,
373 1.26 briggs IFM_ETHER|IFM_AUTO);
374 1.26 briggs }
375 1.26 briggs sc->sc_flags |= SMC_FLAGS_HAS_MII;
376 1.26 briggs break;
377 1.45 scw } else
378 1.45 scw if (sc->sc_chipid == CHIP_91C111) {
379 1.45 scw /*
380 1.45 scw * XXX: Should bring it out of low-power mode
381 1.45 scw */
382 1.47 mycroft aprint_normal("EPH interface in low power mode\n");
383 1.45 scw sc->sc_internal_phy = 0;
384 1.45 scw return;
385 1.26 briggs }
386 1.26 briggs /*FALLTHROUGH*/
387 1.26 briggs default:
388 1.47 mycroft aprint_normal("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ?
389 1.26 briggs "AUI" : "UTP");
390 1.26 briggs for (i = 0; i < NSMC91CxxMEDIA; i++)
391 1.26 briggs ifmedia_add(ifm, smc91cxx_media[i], 0, NULL);
392 1.26 briggs ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T));
393 1.26 briggs break;
394 1.26 briggs }
395 1.2 thorpej
396 1.5 explorer #if NRND > 0
397 1.65 cegger rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev),
398 1.15 explorer RND_TYPE_NET, 0);
399 1.5 explorer #endif
400 1.25 jhawk
401 1.60 kiyohara callout_init(&sc->sc_mii_callout, 0);
402 1.60 kiyohara
403 1.25 jhawk /* The attach is successful. */
404 1.25 jhawk sc->sc_flags |= SMC_FLAGS_ATTACHED;
405 1.2 thorpej }
406 1.2 thorpej
407 1.2 thorpej /*
408 1.2 thorpej * Change media according to request.
409 1.2 thorpej */
410 1.2 thorpej int
411 1.2 thorpej smc91cxx_mediachange(ifp)
412 1.2 thorpej struct ifnet *ifp;
413 1.2 thorpej {
414 1.2 thorpej struct smc91cxx_softc *sc = ifp->if_softc;
415 1.2 thorpej
416 1.26 briggs return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media));
417 1.2 thorpej }
418 1.2 thorpej
419 1.2 thorpej int
420 1.2 thorpej smc91cxx_set_media(sc, media)
421 1.2 thorpej struct smc91cxx_softc *sc;
422 1.2 thorpej int media;
423 1.2 thorpej {
424 1.2 thorpej bus_space_tag_t bst = sc->sc_bst;
425 1.2 thorpej bus_space_handle_t bsh = sc->sc_bsh;
426 1.2 thorpej u_int16_t tmp;
427 1.64 dyoung int rc;
428 1.2 thorpej
429 1.4 thorpej /*
430 1.4 thorpej * If the interface is not currently powered on, just return.
431 1.4 thorpej * When it is enabled later, smc91cxx_init() will properly set
432 1.4 thorpej * up the media for us.
433 1.4 thorpej */
434 1.25 jhawk if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0)
435 1.4 thorpej return (0);
436 1.4 thorpej
437 1.2 thorpej if (IFM_TYPE(media) != IFM_ETHER)
438 1.2 thorpej return (EINVAL);
439 1.2 thorpej
440 1.64 dyoung if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0 ||
441 1.64 dyoung (rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
442 1.64 dyoung rc = 0;
443 1.26 briggs
444 1.2 thorpej switch (IFM_SUBTYPE(media)) {
445 1.2 thorpej case IFM_10_T:
446 1.2 thorpej case IFM_10_5:
447 1.2 thorpej SMC_SELECT_BANK(sc, 1);
448 1.2 thorpej tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
449 1.2 thorpej if (IFM_SUBTYPE(media) == IFM_10_5)
450 1.2 thorpej tmp |= CR_AUI_SELECT;
451 1.2 thorpej else
452 1.2 thorpej tmp &= ~CR_AUI_SELECT;
453 1.2 thorpej bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp);
454 1.2 thorpej delay(20000); /* XXX is this needed? */
455 1.2 thorpej break;
456 1.2 thorpej
457 1.2 thorpej default:
458 1.2 thorpej return (EINVAL);
459 1.2 thorpej }
460 1.2 thorpej
461 1.64 dyoung return rc;
462 1.2 thorpej }
463 1.2 thorpej
464 1.2 thorpej /*
465 1.2 thorpej * Notify the world which media we're using.
466 1.2 thorpej */
467 1.2 thorpej void
468 1.2 thorpej smc91cxx_mediastatus(ifp, ifmr)
469 1.2 thorpej struct ifnet *ifp;
470 1.2 thorpej struct ifmediareq *ifmr;
471 1.2 thorpej {
472 1.2 thorpej struct smc91cxx_softc *sc = ifp->if_softc;
473 1.2 thorpej bus_space_tag_t bst = sc->sc_bst;
474 1.2 thorpej bus_space_handle_t bsh = sc->sc_bsh;
475 1.2 thorpej u_int16_t tmp;
476 1.2 thorpej
477 1.25 jhawk if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) {
478 1.4 thorpej ifmr->ifm_active = IFM_ETHER | IFM_NONE;
479 1.4 thorpej ifmr->ifm_status = 0;
480 1.4 thorpej return;
481 1.4 thorpej }
482 1.4 thorpej
483 1.26 briggs /*
484 1.26 briggs * If we have MII, go ask the PHY what's going on.
485 1.26 briggs */
486 1.26 briggs if (sc->sc_flags & SMC_FLAGS_HAS_MII) {
487 1.26 briggs mii_pollstat(&sc->sc_mii);
488 1.26 briggs ifmr->ifm_active = sc->sc_mii.mii_media_active;
489 1.26 briggs ifmr->ifm_status = sc->sc_mii.mii_media_status;
490 1.26 briggs return;
491 1.26 briggs }
492 1.26 briggs
493 1.2 thorpej SMC_SELECT_BANK(sc, 1);
494 1.2 thorpej tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
495 1.2 thorpej ifmr->ifm_active =
496 1.2 thorpej IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T);
497 1.2 thorpej }
498 1.2 thorpej
499 1.2 thorpej /*
500 1.2 thorpej * Reset and initialize the chip.
501 1.2 thorpej */
502 1.2 thorpej void
503 1.2 thorpej smc91cxx_init(sc)
504 1.2 thorpej struct smc91cxx_softc *sc;
505 1.2 thorpej {
506 1.2 thorpej struct ifnet *ifp = &sc->sc_ec.ec_if;
507 1.2 thorpej bus_space_tag_t bst = sc->sc_bst;
508 1.2 thorpej bus_space_handle_t bsh = sc->sc_bsh;
509 1.2 thorpej u_int16_t tmp;
510 1.61 dyoung const u_int8_t *enaddr;
511 1.2 thorpej int s, i;
512 1.2 thorpej
513 1.11 mycroft s = splnet();
514 1.2 thorpej
515 1.2 thorpej /*
516 1.46 wiz * This resets the registers mostly to defaults, but doesn't
517 1.2 thorpej * affect the EEPROM. After the reset cycle, we pause briefly
518 1.2 thorpej * for the chip to recover.
519 1.2 thorpej *
520 1.2 thorpej * XXX how long are we really supposed to delay? --thorpej
521 1.2 thorpej */
522 1.2 thorpej SMC_SELECT_BANK(sc, 0);
523 1.2 thorpej bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET);
524 1.2 thorpej delay(100);
525 1.2 thorpej bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0);
526 1.2 thorpej delay(200);
527 1.2 thorpej
528 1.2 thorpej bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0);
529 1.2 thorpej
530 1.2 thorpej /* Set the Ethernet address. */
531 1.2 thorpej SMC_SELECT_BANK(sc, 1);
532 1.61 dyoung enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl);
533 1.2 thorpej for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
534 1.2 thorpej tmp = enaddr[i + 1] << 8 | enaddr[i];
535 1.2 thorpej bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp);
536 1.2 thorpej }
537 1.2 thorpej
538 1.2 thorpej /*
539 1.2 thorpej * Set the control register to automatically release successfully
540 1.2 thorpej * transmitted packets (making the best use of our limited memory)
541 1.2 thorpej * and enable the EPH interrupt on certain TX errors.
542 1.2 thorpej */
543 1.2 thorpej bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE |
544 1.2 thorpej CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE));
545 1.2 thorpej
546 1.2 thorpej /*
547 1.2 thorpej * Reset the MMU and wait for it to be un-busy.
548 1.2 thorpej */
549 1.2 thorpej SMC_SELECT_BANK(sc, 2);
550 1.2 thorpej bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET);
551 1.67 matt sc->sc_txpacketno = ARR_FAILED;
552 1.48 mycroft for (;;) {
553 1.48 mycroft tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W);
554 1.48 mycroft if (tmp == 0xffff) /* card went away! */
555 1.48 mycroft return;
556 1.48 mycroft if ((tmp & MMUCR_BUSY) == 0)
557 1.48 mycroft break;
558 1.48 mycroft }
559 1.2 thorpej
560 1.2 thorpej /*
561 1.2 thorpej * Disable all interrupts.
562 1.2 thorpej */
563 1.67 matt smc91cxx_intr_mask_write(bst, bsh, 0);
564 1.2 thorpej
565 1.2 thorpej /*
566 1.45 scw * On the 91c111, enable auto-negotiation, and set the LED
567 1.45 scw * status pins to something sane.
568 1.45 scw * XXX: Should be some way for MD code to decide the latter.
569 1.45 scw */
570 1.45 scw SMC_SELECT_BANK(sc, 0);
571 1.45 scw if (sc->sc_chipid == CHIP_91C111) {
572 1.45 scw bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W,
573 1.45 scw RPC_ANEG |
574 1.45 scw (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) |
575 1.45 scw (RPC_LS_TXRX << RPC_LSB_SHIFT));
576 1.45 scw }
577 1.45 scw
578 1.45 scw /*
579 1.2 thorpej * Set current media.
580 1.2 thorpej */
581 1.26 briggs smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media);
582 1.2 thorpej
583 1.2 thorpej /*
584 1.2 thorpej * Set the receive filter. We want receive enable and auto
585 1.2 thorpej * strip of CRC from received packet. If we are in promisc. mode,
586 1.2 thorpej * then set that bit as well.
587 1.2 thorpej *
588 1.2 thorpej * XXX Initialize multicast filter. For now, we just accept
589 1.2 thorpej * XXX all multicast.
590 1.2 thorpej */
591 1.2 thorpej SMC_SELECT_BANK(sc, 0);
592 1.2 thorpej
593 1.2 thorpej tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL;
594 1.2 thorpej if (ifp->if_flags & IFF_PROMISC)
595 1.2 thorpej tmp |= RCR_PROMISC;
596 1.2 thorpej
597 1.2 thorpej bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp);
598 1.2 thorpej
599 1.2 thorpej /*
600 1.2 thorpej * Set transmitter control to "enabled".
601 1.2 thorpej */
602 1.2 thorpej tmp = TCR_ENABLE;
603 1.2 thorpej
604 1.2 thorpej #ifndef SMC91CXX_SW_PAD
605 1.2 thorpej /*
606 1.2 thorpej * Enable hardware padding of transmitted packets.
607 1.2 thorpej * XXX doesn't work?
608 1.2 thorpej */
609 1.2 thorpej tmp |= TCR_PAD_ENABLE;
610 1.2 thorpej #endif
611 1.2 thorpej
612 1.2 thorpej bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp);
613 1.2 thorpej
614 1.2 thorpej /*
615 1.2 thorpej * Now, enable interrupts.
616 1.2 thorpej */
617 1.2 thorpej SMC_SELECT_BANK(sc, 2);
618 1.2 thorpej
619 1.67 matt sc->sc_intmask = IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT;
620 1.45 scw if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) {
621 1.67 matt sc->sc_intmask |= IM_MD_INT;
622 1.45 scw }
623 1.67 matt smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask);
624 1.2 thorpej
625 1.2 thorpej /* Interface is now running, with no output active. */
626 1.2 thorpej ifp->if_flags |= IFF_RUNNING;
627 1.2 thorpej ifp->if_flags &= ~IFF_OACTIVE;
628 1.2 thorpej
629 1.26 briggs if (sc->sc_flags & SMC_FLAGS_HAS_MII) {
630 1.26 briggs /* Start the one second clock. */
631 1.26 briggs callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc);
632 1.26 briggs }
633 1.26 briggs
634 1.2 thorpej /*
635 1.2 thorpej * Attempt to start any pending transmission.
636 1.2 thorpej */
637 1.2 thorpej smc91cxx_start(ifp);
638 1.2 thorpej
639 1.2 thorpej splx(s);
640 1.2 thorpej }
641 1.2 thorpej
642 1.2 thorpej /*
643 1.2 thorpej * Start output on an interface.
644 1.11 mycroft * Must be called at splnet or interrupt level.
645 1.2 thorpej */
646 1.2 thorpej void
647 1.2 thorpej smc91cxx_start(ifp)
648 1.2 thorpej struct ifnet *ifp;
649 1.2 thorpej {
650 1.2 thorpej struct smc91cxx_softc *sc = ifp->if_softc;
651 1.2 thorpej bus_space_tag_t bst = sc->sc_bst;
652 1.2 thorpej bus_space_handle_t bsh = sc->sc_bsh;
653 1.2 thorpej u_int len;
654 1.43 scw struct mbuf *m;
655 1.2 thorpej u_int16_t length, npages;
656 1.67 matt u_int16_t oddbyte;
657 1.2 thorpej u_int8_t packetno;
658 1.2 thorpej int timo, pad;
659 1.2 thorpej
660 1.2 thorpej if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
661 1.2 thorpej return;
662 1.2 thorpej
663 1.2 thorpej again:
664 1.2 thorpej /*
665 1.2 thorpej * Peek at the next packet.
666 1.2 thorpej */
667 1.32 thorpej IFQ_POLL(&ifp->if_snd, m);
668 1.32 thorpej if (m == NULL)
669 1.2 thorpej return;
670 1.2 thorpej
671 1.2 thorpej /*
672 1.2 thorpej * Compute the frame length and set pad to give an overall even
673 1.2 thorpej * number of bytes. Below, we assume that the packet length
674 1.2 thorpej * is even.
675 1.2 thorpej */
676 1.43 scw for (len = 0; m != NULL; m = m->m_next)
677 1.2 thorpej len += m->m_len;
678 1.2 thorpej pad = (len & 1);
679 1.2 thorpej
680 1.2 thorpej /*
681 1.2 thorpej * We drop packets that are too large. Perhaps we should
682 1.2 thorpej * truncate them instead?
683 1.2 thorpej */
684 1.2 thorpej if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) {
685 1.65 cegger printf("%s: large packet discarded\n", device_xname(&sc->sc_dev));
686 1.2 thorpej ifp->if_oerrors++;
687 1.32 thorpej IFQ_DEQUEUE(&ifp->if_snd, m);
688 1.2 thorpej m_freem(m);
689 1.2 thorpej goto readcheck;
690 1.2 thorpej }
691 1.2 thorpej
692 1.2 thorpej #ifdef SMC91CXX_SW_PAD
693 1.2 thorpej /*
694 1.2 thorpej * Not using hardware padding; pad to ETHER_MIN_LEN.
695 1.2 thorpej */
696 1.2 thorpej if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN))
697 1.2 thorpej pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
698 1.2 thorpej #endif
699 1.2 thorpej
700 1.2 thorpej length = pad + len;
701 1.2 thorpej
702 1.2 thorpej /*
703 1.2 thorpej * The MMU has a 256 byte page size. The MMU expects us to
704 1.2 thorpej * ask for "npages - 1". We include space for the status word,
705 1.2 thorpej * byte count, and control bytes in the allocation request.
706 1.2 thorpej */
707 1.67 matt npages = ((length & ~1) + 6) >> 8;
708 1.2 thorpej
709 1.2 thorpej /*
710 1.2 thorpej * Now allocate the memory.
711 1.2 thorpej */
712 1.2 thorpej SMC_SELECT_BANK(sc, 2);
713 1.2 thorpej bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages);
714 1.2 thorpej
715 1.2 thorpej timo = MEMORY_WAIT_TIME;
716 1.67 matt if (__predict_false((sc->sc_txpacketno & ARR_FAILED) == 0)) {
717 1.67 matt packetno = sc->sc_txpacketno;
718 1.67 matt sc->sc_txpacketno = ARR_FAILED;
719 1.67 matt } else {
720 1.67 matt do {
721 1.67 matt if (bus_space_read_1(bst, bsh,
722 1.67 matt INTR_STAT_REG_B) & IM_ALLOC_INT)
723 1.67 matt break;
724 1.67 matt delay(1);
725 1.67 matt } while (--timo);
726 1.67 matt }
727 1.2 thorpej
728 1.2 thorpej packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B);
729 1.2 thorpej
730 1.2 thorpej if (packetno & ARR_FAILED || timo == 0) {
731 1.2 thorpej /*
732 1.2 thorpej * No transmit memory is available. Record the number
733 1.2 thorpej * of requestd pages and enable the allocation completion
734 1.2 thorpej * interrupt. Set up the watchdog timer in case we miss
735 1.2 thorpej * the interrupt. Mark the interface as active so that
736 1.2 thorpej * no one else attempts to transmit while we're allocating
737 1.2 thorpej * memory.
738 1.2 thorpej */
739 1.67 matt sc->sc_intmask |= IM_ALLOC_INT;
740 1.67 matt smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask);
741 1.2 thorpej ifp->if_timer = 5;
742 1.2 thorpej ifp->if_flags |= IFF_OACTIVE;
743 1.2 thorpej
744 1.2 thorpej return;
745 1.2 thorpej }
746 1.2 thorpej
747 1.2 thorpej /*
748 1.2 thorpej * We have a packet number - set the data window.
749 1.2 thorpej */
750 1.2 thorpej bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno);
751 1.2 thorpej
752 1.2 thorpej /*
753 1.2 thorpej * Point to the beginning of the packet.
754 1.2 thorpej */
755 1.2 thorpej bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */);
756 1.2 thorpej
757 1.2 thorpej /*
758 1.2 thorpej * Send the packet length (+6 for stats, length, and control bytes)
759 1.2 thorpej * and the status word (set to zeros).
760 1.2 thorpej */
761 1.2 thorpej bus_space_write_2(bst, bsh, DATA_REG_W, 0);
762 1.52 pooka bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff);
763 1.2 thorpej
764 1.2 thorpej /*
765 1.2 thorpej * Get the packet from the kernel. This will include the Ethernet
766 1.2 thorpej * frame header, MAC address, etc.
767 1.2 thorpej */
768 1.32 thorpej IFQ_DEQUEUE(&ifp->if_snd, m);
769 1.2 thorpej
770 1.2 thorpej /*
771 1.2 thorpej * Push the packet out to the card.
772 1.2 thorpej */
773 1.67 matt oddbyte = smc91cxx_copy_tx_frame(sc, m);
774 1.2 thorpej
775 1.2 thorpej #ifdef SMC91CXX_SW_PAD
776 1.67 matt #if BYTE_ORDER == LITTLE_ENDIAN
777 1.67 matt if (pad > 1 && (pad & 1)) {
778 1.67 matt bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte << 0);
779 1.67 matt oddbyte = 0;
780 1.67 matt }
781 1.67 matt #else
782 1.68 nakayama if (pad > 1 && (pad & 1)) {
783 1.67 matt bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte << 8);
784 1.67 matt oddbyte = 0;
785 1.67 matt }
786 1.67 matt #endif
787 1.67 matt
788 1.2 thorpej /*
789 1.2 thorpej * Push out padding.
790 1.2 thorpej */
791 1.2 thorpej while (pad > 1) {
792 1.2 thorpej bus_space_write_2(bst, bsh, DATA_REG_W, 0);
793 1.2 thorpej pad -= 2;
794 1.2 thorpej }
795 1.2 thorpej #endif
796 1.2 thorpej
797 1.2 thorpej /*
798 1.2 thorpej * Push out control byte and unused packet byte. The control byte
799 1.2 thorpej * is 0, meaning the packet is even lengthed and no special
800 1.2 thorpej * CRC handling is necessary.
801 1.2 thorpej */
802 1.67 matt #if BYTE_ORDER == LITTLE_ENDIAN
803 1.67 matt bus_space_write_2(bst, bsh, DATA_REG_W,
804 1.67 matt oddbyte | (pad ? (CTLB_ODD << 8) : 0));
805 1.67 matt #else
806 1.67 matt bus_space_write_2(bst, bsh, DATA_REG_W,
807 1.67 matt (oddbyte << 8) | (pad ? CTLB_ODD : 0));
808 1.67 matt #endif
809 1.2 thorpej
810 1.2 thorpej /*
811 1.2 thorpej * Enable transmit interrupts and let the chip go. Set a watchdog
812 1.2 thorpej * in case we miss the interrupt.
813 1.2 thorpej */
814 1.67 matt sc->sc_intmask |= IM_TX_INT | IM_TX_EMPTY_INT;
815 1.67 matt smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask);
816 1.2 thorpej
817 1.2 thorpej bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE);
818 1.2 thorpej
819 1.2 thorpej ifp->if_timer = 5;
820 1.2 thorpej
821 1.2 thorpej #if NBPFILTER > 0
822 1.2 thorpej /* Hand off a copy to the bpf. */
823 1.2 thorpej if (ifp->if_bpf)
824 1.43 scw bpf_mtap(ifp->if_bpf, m);
825 1.2 thorpej #endif
826 1.2 thorpej
827 1.2 thorpej ifp->if_opackets++;
828 1.43 scw m_freem(m);
829 1.2 thorpej
830 1.2 thorpej readcheck:
831 1.2 thorpej /*
832 1.2 thorpej * Check for incoming pcakets. We don't want to overflow the small
833 1.2 thorpej * RX FIFO. If nothing has arrived, attempt to queue another
834 1.2 thorpej * transmit packet.
835 1.2 thorpej */
836 1.2 thorpej if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY)
837 1.2 thorpej goto again;
838 1.2 thorpej }
839 1.2 thorpej
840 1.2 thorpej /*
841 1.43 scw * Squirt a (possibly misaligned) mbuf to the device
842 1.43 scw */
843 1.67 matt uint8_t
844 1.43 scw smc91cxx_copy_tx_frame(sc, m0)
845 1.43 scw struct smc91cxx_softc *sc;
846 1.43 scw struct mbuf *m0;
847 1.43 scw {
848 1.43 scw bus_space_tag_t bst = sc->sc_bst;
849 1.43 scw bus_space_handle_t bsh = sc->sc_bsh;
850 1.43 scw struct mbuf *m;
851 1.43 scw int len, leftover;
852 1.43 scw u_int16_t dbuf;
853 1.43 scw u_int8_t *p;
854 1.43 scw #ifdef DIAGNOSTIC
855 1.43 scw u_int8_t *lim;
856 1.43 scw #endif
857 1.43 scw
858 1.43 scw /* start out with no leftover data */
859 1.43 scw leftover = 0;
860 1.43 scw dbuf = 0;
861 1.43 scw
862 1.43 scw /* Process the chain of mbufs */
863 1.43 scw for (m = m0; m != NULL; m = m->m_next) {
864 1.43 scw /*
865 1.43 scw * Process all of the data in a single mbuf.
866 1.43 scw */
867 1.43 scw p = mtod(m, u_int8_t *);
868 1.43 scw len = m->m_len;
869 1.43 scw #ifdef DIAGNOSTIC
870 1.43 scw lim = p + len;
871 1.43 scw #endif
872 1.43 scw
873 1.43 scw while (len > 0) {
874 1.43 scw if (leftover) {
875 1.43 scw /*
876 1.43 scw * Data left over (from mbuf or realignment).
877 1.43 scw * Buffer the next byte, and write it and
878 1.43 scw * the leftover data out.
879 1.43 scw */
880 1.43 scw dbuf |= *p++ << 8;
881 1.43 scw len--;
882 1.43 scw bus_space_write_2(bst, bsh, DATA_REG_W, dbuf);
883 1.43 scw leftover = 0;
884 1.43 scw } else if ((long) p & 1) {
885 1.43 scw /*
886 1.43 scw * Misaligned data. Buffer the next byte.
887 1.43 scw */
888 1.43 scw dbuf = *p++;
889 1.43 scw len--;
890 1.43 scw leftover = 1;
891 1.43 scw } else {
892 1.43 scw /*
893 1.43 scw * Aligned data. This is the case we like.
894 1.43 scw *
895 1.43 scw * Write-region out as much as we can, then
896 1.43 scw * buffer the remaining byte (if any).
897 1.43 scw */
898 1.43 scw leftover = len & 1;
899 1.43 scw len &= ~1;
900 1.43 scw bus_space_write_multi_stream_2(bst, bsh,
901 1.43 scw DATA_REG_W, (u_int16_t *)p, len >> 1);
902 1.43 scw p += len;
903 1.43 scw
904 1.43 scw if (leftover)
905 1.43 scw dbuf = *p++;
906 1.43 scw len = 0;
907 1.43 scw }
908 1.43 scw }
909 1.43 scw if (len < 0)
910 1.43 scw panic("smc91cxx_copy_tx_frame: negative len");
911 1.43 scw #ifdef DIAGNOSTIC
912 1.43 scw if (p != lim)
913 1.43 scw panic("smc91cxx_copy_tx_frame: p != lim");
914 1.43 scw #endif
915 1.43 scw }
916 1.67 matt return dbuf;
917 1.43 scw }
918 1.43 scw
919 1.43 scw /*
920 1.2 thorpej * Interrupt service routine.
921 1.2 thorpej */
922 1.2 thorpej int
923 1.2 thorpej smc91cxx_intr(arg)
924 1.2 thorpej void *arg;
925 1.2 thorpej {
926 1.2 thorpej struct smc91cxx_softc *sc = arg;
927 1.2 thorpej struct ifnet *ifp = &sc->sc_ec.ec_if;
928 1.2 thorpej bus_space_tag_t bst = sc->sc_bst;
929 1.2 thorpej bus_space_handle_t bsh = sc->sc_bsh;
930 1.2 thorpej u_int8_t mask, interrupts, status;
931 1.67 matt u_int16_t packetno, tx_status, card_stats, v;
932 1.2 thorpej
933 1.25 jhawk if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 ||
934 1.55 thorpej !device_is_active(&sc->sc_dev))
935 1.4 thorpej return (0);
936 1.4 thorpej
937 1.2 thorpej SMC_SELECT_BANK(sc, 2);
938 1.2 thorpej
939 1.2 thorpej /*
940 1.67 matt * Obtain the current interrupt status and mask.
941 1.2 thorpej */
942 1.67 matt v = bus_space_read_2(bst, bsh, INTR_STAT_REG_B);
943 1.2 thorpej
944 1.2 thorpej /*
945 1.2 thorpej * Get the set of interrupt which occurred and eliminate any
946 1.2 thorpej * which are not enabled.
947 1.2 thorpej */
948 1.67 matt #if BYTE_ORDER == LITTLE_ENDIAN
949 1.67 matt mask = v >> 8;
950 1.67 matt interrupts = v & 0xff;
951 1.67 matt #else
952 1.67 matt interrupts = v >> 8;
953 1.67 matt mask = v & 0xff;
954 1.67 matt #endif
955 1.67 matt KDASSERT(mask == sc->sc_intmask);
956 1.2 thorpej status = interrupts & mask;
957 1.2 thorpej
958 1.2 thorpej /* Ours? */
959 1.2 thorpej if (status == 0)
960 1.2 thorpej return (0);
961 1.2 thorpej
962 1.2 thorpej /*
963 1.2 thorpej * It's ours; disable all interrupts while we process them.
964 1.2 thorpej */
965 1.67 matt smc91cxx_intr_mask_write(bst, bsh, 0);
966 1.2 thorpej
967 1.2 thorpej /*
968 1.2 thorpej * Receive overrun interrupts.
969 1.2 thorpej */
970 1.2 thorpej if (status & IM_RX_OVRN_INT) {
971 1.67 matt smc91cxx_intr_ack_write(bst, bsh, IM_RX_OVRN_INT);
972 1.2 thorpej ifp->if_ierrors++;
973 1.2 thorpej }
974 1.2 thorpej
975 1.2 thorpej /*
976 1.2 thorpej * Receive interrupts.
977 1.2 thorpej */
978 1.2 thorpej if (status & IM_RCV_INT) {
979 1.2 thorpej #if 1 /* DIAGNOSTIC */
980 1.2 thorpej packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W);
981 1.36 pooka if (packetno & FIFO_REMPTY) {
982 1.65 cegger aprint_error_dev(&sc->sc_dev, "receive interrupt on empty fifo\n");
983 1.36 pooka goto out;
984 1.36 pooka } else
985 1.2 thorpej #endif
986 1.2 thorpej smc91cxx_read(sc);
987 1.2 thorpej }
988 1.2 thorpej
989 1.2 thorpej /*
990 1.2 thorpej * Memory allocation interrupts.
991 1.2 thorpej */
992 1.2 thorpej if (status & IM_ALLOC_INT) {
993 1.2 thorpej /* Disable this interrupt. */
994 1.2 thorpej mask &= ~IM_ALLOC_INT;
995 1.67 matt sc->sc_intmask &= ~IM_ALLOC_INT;
996 1.2 thorpej
997 1.2 thorpej /*
998 1.67 matt * Save allocated packet number for use in start
999 1.2 thorpej */
1000 1.67 matt packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B);
1001 1.67 matt KASSERT(sc->sc_txpacketno & ARR_FAILED);
1002 1.67 matt sc->sc_txpacketno = packetno;
1003 1.2 thorpej
1004 1.67 matt /*
1005 1.67 matt * We can transmit again!
1006 1.67 matt */
1007 1.2 thorpej ifp->if_flags &= ~IFF_OACTIVE;
1008 1.2 thorpej ifp->if_timer = 0;
1009 1.2 thorpej }
1010 1.2 thorpej
1011 1.2 thorpej /*
1012 1.2 thorpej * Transmit complete interrupt. Handle transmission error messages.
1013 1.2 thorpej * This will only be called on error condition because of AUTO RELEASE
1014 1.2 thorpej * mode.
1015 1.2 thorpej */
1016 1.2 thorpej if (status & IM_TX_INT) {
1017 1.67 matt smc91cxx_intr_ack_write(bst, bsh, IM_TX_INT);
1018 1.2 thorpej
1019 1.2 thorpej packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) &
1020 1.2 thorpej FIFO_TX_MASK;
1021 1.2 thorpej
1022 1.2 thorpej /*
1023 1.2 thorpej * Select this as the packet to read from.
1024 1.2 thorpej */
1025 1.2 thorpej bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno);
1026 1.2 thorpej
1027 1.2 thorpej /*
1028 1.2 thorpej * Position the pointer to the beginning of the packet.
1029 1.2 thorpej */
1030 1.2 thorpej bus_space_write_2(bst, bsh, POINTER_REG_W,
1031 1.2 thorpej PTR_AUTOINC | PTR_READ /* | 0x0000 */);
1032 1.2 thorpej
1033 1.2 thorpej /*
1034 1.2 thorpej * Fetch the TX status word. This will be a copy of
1035 1.2 thorpej * the EPH_STATUS_REG_W at the time of the transmission
1036 1.2 thorpej * failure.
1037 1.2 thorpej */
1038 1.2 thorpej tx_status = bus_space_read_2(bst, bsh, DATA_REG_W);
1039 1.2 thorpej
1040 1.67 matt if (tx_status & EPHSR_TX_SUC) {
1041 1.67 matt static struct timeval txsuc_last;
1042 1.67 matt static int txsuc_count;
1043 1.67 matt if (ppsratecheck(&txsuc_last, &txsuc_count, 1))
1044 1.67 matt printf("%s: successful packet caused TX"
1045 1.67 matt " interrupt?!\n", sc->sc_dev.dv_xname);
1046 1.67 matt } else
1047 1.2 thorpej ifp->if_oerrors++;
1048 1.2 thorpej
1049 1.2 thorpej if (tx_status & EPHSR_LATCOL)
1050 1.2 thorpej ifp->if_collisions++;
1051 1.2 thorpej
1052 1.67 matt /* Disable this interrupt (start will reenable if needed). */
1053 1.67 matt mask &= ~IM_TX_INT;
1054 1.67 matt sc->sc_intmask &= ~IM_TX_INT;
1055 1.67 matt
1056 1.2 thorpej /*
1057 1.2 thorpej * Some of these errors disable the transmitter; reenable it.
1058 1.2 thorpej */
1059 1.2 thorpej SMC_SELECT_BANK(sc, 0);
1060 1.2 thorpej #ifdef SMC91CXX_SW_PAD
1061 1.2 thorpej bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE);
1062 1.2 thorpej #else
1063 1.2 thorpej bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W,
1064 1.2 thorpej TCR_ENABLE | TCR_PAD_ENABLE);
1065 1.2 thorpej #endif
1066 1.2 thorpej
1067 1.2 thorpej /*
1068 1.2 thorpej * Kill the failed packet and wait for the MMU to unbusy.
1069 1.2 thorpej */
1070 1.2 thorpej SMC_SELECT_BANK(sc, 2);
1071 1.2 thorpej while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
1072 1.2 thorpej /* XXX bound this loop! */ ;
1073 1.2 thorpej bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT);
1074 1.2 thorpej
1075 1.2 thorpej ifp->if_timer = 0;
1076 1.2 thorpej }
1077 1.2 thorpej
1078 1.2 thorpej /*
1079 1.2 thorpej * Transmit underrun interrupts. We use this opportunity to
1080 1.2 thorpej * update transmit statistics from the card.
1081 1.2 thorpej */
1082 1.2 thorpej if (status & IM_TX_EMPTY_INT) {
1083 1.67 matt smc91cxx_intr_ack_write(bst, bsh, IM_TX_EMPTY_INT);
1084 1.2 thorpej
1085 1.2 thorpej /* Disable this interrupt. */
1086 1.2 thorpej mask &= ~IM_TX_EMPTY_INT;
1087 1.67 matt sc->sc_intmask &= ~IM_TX_EMPTY_INT;
1088 1.2 thorpej
1089 1.2 thorpej SMC_SELECT_BANK(sc, 0);
1090 1.2 thorpej card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W);
1091 1.2 thorpej
1092 1.2 thorpej /* Single collisions. */
1093 1.2 thorpej ifp->if_collisions += card_stats & ECR_COLN_MASK;
1094 1.2 thorpej
1095 1.2 thorpej /* Multiple collisions. */
1096 1.2 thorpej ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4;
1097 1.2 thorpej
1098 1.2 thorpej SMC_SELECT_BANK(sc, 2);
1099 1.2 thorpej
1100 1.2 thorpej ifp->if_timer = 0;
1101 1.45 scw }
1102 1.45 scw
1103 1.45 scw if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy &&
1104 1.45 scw (status & IM_MD_INT)) {
1105 1.45 scw /*
1106 1.45 scw * Internal PHY status change
1107 1.45 scw */
1108 1.45 scw mii_tick(&sc->sc_mii);
1109 1.2 thorpej }
1110 1.2 thorpej
1111 1.2 thorpej /*
1112 1.2 thorpej * Other errors. Reset the interface.
1113 1.2 thorpej */
1114 1.2 thorpej if (status & IM_EPH_INT) {
1115 1.2 thorpej smc91cxx_stop(sc);
1116 1.2 thorpej smc91cxx_init(sc);
1117 1.2 thorpej }
1118 1.2 thorpej
1119 1.2 thorpej /*
1120 1.2 thorpej * Attempt to queue more packets for transmission.
1121 1.2 thorpej */
1122 1.2 thorpej smc91cxx_start(ifp);
1123 1.2 thorpej
1124 1.36 pooka out:
1125 1.2 thorpej /*
1126 1.2 thorpej * Reenable the interrupts we wish to receive now that processing
1127 1.2 thorpej * is complete.
1128 1.2 thorpej */
1129 1.67 matt mask |= sc->sc_intmask;
1130 1.67 matt smc91cxx_intr_mask_write(bst, bsh, mask);
1131 1.5 explorer
1132 1.5 explorer #if NRND > 0
1133 1.5 explorer if (status)
1134 1.5 explorer rnd_add_uint32(&sc->rnd_source, status);
1135 1.5 explorer #endif
1136 1.2 thorpej
1137 1.2 thorpej return (1);
1138 1.2 thorpej }
1139 1.2 thorpej
1140 1.2 thorpej /*
1141 1.2 thorpej * Read a packet from the card and pass it up to the kernel.
1142 1.2 thorpej * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2!
1143 1.2 thorpej */
1144 1.2 thorpej void
1145 1.2 thorpej smc91cxx_read(sc)
1146 1.2 thorpej struct smc91cxx_softc *sc;
1147 1.2 thorpej {
1148 1.2 thorpej struct ifnet *ifp = &sc->sc_ec.ec_if;
1149 1.2 thorpej bus_space_tag_t bst = sc->sc_bst;
1150 1.2 thorpej bus_space_handle_t bsh = sc->sc_bsh;
1151 1.2 thorpej struct ether_header *eh;
1152 1.2 thorpej struct mbuf *m;
1153 1.2 thorpej u_int16_t status, packetno, packetlen;
1154 1.2 thorpej u_int8_t *data;
1155 1.41 scw u_int32_t dr;
1156 1.2 thorpej
1157 1.2 thorpej again:
1158 1.2 thorpej /*
1159 1.2 thorpej * Set data pointer to the beginning of the packet. Since
1160 1.2 thorpej * PTR_RCV is set, the packet number will be found automatically
1161 1.2 thorpej * in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1162 1.2 thorpej */
1163 1.67 matt packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W);
1164 1.67 matt if (packetno & FIFO_REMPTY)
1165 1.67 matt return;
1166 1.67 matt
1167 1.2 thorpej bus_space_write_2(bst, bsh, POINTER_REG_W,
1168 1.2 thorpej PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */);
1169 1.2 thorpej
1170 1.2 thorpej /*
1171 1.2 thorpej * First two words are status and packet length.
1172 1.2 thorpej */
1173 1.41 scw if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) {
1174 1.41 scw status = bus_space_read_2(bst, bsh, DATA_REG_W);
1175 1.41 scw packetlen = bus_space_read_2(bst, bsh, DATA_REG_W);
1176 1.41 scw } else {
1177 1.41 scw dr = bus_space_read_4(bst, bsh, DATA_REG_W);
1178 1.41 scw #if BYTE_ORDER == LITTLE_ENDIAN
1179 1.41 scw status = (u_int16_t)dr;
1180 1.41 scw packetlen = (u_int16_t)(dr >> 16);
1181 1.41 scw #else
1182 1.41 scw packetlen = (u_int16_t)dr;
1183 1.41 scw status = (u_int16_t)(dr >> 16);
1184 1.41 scw #endif
1185 1.41 scw }
1186 1.41 scw
1187 1.41 scw packetlen &= RLEN_MASK;
1188 1.67 matt if (packetlen < ETHER_MIN_LEN - ETHER_CRC_LEN + 6 || packetlen > 1534) {
1189 1.67 matt ifp->if_ierrors++;
1190 1.67 matt goto out;
1191 1.67 matt }
1192 1.2 thorpej
1193 1.2 thorpej /*
1194 1.2 thorpej * The packet length includes 3 extra words: status, length,
1195 1.2 thorpej * and an extra word that includes the control byte.
1196 1.2 thorpej */
1197 1.2 thorpej packetlen -= 6;
1198 1.2 thorpej
1199 1.2 thorpej /*
1200 1.2 thorpej * Account for receive errors and discard.
1201 1.2 thorpej */
1202 1.2 thorpej if (status & RS_ERRORS) {
1203 1.2 thorpej ifp->if_ierrors++;
1204 1.2 thorpej goto out;
1205 1.2 thorpej }
1206 1.2 thorpej
1207 1.2 thorpej /*
1208 1.2 thorpej * Adjust for odd-length packet.
1209 1.2 thorpej */
1210 1.2 thorpej if (status & RS_ODDFRAME)
1211 1.2 thorpej packetlen++;
1212 1.2 thorpej
1213 1.2 thorpej /*
1214 1.2 thorpej * Allocate a header mbuf.
1215 1.2 thorpej */
1216 1.2 thorpej MGETHDR(m, M_DONTWAIT, MT_DATA);
1217 1.2 thorpej if (m == NULL)
1218 1.2 thorpej goto out;
1219 1.2 thorpej m->m_pkthdr.rcvif = ifp;
1220 1.33 itojun m->m_pkthdr.len = packetlen;
1221 1.2 thorpej
1222 1.2 thorpej /*
1223 1.2 thorpej * Always put the packet in a cluster.
1224 1.2 thorpej * XXX should chain small mbufs if less than threshold.
1225 1.2 thorpej */
1226 1.2 thorpej MCLGET(m, M_DONTWAIT);
1227 1.2 thorpej if ((m->m_flags & M_EXT) == 0) {
1228 1.2 thorpej m_freem(m);
1229 1.2 thorpej ifp->if_ierrors++;
1230 1.65 cegger aprint_error_dev(&sc->sc_dev, "can't allocate cluster for incoming packet\n");
1231 1.2 thorpej goto out;
1232 1.2 thorpej }
1233 1.2 thorpej
1234 1.2 thorpej /*
1235 1.38 thorpej * Pull the packet off the interface. Make sure the payload
1236 1.38 thorpej * is aligned.
1237 1.2 thorpej */
1238 1.41 scw if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) {
1239 1.59 christos m->m_data = (char *) ALIGN(mtod(m, char *) +
1240 1.41 scw sizeof(struct ether_header)) - sizeof(struct ether_header);
1241 1.41 scw
1242 1.41 scw eh = mtod(m, struct ether_header *);
1243 1.41 scw data = mtod(m, u_int8_t *);
1244 1.67 matt KASSERT(trunc_page((uintptr_t)data) == trunc_page((uintptr_t)data + packetlen - 1));
1245 1.41 scw if (packetlen > 1)
1246 1.41 scw bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W,
1247 1.41 scw (u_int16_t *)data, packetlen >> 1);
1248 1.41 scw if (packetlen & 1) {
1249 1.41 scw data += packetlen & ~1;
1250 1.41 scw *data = bus_space_read_1(bst, bsh, DATA_REG_B);
1251 1.41 scw }
1252 1.41 scw } else {
1253 1.43 scw u_int8_t *dp;
1254 1.43 scw
1255 1.59 christos m->m_data = (void *) ALIGN(mtod(m, void *));
1256 1.41 scw eh = mtod(m, struct ether_header *);
1257 1.43 scw dp = data = mtod(m, u_int8_t *);
1258 1.67 matt KASSERT(trunc_page((uintptr_t)data) == trunc_page((uintptr_t)data + packetlen - 1));
1259 1.41 scw if (packetlen > 3)
1260 1.41 scw bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W,
1261 1.41 scw (u_int32_t *)data, packetlen >> 2);
1262 1.41 scw if (packetlen & 3) {
1263 1.41 scw data += packetlen & ~3;
1264 1.41 scw *((u_int32_t *)data) =
1265 1.41 scw bus_space_read_stream_4(bst, bsh, DATA_REG_W);
1266 1.41 scw }
1267 1.2 thorpej }
1268 1.2 thorpej
1269 1.2 thorpej ifp->if_ipackets++;
1270 1.2 thorpej
1271 1.21 itojun /*
1272 1.21 itojun * Make sure to behave as IFF_SIMPLEX in all cases.
1273 1.21 itojun * This is to cope with SMC91C92 (Megahertz XJ10BT), which
1274 1.21 itojun * loops back packets to itself on promiscuous mode.
1275 1.21 itojun * (should be ensured by chipset configuration)
1276 1.21 itojun */
1277 1.19 itojun if ((ifp->if_flags & IFF_PROMISC) != 0) {
1278 1.19 itojun /*
1279 1.23 itojun * Drop packet looped back from myself.
1280 1.19 itojun */
1281 1.61 dyoung if (ether_cmp(eh->ether_shost, CLLADDR(ifp->if_sadl)) == 0) {
1282 1.2 thorpej m_freem(m);
1283 1.2 thorpej goto out;
1284 1.2 thorpej }
1285 1.2 thorpej }
1286 1.21 itojun
1287 1.43 scw m->m_pkthdr.len = m->m_len = packetlen;
1288 1.43 scw
1289 1.21 itojun #if NBPFILTER > 0
1290 1.21 itojun /*
1291 1.21 itojun * Hand the packet off to bpf listeners.
1292 1.21 itojun */
1293 1.21 itojun if (ifp->if_bpf)
1294 1.21 itojun bpf_mtap(ifp->if_bpf, m);
1295 1.21 itojun #endif
1296 1.2 thorpej
1297 1.17 thorpej (*ifp->if_input)(ifp, m);
1298 1.2 thorpej
1299 1.2 thorpej out:
1300 1.2 thorpej /*
1301 1.2 thorpej * Tell the card to free the memory occupied by this packet.
1302 1.2 thorpej */
1303 1.2 thorpej while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
1304 1.2 thorpej /* XXX bound this loop! */ ;
1305 1.2 thorpej bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE);
1306 1.2 thorpej
1307 1.2 thorpej /*
1308 1.2 thorpej * Check for another packet.
1309 1.2 thorpej */
1310 1.2 thorpej packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W);
1311 1.2 thorpej if (packetno & FIFO_REMPTY)
1312 1.2 thorpej return;
1313 1.2 thorpej goto again;
1314 1.2 thorpej }
1315 1.2 thorpej
1316 1.2 thorpej /*
1317 1.2 thorpej * Process an ioctl request.
1318 1.2 thorpej */
1319 1.2 thorpej int
1320 1.2 thorpej smc91cxx_ioctl(ifp, cmd, data)
1321 1.2 thorpej struct ifnet *ifp;
1322 1.2 thorpej u_long cmd;
1323 1.59 christos void *data;
1324 1.2 thorpej {
1325 1.2 thorpej struct smc91cxx_softc *sc = ifp->if_softc;
1326 1.2 thorpej struct ifaddr *ifa = (struct ifaddr *)data;
1327 1.2 thorpej struct ifreq *ifr = (struct ifreq *)data;
1328 1.2 thorpej int s, error = 0;
1329 1.2 thorpej
1330 1.11 mycroft s = splnet();
1331 1.2 thorpej
1332 1.2 thorpej switch (cmd) {
1333 1.2 thorpej case SIOCSIFADDR:
1334 1.4 thorpej if ((error = smc91cxx_enable(sc)) != 0)
1335 1.4 thorpej break;
1336 1.2 thorpej ifp->if_flags |= IFF_UP;
1337 1.2 thorpej switch (ifa->ifa_addr->sa_family) {
1338 1.2 thorpej #ifdef INET
1339 1.2 thorpej case AF_INET:
1340 1.2 thorpej smc91cxx_init(sc);
1341 1.2 thorpej arp_ifinit(ifp, ifa);
1342 1.2 thorpej break;
1343 1.2 thorpej #endif
1344 1.2 thorpej default:
1345 1.2 thorpej smc91cxx_init(sc);
1346 1.2 thorpej break;
1347 1.2 thorpej }
1348 1.2 thorpej break;
1349 1.2 thorpej
1350 1.2 thorpej
1351 1.2 thorpej case SIOCSIFFLAGS:
1352 1.2 thorpej if ((ifp->if_flags & IFF_UP) == 0 &&
1353 1.2 thorpej (ifp->if_flags & IFF_RUNNING) != 0) {
1354 1.2 thorpej /*
1355 1.2 thorpej * If interface is marked down and it is running,
1356 1.2 thorpej * stop it.
1357 1.2 thorpej */
1358 1.2 thorpej smc91cxx_stop(sc);
1359 1.2 thorpej ifp->if_flags &= ~IFF_RUNNING;
1360 1.4 thorpej smc91cxx_disable(sc);
1361 1.2 thorpej } else if ((ifp->if_flags & IFF_UP) != 0 &&
1362 1.2 thorpej (ifp->if_flags & IFF_RUNNING) == 0) {
1363 1.2 thorpej /*
1364 1.2 thorpej * If interface is marked up and it is stopped,
1365 1.2 thorpej * start it.
1366 1.2 thorpej */
1367 1.4 thorpej if ((error = smc91cxx_enable(sc)) != 0)
1368 1.4 thorpej break;
1369 1.2 thorpej smc91cxx_init(sc);
1370 1.14 thorpej } else if ((ifp->if_flags & IFF_UP) != 0) {
1371 1.2 thorpej /*
1372 1.2 thorpej * Reset the interface to pick up changes in any
1373 1.2 thorpej * other flags that affect hardware registers.
1374 1.2 thorpej */
1375 1.2 thorpej smc91cxx_reset(sc);
1376 1.2 thorpej }
1377 1.2 thorpej break;
1378 1.2 thorpej
1379 1.2 thorpej case SIOCADDMULTI:
1380 1.2 thorpej case SIOCDELMULTI:
1381 1.25 jhawk if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) {
1382 1.4 thorpej error = EIO;
1383 1.4 thorpej break;
1384 1.4 thorpej }
1385 1.4 thorpej
1386 1.62 dyoung if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
1387 1.2 thorpej /*
1388 1.2 thorpej * Multicast list has changed; set the hardware
1389 1.2 thorpej * filter accordingly.
1390 1.2 thorpej */
1391 1.49 thorpej if (ifp->if_flags & IFF_RUNNING)
1392 1.49 thorpej smc91cxx_reset(sc);
1393 1.2 thorpej error = 0;
1394 1.2 thorpej }
1395 1.2 thorpej break;
1396 1.2 thorpej
1397 1.2 thorpej case SIOCGIFMEDIA:
1398 1.2 thorpej case SIOCSIFMEDIA:
1399 1.26 briggs error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
1400 1.2 thorpej break;
1401 1.2 thorpej
1402 1.2 thorpej default:
1403 1.2 thorpej error = EINVAL;
1404 1.2 thorpej break;
1405 1.2 thorpej }
1406 1.2 thorpej
1407 1.2 thorpej splx(s);
1408 1.2 thorpej return (error);
1409 1.2 thorpej }
1410 1.2 thorpej
1411 1.2 thorpej /*
1412 1.2 thorpej * Reset the interface.
1413 1.2 thorpej */
1414 1.2 thorpej void
1415 1.2 thorpej smc91cxx_reset(sc)
1416 1.2 thorpej struct smc91cxx_softc *sc;
1417 1.2 thorpej {
1418 1.2 thorpej int s;
1419 1.2 thorpej
1420 1.11 mycroft s = splnet();
1421 1.2 thorpej smc91cxx_stop(sc);
1422 1.2 thorpej smc91cxx_init(sc);
1423 1.2 thorpej splx(s);
1424 1.2 thorpej }
1425 1.2 thorpej
1426 1.2 thorpej /*
1427 1.2 thorpej * Watchdog timer.
1428 1.2 thorpej */
1429 1.2 thorpej void
1430 1.2 thorpej smc91cxx_watchdog(ifp)
1431 1.2 thorpej struct ifnet *ifp;
1432 1.2 thorpej {
1433 1.2 thorpej struct smc91cxx_softc *sc = ifp->if_softc;
1434 1.2 thorpej
1435 1.65 cegger log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev));
1436 1.2 thorpej ifp->if_oerrors++;
1437 1.2 thorpej smc91cxx_reset(sc);
1438 1.2 thorpej }
1439 1.2 thorpej
1440 1.2 thorpej /*
1441 1.2 thorpej * Stop output on the interface.
1442 1.2 thorpej */
1443 1.2 thorpej void
1444 1.2 thorpej smc91cxx_stop(sc)
1445 1.2 thorpej struct smc91cxx_softc *sc;
1446 1.2 thorpej {
1447 1.2 thorpej bus_space_tag_t bst = sc->sc_bst;
1448 1.2 thorpej bus_space_handle_t bsh = sc->sc_bsh;
1449 1.2 thorpej
1450 1.2 thorpej /*
1451 1.2 thorpej * Clear interrupt mask; disable all interrupts.
1452 1.2 thorpej */
1453 1.2 thorpej SMC_SELECT_BANK(sc, 2);
1454 1.67 matt smc91cxx_intr_mask_write(bst, bsh, 0);
1455 1.2 thorpej
1456 1.2 thorpej /*
1457 1.2 thorpej * Disable transmitter and receiver.
1458 1.2 thorpej */
1459 1.2 thorpej SMC_SELECT_BANK(sc, 0);
1460 1.2 thorpej bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0);
1461 1.2 thorpej bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0);
1462 1.2 thorpej
1463 1.2 thorpej /*
1464 1.2 thorpej * Cancel watchdog timer.
1465 1.2 thorpej */
1466 1.2 thorpej sc->sc_ec.ec_if.if_timer = 0;
1467 1.4 thorpej }
1468 1.4 thorpej
1469 1.4 thorpej /*
1470 1.4 thorpej * Enable power on the interface.
1471 1.4 thorpej */
1472 1.4 thorpej int
1473 1.4 thorpej smc91cxx_enable(sc)
1474 1.4 thorpej struct smc91cxx_softc *sc;
1475 1.4 thorpej {
1476 1.4 thorpej
1477 1.25 jhawk if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) {
1478 1.4 thorpej if ((*sc->sc_enable)(sc) != 0) {
1479 1.65 cegger aprint_error_dev(&sc->sc_dev, "device enable failed\n");
1480 1.4 thorpej return (EIO);
1481 1.4 thorpej }
1482 1.4 thorpej }
1483 1.4 thorpej
1484 1.25 jhawk sc->sc_flags |= SMC_FLAGS_ENABLED;
1485 1.4 thorpej return (0);
1486 1.4 thorpej }
1487 1.4 thorpej
1488 1.4 thorpej /*
1489 1.4 thorpej * Disable power on the interface.
1490 1.4 thorpej */
1491 1.4 thorpej void
1492 1.4 thorpej smc91cxx_disable(sc)
1493 1.4 thorpej struct smc91cxx_softc *sc;
1494 1.4 thorpej {
1495 1.4 thorpej
1496 1.25 jhawk if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) {
1497 1.4 thorpej (*sc->sc_disable)(sc);
1498 1.25 jhawk sc->sc_flags &= ~SMC_FLAGS_ENABLED;
1499 1.4 thorpej }
1500 1.13 thorpej }
1501 1.13 thorpej
1502 1.13 thorpej int
1503 1.13 thorpej smc91cxx_activate(self, act)
1504 1.13 thorpej struct device *self;
1505 1.13 thorpej enum devact act;
1506 1.13 thorpej {
1507 1.13 thorpej struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self;
1508 1.13 thorpej int rv = 0, s;
1509 1.13 thorpej
1510 1.13 thorpej s = splnet();
1511 1.13 thorpej switch (act) {
1512 1.13 thorpej case DVACT_ACTIVATE:
1513 1.13 thorpej rv = EOPNOTSUPP;
1514 1.13 thorpej break;
1515 1.13 thorpej
1516 1.13 thorpej case DVACT_DEACTIVATE:
1517 1.24 enami if_deactivate(&sc->sc_ec.ec_if);
1518 1.13 thorpej break;
1519 1.13 thorpej }
1520 1.13 thorpej splx(s);
1521 1.13 thorpej return (rv);
1522 1.22 itojun }
1523 1.22 itojun
1524 1.22 itojun int
1525 1.58 christos smc91cxx_detach(struct device *self, int flags)
1526 1.22 itojun {
1527 1.22 itojun struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self;
1528 1.22 itojun struct ifnet *ifp = &sc->sc_ec.ec_if;
1529 1.22 itojun
1530 1.25 jhawk /* Succeed now if there's no work to do. */
1531 1.25 jhawk if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0)
1532 1.25 jhawk return (0);
1533 1.25 jhawk
1534 1.25 jhawk
1535 1.25 jhawk /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */
1536 1.22 itojun smc91cxx_disable(sc);
1537 1.22 itojun
1538 1.22 itojun /* smc91cxx_attach() never fails */
1539 1.22 itojun
1540 1.22 itojun /* Delete all media. */
1541 1.26 briggs ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
1542 1.22 itojun
1543 1.22 itojun #if NRND > 0
1544 1.22 itojun rnd_detach_source(&sc->rnd_source);
1545 1.22 itojun #endif
1546 1.22 itojun ether_ifdetach(ifp);
1547 1.22 itojun if_detach(ifp);
1548 1.22 itojun
1549 1.22 itojun return (0);
1550 1.2 thorpej }
1551 1.26 briggs
1552 1.26 briggs u_int32_t
1553 1.26 briggs smc91cxx_mii_bitbang_read(self)
1554 1.26 briggs struct device *self;
1555 1.26 briggs {
1556 1.26 briggs struct smc91cxx_softc *sc = (void *) self;
1557 1.26 briggs
1558 1.26 briggs /* We're already in bank 3. */
1559 1.26 briggs return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W));
1560 1.26 briggs }
1561 1.26 briggs
1562 1.26 briggs void
1563 1.26 briggs smc91cxx_mii_bitbang_write(self, val)
1564 1.26 briggs struct device *self;
1565 1.26 briggs u_int32_t val;
1566 1.26 briggs {
1567 1.26 briggs struct smc91cxx_softc *sc = (void *) self;
1568 1.26 briggs
1569 1.26 briggs /* We're already in bank 3. */
1570 1.26 briggs bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val);
1571 1.26 briggs }
1572 1.26 briggs
1573 1.26 briggs int
1574 1.26 briggs smc91cxx_mii_readreg(self, phy, reg)
1575 1.26 briggs struct device *self;
1576 1.26 briggs int phy, reg;
1577 1.26 briggs {
1578 1.26 briggs struct smc91cxx_softc *sc = (void *) self;
1579 1.26 briggs int val;
1580 1.26 briggs
1581 1.26 briggs SMC_SELECT_BANK(sc, 3);
1582 1.26 briggs
1583 1.26 briggs val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg);
1584 1.26 briggs
1585 1.26 briggs SMC_SELECT_BANK(sc, 2);
1586 1.26 briggs
1587 1.26 briggs return (val);
1588 1.26 briggs }
1589 1.26 briggs
1590 1.26 briggs void
1591 1.26 briggs smc91cxx_mii_writereg(self, phy, reg, val)
1592 1.26 briggs struct device *self;
1593 1.26 briggs int phy, reg, val;
1594 1.26 briggs {
1595 1.26 briggs struct smc91cxx_softc *sc = (void *) self;
1596 1.26 briggs
1597 1.26 briggs SMC_SELECT_BANK(sc, 3);
1598 1.26 briggs
1599 1.26 briggs mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val);
1600 1.26 briggs
1601 1.26 briggs SMC_SELECT_BANK(sc, 2);
1602 1.26 briggs }
1603 1.26 briggs
1604 1.26 briggs void
1605 1.26 briggs smc91cxx_statchg(self)
1606 1.26 briggs struct device *self;
1607 1.26 briggs {
1608 1.26 briggs struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self;
1609 1.26 briggs bus_space_tag_t bst = sc->sc_bst;
1610 1.26 briggs bus_space_handle_t bsh = sc->sc_bsh;
1611 1.26 briggs int mctl;
1612 1.26 briggs
1613 1.26 briggs SMC_SELECT_BANK(sc, 0);
1614 1.26 briggs mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W);
1615 1.26 briggs if (sc->sc_mii.mii_media_active & IFM_FDX)
1616 1.26 briggs mctl |= TCR_SWFDUP;
1617 1.26 briggs else
1618 1.26 briggs mctl &= ~TCR_SWFDUP;
1619 1.26 briggs bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl);
1620 1.26 briggs SMC_SELECT_BANK(sc, 2); /* back to operating window */
1621 1.26 briggs }
1622 1.26 briggs
1623 1.26 briggs /*
1624 1.26 briggs * One second timer, used to tick the MII.
1625 1.26 briggs */
1626 1.26 briggs void
1627 1.26 briggs smc91cxx_tick(arg)
1628 1.26 briggs void *arg;
1629 1.26 briggs {
1630 1.26 briggs struct smc91cxx_softc *sc = arg;
1631 1.26 briggs int s;
1632 1.26 briggs
1633 1.26 briggs #ifdef DIAGNOSTIC
1634 1.26 briggs if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0)
1635 1.26 briggs panic("smc91cxx_tick");
1636 1.26 briggs #endif
1637 1.26 briggs
1638 1.55 thorpej if (!device_is_active(&sc->sc_dev))
1639 1.26 briggs return;
1640 1.26 briggs
1641 1.26 briggs s = splnet();
1642 1.26 briggs mii_tick(&sc->sc_mii);
1643 1.26 briggs splx(s);
1644 1.26 briggs
1645 1.26 briggs callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc);
1646 1.26 briggs }
1647 1.26 briggs
1648