smc91cxx.c revision 1.26
1 /* $NetBSD: smc91cxx.c,v 1.26 2000/07/30 21:34:48 briggs Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Gardner Buchanan <gbuchanan (at) shl.com> 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Gardner Buchanan. 55 * 4. The name of Gardner Buchanan may not be used to endorse or promote 56 * products derived from this software without specific prior written 57 * permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 71 */ 72 73 /* 74 * Core driver for the SMC 91Cxx family of Ethernet chips. 75 * 76 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 77 * written for NetBSD/amiga by Michael Hitch. 78 */ 79 80 #include "opt_inet.h" 81 #include "opt_ccitt.h" 82 #include "opt_llc.h" 83 #include "opt_ns.h" 84 #include "bpfilter.h" 85 #include "rnd.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/mbuf.h> 90 #include <sys/syslog.h> 91 #include <sys/socket.h> 92 #include <sys/device.h> 93 #include <sys/kernel.h> 94 #include <sys/malloc.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #if NRND > 0 98 #include <sys/rnd.h> 99 #endif 100 101 #include <machine/bus.h> 102 #include <machine/intr.h> 103 104 #include <net/if.h> 105 #include <net/if_dl.h> 106 #include <net/if_ether.h> 107 #include <net/if_media.h> 108 109 #ifdef INET 110 #include <netinet/in.h> 111 #include <netinet/if_inarp.h> 112 #include <netinet/in_systm.h> 113 #include <netinet/in_var.h> 114 #include <netinet/ip.h> 115 #endif 116 117 #ifdef NS 118 #include <netns/ns.h> 119 #include <netns/ns_if.h> 120 #endif 121 122 #if defined(CCITT) && defined(LLC) 123 #include <sys/socketvar.h> 124 #include <netccitt/x25.h> 125 #include <netccitt/pk.h> 126 #include <netccitt/pk_var.h> 127 #include <netccitt/pk_extern.h> 128 #endif 129 130 #if NBPFILTER > 0 131 #include <net/bpf.h> 132 #include <net/bpfdesc.h> 133 #endif 134 135 #include <dev/mii/mii.h> 136 #include <dev/mii/miivar.h> 137 #include <dev/mii/mii_bitbang.h> 138 139 #include <dev/ic/smc91cxxreg.h> 140 #include <dev/ic/smc91cxxvar.h> 141 142 /* XXX Hardware padding doesn't work yet(?) */ 143 #define SMC91CXX_SW_PAD 144 145 const char *smc91cxx_idstrs[] = { 146 NULL, /* 0 */ 147 NULL, /* 1 */ 148 NULL, /* 2 */ 149 "SMC91C90/91C92", /* 3 */ 150 "SMC91C94", /* 4 */ 151 "SMC91C95", /* 5 */ 152 NULL, /* 6 */ 153 "SMC91C100", /* 7 */ 154 "SMC91C100FD", /* 8 */ 155 NULL, /* 9 */ 156 NULL, /* 10 */ 157 NULL, /* 11 */ 158 NULL, /* 12 */ 159 NULL, /* 13 */ 160 NULL, /* 14 */ 161 NULL, /* 15 */ 162 }; 163 164 /* Supported media types. */ 165 const int smc91cxx_media[] = { 166 IFM_ETHER|IFM_10_T, 167 IFM_ETHER|IFM_10_5, 168 }; 169 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 170 171 /* 172 * MII bit-bang glue. 173 */ 174 u_int32_t smc91cxx_mii_bitbang_read __P((struct device *)); 175 void smc91cxx_mii_bitbang_write __P((struct device *, u_int32_t)); 176 177 const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 178 smc91cxx_mii_bitbang_read, 179 smc91cxx_mii_bitbang_write, 180 { 181 MR_MDO, /* MII_BIT_MDO */ 182 MR_MDI, /* MII_BIT_MDI */ 183 MR_MCLK, /* MII_BIT_MDC */ 184 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 185 0, /* MII_BIT_DIR_PHY_HOST */ 186 } 187 }; 188 189 /* MII callbacks */ 190 int smc91cxx_mii_readreg __P((struct device *, int, int)); 191 void smc91cxx_mii_writereg __P((struct device *, int, int, int)); 192 void smc91cxx_statchg __P((struct device *)); 193 void smc91cxx_tick __P((void *)); 194 195 int smc91cxx_mediachange __P((struct ifnet *)); 196 void smc91cxx_mediastatus __P((struct ifnet *, struct ifmediareq *)); 197 198 int smc91cxx_set_media __P((struct smc91cxx_softc *, int)); 199 200 void smc91cxx_init __P((struct smc91cxx_softc *)); 201 void smc91cxx_read __P((struct smc91cxx_softc *)); 202 void smc91cxx_reset __P((struct smc91cxx_softc *)); 203 void smc91cxx_start __P((struct ifnet *)); 204 void smc91cxx_resume __P((struct smc91cxx_softc *)); 205 void smc91cxx_stop __P((struct smc91cxx_softc *)); 206 void smc91cxx_watchdog __P((struct ifnet *)); 207 int smc91cxx_ioctl __P((struct ifnet *, u_long, caddr_t)); 208 209 static __inline int ether_cmp __P((void *, void *)); 210 static __inline int 211 ether_cmp(va, vb) 212 void *va, *vb; 213 { 214 u_int8_t *a = va; 215 u_int8_t *b = vb; 216 217 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 218 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 219 } 220 221 void 222 smc91cxx_attach(sc, myea) 223 struct smc91cxx_softc *sc; 224 u_int8_t *myea; 225 { 226 struct ifnet *ifp = &sc->sc_ec.ec_if; 227 bus_space_tag_t bst = sc->sc_bst; 228 bus_space_handle_t bsh = sc->sc_bsh; 229 struct ifmedia *ifm = &sc->sc_mii.mii_media; 230 const char *idstr; 231 u_int32_t miicapabilities; 232 u_int16_t tmp; 233 u_int8_t enaddr[ETHER_ADDR_LEN]; 234 int i, aui, mult, memsize; 235 char pbuf[9]; 236 237 /* Make sure the chip is stopped. */ 238 smc91cxx_stop(sc); 239 240 SMC_SELECT_BANK(sc, 3); 241 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 242 sc->sc_chipid = RR_ID(tmp); 243 /* check magic number */ 244 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 245 idstr = NULL; 246 printf("%s: invalid BSR 0x%04x\n", sc->sc_dev.dv_xname, tmp); 247 } else 248 idstr = smc91cxx_idstrs[sc->sc_chipid]; 249 printf("%s: ", sc->sc_dev.dv_xname); 250 if (idstr != NULL) 251 printf("%s, ", idstr); 252 else 253 printf("unknown chip id %d, ", sc->sc_chipid); 254 printf("revision %d, ", RR_REV(tmp)); 255 256 SMC_SELECT_BANK(sc, 0); 257 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 258 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 259 if (memsize == 255) memsize++; 260 memsize *= 256 * mult; 261 262 format_bytes(pbuf, sizeof(pbuf), memsize); 263 printf("%s\n", pbuf); 264 265 /* Read the station address from the chip. */ 266 SMC_SELECT_BANK(sc, 1); 267 if (myea == NULL) { 268 myea = enaddr; 269 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 270 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 271 myea[i + 1] = (tmp >> 8) & 0xff; 272 myea[i] = tmp & 0xff; 273 } 274 } 275 printf("%s: MAC address %s, ", sc->sc_dev.dv_xname, 276 ether_sprintf(myea)); 277 278 /* Initialize the ifnet structure. */ 279 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 280 ifp->if_softc = sc; 281 ifp->if_start = smc91cxx_start; 282 ifp->if_ioctl = smc91cxx_ioctl; 283 ifp->if_watchdog = smc91cxx_watchdog; 284 ifp->if_flags = 285 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 286 287 /* Attach the interface. */ 288 if_attach(ifp); 289 ether_ifattach(ifp, myea); 290 291 /* 292 * Initialize our media structures and MII info. We will 293 * probe the MII if we are on the SMC91Cxx 294 */ 295 sc->sc_mii.mii_ifp = ifp; 296 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 297 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 298 sc->sc_mii.mii_statchg = smc91cxx_statchg; 299 ifmedia_init(ifm, 0, smc91cxx_mediachange, smc91cxx_mediastatus); 300 301 SMC_SELECT_BANK(sc, 1); 302 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 303 304 miicapabilities = BMSR_MEDIAMASK; 305 switch (sc->sc_chipid) { 306 case CHIP_91100: 307 /* 308 * The 91100 does not have full-duplex capabilities, 309 * even if the PHY does. 310 */ 311 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 312 case CHIP_91100FD: 313 if (tmp & CR_MII_SELECT) { 314 printf("default media MII\n"); 315 mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, 316 MII_PHY_ANY, MII_OFFSET_ANY, 0); 317 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 318 ifmedia_add(&sc->sc_mii.mii_media, 319 IFM_ETHER|IFM_NONE, 0, NULL); 320 ifmedia_set(&sc->sc_mii.mii_media, 321 IFM_ETHER|IFM_NONE); 322 } else { 323 ifmedia_set(&sc->sc_mii.mii_media, 324 IFM_ETHER|IFM_AUTO); 325 } 326 sc->sc_flags |= SMC_FLAGS_HAS_MII; 327 break; 328 } 329 /*FALLTHROUGH*/ 330 default: 331 printf("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ? 332 "AUI" : "UTP"); 333 for (i = 0; i < NSMC91CxxMEDIA; i++) 334 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 335 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 336 break; 337 } 338 339 #if NBPFILTER > 0 340 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 341 #endif 342 343 #if NRND > 0 344 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 345 RND_TYPE_NET, 0); 346 #endif 347 348 /* The attach is successful. */ 349 sc->sc_flags |= SMC_FLAGS_ATTACHED; 350 } 351 352 /* 353 * Change media according to request. 354 */ 355 int 356 smc91cxx_mediachange(ifp) 357 struct ifnet *ifp; 358 { 359 struct smc91cxx_softc *sc = ifp->if_softc; 360 361 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 362 } 363 364 int 365 smc91cxx_set_media(sc, media) 366 struct smc91cxx_softc *sc; 367 int media; 368 { 369 bus_space_tag_t bst = sc->sc_bst; 370 bus_space_handle_t bsh = sc->sc_bsh; 371 u_int16_t tmp; 372 373 /* 374 * If the interface is not currently powered on, just return. 375 * When it is enabled later, smc91cxx_init() will properly set 376 * up the media for us. 377 */ 378 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 379 return (0); 380 381 if (IFM_TYPE(media) != IFM_ETHER) 382 return (EINVAL); 383 384 if (sc->sc_flags & SMC_FLAGS_HAS_MII) 385 return (mii_mediachg(&sc->sc_mii)); 386 387 switch (IFM_SUBTYPE(media)) { 388 case IFM_10_T: 389 case IFM_10_5: 390 SMC_SELECT_BANK(sc, 1); 391 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 392 if (IFM_SUBTYPE(media) == IFM_10_5) 393 tmp |= CR_AUI_SELECT; 394 else 395 tmp &= ~CR_AUI_SELECT; 396 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 397 delay(20000); /* XXX is this needed? */ 398 break; 399 400 default: 401 return (EINVAL); 402 } 403 404 return (0); 405 } 406 407 /* 408 * Notify the world which media we're using. 409 */ 410 void 411 smc91cxx_mediastatus(ifp, ifmr) 412 struct ifnet *ifp; 413 struct ifmediareq *ifmr; 414 { 415 struct smc91cxx_softc *sc = ifp->if_softc; 416 bus_space_tag_t bst = sc->sc_bst; 417 bus_space_handle_t bsh = sc->sc_bsh; 418 u_int16_t tmp; 419 420 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 421 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 422 ifmr->ifm_status = 0; 423 return; 424 } 425 426 /* 427 * If we have MII, go ask the PHY what's going on. 428 */ 429 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 430 mii_pollstat(&sc->sc_mii); 431 ifmr->ifm_active = sc->sc_mii.mii_media_active; 432 ifmr->ifm_status = sc->sc_mii.mii_media_status; 433 return; 434 } 435 436 SMC_SELECT_BANK(sc, 1); 437 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 438 ifmr->ifm_active = 439 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 440 } 441 442 /* 443 * Reset and initialize the chip. 444 */ 445 void 446 smc91cxx_init(sc) 447 struct smc91cxx_softc *sc; 448 { 449 struct ifnet *ifp = &sc->sc_ec.ec_if; 450 bus_space_tag_t bst = sc->sc_bst; 451 bus_space_handle_t bsh = sc->sc_bsh; 452 u_int16_t tmp; 453 u_int8_t *enaddr; 454 int s, i; 455 456 s = splnet(); 457 458 /* 459 * This resets the registersmostly to defaults, but doesn't 460 * affect the EEPROM. After the reset cycle, we pause briefly 461 * for the chip to recover. 462 * 463 * XXX how long are we really supposed to delay? --thorpej 464 */ 465 SMC_SELECT_BANK(sc, 0); 466 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 467 delay(100); 468 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 469 delay(200); 470 471 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 472 473 /* Set the Ethernet address. */ 474 SMC_SELECT_BANK(sc, 1); 475 enaddr = (u_int8_t *)LLADDR(ifp->if_sadl); 476 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 477 tmp = enaddr[i + 1] << 8 | enaddr[i]; 478 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 479 } 480 481 /* 482 * Set the control register to automatically release successfully 483 * transmitted packets (making the best use of our limited memory) 484 * and enable the EPH interrupt on certain TX errors. 485 */ 486 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 487 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 488 489 /* 490 * Reset the MMU and wait for it to be un-busy. 491 */ 492 SMC_SELECT_BANK(sc, 2); 493 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 494 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 495 /* XXX bound this loop! */ ; 496 497 /* 498 * Disable all interrupts. 499 */ 500 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 501 502 /* 503 * Set current media. 504 */ 505 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 506 507 /* 508 * Set the receive filter. We want receive enable and auto 509 * strip of CRC from received packet. If we are in promisc. mode, 510 * then set that bit as well. 511 * 512 * XXX Initialize multicast filter. For now, we just accept 513 * XXX all multicast. 514 */ 515 SMC_SELECT_BANK(sc, 0); 516 517 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 518 if (ifp->if_flags & IFF_PROMISC) 519 tmp |= RCR_PROMISC; 520 521 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 522 523 /* 524 * Set transmitter control to "enabled". 525 */ 526 tmp = TCR_ENABLE; 527 528 #ifndef SMC91CXX_SW_PAD 529 /* 530 * Enable hardware padding of transmitted packets. 531 * XXX doesn't work? 532 */ 533 tmp |= TCR_PAD_ENABLE; 534 #endif 535 536 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 537 538 /* 539 * Now, enable interrupts. 540 */ 541 SMC_SELECT_BANK(sc, 2); 542 543 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 544 IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT); 545 546 /* Interface is now running, with no output active. */ 547 ifp->if_flags |= IFF_RUNNING; 548 ifp->if_flags &= ~IFF_OACTIVE; 549 550 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 551 /* Start the one second clock. */ 552 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 553 } 554 555 /* 556 * Attempt to start any pending transmission. 557 */ 558 smc91cxx_start(ifp); 559 560 splx(s); 561 } 562 563 /* 564 * Start output on an interface. 565 * Must be called at splnet or interrupt level. 566 */ 567 void 568 smc91cxx_start(ifp) 569 struct ifnet *ifp; 570 { 571 struct smc91cxx_softc *sc = ifp->if_softc; 572 bus_space_tag_t bst = sc->sc_bst; 573 bus_space_handle_t bsh = sc->sc_bsh; 574 u_int len; 575 struct mbuf *m, *top; 576 u_int16_t length, npages; 577 u_int8_t packetno; 578 int timo, pad; 579 580 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 581 return; 582 583 again: 584 /* 585 * Peek at the next packet. 586 */ 587 if ((m = ifp->if_snd.ifq_head) == NULL) 588 return; 589 590 /* 591 * Compute the frame length and set pad to give an overall even 592 * number of bytes. Below, we assume that the packet length 593 * is even. 594 */ 595 for (len = 0, top = m; m != NULL; m = m->m_next) 596 len += m->m_len; 597 pad = (len & 1); 598 599 /* 600 * We drop packets that are too large. Perhaps we should 601 * truncate them instead? 602 */ 603 if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 604 printf("%s: large packet discarded\n", sc->sc_dev.dv_xname); 605 ifp->if_oerrors++; 606 IF_DEQUEUE(&ifp->if_snd, m); 607 m_freem(m); 608 goto readcheck; 609 } 610 611 #ifdef SMC91CXX_SW_PAD 612 /* 613 * Not using hardware padding; pad to ETHER_MIN_LEN. 614 */ 615 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 616 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 617 #endif 618 619 length = pad + len; 620 621 /* 622 * The MMU has a 256 byte page size. The MMU expects us to 623 * ask for "npages - 1". We include space for the status word, 624 * byte count, and control bytes in the allocation request. 625 */ 626 npages = (length + 6) >> 8; 627 628 /* 629 * Now allocate the memory. 630 */ 631 SMC_SELECT_BANK(sc, 2); 632 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 633 634 timo = MEMORY_WAIT_TIME; 635 do { 636 if (bus_space_read_1(bst, bsh, INTR_STAT_REG_B) & IM_ALLOC_INT) 637 break; 638 delay(1); 639 } while (--timo); 640 641 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 642 643 if (packetno & ARR_FAILED || timo == 0) { 644 /* 645 * No transmit memory is available. Record the number 646 * of requestd pages and enable the allocation completion 647 * interrupt. Set up the watchdog timer in case we miss 648 * the interrupt. Mark the interface as active so that 649 * no one else attempts to transmit while we're allocating 650 * memory. 651 */ 652 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 653 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | IM_ALLOC_INT); 654 655 ifp->if_timer = 5; 656 ifp->if_flags |= IFF_OACTIVE; 657 658 return; 659 } 660 661 /* 662 * We have a packet number - set the data window. 663 */ 664 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 665 666 /* 667 * Point to the beginning of the packet. 668 */ 669 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 670 671 /* 672 * Send the packet length (+6 for stats, length, and control bytes) 673 * and the status word (set to zeros). 674 */ 675 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 676 bus_space_write_1(bst, bsh, DATA_REG_B, (length + 6) & 0xff); 677 bus_space_write_1(bst, bsh, DATA_REG_B, ((length + 6) >> 8) & 0xff); 678 679 /* 680 * Get the packet from the kernel. This will include the Ethernet 681 * frame header, MAC address, etc. 682 */ 683 IF_DEQUEUE(&ifp->if_snd, m); 684 685 /* 686 * Push the packet out to the card. 687 */ 688 for (top = m; m != NULL; m = m->m_next) { 689 /* Words... */ 690 bus_space_write_multi_2(bst, bsh, DATA_REG_W, 691 mtod(m, u_int16_t *), m->m_len >> 1); 692 693 /* ...and the remaining byte, if any. */ 694 if (m->m_len & 1) 695 bus_space_write_1(bst, bsh, DATA_REG_B, 696 *(u_int8_t *)(mtod(m, u_int8_t *) + (m->m_len - 1))); 697 } 698 699 #ifdef SMC91CXX_SW_PAD 700 /* 701 * Push out padding. 702 */ 703 while (pad > 1) { 704 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 705 pad -= 2; 706 } 707 if (pad) 708 bus_space_write_1(bst, bsh, DATA_REG_B, 0); 709 #endif 710 711 /* 712 * Push out control byte and unused packet byte. The control byte 713 * is 0, meaning the packet is even lengthed and no special 714 * CRC handling is necessary. 715 */ 716 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 717 718 /* 719 * Enable transmit interrupts and let the chip go. Set a watchdog 720 * in case we miss the interrupt. 721 */ 722 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 723 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | 724 IM_TX_INT | IM_TX_EMPTY_INT); 725 726 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 727 728 ifp->if_timer = 5; 729 730 #if NBPFILTER > 0 731 /* Hand off a copy to the bpf. */ 732 if (ifp->if_bpf) 733 bpf_mtap(ifp->if_bpf, top); 734 #endif 735 736 ifp->if_opackets++; 737 m_freem(top); 738 739 readcheck: 740 /* 741 * Check for incoming pcakets. We don't want to overflow the small 742 * RX FIFO. If nothing has arrived, attempt to queue another 743 * transmit packet. 744 */ 745 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 746 goto again; 747 } 748 749 /* 750 * Interrupt service routine. 751 */ 752 int 753 smc91cxx_intr(arg) 754 void *arg; 755 { 756 struct smc91cxx_softc *sc = arg; 757 struct ifnet *ifp = &sc->sc_ec.ec_if; 758 bus_space_tag_t bst = sc->sc_bst; 759 bus_space_handle_t bsh = sc->sc_bsh; 760 u_int8_t mask, interrupts, status; 761 u_int16_t packetno, tx_status, card_stats; 762 763 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 764 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 765 return (0); 766 767 SMC_SELECT_BANK(sc, 2); 768 769 /* 770 * Obtain the current interrupt mask. 771 */ 772 mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 773 774 /* 775 * Get the set of interrupt which occurred and eliminate any 776 * which are not enabled. 777 */ 778 interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B); 779 status = interrupts & mask; 780 781 /* Ours? */ 782 if (status == 0) 783 return (0); 784 785 /* 786 * It's ours; disable all interrupts while we process them. 787 */ 788 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 789 790 /* 791 * Receive overrun interrupts. 792 */ 793 if (status & IM_RX_OVRN_INT) { 794 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_RX_OVRN_INT); 795 ifp->if_ierrors++; 796 } 797 798 /* 799 * Receive interrupts. 800 */ 801 if (status & IM_RCV_INT) { 802 #if 1 /* DIAGNOSTIC */ 803 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 804 if (packetno & FIFO_REMPTY) 805 printf("%s: receive interrupt on empty fifo\n", 806 sc->sc_dev.dv_xname); 807 else 808 #endif 809 smc91cxx_read(sc); 810 } 811 812 /* 813 * Memory allocation interrupts. 814 */ 815 if (status & IM_ALLOC_INT) { 816 /* Disable this interrupt. */ 817 mask &= ~IM_ALLOC_INT; 818 819 /* 820 * Release the just-allocated memory. We will reallocate 821 * it through the normal start logic. 822 */ 823 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 824 /* XXX bound this loop! */ ; 825 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 826 827 ifp->if_flags &= ~IFF_OACTIVE; 828 ifp->if_timer = 0; 829 } 830 831 /* 832 * Transmit complete interrupt. Handle transmission error messages. 833 * This will only be called on error condition because of AUTO RELEASE 834 * mode. 835 */ 836 if (status & IM_TX_INT) { 837 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_INT); 838 839 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 840 FIFO_TX_MASK; 841 842 /* 843 * Select this as the packet to read from. 844 */ 845 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 846 847 /* 848 * Position the pointer to the beginning of the packet. 849 */ 850 bus_space_write_2(bst, bsh, POINTER_REG_W, 851 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 852 853 /* 854 * Fetch the TX status word. This will be a copy of 855 * the EPH_STATUS_REG_W at the time of the transmission 856 * failure. 857 */ 858 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 859 860 if (tx_status & EPHSR_TX_SUC) 861 printf("%s: successful packet caused TX interrupt?!\n", 862 sc->sc_dev.dv_xname); 863 else 864 ifp->if_oerrors++; 865 866 if (tx_status & EPHSR_LATCOL) 867 ifp->if_collisions++; 868 869 /* 870 * Some of these errors disable the transmitter; reenable it. 871 */ 872 SMC_SELECT_BANK(sc, 0); 873 #ifdef SMC91CXX_SW_PAD 874 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 875 #else 876 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 877 TCR_ENABLE | TCR_PAD_ENABLE); 878 #endif 879 880 /* 881 * Kill the failed packet and wait for the MMU to unbusy. 882 */ 883 SMC_SELECT_BANK(sc, 2); 884 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 885 /* XXX bound this loop! */ ; 886 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 887 888 ifp->if_timer = 0; 889 } 890 891 /* 892 * Transmit underrun interrupts. We use this opportunity to 893 * update transmit statistics from the card. 894 */ 895 if (status & IM_TX_EMPTY_INT) { 896 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 897 898 /* Disable this interrupt. */ 899 mask &= ~IM_TX_EMPTY_INT; 900 901 SMC_SELECT_BANK(sc, 0); 902 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 903 904 /* Single collisions. */ 905 ifp->if_collisions += card_stats & ECR_COLN_MASK; 906 907 /* Multiple collisions. */ 908 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 909 910 SMC_SELECT_BANK(sc, 2); 911 912 ifp->if_timer = 0; 913 } 914 915 /* 916 * Other errors. Reset the interface. 917 */ 918 if (status & IM_EPH_INT) { 919 smc91cxx_stop(sc); 920 smc91cxx_init(sc); 921 } 922 923 /* 924 * Attempt to queue more packets for transmission. 925 */ 926 smc91cxx_start(ifp); 927 928 /* 929 * Reenable the interrupts we wish to receive now that processing 930 * is complete. 931 */ 932 mask |= bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 933 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 934 935 #if NRND > 0 936 if (status) 937 rnd_add_uint32(&sc->rnd_source, status); 938 #endif 939 940 return (1); 941 } 942 943 /* 944 * Read a packet from the card and pass it up to the kernel. 945 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 946 */ 947 void 948 smc91cxx_read(sc) 949 struct smc91cxx_softc *sc; 950 { 951 struct ifnet *ifp = &sc->sc_ec.ec_if; 952 bus_space_tag_t bst = sc->sc_bst; 953 bus_space_handle_t bsh = sc->sc_bsh; 954 struct ether_header *eh; 955 struct mbuf *m; 956 u_int16_t status, packetno, packetlen; 957 u_int8_t *data; 958 959 again: 960 /* 961 * Set data pointer to the beginning of the packet. Since 962 * PTR_RCV is set, the packet number will be found automatically 963 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 964 */ 965 bus_space_write_2(bst, bsh, POINTER_REG_W, 966 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 967 968 /* 969 * First two words are status and packet length. 970 */ 971 status = bus_space_read_2(bst, bsh, DATA_REG_W); 972 packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); 973 974 /* 975 * The packet length includes 3 extra words: status, length, 976 * and an extra word that includes the control byte. 977 */ 978 packetlen -= 6; 979 980 /* 981 * Account for receive errors and discard. 982 */ 983 if (status & RS_ERRORS) { 984 ifp->if_ierrors++; 985 goto out; 986 } 987 988 /* 989 * Adjust for odd-length packet. 990 */ 991 if (status & RS_ODDFRAME) 992 packetlen++; 993 994 /* 995 * Allocate a header mbuf. 996 */ 997 MGETHDR(m, M_DONTWAIT, MT_DATA); 998 if (m == NULL) 999 goto out; 1000 1001 m->m_pkthdr.rcvif = ifp; 1002 m->m_pkthdr.len = m->m_len = packetlen; 1003 1004 /* 1005 * Always put the packet in a cluster. 1006 * XXX should chain small mbufs if less than threshold. 1007 */ 1008 MCLGET(m, M_DONTWAIT); 1009 if ((m->m_flags & M_EXT) == 0) { 1010 m_freem(m); 1011 ifp->if_ierrors++; 1012 printf("%s: can't allocate cluster for incoming packet\n", 1013 sc->sc_dev.dv_xname); 1014 goto out; 1015 } 1016 1017 /* 1018 * Pull the packet off the interface. 1019 */ 1020 eh = mtod(m, struct ether_header *); 1021 data = mtod(m, u_int8_t *); 1022 bus_space_read_multi_2(bst, bsh, DATA_REG_W, (u_int16_t *)data, 1023 packetlen >> 1); 1024 if (packetlen & 1) { 1025 data += packetlen & ~1; 1026 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1027 } 1028 1029 ifp->if_ipackets++; 1030 1031 /* 1032 * Make sure to behave as IFF_SIMPLEX in all cases. 1033 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1034 * loops back packets to itself on promiscuous mode. 1035 * (should be ensured by chipset configuration) 1036 */ 1037 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1038 /* 1039 * Drop packet looped back from myself. 1040 */ 1041 if (ether_cmp(eh->ether_shost, LLADDR(ifp->if_sadl)) == 0) { 1042 m_freem(m); 1043 goto out; 1044 } 1045 } 1046 1047 #if NBPFILTER > 0 1048 /* 1049 * Hand the packet off to bpf listeners. 1050 */ 1051 if (ifp->if_bpf) 1052 bpf_mtap(ifp->if_bpf, m); 1053 #endif 1054 1055 /* 1056 * If this is unicast and not for me, drop it. 1057 */ 1058 if ((eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 1059 ether_cmp(eh->ether_dhost, LLADDR(ifp->if_sadl)) != 0) { 1060 m_freem(m); 1061 goto out; 1062 } 1063 1064 m->m_pkthdr.len = m->m_len = packetlen; 1065 (*ifp->if_input)(ifp, m); 1066 1067 out: 1068 /* 1069 * Tell the card to free the memory occupied by this packet. 1070 */ 1071 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1072 /* XXX bound this loop! */ ; 1073 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1074 1075 /* 1076 * Check for another packet. 1077 */ 1078 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1079 if (packetno & FIFO_REMPTY) 1080 return; 1081 goto again; 1082 } 1083 1084 /* 1085 * Process an ioctl request. 1086 */ 1087 int 1088 smc91cxx_ioctl(ifp, cmd, data) 1089 struct ifnet *ifp; 1090 u_long cmd; 1091 caddr_t data; 1092 { 1093 struct smc91cxx_softc *sc = ifp->if_softc; 1094 struct ifaddr *ifa = (struct ifaddr *)data; 1095 struct ifreq *ifr = (struct ifreq *)data; 1096 int s, error = 0; 1097 1098 s = splnet(); 1099 1100 switch (cmd) { 1101 case SIOCSIFADDR: 1102 if ((error = smc91cxx_enable(sc)) != 0) 1103 break; 1104 ifp->if_flags |= IFF_UP; 1105 switch (ifa->ifa_addr->sa_family) { 1106 #ifdef INET 1107 case AF_INET: 1108 smc91cxx_init(sc); 1109 arp_ifinit(ifp, ifa); 1110 break; 1111 #endif 1112 #ifdef NS 1113 case AF_NS: 1114 { 1115 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1116 1117 if (ns_nullhost(*ina)) 1118 ina->x_host = 1119 *(union ns_host *)LLADDR(ifp->if_sadl); 1120 else { 1121 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1122 ETHER_ADDR_LEN); 1123 } 1124 1125 /* 1126 * Set new address. Reset, because the receiver 1127 * has to be stopped before we can set the new 1128 * MAC address. 1129 */ 1130 smc91cxx_reset(sc); 1131 break; 1132 } 1133 #endif 1134 default: 1135 smc91cxx_init(sc); 1136 break; 1137 } 1138 break; 1139 1140 #if defined(CCITT) && defined(LLC) 1141 case SIOCSIFCONF_X25: 1142 if ((error = smc91cxx_enable(sc)) != 0) 1143 break; 1144 ifp->if_flags |= IFF_UP; 1145 ifa->ifa_rtrequest = cons_rtrequest; /* XXX */ 1146 error = x25_llcglue(PRC_IFUP, ifa->ifa_addr); 1147 if (error == 0) 1148 smc91cxx_init(sc); 1149 break; 1150 #endif 1151 1152 case SIOCSIFFLAGS: 1153 if ((ifp->if_flags & IFF_UP) == 0 && 1154 (ifp->if_flags & IFF_RUNNING) != 0) { 1155 /* 1156 * If interface is marked down and it is running, 1157 * stop it. 1158 */ 1159 smc91cxx_stop(sc); 1160 ifp->if_flags &= ~IFF_RUNNING; 1161 smc91cxx_disable(sc); 1162 } else if ((ifp->if_flags & IFF_UP) != 0 && 1163 (ifp->if_flags & IFF_RUNNING) == 0) { 1164 /* 1165 * If interface is marked up and it is stopped, 1166 * start it. 1167 */ 1168 if ((error = smc91cxx_enable(sc)) != 0) 1169 break; 1170 smc91cxx_init(sc); 1171 } else if ((ifp->if_flags & IFF_UP) != 0) { 1172 /* 1173 * Reset the interface to pick up changes in any 1174 * other flags that affect hardware registers. 1175 */ 1176 smc91cxx_reset(sc); 1177 } 1178 break; 1179 1180 case SIOCADDMULTI: 1181 case SIOCDELMULTI: 1182 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1183 error = EIO; 1184 break; 1185 } 1186 1187 error = (cmd == SIOCADDMULTI) ? 1188 ether_addmulti(ifr, &sc->sc_ec) : 1189 ether_delmulti(ifr, &sc->sc_ec); 1190 if (error == ENETRESET) { 1191 /* 1192 * Multicast list has changed; set the hardware 1193 * filter accordingly. 1194 */ 1195 smc91cxx_reset(sc); 1196 error = 0; 1197 } 1198 break; 1199 1200 case SIOCGIFMEDIA: 1201 case SIOCSIFMEDIA: 1202 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1203 break; 1204 1205 default: 1206 error = EINVAL; 1207 break; 1208 } 1209 1210 splx(s); 1211 return (error); 1212 } 1213 1214 /* 1215 * Reset the interface. 1216 */ 1217 void 1218 smc91cxx_reset(sc) 1219 struct smc91cxx_softc *sc; 1220 { 1221 int s; 1222 1223 s = splnet(); 1224 smc91cxx_stop(sc); 1225 smc91cxx_init(sc); 1226 splx(s); 1227 } 1228 1229 /* 1230 * Watchdog timer. 1231 */ 1232 void 1233 smc91cxx_watchdog(ifp) 1234 struct ifnet *ifp; 1235 { 1236 struct smc91cxx_softc *sc = ifp->if_softc; 1237 1238 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1239 ifp->if_oerrors++; 1240 smc91cxx_reset(sc); 1241 } 1242 1243 /* 1244 * Stop output on the interface. 1245 */ 1246 void 1247 smc91cxx_stop(sc) 1248 struct smc91cxx_softc *sc; 1249 { 1250 bus_space_tag_t bst = sc->sc_bst; 1251 bus_space_handle_t bsh = sc->sc_bsh; 1252 1253 /* 1254 * Clear interrupt mask; disable all interrupts. 1255 */ 1256 SMC_SELECT_BANK(sc, 2); 1257 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 1258 1259 /* 1260 * Disable transmitter and receiver. 1261 */ 1262 SMC_SELECT_BANK(sc, 0); 1263 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1264 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1265 1266 /* 1267 * Cancel watchdog timer. 1268 */ 1269 sc->sc_ec.ec_if.if_timer = 0; 1270 } 1271 1272 /* 1273 * Enable power on the interface. 1274 */ 1275 int 1276 smc91cxx_enable(sc) 1277 struct smc91cxx_softc *sc; 1278 { 1279 1280 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1281 if ((*sc->sc_enable)(sc) != 0) { 1282 printf("%s: device enable failed\n", 1283 sc->sc_dev.dv_xname); 1284 return (EIO); 1285 } 1286 } 1287 1288 sc->sc_flags |= SMC_FLAGS_ENABLED; 1289 return (0); 1290 } 1291 1292 /* 1293 * Disable power on the interface. 1294 */ 1295 void 1296 smc91cxx_disable(sc) 1297 struct smc91cxx_softc *sc; 1298 { 1299 1300 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1301 (*sc->sc_disable)(sc); 1302 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1303 } 1304 } 1305 1306 int 1307 smc91cxx_activate(self, act) 1308 struct device *self; 1309 enum devact act; 1310 { 1311 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1312 int rv = 0, s; 1313 1314 s = splnet(); 1315 switch (act) { 1316 case DVACT_ACTIVATE: 1317 rv = EOPNOTSUPP; 1318 break; 1319 1320 case DVACT_DEACTIVATE: 1321 if_deactivate(&sc->sc_ec.ec_if); 1322 break; 1323 } 1324 splx(s); 1325 return (rv); 1326 } 1327 1328 int 1329 smc91cxx_detach(self, flags) 1330 struct device *self; 1331 int flags; 1332 { 1333 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1334 struct ifnet *ifp = &sc->sc_ec.ec_if; 1335 1336 /* Succeed now if there's no work to do. */ 1337 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1338 return (0); 1339 1340 1341 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1342 smc91cxx_disable(sc); 1343 1344 /* smc91cxx_attach() never fails */ 1345 1346 /* Delete all media. */ 1347 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1348 1349 #if NRND > 0 1350 rnd_detach_source(&sc->rnd_source); 1351 #endif 1352 #if NBPFILTER > 0 1353 bpfdetach(ifp); 1354 #endif 1355 ether_ifdetach(ifp); 1356 if_detach(ifp); 1357 1358 return (0); 1359 } 1360 1361 u_int32_t 1362 smc91cxx_mii_bitbang_read(self) 1363 struct device *self; 1364 { 1365 struct smc91cxx_softc *sc = (void *) self; 1366 1367 /* We're already in bank 3. */ 1368 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1369 } 1370 1371 void 1372 smc91cxx_mii_bitbang_write(self, val) 1373 struct device *self; 1374 u_int32_t val; 1375 { 1376 struct smc91cxx_softc *sc = (void *) self; 1377 1378 /* We're already in bank 3. */ 1379 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1380 } 1381 1382 int 1383 smc91cxx_mii_readreg(self, phy, reg) 1384 struct device *self; 1385 int phy, reg; 1386 { 1387 struct smc91cxx_softc *sc = (void *) self; 1388 int val; 1389 1390 SMC_SELECT_BANK(sc, 3); 1391 1392 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1393 1394 SMC_SELECT_BANK(sc, 2); 1395 1396 return (val); 1397 } 1398 1399 void 1400 smc91cxx_mii_writereg(self, phy, reg, val) 1401 struct device *self; 1402 int phy, reg, val; 1403 { 1404 struct smc91cxx_softc *sc = (void *) self; 1405 1406 SMC_SELECT_BANK(sc, 3); 1407 1408 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1409 1410 SMC_SELECT_BANK(sc, 2); 1411 } 1412 1413 void 1414 smc91cxx_statchg(self) 1415 struct device *self; 1416 { 1417 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1418 bus_space_tag_t bst = sc->sc_bst; 1419 bus_space_handle_t bsh = sc->sc_bsh; 1420 int mctl; 1421 1422 SMC_SELECT_BANK(sc, 0); 1423 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1424 if (sc->sc_mii.mii_media_active & IFM_FDX) 1425 mctl |= TCR_SWFDUP; 1426 else 1427 mctl &= ~TCR_SWFDUP; 1428 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1429 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1430 } 1431 1432 /* 1433 * One second timer, used to tick the MII. 1434 */ 1435 void 1436 smc91cxx_tick(arg) 1437 void *arg; 1438 { 1439 struct smc91cxx_softc *sc = arg; 1440 int s; 1441 1442 #ifdef DIAGNOSTIC 1443 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1444 panic("smc91cxx_tick"); 1445 #endif 1446 1447 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1448 return; 1449 1450 s = splnet(); 1451 mii_tick(&sc->sc_mii); 1452 splx(s); 1453 1454 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1455 } 1456 1457
Indexes created Wed Sep 24 05:09:52 GMT 2025