smc91cxx.c revision 1.47
1 /* $NetBSD: smc91cxx.c,v 1.47 2004/08/08 16:20:43 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Gardner Buchanan <gbuchanan (at) shl.com> 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Gardner Buchanan. 55 * 4. The name of Gardner Buchanan may not be used to endorse or promote 56 * products derived from this software without specific prior written 57 * permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 71 */ 72 73 /* 74 * Core driver for the SMC 91Cxx family of Ethernet chips. 75 * 76 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 77 * written for NetBSD/amiga by Michael Hitch. 78 */ 79 80 #include <sys/cdefs.h> 81 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.47 2004/08/08 16:20:43 mycroft Exp $"); 82 83 #include "opt_inet.h" 84 #include "opt_ccitt.h" 85 #include "opt_llc.h" 86 #include "opt_ns.h" 87 #include "bpfilter.h" 88 #include "rnd.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/mbuf.h> 93 #include <sys/syslog.h> 94 #include <sys/socket.h> 95 #include <sys/device.h> 96 #include <sys/kernel.h> 97 #include <sys/malloc.h> 98 #include <sys/ioctl.h> 99 #include <sys/errno.h> 100 #if NRND > 0 101 #include <sys/rnd.h> 102 #endif 103 104 #include <machine/bus.h> 105 #include <machine/intr.h> 106 107 #include <net/if.h> 108 #include <net/if_dl.h> 109 #include <net/if_ether.h> 110 #include <net/if_media.h> 111 112 #ifdef INET 113 #include <netinet/in.h> 114 #include <netinet/if_inarp.h> 115 #include <netinet/in_systm.h> 116 #include <netinet/in_var.h> 117 #include <netinet/ip.h> 118 #endif 119 120 #ifdef NS 121 #include <netns/ns.h> 122 #include <netns/ns_if.h> 123 #endif 124 125 #if defined(CCITT) && defined(LLC) 126 #include <sys/socketvar.h> 127 #include <netccitt/x25.h> 128 #include <netccitt/pk.h> 129 #include <netccitt/pk_var.h> 130 #include <netccitt/pk_extern.h> 131 #endif 132 133 #if NBPFILTER > 0 134 #include <net/bpf.h> 135 #include <net/bpfdesc.h> 136 #endif 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 #include <dev/mii/mii_bitbang.h> 141 142 #include <dev/ic/smc91cxxreg.h> 143 #include <dev/ic/smc91cxxvar.h> 144 145 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 146 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 147 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 148 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 149 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 150 151 #define bus_space_write_stream_4 bus_space_write_4 152 #define bus_space_read_stream_4 bus_space_read_4 153 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 154 155 /* XXX Hardware padding doesn't work yet(?) */ 156 #define SMC91CXX_SW_PAD 157 158 const char *smc91cxx_idstrs[] = { 159 NULL, /* 0 */ 160 NULL, /* 1 */ 161 NULL, /* 2 */ 162 "SMC91C90/91C92", /* 3 */ 163 "SMC91C94/91C96", /* 4 */ 164 "SMC91C95", /* 5 */ 165 NULL, /* 6 */ 166 "SMC91C100", /* 7 */ 167 "SMC91C100FD", /* 8 */ 168 "SMC91C111", /* 9 */ 169 NULL, /* 10 */ 170 NULL, /* 11 */ 171 NULL, /* 12 */ 172 NULL, /* 13 */ 173 NULL, /* 14 */ 174 NULL, /* 15 */ 175 }; 176 177 /* Supported media types. */ 178 const int smc91cxx_media[] = { 179 IFM_ETHER|IFM_10_T, 180 IFM_ETHER|IFM_10_5, 181 }; 182 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 183 184 /* 185 * MII bit-bang glue. 186 */ 187 u_int32_t smc91cxx_mii_bitbang_read __P((struct device *)); 188 void smc91cxx_mii_bitbang_write __P((struct device *, u_int32_t)); 189 190 const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 191 smc91cxx_mii_bitbang_read, 192 smc91cxx_mii_bitbang_write, 193 { 194 MR_MDO, /* MII_BIT_MDO */ 195 MR_MDI, /* MII_BIT_MDI */ 196 MR_MCLK, /* MII_BIT_MDC */ 197 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 198 0, /* MII_BIT_DIR_PHY_HOST */ 199 } 200 }; 201 202 /* MII callbacks */ 203 int smc91cxx_mii_readreg __P((struct device *, int, int)); 204 void smc91cxx_mii_writereg __P((struct device *, int, int, int)); 205 void smc91cxx_statchg __P((struct device *)); 206 void smc91cxx_tick __P((void *)); 207 208 int smc91cxx_mediachange __P((struct ifnet *)); 209 void smc91cxx_mediastatus __P((struct ifnet *, struct ifmediareq *)); 210 211 int smc91cxx_set_media __P((struct smc91cxx_softc *, int)); 212 213 void smc91cxx_init __P((struct smc91cxx_softc *)); 214 void smc91cxx_read __P((struct smc91cxx_softc *)); 215 void smc91cxx_reset __P((struct smc91cxx_softc *)); 216 void smc91cxx_start __P((struct ifnet *)); 217 void smc91cxx_copy_tx_frame __P((struct smc91cxx_softc *, struct mbuf *)); 218 void smc91cxx_resume __P((struct smc91cxx_softc *)); 219 void smc91cxx_stop __P((struct smc91cxx_softc *)); 220 void smc91cxx_watchdog __P((struct ifnet *)); 221 int smc91cxx_ioctl __P((struct ifnet *, u_long, caddr_t)); 222 223 static __inline int ether_cmp __P((void *, void *)); 224 static __inline int 225 ether_cmp(va, vb) 226 void *va, *vb; 227 { 228 u_int8_t *a = va; 229 u_int8_t *b = vb; 230 231 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 232 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 233 } 234 235 void 236 smc91cxx_attach(sc, myea) 237 struct smc91cxx_softc *sc; 238 u_int8_t *myea; 239 { 240 struct ifnet *ifp = &sc->sc_ec.ec_if; 241 bus_space_tag_t bst = sc->sc_bst; 242 bus_space_handle_t bsh = sc->sc_bsh; 243 struct ifmedia *ifm = &sc->sc_mii.mii_media; 244 const char *idstr; 245 u_int32_t miicapabilities; 246 u_int16_t tmp; 247 u_int8_t enaddr[ETHER_ADDR_LEN]; 248 int i, aui, mult, scale, memsize; 249 char pbuf[9]; 250 251 tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W); 252 /* check magic number */ 253 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 254 aprint_error("%s: failed to detect chip, bsr=%04x\n", 255 sc->sc_dev.dv_xname, tmp); 256 return; 257 } 258 259 /* Make sure the chip is stopped. */ 260 smc91cxx_stop(sc); 261 262 SMC_SELECT_BANK(sc, 3); 263 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 264 sc->sc_chipid = RR_ID(tmp); 265 idstr = smc91cxx_idstrs[sc->sc_chipid]; 266 267 aprint_normal("%s: ", sc->sc_dev.dv_xname); 268 if (idstr != NULL) 269 aprint_normal("%s, ", idstr); 270 else 271 aprint_normal("unknown chip id %d, ", sc->sc_chipid); 272 aprint_normal("revision %d, ", RR_REV(tmp)); 273 274 SMC_SELECT_BANK(sc, 0); 275 switch (sc->sc_chipid) { 276 default: 277 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 278 scale = MIR_SCALE_91C9x; 279 break; 280 281 case CHIP_91C111: 282 mult = MIR_MULT_91C111; 283 scale = MIR_SCALE_91C111; 284 } 285 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 286 if (memsize == 255) memsize++; 287 memsize *= scale * mult; 288 289 format_bytes(pbuf, sizeof(pbuf), memsize); 290 aprint_normal("buffer size: %s\n", pbuf); 291 292 /* Read the station address from the chip. */ 293 SMC_SELECT_BANK(sc, 1); 294 if (myea == NULL) { 295 myea = enaddr; 296 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 297 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 298 myea[i + 1] = (tmp >> 8) & 0xff; 299 myea[i] = tmp & 0xff; 300 } 301 } 302 aprint_normal("%s: MAC address %s, ", sc->sc_dev.dv_xname, 303 ether_sprintf(myea)); 304 305 /* Initialize the ifnet structure. */ 306 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 307 ifp->if_softc = sc; 308 ifp->if_start = smc91cxx_start; 309 ifp->if_ioctl = smc91cxx_ioctl; 310 ifp->if_watchdog = smc91cxx_watchdog; 311 ifp->if_flags = 312 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 313 IFQ_SET_READY(&ifp->if_snd); 314 315 /* Attach the interface. */ 316 if_attach(ifp); 317 ether_ifattach(ifp, myea); 318 319 /* 320 * Initialize our media structures and MII info. We will 321 * probe the MII if we are on the SMC91Cxx 322 */ 323 sc->sc_mii.mii_ifp = ifp; 324 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 325 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 326 sc->sc_mii.mii_statchg = smc91cxx_statchg; 327 ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, smc91cxx_mediastatus); 328 329 SMC_SELECT_BANK(sc, 1); 330 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 331 332 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 333 switch (sc->sc_chipid) { 334 case CHIP_91100: 335 /* 336 * The 91100 does not have full-duplex capabilities, 337 * even if the PHY does. 338 */ 339 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 340 case CHIP_91100FD: 341 case CHIP_91C111: 342 if (tmp & CR_MII_SELECT) { 343 aprint_normal("default media MII"); 344 if (sc->sc_chipid == CHIP_91C111) { 345 aprint_normal(" (%s PHY)\n", (tmp & CR_AUI_SELECT) ? 346 "external" : "internal"); 347 sc->sc_internal_phy = !(tmp & CR_AUI_SELECT); 348 } else 349 aprint_normal("\n"); 350 mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, 351 MII_PHY_ANY, MII_OFFSET_ANY, 0); 352 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 353 ifmedia_add(&sc->sc_mii.mii_media, 354 IFM_ETHER|IFM_NONE, 0, NULL); 355 ifmedia_set(&sc->sc_mii.mii_media, 356 IFM_ETHER|IFM_NONE); 357 } else { 358 ifmedia_set(&sc->sc_mii.mii_media, 359 IFM_ETHER|IFM_AUTO); 360 } 361 sc->sc_flags |= SMC_FLAGS_HAS_MII; 362 break; 363 } else 364 if (sc->sc_chipid == CHIP_91C111) { 365 /* 366 * XXX: Should bring it out of low-power mode 367 */ 368 aprint_normal("EPH interface in low power mode\n"); 369 sc->sc_internal_phy = 0; 370 return; 371 } 372 /*FALLTHROUGH*/ 373 default: 374 aprint_normal("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ? 375 "AUI" : "UTP"); 376 for (i = 0; i < NSMC91CxxMEDIA; i++) 377 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 378 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 379 break; 380 } 381 382 #if NRND > 0 383 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 384 RND_TYPE_NET, 0); 385 #endif 386 387 /* The attach is successful. */ 388 sc->sc_flags |= SMC_FLAGS_ATTACHED; 389 } 390 391 /* 392 * Change media according to request. 393 */ 394 int 395 smc91cxx_mediachange(ifp) 396 struct ifnet *ifp; 397 { 398 struct smc91cxx_softc *sc = ifp->if_softc; 399 400 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 401 } 402 403 int 404 smc91cxx_set_media(sc, media) 405 struct smc91cxx_softc *sc; 406 int media; 407 { 408 bus_space_tag_t bst = sc->sc_bst; 409 bus_space_handle_t bsh = sc->sc_bsh; 410 u_int16_t tmp; 411 412 /* 413 * If the interface is not currently powered on, just return. 414 * When it is enabled later, smc91cxx_init() will properly set 415 * up the media for us. 416 */ 417 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 418 return (0); 419 420 if (IFM_TYPE(media) != IFM_ETHER) 421 return (EINVAL); 422 423 if (sc->sc_flags & SMC_FLAGS_HAS_MII) 424 return (mii_mediachg(&sc->sc_mii)); 425 426 switch (IFM_SUBTYPE(media)) { 427 case IFM_10_T: 428 case IFM_10_5: 429 SMC_SELECT_BANK(sc, 1); 430 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 431 if (IFM_SUBTYPE(media) == IFM_10_5) 432 tmp |= CR_AUI_SELECT; 433 else 434 tmp &= ~CR_AUI_SELECT; 435 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 436 delay(20000); /* XXX is this needed? */ 437 break; 438 439 default: 440 return (EINVAL); 441 } 442 443 return (0); 444 } 445 446 /* 447 * Notify the world which media we're using. 448 */ 449 void 450 smc91cxx_mediastatus(ifp, ifmr) 451 struct ifnet *ifp; 452 struct ifmediareq *ifmr; 453 { 454 struct smc91cxx_softc *sc = ifp->if_softc; 455 bus_space_tag_t bst = sc->sc_bst; 456 bus_space_handle_t bsh = sc->sc_bsh; 457 u_int16_t tmp; 458 459 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 460 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 461 ifmr->ifm_status = 0; 462 return; 463 } 464 465 /* 466 * If we have MII, go ask the PHY what's going on. 467 */ 468 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 469 mii_pollstat(&sc->sc_mii); 470 ifmr->ifm_active = sc->sc_mii.mii_media_active; 471 ifmr->ifm_status = sc->sc_mii.mii_media_status; 472 return; 473 } 474 475 SMC_SELECT_BANK(sc, 1); 476 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 477 ifmr->ifm_active = 478 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 479 } 480 481 /* 482 * Reset and initialize the chip. 483 */ 484 void 485 smc91cxx_init(sc) 486 struct smc91cxx_softc *sc; 487 { 488 struct ifnet *ifp = &sc->sc_ec.ec_if; 489 bus_space_tag_t bst = sc->sc_bst; 490 bus_space_handle_t bsh = sc->sc_bsh; 491 u_int16_t tmp; 492 u_int8_t *enaddr; 493 int s, i; 494 495 s = splnet(); 496 497 /* 498 * This resets the registers mostly to defaults, but doesn't 499 * affect the EEPROM. After the reset cycle, we pause briefly 500 * for the chip to recover. 501 * 502 * XXX how long are we really supposed to delay? --thorpej 503 */ 504 SMC_SELECT_BANK(sc, 0); 505 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 506 delay(100); 507 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 508 delay(200); 509 510 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 511 512 /* Set the Ethernet address. */ 513 SMC_SELECT_BANK(sc, 1); 514 enaddr = (u_int8_t *)LLADDR(ifp->if_sadl); 515 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 516 tmp = enaddr[i + 1] << 8 | enaddr[i]; 517 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 518 } 519 520 /* 521 * Set the control register to automatically release successfully 522 * transmitted packets (making the best use of our limited memory) 523 * and enable the EPH interrupt on certain TX errors. 524 */ 525 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 526 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 527 528 /* 529 * Reset the MMU and wait for it to be un-busy. 530 */ 531 SMC_SELECT_BANK(sc, 2); 532 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 533 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 534 /* XXX bound this loop! */ ; 535 536 /* 537 * Disable all interrupts. 538 */ 539 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 540 541 /* 542 * On the 91c111, enable auto-negotiation, and set the LED 543 * status pins to something sane. 544 * XXX: Should be some way for MD code to decide the latter. 545 */ 546 SMC_SELECT_BANK(sc, 0); 547 if (sc->sc_chipid == CHIP_91C111) { 548 bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W, 549 RPC_ANEG | 550 (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) | 551 (RPC_LS_TXRX << RPC_LSB_SHIFT)); 552 } 553 554 /* 555 * Set current media. 556 */ 557 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 558 559 /* 560 * Set the receive filter. We want receive enable and auto 561 * strip of CRC from received packet. If we are in promisc. mode, 562 * then set that bit as well. 563 * 564 * XXX Initialize multicast filter. For now, we just accept 565 * XXX all multicast. 566 */ 567 SMC_SELECT_BANK(sc, 0); 568 569 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 570 if (ifp->if_flags & IFF_PROMISC) 571 tmp |= RCR_PROMISC; 572 573 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 574 575 /* 576 * Set transmitter control to "enabled". 577 */ 578 tmp = TCR_ENABLE; 579 580 #ifndef SMC91CXX_SW_PAD 581 /* 582 * Enable hardware padding of transmitted packets. 583 * XXX doesn't work? 584 */ 585 tmp |= TCR_PAD_ENABLE; 586 #endif 587 588 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 589 590 /* 591 * Now, enable interrupts. 592 */ 593 SMC_SELECT_BANK(sc, 2); 594 595 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) { 596 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 597 IM_EPH_INT | IM_RX_OVRN_INT | 598 IM_RCV_INT | IM_TX_INT | IM_MD_INT); 599 } else { 600 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 601 IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT); 602 } 603 604 /* Interface is now running, with no output active. */ 605 ifp->if_flags |= IFF_RUNNING; 606 ifp->if_flags &= ~IFF_OACTIVE; 607 608 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 609 /* Start the one second clock. */ 610 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 611 } 612 613 /* 614 * Attempt to start any pending transmission. 615 */ 616 smc91cxx_start(ifp); 617 618 splx(s); 619 } 620 621 /* 622 * Start output on an interface. 623 * Must be called at splnet or interrupt level. 624 */ 625 void 626 smc91cxx_start(ifp) 627 struct ifnet *ifp; 628 { 629 struct smc91cxx_softc *sc = ifp->if_softc; 630 bus_space_tag_t bst = sc->sc_bst; 631 bus_space_handle_t bsh = sc->sc_bsh; 632 u_int len; 633 struct mbuf *m; 634 u_int16_t length, npages; 635 u_int8_t packetno; 636 int timo, pad; 637 638 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 639 return; 640 641 again: 642 /* 643 * Peek at the next packet. 644 */ 645 IFQ_POLL(&ifp->if_snd, m); 646 if (m == NULL) 647 return; 648 649 /* 650 * Compute the frame length and set pad to give an overall even 651 * number of bytes. Below, we assume that the packet length 652 * is even. 653 */ 654 for (len = 0; m != NULL; m = m->m_next) 655 len += m->m_len; 656 pad = (len & 1); 657 658 /* 659 * We drop packets that are too large. Perhaps we should 660 * truncate them instead? 661 */ 662 if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 663 printf("%s: large packet discarded\n", sc->sc_dev.dv_xname); 664 ifp->if_oerrors++; 665 IFQ_DEQUEUE(&ifp->if_snd, m); 666 m_freem(m); 667 goto readcheck; 668 } 669 670 #ifdef SMC91CXX_SW_PAD 671 /* 672 * Not using hardware padding; pad to ETHER_MIN_LEN. 673 */ 674 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 675 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 676 #endif 677 678 length = pad + len; 679 680 /* 681 * The MMU has a 256 byte page size. The MMU expects us to 682 * ask for "npages - 1". We include space for the status word, 683 * byte count, and control bytes in the allocation request. 684 */ 685 npages = (length + 6) >> 8; 686 687 /* 688 * Now allocate the memory. 689 */ 690 SMC_SELECT_BANK(sc, 2); 691 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 692 693 timo = MEMORY_WAIT_TIME; 694 do { 695 if (bus_space_read_1(bst, bsh, INTR_STAT_REG_B) & IM_ALLOC_INT) 696 break; 697 delay(1); 698 } while (--timo); 699 700 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 701 702 if (packetno & ARR_FAILED || timo == 0) { 703 /* 704 * No transmit memory is available. Record the number 705 * of requestd pages and enable the allocation completion 706 * interrupt. Set up the watchdog timer in case we miss 707 * the interrupt. Mark the interface as active so that 708 * no one else attempts to transmit while we're allocating 709 * memory. 710 */ 711 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 712 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | IM_ALLOC_INT); 713 714 ifp->if_timer = 5; 715 ifp->if_flags |= IFF_OACTIVE; 716 717 return; 718 } 719 720 /* 721 * We have a packet number - set the data window. 722 */ 723 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 724 725 /* 726 * Point to the beginning of the packet. 727 */ 728 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 729 730 /* 731 * Send the packet length (+6 for stats, length, and control bytes) 732 * and the status word (set to zeros). 733 */ 734 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 735 bus_space_write_1(bst, bsh, DATA_REG_B, (length + 6) & 0xff); 736 bus_space_write_1(bst, bsh, DATA_REG_B, ((length + 6) >> 8) & 0xff); 737 738 /* 739 * Get the packet from the kernel. This will include the Ethernet 740 * frame header, MAC address, etc. 741 */ 742 IFQ_DEQUEUE(&ifp->if_snd, m); 743 744 /* 745 * Push the packet out to the card. 746 */ 747 smc91cxx_copy_tx_frame(sc, m); 748 749 #ifdef SMC91CXX_SW_PAD 750 /* 751 * Push out padding. 752 */ 753 while (pad > 1) { 754 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 755 pad -= 2; 756 } 757 if (pad) 758 bus_space_write_1(bst, bsh, DATA_REG_B, 0); 759 #endif 760 761 /* 762 * Push out control byte and unused packet byte. The control byte 763 * is 0, meaning the packet is even lengthed and no special 764 * CRC handling is necessary. 765 */ 766 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 767 768 /* 769 * Enable transmit interrupts and let the chip go. Set a watchdog 770 * in case we miss the interrupt. 771 */ 772 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 773 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | 774 IM_TX_INT | IM_TX_EMPTY_INT); 775 776 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 777 778 ifp->if_timer = 5; 779 780 #if NBPFILTER > 0 781 /* Hand off a copy to the bpf. */ 782 if (ifp->if_bpf) 783 bpf_mtap(ifp->if_bpf, m); 784 #endif 785 786 ifp->if_opackets++; 787 m_freem(m); 788 789 readcheck: 790 /* 791 * Check for incoming pcakets. We don't want to overflow the small 792 * RX FIFO. If nothing has arrived, attempt to queue another 793 * transmit packet. 794 */ 795 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 796 goto again; 797 } 798 799 /* 800 * Squirt a (possibly misaligned) mbuf to the device 801 */ 802 void 803 smc91cxx_copy_tx_frame(sc, m0) 804 struct smc91cxx_softc *sc; 805 struct mbuf *m0; 806 { 807 bus_space_tag_t bst = sc->sc_bst; 808 bus_space_handle_t bsh = sc->sc_bsh; 809 struct mbuf *m; 810 int len, leftover; 811 u_int16_t dbuf; 812 u_int8_t *p; 813 #ifdef DIAGNOSTIC 814 u_int8_t *lim; 815 #endif 816 817 /* start out with no leftover data */ 818 leftover = 0; 819 dbuf = 0; 820 821 /* Process the chain of mbufs */ 822 for (m = m0; m != NULL; m = m->m_next) { 823 /* 824 * Process all of the data in a single mbuf. 825 */ 826 p = mtod(m, u_int8_t *); 827 len = m->m_len; 828 #ifdef DIAGNOSTIC 829 lim = p + len; 830 #endif 831 832 while (len > 0) { 833 if (leftover) { 834 /* 835 * Data left over (from mbuf or realignment). 836 * Buffer the next byte, and write it and 837 * the leftover data out. 838 */ 839 dbuf |= *p++ << 8; 840 len--; 841 bus_space_write_2(bst, bsh, DATA_REG_W, dbuf); 842 leftover = 0; 843 } else if ((long) p & 1) { 844 /* 845 * Misaligned data. Buffer the next byte. 846 */ 847 dbuf = *p++; 848 len--; 849 leftover = 1; 850 } else { 851 /* 852 * Aligned data. This is the case we like. 853 * 854 * Write-region out as much as we can, then 855 * buffer the remaining byte (if any). 856 */ 857 leftover = len & 1; 858 len &= ~1; 859 bus_space_write_multi_stream_2(bst, bsh, 860 DATA_REG_W, (u_int16_t *)p, len >> 1); 861 p += len; 862 863 if (leftover) 864 dbuf = *p++; 865 len = 0; 866 } 867 } 868 if (len < 0) 869 panic("smc91cxx_copy_tx_frame: negative len"); 870 #ifdef DIAGNOSTIC 871 if (p != lim) 872 panic("smc91cxx_copy_tx_frame: p != lim"); 873 #endif 874 } 875 if (leftover) 876 bus_space_write_1(bst, bsh, DATA_REG_B, dbuf); 877 } 878 879 /* 880 * Interrupt service routine. 881 */ 882 int 883 smc91cxx_intr(arg) 884 void *arg; 885 { 886 struct smc91cxx_softc *sc = arg; 887 struct ifnet *ifp = &sc->sc_ec.ec_if; 888 bus_space_tag_t bst = sc->sc_bst; 889 bus_space_handle_t bsh = sc->sc_bsh; 890 u_int8_t mask, interrupts, status; 891 u_int16_t packetno, tx_status, card_stats; 892 893 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 894 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 895 return (0); 896 897 SMC_SELECT_BANK(sc, 2); 898 899 /* 900 * Obtain the current interrupt mask. 901 */ 902 mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 903 904 /* 905 * Get the set of interrupt which occurred and eliminate any 906 * which are not enabled. 907 */ 908 interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B); 909 status = interrupts & mask; 910 911 /* Ours? */ 912 if (status == 0) 913 return (0); 914 915 /* 916 * It's ours; disable all interrupts while we process them. 917 */ 918 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 919 920 /* 921 * Receive overrun interrupts. 922 */ 923 if (status & IM_RX_OVRN_INT) { 924 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_RX_OVRN_INT); 925 ifp->if_ierrors++; 926 } 927 928 /* 929 * Receive interrupts. 930 */ 931 if (status & IM_RCV_INT) { 932 #if 1 /* DIAGNOSTIC */ 933 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 934 if (packetno & FIFO_REMPTY) { 935 printf("%s: receive interrupt on empty fifo\n", 936 sc->sc_dev.dv_xname); 937 goto out; 938 } else 939 #endif 940 smc91cxx_read(sc); 941 } 942 943 /* 944 * Memory allocation interrupts. 945 */ 946 if (status & IM_ALLOC_INT) { 947 /* Disable this interrupt. */ 948 mask &= ~IM_ALLOC_INT; 949 950 /* 951 * Release the just-allocated memory. We will reallocate 952 * it through the normal start logic. 953 */ 954 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 955 /* XXX bound this loop! */ ; 956 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 957 958 ifp->if_flags &= ~IFF_OACTIVE; 959 ifp->if_timer = 0; 960 } 961 962 /* 963 * Transmit complete interrupt. Handle transmission error messages. 964 * This will only be called on error condition because of AUTO RELEASE 965 * mode. 966 */ 967 if (status & IM_TX_INT) { 968 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_INT); 969 970 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 971 FIFO_TX_MASK; 972 973 /* 974 * Select this as the packet to read from. 975 */ 976 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 977 978 /* 979 * Position the pointer to the beginning of the packet. 980 */ 981 bus_space_write_2(bst, bsh, POINTER_REG_W, 982 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 983 984 /* 985 * Fetch the TX status word. This will be a copy of 986 * the EPH_STATUS_REG_W at the time of the transmission 987 * failure. 988 */ 989 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 990 991 if (tx_status & EPHSR_TX_SUC) 992 printf("%s: successful packet caused TX interrupt?!\n", 993 sc->sc_dev.dv_xname); 994 else 995 ifp->if_oerrors++; 996 997 if (tx_status & EPHSR_LATCOL) 998 ifp->if_collisions++; 999 1000 /* 1001 * Some of these errors disable the transmitter; reenable it. 1002 */ 1003 SMC_SELECT_BANK(sc, 0); 1004 #ifdef SMC91CXX_SW_PAD 1005 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 1006 #else 1007 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 1008 TCR_ENABLE | TCR_PAD_ENABLE); 1009 #endif 1010 1011 /* 1012 * Kill the failed packet and wait for the MMU to unbusy. 1013 */ 1014 SMC_SELECT_BANK(sc, 2); 1015 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1016 /* XXX bound this loop! */ ; 1017 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 1018 1019 ifp->if_timer = 0; 1020 } 1021 1022 /* 1023 * Transmit underrun interrupts. We use this opportunity to 1024 * update transmit statistics from the card. 1025 */ 1026 if (status & IM_TX_EMPTY_INT) { 1027 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 1028 1029 /* Disable this interrupt. */ 1030 mask &= ~IM_TX_EMPTY_INT; 1031 1032 SMC_SELECT_BANK(sc, 0); 1033 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 1034 1035 /* Single collisions. */ 1036 ifp->if_collisions += card_stats & ECR_COLN_MASK; 1037 1038 /* Multiple collisions. */ 1039 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 1040 1041 SMC_SELECT_BANK(sc, 2); 1042 1043 ifp->if_timer = 0; 1044 } 1045 1046 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy && 1047 (status & IM_MD_INT)) { 1048 /* 1049 * Internal PHY status change 1050 */ 1051 mii_tick(&sc->sc_mii); 1052 } 1053 1054 /* 1055 * Other errors. Reset the interface. 1056 */ 1057 if (status & IM_EPH_INT) { 1058 smc91cxx_stop(sc); 1059 smc91cxx_init(sc); 1060 } 1061 1062 /* 1063 * Attempt to queue more packets for transmission. 1064 */ 1065 smc91cxx_start(ifp); 1066 1067 out: 1068 /* 1069 * Reenable the interrupts we wish to receive now that processing 1070 * is complete. 1071 */ 1072 mask |= bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 1073 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 1074 1075 #if NRND > 0 1076 if (status) 1077 rnd_add_uint32(&sc->rnd_source, status); 1078 #endif 1079 1080 return (1); 1081 } 1082 1083 /* 1084 * Read a packet from the card and pass it up to the kernel. 1085 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 1086 */ 1087 void 1088 smc91cxx_read(sc) 1089 struct smc91cxx_softc *sc; 1090 { 1091 struct ifnet *ifp = &sc->sc_ec.ec_if; 1092 bus_space_tag_t bst = sc->sc_bst; 1093 bus_space_handle_t bsh = sc->sc_bsh; 1094 struct ether_header *eh; 1095 struct mbuf *m; 1096 u_int16_t status, packetno, packetlen; 1097 u_int8_t *data; 1098 u_int32_t dr; 1099 1100 again: 1101 /* 1102 * Set data pointer to the beginning of the packet. Since 1103 * PTR_RCV is set, the packet number will be found automatically 1104 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1105 */ 1106 bus_space_write_2(bst, bsh, POINTER_REG_W, 1107 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 1108 1109 /* 1110 * First two words are status and packet length. 1111 */ 1112 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1113 status = bus_space_read_2(bst, bsh, DATA_REG_W); 1114 packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); 1115 } else { 1116 dr = bus_space_read_4(bst, bsh, DATA_REG_W); 1117 #if BYTE_ORDER == LITTLE_ENDIAN 1118 status = (u_int16_t)dr; 1119 packetlen = (u_int16_t)(dr >> 16); 1120 #else 1121 packetlen = (u_int16_t)dr; 1122 status = (u_int16_t)(dr >> 16); 1123 #endif 1124 } 1125 1126 packetlen &= RLEN_MASK; 1127 1128 /* 1129 * The packet length includes 3 extra words: status, length, 1130 * and an extra word that includes the control byte. 1131 */ 1132 packetlen -= 6; 1133 1134 /* 1135 * Account for receive errors and discard. 1136 */ 1137 if (status & RS_ERRORS) { 1138 ifp->if_ierrors++; 1139 goto out; 1140 } 1141 1142 /* 1143 * Adjust for odd-length packet. 1144 */ 1145 if (status & RS_ODDFRAME) 1146 packetlen++; 1147 1148 /* 1149 * Allocate a header mbuf. 1150 */ 1151 MGETHDR(m, M_DONTWAIT, MT_DATA); 1152 if (m == NULL) 1153 goto out; 1154 m->m_pkthdr.rcvif = ifp; 1155 m->m_pkthdr.len = packetlen; 1156 1157 /* 1158 * Always put the packet in a cluster. 1159 * XXX should chain small mbufs if less than threshold. 1160 */ 1161 MCLGET(m, M_DONTWAIT); 1162 if ((m->m_flags & M_EXT) == 0) { 1163 m_freem(m); 1164 ifp->if_ierrors++; 1165 printf("%s: can't allocate cluster for incoming packet\n", 1166 sc->sc_dev.dv_xname); 1167 goto out; 1168 } 1169 1170 /* 1171 * Pull the packet off the interface. Make sure the payload 1172 * is aligned. 1173 */ 1174 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1175 m->m_data = (caddr_t) ALIGN(mtod(m, caddr_t) + 1176 sizeof(struct ether_header)) - sizeof(struct ether_header); 1177 1178 eh = mtod(m, struct ether_header *); 1179 data = mtod(m, u_int8_t *); 1180 if (packetlen > 1) 1181 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 1182 (u_int16_t *)data, packetlen >> 1); 1183 if (packetlen & 1) { 1184 data += packetlen & ~1; 1185 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1186 } 1187 } else { 1188 u_int8_t *dp; 1189 1190 m->m_data = (caddr_t) ALIGN(mtod(m, caddr_t)); 1191 eh = mtod(m, struct ether_header *); 1192 dp = data = mtod(m, u_int8_t *); 1193 if (packetlen > 3) 1194 bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W, 1195 (u_int32_t *)data, packetlen >> 2); 1196 if (packetlen & 3) { 1197 data += packetlen & ~3; 1198 *((u_int32_t *)data) = 1199 bus_space_read_stream_4(bst, bsh, DATA_REG_W); 1200 } 1201 } 1202 1203 ifp->if_ipackets++; 1204 1205 /* 1206 * Make sure to behave as IFF_SIMPLEX in all cases. 1207 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1208 * loops back packets to itself on promiscuous mode. 1209 * (should be ensured by chipset configuration) 1210 */ 1211 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1212 /* 1213 * Drop packet looped back from myself. 1214 */ 1215 if (ether_cmp(eh->ether_shost, LLADDR(ifp->if_sadl)) == 0) { 1216 m_freem(m); 1217 goto out; 1218 } 1219 } 1220 1221 m->m_pkthdr.len = m->m_len = packetlen; 1222 1223 #if NBPFILTER > 0 1224 /* 1225 * Hand the packet off to bpf listeners. 1226 */ 1227 if (ifp->if_bpf) 1228 bpf_mtap(ifp->if_bpf, m); 1229 #endif 1230 1231 (*ifp->if_input)(ifp, m); 1232 1233 out: 1234 /* 1235 * Tell the card to free the memory occupied by this packet. 1236 */ 1237 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1238 /* XXX bound this loop! */ ; 1239 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1240 1241 /* 1242 * Check for another packet. 1243 */ 1244 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1245 if (packetno & FIFO_REMPTY) 1246 return; 1247 goto again; 1248 } 1249 1250 /* 1251 * Process an ioctl request. 1252 */ 1253 int 1254 smc91cxx_ioctl(ifp, cmd, data) 1255 struct ifnet *ifp; 1256 u_long cmd; 1257 caddr_t data; 1258 { 1259 struct smc91cxx_softc *sc = ifp->if_softc; 1260 struct ifaddr *ifa = (struct ifaddr *)data; 1261 struct ifreq *ifr = (struct ifreq *)data; 1262 int s, error = 0; 1263 1264 s = splnet(); 1265 1266 switch (cmd) { 1267 case SIOCSIFADDR: 1268 if ((error = smc91cxx_enable(sc)) != 0) 1269 break; 1270 ifp->if_flags |= IFF_UP; 1271 switch (ifa->ifa_addr->sa_family) { 1272 #ifdef INET 1273 case AF_INET: 1274 smc91cxx_init(sc); 1275 arp_ifinit(ifp, ifa); 1276 break; 1277 #endif 1278 #ifdef NS 1279 case AF_NS: 1280 { 1281 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1282 1283 if (ns_nullhost(*ina)) 1284 ina->x_host = 1285 *(union ns_host *)LLADDR(ifp->if_sadl); 1286 else { 1287 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 1288 ETHER_ADDR_LEN); 1289 } 1290 1291 /* 1292 * Set new address. Reset, because the receiver 1293 * has to be stopped before we can set the new 1294 * MAC address. 1295 */ 1296 smc91cxx_reset(sc); 1297 break; 1298 } 1299 #endif 1300 default: 1301 smc91cxx_init(sc); 1302 break; 1303 } 1304 break; 1305 1306 #if defined(CCITT) && defined(LLC) 1307 case SIOCSIFCONF_X25: 1308 if ((error = smc91cxx_enable(sc)) != 0) 1309 break; 1310 ifp->if_flags |= IFF_UP; 1311 ifa->ifa_rtrequest = cons_rtrequest; /* XXX */ 1312 error = x25_llcglue(PRC_IFUP, ifa->ifa_addr); 1313 if (error == 0) 1314 smc91cxx_init(sc); 1315 break; 1316 #endif 1317 1318 case SIOCSIFFLAGS: 1319 if ((ifp->if_flags & IFF_UP) == 0 && 1320 (ifp->if_flags & IFF_RUNNING) != 0) { 1321 /* 1322 * If interface is marked down and it is running, 1323 * stop it. 1324 */ 1325 smc91cxx_stop(sc); 1326 ifp->if_flags &= ~IFF_RUNNING; 1327 smc91cxx_disable(sc); 1328 } else if ((ifp->if_flags & IFF_UP) != 0 && 1329 (ifp->if_flags & IFF_RUNNING) == 0) { 1330 /* 1331 * If interface is marked up and it is stopped, 1332 * start it. 1333 */ 1334 if ((error = smc91cxx_enable(sc)) != 0) 1335 break; 1336 smc91cxx_init(sc); 1337 } else if ((ifp->if_flags & IFF_UP) != 0) { 1338 /* 1339 * Reset the interface to pick up changes in any 1340 * other flags that affect hardware registers. 1341 */ 1342 smc91cxx_reset(sc); 1343 } 1344 break; 1345 1346 case SIOCADDMULTI: 1347 case SIOCDELMULTI: 1348 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1349 error = EIO; 1350 break; 1351 } 1352 1353 error = (cmd == SIOCADDMULTI) ? 1354 ether_addmulti(ifr, &sc->sc_ec) : 1355 ether_delmulti(ifr, &sc->sc_ec); 1356 if (error == ENETRESET) { 1357 /* 1358 * Multicast list has changed; set the hardware 1359 * filter accordingly. 1360 */ 1361 smc91cxx_reset(sc); 1362 error = 0; 1363 } 1364 break; 1365 1366 case SIOCGIFMEDIA: 1367 case SIOCSIFMEDIA: 1368 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1369 break; 1370 1371 default: 1372 error = EINVAL; 1373 break; 1374 } 1375 1376 splx(s); 1377 return (error); 1378 } 1379 1380 /* 1381 * Reset the interface. 1382 */ 1383 void 1384 smc91cxx_reset(sc) 1385 struct smc91cxx_softc *sc; 1386 { 1387 int s; 1388 1389 s = splnet(); 1390 smc91cxx_stop(sc); 1391 smc91cxx_init(sc); 1392 splx(s); 1393 } 1394 1395 /* 1396 * Watchdog timer. 1397 */ 1398 void 1399 smc91cxx_watchdog(ifp) 1400 struct ifnet *ifp; 1401 { 1402 struct smc91cxx_softc *sc = ifp->if_softc; 1403 1404 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1405 ifp->if_oerrors++; 1406 smc91cxx_reset(sc); 1407 } 1408 1409 /* 1410 * Stop output on the interface. 1411 */ 1412 void 1413 smc91cxx_stop(sc) 1414 struct smc91cxx_softc *sc; 1415 { 1416 bus_space_tag_t bst = sc->sc_bst; 1417 bus_space_handle_t bsh = sc->sc_bsh; 1418 1419 /* 1420 * Clear interrupt mask; disable all interrupts. 1421 */ 1422 SMC_SELECT_BANK(sc, 2); 1423 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 1424 1425 /* 1426 * Disable transmitter and receiver. 1427 */ 1428 SMC_SELECT_BANK(sc, 0); 1429 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1430 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1431 1432 /* 1433 * Cancel watchdog timer. 1434 */ 1435 sc->sc_ec.ec_if.if_timer = 0; 1436 } 1437 1438 /* 1439 * Enable power on the interface. 1440 */ 1441 int 1442 smc91cxx_enable(sc) 1443 struct smc91cxx_softc *sc; 1444 { 1445 1446 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1447 if ((*sc->sc_enable)(sc) != 0) { 1448 printf("%s: device enable failed\n", 1449 sc->sc_dev.dv_xname); 1450 return (EIO); 1451 } 1452 } 1453 1454 sc->sc_flags |= SMC_FLAGS_ENABLED; 1455 return (0); 1456 } 1457 1458 /* 1459 * Disable power on the interface. 1460 */ 1461 void 1462 smc91cxx_disable(sc) 1463 struct smc91cxx_softc *sc; 1464 { 1465 1466 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1467 (*sc->sc_disable)(sc); 1468 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1469 } 1470 } 1471 1472 int 1473 smc91cxx_activate(self, act) 1474 struct device *self; 1475 enum devact act; 1476 { 1477 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1478 int rv = 0, s; 1479 1480 s = splnet(); 1481 switch (act) { 1482 case DVACT_ACTIVATE: 1483 rv = EOPNOTSUPP; 1484 break; 1485 1486 case DVACT_DEACTIVATE: 1487 if_deactivate(&sc->sc_ec.ec_if); 1488 break; 1489 } 1490 splx(s); 1491 return (rv); 1492 } 1493 1494 int 1495 smc91cxx_detach(self, flags) 1496 struct device *self; 1497 int flags; 1498 { 1499 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1500 struct ifnet *ifp = &sc->sc_ec.ec_if; 1501 1502 /* Succeed now if there's no work to do. */ 1503 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1504 return (0); 1505 1506 1507 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1508 smc91cxx_disable(sc); 1509 1510 /* smc91cxx_attach() never fails */ 1511 1512 /* Delete all media. */ 1513 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1514 1515 #if NRND > 0 1516 rnd_detach_source(&sc->rnd_source); 1517 #endif 1518 ether_ifdetach(ifp); 1519 if_detach(ifp); 1520 1521 return (0); 1522 } 1523 1524 u_int32_t 1525 smc91cxx_mii_bitbang_read(self) 1526 struct device *self; 1527 { 1528 struct smc91cxx_softc *sc = (void *) self; 1529 1530 /* We're already in bank 3. */ 1531 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1532 } 1533 1534 void 1535 smc91cxx_mii_bitbang_write(self, val) 1536 struct device *self; 1537 u_int32_t val; 1538 { 1539 struct smc91cxx_softc *sc = (void *) self; 1540 1541 /* We're already in bank 3. */ 1542 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1543 } 1544 1545 int 1546 smc91cxx_mii_readreg(self, phy, reg) 1547 struct device *self; 1548 int phy, reg; 1549 { 1550 struct smc91cxx_softc *sc = (void *) self; 1551 int val; 1552 1553 SMC_SELECT_BANK(sc, 3); 1554 1555 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1556 1557 SMC_SELECT_BANK(sc, 2); 1558 1559 return (val); 1560 } 1561 1562 void 1563 smc91cxx_mii_writereg(self, phy, reg, val) 1564 struct device *self; 1565 int phy, reg, val; 1566 { 1567 struct smc91cxx_softc *sc = (void *) self; 1568 1569 SMC_SELECT_BANK(sc, 3); 1570 1571 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1572 1573 SMC_SELECT_BANK(sc, 2); 1574 } 1575 1576 void 1577 smc91cxx_statchg(self) 1578 struct device *self; 1579 { 1580 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1581 bus_space_tag_t bst = sc->sc_bst; 1582 bus_space_handle_t bsh = sc->sc_bsh; 1583 int mctl; 1584 1585 SMC_SELECT_BANK(sc, 0); 1586 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1587 if (sc->sc_mii.mii_media_active & IFM_FDX) 1588 mctl |= TCR_SWFDUP; 1589 else 1590 mctl &= ~TCR_SWFDUP; 1591 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1592 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1593 } 1594 1595 /* 1596 * One second timer, used to tick the MII. 1597 */ 1598 void 1599 smc91cxx_tick(arg) 1600 void *arg; 1601 { 1602 struct smc91cxx_softc *sc = arg; 1603 int s; 1604 1605 #ifdef DIAGNOSTIC 1606 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1607 panic("smc91cxx_tick"); 1608 #endif 1609 1610 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1611 return; 1612 1613 s = splnet(); 1614 mii_tick(&sc->sc_mii); 1615 splx(s); 1616 1617 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1618 } 1619 1620
Indexes created Fri Sep 26 20:09:58 GMT 2025