smc91cxx.c revision 1.75
1 /* $NetBSD: smc91cxx.c,v 1.75 2009/05/12 14:25:18 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Gardner Buchanan <gbuchanan (at) shl.com> 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Gardner Buchanan. 48 * 4. The name of Gardner Buchanan may not be used to endorse or promote 49 * products derived from this software without specific prior written 50 * permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 64 */ 65 66 /* 67 * Core driver for the SMC 91Cxx family of Ethernet chips. 68 * 69 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 70 * written for NetBSD/amiga by Michael Hitch. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.75 2009/05/12 14:25:18 cegger Exp $"); 75 76 #include "opt_inet.h" 77 #include "bpfilter.h" 78 #include "rnd.h" 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/mbuf.h> 83 #include <sys/syslog.h> 84 #include <sys/socket.h> 85 #include <sys/device.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #if NRND > 0 91 #include <sys/rnd.h> 92 #endif 93 94 #include <sys/bus.h> 95 #include <sys/intr.h> 96 97 #include <uvm/uvm_extern.h> 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_ether.h> 102 #include <net/if_media.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/if_inarp.h> 107 #include <netinet/in_systm.h> 108 #include <netinet/in_var.h> 109 #include <netinet/ip.h> 110 #endif 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #include <net/bpfdesc.h> 115 #endif 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 #include <dev/mii/mii_bitbang.h> 120 121 #include <dev/ic/smc91cxxreg.h> 122 #include <dev/ic/smc91cxxvar.h> 123 124 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 125 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 126 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 127 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 128 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 129 130 #define bus_space_write_stream_4 bus_space_write_4 131 #define bus_space_read_stream_4 bus_space_read_4 132 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 133 134 /* XXX Hardware padding doesn't work yet(?) */ 135 #define SMC91CXX_SW_PAD 136 137 const char *smc91cxx_idstrs[] = { 138 NULL, /* 0 */ 139 NULL, /* 1 */ 140 NULL, /* 2 */ 141 "SMC91C90/91C92", /* 3 */ 142 "SMC91C94/91C96", /* 4 */ 143 "SMC91C95", /* 5 */ 144 NULL, /* 6 */ 145 "SMC91C100", /* 7 */ 146 "SMC91C100FD", /* 8 */ 147 "SMC91C111", /* 9 */ 148 NULL, /* 10 */ 149 NULL, /* 11 */ 150 NULL, /* 12 */ 151 NULL, /* 13 */ 152 NULL, /* 14 */ 153 NULL, /* 15 */ 154 }; 155 156 /* Supported media types. */ 157 const int smc91cxx_media[] = { 158 IFM_ETHER|IFM_10_T, 159 IFM_ETHER|IFM_10_5, 160 }; 161 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 162 163 /* 164 * MII bit-bang glue. 165 */ 166 u_int32_t smc91cxx_mii_bitbang_read(device_t); 167 void smc91cxx_mii_bitbang_write(device_t, u_int32_t); 168 169 const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 170 smc91cxx_mii_bitbang_read, 171 smc91cxx_mii_bitbang_write, 172 { 173 MR_MDO, /* MII_BIT_MDO */ 174 MR_MDI, /* MII_BIT_MDI */ 175 MR_MCLK, /* MII_BIT_MDC */ 176 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 177 0, /* MII_BIT_DIR_PHY_HOST */ 178 } 179 }; 180 181 /* MII callbacks */ 182 int smc91cxx_mii_readreg(device_t, int, int); 183 void smc91cxx_mii_writereg(device_t, int, int, int); 184 void smc91cxx_statchg(device_t); 185 void smc91cxx_tick(void *); 186 187 int smc91cxx_mediachange(struct ifnet *); 188 void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *); 189 190 int smc91cxx_set_media(struct smc91cxx_softc *, int); 191 192 void smc91cxx_init(struct smc91cxx_softc *); 193 void smc91cxx_read(struct smc91cxx_softc *); 194 void smc91cxx_reset(struct smc91cxx_softc *); 195 void smc91cxx_start(struct ifnet *); 196 uint8_t smc91cxx_copy_tx_frame(struct smc91cxx_softc *, struct mbuf *); 197 void smc91cxx_resume(struct smc91cxx_softc *); 198 void smc91cxx_stop(struct smc91cxx_softc *); 199 void smc91cxx_watchdog(struct ifnet *); 200 int smc91cxx_ioctl(struct ifnet *, u_long, void *); 201 202 static inline int ether_cmp(const void *, const void *); 203 static inline int 204 ether_cmp(const void *va, const void *vb) 205 { 206 const u_int8_t *a = va; 207 const u_int8_t *b = vb; 208 209 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 210 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 211 } 212 213 static inline void 214 smc91cxx_intr_mask_write(bus_space_tag_t bst, bus_space_handle_t bsh, 215 uint8_t mask) 216 { 217 KDASSERT((mask & IM_ERCV_INT) == 0); 218 #ifdef SMC91CXX_NO_BYTE_WRITE 219 #if BYTE_ORDER == LITTLE_ENDIAN 220 bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask << 8); 221 #else 222 bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask); 223 #endif 224 #else 225 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 226 #endif 227 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 228 } 229 230 static inline void 231 smc91cxx_intr_ack_write(bus_space_tag_t bst, bus_space_handle_t bsh, 232 uint8_t mask) 233 { 234 #ifdef SMC91CXX_NO_BYTE_WRITE 235 #if BYTE_ORDER == LITTLE_ENDIAN 236 bus_space_write_2(bst, bsh, INTR_ACK_REG_B, 237 mask | (bus_space_read_2(bst, bsh, INTR_ACK_REG_B) & 0xff00)); 238 #else 239 bus_space_write_2(bst, bsh, INTR_ACK_REG_B, 240 (mask << 8) | (bus_space_read_2(bst, bsh, INTR_ACK_REG_B) & 0xff)); 241 #endif 242 #else 243 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, mask); 244 #endif 245 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 246 } 247 248 void 249 smc91cxx_attach(struct smc91cxx_softc *sc, u_int8_t *myea) 250 { 251 struct ifnet *ifp = &sc->sc_ec.ec_if; 252 bus_space_tag_t bst = sc->sc_bst; 253 bus_space_handle_t bsh = sc->sc_bsh; 254 struct ifmedia *ifm = &sc->sc_mii.mii_media; 255 const char *idstr; 256 u_int32_t miicapabilities; 257 u_int16_t tmp; 258 u_int8_t enaddr[ETHER_ADDR_LEN]; 259 int i, aui, mult, scale, memsize; 260 char pbuf[9]; 261 262 tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W); 263 /* check magic number */ 264 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 265 aprint_error_dev(&sc->sc_dev, "failed to detect chip, bsr=%04x\n", tmp); 266 return; 267 } 268 269 /* Make sure the chip is stopped. */ 270 smc91cxx_stop(sc); 271 272 SMC_SELECT_BANK(sc, 3); 273 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 274 sc->sc_chipid = RR_ID(tmp); 275 idstr = smc91cxx_idstrs[sc->sc_chipid]; 276 277 aprint_normal_dev(&sc->sc_dev, ""); 278 if (idstr != NULL) 279 aprint_normal("%s, ", idstr); 280 else 281 aprint_normal("unknown chip id %d, ", sc->sc_chipid); 282 aprint_normal("revision %d, ", RR_REV(tmp)); 283 284 SMC_SELECT_BANK(sc, 0); 285 switch (sc->sc_chipid) { 286 default: 287 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 288 scale = MIR_SCALE_91C9x; 289 break; 290 291 case CHIP_91C111: 292 mult = MIR_MULT_91C111; 293 scale = MIR_SCALE_91C111; 294 } 295 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 296 if (memsize == 255) memsize++; 297 memsize *= scale * mult; 298 299 format_bytes(pbuf, sizeof(pbuf), memsize); 300 aprint_normal("buffer size: %s\n", pbuf); 301 302 /* Read the station address from the chip. */ 303 SMC_SELECT_BANK(sc, 1); 304 if (myea == NULL) { 305 myea = enaddr; 306 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 307 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 308 myea[i + 1] = (tmp >> 8) & 0xff; 309 myea[i] = tmp & 0xff; 310 } 311 } 312 aprint_normal_dev(&sc->sc_dev, "MAC address %s, ", 313 ether_sprintf(myea)); 314 315 /* Initialize the ifnet structure. */ 316 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 317 ifp->if_softc = sc; 318 ifp->if_start = smc91cxx_start; 319 ifp->if_ioctl = smc91cxx_ioctl; 320 ifp->if_watchdog = smc91cxx_watchdog; 321 ifp->if_flags = 322 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 323 IFQ_SET_READY(&ifp->if_snd); 324 325 /* Attach the interface. */ 326 if_attach(ifp); 327 ether_ifattach(ifp, myea); 328 329 /* 330 * Initialize our media structures and MII info. We will 331 * probe the MII if we are on the SMC91Cxx 332 */ 333 sc->sc_mii.mii_ifp = ifp; 334 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 335 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 336 sc->sc_mii.mii_statchg = smc91cxx_statchg; 337 ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, smc91cxx_mediastatus); 338 339 SMC_SELECT_BANK(sc, 1); 340 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 341 342 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 343 switch (sc->sc_chipid) { 344 case CHIP_91100: 345 /* 346 * The 91100 does not have full-duplex capabilities, 347 * even if the PHY does. 348 */ 349 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 350 case CHIP_91100FD: 351 case CHIP_91C111: 352 if (tmp & CR_MII_SELECT) { 353 aprint_normal("default media MII"); 354 if (sc->sc_chipid == CHIP_91C111) { 355 aprint_normal(" (%s PHY)\n", (tmp & CR_AUI_SELECT) ? 356 "external" : "internal"); 357 sc->sc_internal_phy = !(tmp & CR_AUI_SELECT); 358 } else 359 aprint_normal("\n"); 360 mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, 361 MII_PHY_ANY, MII_OFFSET_ANY, 0); 362 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 363 ifmedia_add(&sc->sc_mii.mii_media, 364 IFM_ETHER|IFM_NONE, 0, NULL); 365 ifmedia_set(&sc->sc_mii.mii_media, 366 IFM_ETHER|IFM_NONE); 367 } else { 368 ifmedia_set(&sc->sc_mii.mii_media, 369 IFM_ETHER|IFM_AUTO); 370 } 371 sc->sc_flags |= SMC_FLAGS_HAS_MII; 372 break; 373 } else 374 if (sc->sc_chipid == CHIP_91C111) { 375 /* 376 * XXX: Should bring it out of low-power mode 377 */ 378 aprint_normal("EPH interface in low power mode\n"); 379 sc->sc_internal_phy = 0; 380 return; 381 } 382 /*FALLTHROUGH*/ 383 default: 384 aprint_normal("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ? 385 "AUI" : "UTP"); 386 for (i = 0; i < NSMC91CxxMEDIA; i++) 387 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 388 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 389 break; 390 } 391 392 #if NRND > 0 393 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 394 RND_TYPE_NET, 0); 395 #endif 396 397 callout_init(&sc->sc_mii_callout, 0); 398 399 /* The attach is successful. */ 400 sc->sc_flags |= SMC_FLAGS_ATTACHED; 401 } 402 403 /* 404 * Change media according to request. 405 */ 406 int 407 smc91cxx_mediachange(struct ifnet *ifp) 408 { 409 struct smc91cxx_softc *sc = ifp->if_softc; 410 411 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 412 } 413 414 int 415 smc91cxx_set_media(struct smc91cxx_softc *sc, int media) 416 { 417 bus_space_tag_t bst = sc->sc_bst; 418 bus_space_handle_t bsh = sc->sc_bsh; 419 u_int16_t tmp; 420 int rc; 421 422 /* 423 * If the interface is not currently powered on, just return. 424 * When it is enabled later, smc91cxx_init() will properly set 425 * up the media for us. 426 */ 427 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 428 return (0); 429 430 if (IFM_TYPE(media) != IFM_ETHER) 431 return (EINVAL); 432 433 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0 || 434 (rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 435 rc = 0; 436 437 switch (IFM_SUBTYPE(media)) { 438 case IFM_10_T: 439 case IFM_10_5: 440 SMC_SELECT_BANK(sc, 1); 441 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 442 if (IFM_SUBTYPE(media) == IFM_10_5) 443 tmp |= CR_AUI_SELECT; 444 else 445 tmp &= ~CR_AUI_SELECT; 446 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 447 delay(20000); /* XXX is this needed? */ 448 break; 449 450 default: 451 return (EINVAL); 452 } 453 454 return rc; 455 } 456 457 /* 458 * Notify the world which media we're using. 459 */ 460 void 461 smc91cxx_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 462 { 463 struct smc91cxx_softc *sc = ifp->if_softc; 464 bus_space_tag_t bst = sc->sc_bst; 465 bus_space_handle_t bsh = sc->sc_bsh; 466 u_int16_t tmp; 467 468 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 469 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 470 ifmr->ifm_status = 0; 471 return; 472 } 473 474 /* 475 * If we have MII, go ask the PHY what's going on. 476 */ 477 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 478 mii_pollstat(&sc->sc_mii); 479 ifmr->ifm_active = sc->sc_mii.mii_media_active; 480 ifmr->ifm_status = sc->sc_mii.mii_media_status; 481 return; 482 } 483 484 SMC_SELECT_BANK(sc, 1); 485 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 486 ifmr->ifm_active = 487 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 488 } 489 490 /* 491 * Reset and initialize the chip. 492 */ 493 void 494 smc91cxx_init(struct smc91cxx_softc *sc) 495 { 496 struct ifnet *ifp = &sc->sc_ec.ec_if; 497 bus_space_tag_t bst = sc->sc_bst; 498 bus_space_handle_t bsh = sc->sc_bsh; 499 u_int16_t tmp; 500 const u_int8_t *enaddr; 501 int s, i; 502 503 s = splnet(); 504 505 /* 506 * This resets the registers mostly to defaults, but doesn't 507 * affect the EEPROM. After the reset cycle, we pause briefly 508 * for the chip to recover. 509 * 510 * XXX how long are we really supposed to delay? --thorpej 511 */ 512 SMC_SELECT_BANK(sc, 0); 513 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 514 delay(100); 515 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 516 delay(200); 517 518 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 519 520 /* Set the Ethernet address. */ 521 SMC_SELECT_BANK(sc, 1); 522 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 523 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 524 tmp = enaddr[i + 1] << 8 | enaddr[i]; 525 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 526 } 527 528 /* 529 * Set the control register to automatically release successfully 530 * transmitted packets (making the best use of our limited memory) 531 * and enable the EPH interrupt on certain TX errors. 532 */ 533 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 534 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 535 536 /* 537 * Reset the MMU and wait for it to be un-busy. 538 */ 539 SMC_SELECT_BANK(sc, 2); 540 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 541 sc->sc_txpacketno = ARR_FAILED; 542 for (;;) { 543 tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W); 544 if (tmp == 0xffff) /* card went away! */ 545 return; 546 if ((tmp & MMUCR_BUSY) == 0) 547 break; 548 } 549 550 /* 551 * Disable all interrupts. 552 */ 553 smc91cxx_intr_mask_write(bst, bsh, 0); 554 555 /* 556 * On the 91c111, enable auto-negotiation, and set the LED 557 * status pins to something sane. 558 * XXX: Should be some way for MD code to decide the latter. 559 */ 560 SMC_SELECT_BANK(sc, 0); 561 if (sc->sc_chipid == CHIP_91C111) { 562 bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W, 563 RPC_ANEG | 564 (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) | 565 (RPC_LS_TXRX << RPC_LSB_SHIFT)); 566 } 567 568 /* 569 * Set current media. 570 */ 571 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 572 573 /* 574 * Set the receive filter. We want receive enable and auto 575 * strip of CRC from received packet. If we are in promisc. mode, 576 * then set that bit as well. 577 * 578 * XXX Initialize multicast filter. For now, we just accept 579 * XXX all multicast. 580 */ 581 SMC_SELECT_BANK(sc, 0); 582 583 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 584 if (ifp->if_flags & IFF_PROMISC) 585 tmp |= RCR_PROMISC; 586 587 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 588 589 /* 590 * Set transmitter control to "enabled". 591 */ 592 tmp = TCR_ENABLE; 593 594 #ifndef SMC91CXX_SW_PAD 595 /* 596 * Enable hardware padding of transmitted packets. 597 * XXX doesn't work? 598 */ 599 tmp |= TCR_PAD_ENABLE; 600 #endif 601 602 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 603 604 /* 605 * Now, enable interrupts. 606 */ 607 SMC_SELECT_BANK(sc, 2); 608 609 sc->sc_intmask = IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT; 610 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) { 611 sc->sc_intmask |= IM_MD_INT; 612 } 613 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 614 615 /* Interface is now running, with no output active. */ 616 ifp->if_flags |= IFF_RUNNING; 617 ifp->if_flags &= ~IFF_OACTIVE; 618 619 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 620 /* Start the one second clock. */ 621 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 622 } 623 624 /* 625 * Attempt to start any pending transmission. 626 */ 627 smc91cxx_start(ifp); 628 629 splx(s); 630 } 631 632 /* 633 * Start output on an interface. 634 * Must be called at splnet or interrupt level. 635 */ 636 void 637 smc91cxx_start(struct ifnet *ifp) 638 { 639 struct smc91cxx_softc *sc = ifp->if_softc; 640 bus_space_tag_t bst = sc->sc_bst; 641 bus_space_handle_t bsh = sc->sc_bsh; 642 u_int len; 643 struct mbuf *m; 644 u_int16_t length, npages; 645 u_int16_t oddbyte; 646 u_int8_t packetno; 647 int timo, pad; 648 649 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 650 return; 651 652 again: 653 /* 654 * Peek at the next packet. 655 */ 656 IFQ_POLL(&ifp->if_snd, m); 657 if (m == NULL) 658 return; 659 660 /* 661 * Compute the frame length and set pad to give an overall even 662 * number of bytes. Below, we assume that the packet length 663 * is even. 664 */ 665 for (len = 0; m != NULL; m = m->m_next) 666 len += m->m_len; 667 pad = (len & 1); 668 669 /* 670 * We drop packets that are too large. Perhaps we should 671 * truncate them instead? 672 */ 673 if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 674 printf("%s: large packet discarded\n", device_xname(&sc->sc_dev)); 675 ifp->if_oerrors++; 676 IFQ_DEQUEUE(&ifp->if_snd, m); 677 m_freem(m); 678 goto readcheck; 679 } 680 681 #ifdef SMC91CXX_SW_PAD 682 /* 683 * Not using hardware padding; pad to ETHER_MIN_LEN. 684 */ 685 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 686 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 687 #endif 688 689 length = pad + len; 690 691 /* 692 * The MMU has a 256 byte page size. The MMU expects us to 693 * ask for "npages - 1". We include space for the status word, 694 * byte count, and control bytes in the allocation request. 695 */ 696 npages = ((length & ~1) + 6) >> 8; 697 698 /* 699 * Now allocate the memory. 700 */ 701 SMC_SELECT_BANK(sc, 2); 702 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 703 704 timo = MEMORY_WAIT_TIME; 705 if (__predict_false((sc->sc_txpacketno & ARR_FAILED) == 0)) { 706 packetno = sc->sc_txpacketno; 707 sc->sc_txpacketno = ARR_FAILED; 708 } else { 709 do { 710 if (bus_space_read_1(bst, bsh, 711 INTR_STAT_REG_B) & IM_ALLOC_INT) 712 break; 713 delay(1); 714 } while (--timo); 715 } 716 717 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 718 719 if (packetno & ARR_FAILED || timo == 0) { 720 /* 721 * No transmit memory is available. Record the number 722 * of requestd pages and enable the allocation completion 723 * interrupt. Set up the watchdog timer in case we miss 724 * the interrupt. Mark the interface as active so that 725 * no one else attempts to transmit while we're allocating 726 * memory. 727 */ 728 sc->sc_intmask |= IM_ALLOC_INT; 729 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 730 ifp->if_timer = 5; 731 ifp->if_flags |= IFF_OACTIVE; 732 733 return; 734 } 735 736 /* 737 * We have a packet number - set the data window. 738 */ 739 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 740 741 /* 742 * Point to the beginning of the packet. 743 */ 744 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 745 746 /* 747 * Send the packet length (+6 for stats, length, and control bytes) 748 * and the status word (set to zeros). 749 */ 750 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 751 bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff); 752 753 /* 754 * Get the packet from the kernel. This will include the Ethernet 755 * frame header, MAC address, etc. 756 */ 757 IFQ_DEQUEUE(&ifp->if_snd, m); 758 759 /* 760 * Push the packet out to the card. 761 */ 762 oddbyte = smc91cxx_copy_tx_frame(sc, m); 763 764 #ifdef SMC91CXX_SW_PAD 765 #ifdef SMC91CXX_NO_BYTE_WRITE 766 #if BYTE_ORDER == LITTLE_ENDIAN 767 if (pad > 1 && (pad & 1)) { 768 bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte << 0); 769 oddbyte = 0; 770 } 771 #else 772 if (pad > 1 && (pad & 1)) { 773 bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte << 8); 774 oddbyte = 0; 775 } 776 #endif 777 #endif 778 779 /* 780 * Push out padding. 781 */ 782 while (pad > 1) { 783 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 784 pad -= 2; 785 } 786 #endif 787 788 #ifdef SMC91CXX_NO_BYTE_WRITE 789 /* 790 * Push out control byte and unused packet byte. The control byte 791 * is 0, meaning the packet is even lengthed and no special 792 * CRC handling is necessary. 793 */ 794 #if BYTE_ORDER == LITTLE_ENDIAN 795 bus_space_write_2(bst, bsh, DATA_REG_W, 796 oddbyte | (pad ? (CTLB_ODD << 8) : 0)); 797 #else 798 bus_space_write_2(bst, bsh, DATA_REG_W, 799 (oddbyte << 8) | (pad ? CTLB_ODD : 0)); 800 #endif 801 #else 802 if (pad) 803 bus_space_write_1(bst, bsh, DATA_REG_B, 0); 804 #endif 805 806 /* 807 * Enable transmit interrupts and let the chip go. Set a watchdog 808 * in case we miss the interrupt. 809 */ 810 sc->sc_intmask |= IM_TX_INT | IM_TX_EMPTY_INT; 811 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 812 813 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 814 815 ifp->if_timer = 5; 816 817 #if NBPFILTER > 0 818 /* Hand off a copy to the bpf. */ 819 if (ifp->if_bpf) 820 bpf_mtap(ifp->if_bpf, m); 821 #endif 822 823 ifp->if_opackets++; 824 m_freem(m); 825 826 readcheck: 827 /* 828 * Check for incoming pcakets. We don't want to overflow the small 829 * RX FIFO. If nothing has arrived, attempt to queue another 830 * transmit packet. 831 */ 832 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 833 goto again; 834 } 835 836 /* 837 * Squirt a (possibly misaligned) mbuf to the device 838 */ 839 uint8_t 840 smc91cxx_copy_tx_frame(struct smc91cxx_softc *sc, struct mbuf *m0) 841 { 842 bus_space_tag_t bst = sc->sc_bst; 843 bus_space_handle_t bsh = sc->sc_bsh; 844 struct mbuf *m; 845 int len, leftover; 846 u_int16_t dbuf; 847 u_int8_t *p; 848 #ifdef DIAGNOSTIC 849 u_int8_t *lim; 850 #endif 851 852 /* start out with no leftover data */ 853 leftover = 0; 854 dbuf = 0; 855 856 /* Process the chain of mbufs */ 857 for (m = m0; m != NULL; m = m->m_next) { 858 /* 859 * Process all of the data in a single mbuf. 860 */ 861 p = mtod(m, u_int8_t *); 862 len = m->m_len; 863 #ifdef DIAGNOSTIC 864 lim = p + len; 865 #endif 866 867 while (len > 0) { 868 if (leftover) { 869 /* 870 * Data left over (from mbuf or realignment). 871 * Buffer the next byte, and write it and 872 * the leftover data out. 873 */ 874 dbuf |= *p++ << 8; 875 len--; 876 bus_space_write_2(bst, bsh, DATA_REG_W, dbuf); 877 leftover = 0; 878 } else if ((long) p & 1) { 879 /* 880 * Misaligned data. Buffer the next byte. 881 */ 882 dbuf = *p++; 883 len--; 884 leftover = 1; 885 } else { 886 /* 887 * Aligned data. This is the case we like. 888 * 889 * Write-region out as much as we can, then 890 * buffer the remaining byte (if any). 891 */ 892 leftover = len & 1; 893 len &= ~1; 894 bus_space_write_multi_stream_2(bst, bsh, 895 DATA_REG_W, (u_int16_t *)p, len >> 1); 896 p += len; 897 898 if (leftover) 899 dbuf = *p++; 900 len = 0; 901 } 902 } 903 if (len < 0) 904 panic("smc91cxx_copy_tx_frame: negative len"); 905 #ifdef DIAGNOSTIC 906 if (p != lim) 907 panic("smc91cxx_copy_tx_frame: p != lim"); 908 #endif 909 } 910 #ifndef SMC91CXX_NO_BYTE_WRITE 911 if (leftover) 912 bus_space_write_1(bst, bsh, DATA_REG_B, dbuf); 913 #endif 914 return dbuf; 915 } 916 917 /* 918 * Interrupt service routine. 919 */ 920 int 921 smc91cxx_intr(void *arg) 922 { 923 struct smc91cxx_softc *sc = arg; 924 struct ifnet *ifp = &sc->sc_ec.ec_if; 925 bus_space_tag_t bst = sc->sc_bst; 926 bus_space_handle_t bsh = sc->sc_bsh; 927 u_int8_t mask, interrupts, status; 928 u_int16_t packetno, tx_status, card_stats; 929 #ifdef SMC91CXX_NO_BYTE_WRITE 930 u_int16_t v; 931 #endif 932 933 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 934 !device_is_active(&sc->sc_dev)) 935 return (0); 936 937 SMC_SELECT_BANK(sc, 2); 938 939 /* 940 * Obtain the current interrupt status and mask. 941 */ 942 #ifdef SMC91CXX_NO_BYTE_WRITE 943 v = bus_space_read_2(bst, bsh, INTR_STAT_REG_B); 944 945 /* 946 * Get the set of interrupt which occurred and eliminate any 947 * which are not enabled. 948 */ 949 #if BYTE_ORDER == LITTLE_ENDIAN 950 mask = v >> 8; 951 interrupts = v & 0xff; 952 #else 953 interrupts = v >> 8; 954 mask = v & 0xff; 955 #endif 956 KDASSERT(mask == sc->sc_intmask); 957 #else 958 mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 959 960 /* 961 * Get the set of interrupt which occurred and eliminate any 962 * which are not enabled. 963 */ 964 interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B); 965 #endif 966 status = interrupts & mask; 967 968 /* Ours? */ 969 if (status == 0) 970 return (0); 971 972 /* 973 * It's ours; disable all interrupts while we process them. 974 */ 975 smc91cxx_intr_mask_write(bst, bsh, 0); 976 977 /* 978 * Receive overrun interrupts. 979 */ 980 if (status & IM_RX_OVRN_INT) { 981 smc91cxx_intr_ack_write(bst, bsh, IM_RX_OVRN_INT); 982 ifp->if_ierrors++; 983 } 984 985 /* 986 * Receive interrupts. 987 */ 988 if (status & IM_RCV_INT) { 989 #if 1 /* DIAGNOSTIC */ 990 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 991 if (packetno & FIFO_REMPTY) { 992 aprint_error_dev(&sc->sc_dev, "receive interrupt on empty fifo\n"); 993 goto out; 994 } else 995 #endif 996 smc91cxx_read(sc); 997 } 998 999 /* 1000 * Memory allocation interrupts. 1001 */ 1002 if (status & IM_ALLOC_INT) { 1003 /* Disable this interrupt. */ 1004 mask &= ~IM_ALLOC_INT; 1005 sc->sc_intmask &= ~IM_ALLOC_INT; 1006 1007 /* 1008 * Save allocated packet number for use in start 1009 */ 1010 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 1011 KASSERT(sc->sc_txpacketno & ARR_FAILED); 1012 sc->sc_txpacketno = packetno; 1013 1014 /* 1015 * We can transmit again! 1016 */ 1017 ifp->if_flags &= ~IFF_OACTIVE; 1018 ifp->if_timer = 0; 1019 } 1020 1021 /* 1022 * Transmit complete interrupt. Handle transmission error messages. 1023 * This will only be called on error condition because of AUTO RELEASE 1024 * mode. 1025 */ 1026 if (status & IM_TX_INT) { 1027 smc91cxx_intr_ack_write(bst, bsh, IM_TX_INT); 1028 1029 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 1030 FIFO_TX_MASK; 1031 1032 /* 1033 * Select this as the packet to read from. 1034 */ 1035 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 1036 1037 /* 1038 * Position the pointer to the beginning of the packet. 1039 */ 1040 bus_space_write_2(bst, bsh, POINTER_REG_W, 1041 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 1042 1043 /* 1044 * Fetch the TX status word. This will be a copy of 1045 * the EPH_STATUS_REG_W at the time of the transmission 1046 * failure. 1047 */ 1048 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 1049 1050 if (tx_status & EPHSR_TX_SUC) { 1051 static struct timeval txsuc_last; 1052 static int txsuc_count; 1053 if (ppsratecheck(&txsuc_last, &txsuc_count, 1)) 1054 printf("%s: successful packet caused TX" 1055 " interrupt?!\n", device_xname(&sc->sc_dev)); 1056 } else 1057 ifp->if_oerrors++; 1058 1059 if (tx_status & EPHSR_LATCOL) 1060 ifp->if_collisions++; 1061 1062 /* Disable this interrupt (start will reenable if needed). */ 1063 mask &= ~IM_TX_INT; 1064 sc->sc_intmask &= ~IM_TX_INT; 1065 1066 /* 1067 * Some of these errors disable the transmitter; reenable it. 1068 */ 1069 SMC_SELECT_BANK(sc, 0); 1070 #ifdef SMC91CXX_SW_PAD 1071 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 1072 #else 1073 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 1074 TCR_ENABLE | TCR_PAD_ENABLE); 1075 #endif 1076 1077 /* 1078 * Kill the failed packet and wait for the MMU to unbusy. 1079 */ 1080 SMC_SELECT_BANK(sc, 2); 1081 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1082 /* XXX bound this loop! */ ; 1083 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 1084 1085 ifp->if_timer = 0; 1086 } 1087 1088 /* 1089 * Transmit underrun interrupts. We use this opportunity to 1090 * update transmit statistics from the card. 1091 */ 1092 if (status & IM_TX_EMPTY_INT) { 1093 smc91cxx_intr_ack_write(bst, bsh, IM_TX_EMPTY_INT); 1094 1095 /* Disable this interrupt. */ 1096 mask &= ~IM_TX_EMPTY_INT; 1097 sc->sc_intmask &= ~IM_TX_EMPTY_INT; 1098 1099 SMC_SELECT_BANK(sc, 0); 1100 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 1101 1102 /* Single collisions. */ 1103 ifp->if_collisions += card_stats & ECR_COLN_MASK; 1104 1105 /* Multiple collisions. */ 1106 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 1107 1108 SMC_SELECT_BANK(sc, 2); 1109 1110 ifp->if_timer = 0; 1111 } 1112 1113 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy && 1114 (status & IM_MD_INT)) { 1115 /* 1116 * Internal PHY status change 1117 */ 1118 mii_tick(&sc->sc_mii); 1119 } 1120 1121 /* 1122 * Other errors. Reset the interface. 1123 */ 1124 if (status & IM_EPH_INT) { 1125 smc91cxx_stop(sc); 1126 smc91cxx_init(sc); 1127 } 1128 1129 /* 1130 * Attempt to queue more packets for transmission. 1131 */ 1132 smc91cxx_start(ifp); 1133 1134 out: 1135 /* 1136 * Reenable the interrupts we wish to receive now that processing 1137 * is complete. 1138 */ 1139 mask |= sc->sc_intmask; 1140 smc91cxx_intr_mask_write(bst, bsh, mask); 1141 1142 #if NRND > 0 1143 if (status) 1144 rnd_add_uint32(&sc->rnd_source, status); 1145 #endif 1146 1147 return (1); 1148 } 1149 1150 /* 1151 * Read a packet from the card and pass it up to the kernel. 1152 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 1153 */ 1154 void 1155 smc91cxx_read(struct smc91cxx_softc *sc) 1156 { 1157 struct ifnet *ifp = &sc->sc_ec.ec_if; 1158 bus_space_tag_t bst = sc->sc_bst; 1159 bus_space_handle_t bsh = sc->sc_bsh; 1160 struct ether_header *eh; 1161 struct mbuf *m; 1162 u_int16_t status, packetno, packetlen; 1163 u_int8_t *data; 1164 u_int32_t dr; 1165 1166 again: 1167 /* 1168 * Set data pointer to the beginning of the packet. Since 1169 * PTR_RCV is set, the packet number will be found automatically 1170 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1171 */ 1172 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1173 if (packetno & FIFO_REMPTY) 1174 return; 1175 1176 bus_space_write_2(bst, bsh, POINTER_REG_W, 1177 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 1178 1179 /* 1180 * First two words are status and packet length. 1181 */ 1182 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1183 status = bus_space_read_2(bst, bsh, DATA_REG_W); 1184 packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); 1185 } else { 1186 dr = bus_space_read_4(bst, bsh, DATA_REG_W); 1187 #if BYTE_ORDER == LITTLE_ENDIAN 1188 status = (u_int16_t)dr; 1189 packetlen = (u_int16_t)(dr >> 16); 1190 #else 1191 packetlen = (u_int16_t)dr; 1192 status = (u_int16_t)(dr >> 16); 1193 #endif 1194 } 1195 1196 packetlen &= RLEN_MASK; 1197 if (packetlen < ETHER_MIN_LEN - ETHER_CRC_LEN + 6 || packetlen > 1534) { 1198 ifp->if_ierrors++; 1199 goto out; 1200 } 1201 1202 /* 1203 * The packet length includes 3 extra words: status, length, 1204 * and an extra word that includes the control byte. 1205 */ 1206 packetlen -= 6; 1207 1208 /* 1209 * Account for receive errors and discard. 1210 */ 1211 if (status & RS_ERRORS) { 1212 ifp->if_ierrors++; 1213 goto out; 1214 } 1215 1216 /* 1217 * Adjust for odd-length packet. 1218 */ 1219 if (status & RS_ODDFRAME) 1220 packetlen++; 1221 1222 /* 1223 * Allocate a header mbuf. 1224 */ 1225 MGETHDR(m, M_DONTWAIT, MT_DATA); 1226 if (m == NULL) 1227 goto out; 1228 m->m_pkthdr.rcvif = ifp; 1229 m->m_pkthdr.len = packetlen; 1230 1231 /* 1232 * Always put the packet in a cluster. 1233 * XXX should chain small mbufs if less than threshold. 1234 */ 1235 MCLGET(m, M_DONTWAIT); 1236 if ((m->m_flags & M_EXT) == 0) { 1237 m_freem(m); 1238 ifp->if_ierrors++; 1239 aprint_error_dev(&sc->sc_dev, "can't allocate cluster for incoming packet\n"); 1240 goto out; 1241 } 1242 1243 /* 1244 * Pull the packet off the interface. Make sure the payload 1245 * is aligned. 1246 */ 1247 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1248 m->m_data = (char *) ALIGN(mtod(m, char *) + 1249 sizeof(struct ether_header)) - sizeof(struct ether_header); 1250 1251 eh = mtod(m, struct ether_header *); 1252 data = mtod(m, u_int8_t *); 1253 KASSERT(trunc_page((uintptr_t)data) == trunc_page((uintptr_t)data + packetlen - 1)); 1254 if (packetlen > 1) 1255 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 1256 (u_int16_t *)data, packetlen >> 1); 1257 if (packetlen & 1) { 1258 data += packetlen & ~1; 1259 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1260 } 1261 } else { 1262 u_int8_t *dp; 1263 1264 m->m_data = (void *) ALIGN(mtod(m, void *)); 1265 eh = mtod(m, struct ether_header *); 1266 dp = data = mtod(m, u_int8_t *); 1267 KASSERT(trunc_page((uintptr_t)data) == trunc_page((uintptr_t)data + packetlen - 1)); 1268 if (packetlen > 3) 1269 bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W, 1270 (u_int32_t *)data, packetlen >> 2); 1271 if (packetlen & 3) { 1272 data += packetlen & ~3; 1273 *((u_int32_t *)data) = 1274 bus_space_read_stream_4(bst, bsh, DATA_REG_W); 1275 } 1276 } 1277 1278 ifp->if_ipackets++; 1279 1280 /* 1281 * Make sure to behave as IFF_SIMPLEX in all cases. 1282 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1283 * loops back packets to itself on promiscuous mode. 1284 * (should be ensured by chipset configuration) 1285 */ 1286 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1287 /* 1288 * Drop packet looped back from myself. 1289 */ 1290 if (ether_cmp(eh->ether_shost, CLLADDR(ifp->if_sadl)) == 0) { 1291 m_freem(m); 1292 goto out; 1293 } 1294 } 1295 1296 m->m_pkthdr.len = m->m_len = packetlen; 1297 1298 #if NBPFILTER > 0 1299 /* 1300 * Hand the packet off to bpf listeners. 1301 */ 1302 if (ifp->if_bpf) 1303 bpf_mtap(ifp->if_bpf, m); 1304 #endif 1305 1306 (*ifp->if_input)(ifp, m); 1307 1308 out: 1309 /* 1310 * Tell the card to free the memory occupied by this packet. 1311 */ 1312 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1313 /* XXX bound this loop! */ ; 1314 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1315 1316 /* 1317 * Check for another packet. 1318 */ 1319 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1320 if (packetno & FIFO_REMPTY) 1321 return; 1322 goto again; 1323 } 1324 1325 /* 1326 * Process an ioctl request. 1327 */ 1328 int 1329 smc91cxx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1330 { 1331 struct smc91cxx_softc *sc = ifp->if_softc; 1332 struct ifaddr *ifa = (struct ifaddr *)data; 1333 struct ifreq *ifr = (struct ifreq *)data; 1334 int s, error = 0; 1335 1336 s = splnet(); 1337 1338 switch (cmd) { 1339 case SIOCINITIFADDR: 1340 if ((error = smc91cxx_enable(sc)) != 0) 1341 break; 1342 ifp->if_flags |= IFF_UP; 1343 smc91cxx_init(sc); 1344 switch (ifa->ifa_addr->sa_family) { 1345 #ifdef INET 1346 case AF_INET: 1347 arp_ifinit(ifp, ifa); 1348 break; 1349 #endif 1350 default: 1351 break; 1352 } 1353 break; 1354 1355 1356 case SIOCSIFFLAGS: 1357 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1358 break; 1359 /* XXX re-use ether_ioctl() */ 1360 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1361 case IFF_RUNNING: 1362 /* 1363 * If interface is marked down and it is running, 1364 * stop it. 1365 */ 1366 smc91cxx_stop(sc); 1367 ifp->if_flags &= ~IFF_RUNNING; 1368 smc91cxx_disable(sc); 1369 break; 1370 case IFF_UP: 1371 /* 1372 * If interface is marked up and it is stopped, 1373 * start it. 1374 */ 1375 if ((error = smc91cxx_enable(sc)) != 0) 1376 break; 1377 smc91cxx_init(sc); 1378 break; 1379 case IFF_UP|IFF_RUNNING: 1380 /* 1381 * Reset the interface to pick up changes in any 1382 * other flags that affect hardware registers. 1383 */ 1384 smc91cxx_reset(sc); 1385 break; 1386 case 0: 1387 break; 1388 } 1389 break; 1390 1391 case SIOCADDMULTI: 1392 case SIOCDELMULTI: 1393 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1394 error = EIO; 1395 break; 1396 } 1397 1398 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1399 /* 1400 * Multicast list has changed; set the hardware 1401 * filter accordingly. 1402 */ 1403 if (ifp->if_flags & IFF_RUNNING) 1404 smc91cxx_reset(sc); 1405 error = 0; 1406 } 1407 break; 1408 1409 case SIOCGIFMEDIA: 1410 case SIOCSIFMEDIA: 1411 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1412 break; 1413 1414 default: 1415 error = ether_ioctl(ifp, cmd, data); 1416 break; 1417 } 1418 1419 splx(s); 1420 return (error); 1421 } 1422 1423 /* 1424 * Reset the interface. 1425 */ 1426 void 1427 smc91cxx_reset(struct smc91cxx_softc *sc) 1428 { 1429 int s; 1430 1431 s = splnet(); 1432 smc91cxx_stop(sc); 1433 smc91cxx_init(sc); 1434 splx(s); 1435 } 1436 1437 /* 1438 * Watchdog timer. 1439 */ 1440 void 1441 smc91cxx_watchdog(struct ifnet *ifp) 1442 { 1443 struct smc91cxx_softc *sc = ifp->if_softc; 1444 1445 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 1446 ifp->if_oerrors++; 1447 smc91cxx_reset(sc); 1448 } 1449 1450 /* 1451 * Stop output on the interface. 1452 */ 1453 void 1454 smc91cxx_stop(struct smc91cxx_softc *sc) 1455 { 1456 bus_space_tag_t bst = sc->sc_bst; 1457 bus_space_handle_t bsh = sc->sc_bsh; 1458 1459 /* 1460 * Clear interrupt mask; disable all interrupts. 1461 */ 1462 SMC_SELECT_BANK(sc, 2); 1463 smc91cxx_intr_mask_write(bst, bsh, 0); 1464 1465 /* 1466 * Disable transmitter and receiver. 1467 */ 1468 SMC_SELECT_BANK(sc, 0); 1469 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1470 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1471 1472 /* 1473 * Cancel watchdog timer. 1474 */ 1475 sc->sc_ec.ec_if.if_timer = 0; 1476 } 1477 1478 /* 1479 * Enable power on the interface. 1480 */ 1481 int 1482 smc91cxx_enable(struct smc91cxx_softc *sc) 1483 { 1484 1485 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1486 if ((*sc->sc_enable)(sc) != 0) { 1487 aprint_error_dev(&sc->sc_dev, "device enable failed\n"); 1488 return (EIO); 1489 } 1490 } 1491 1492 sc->sc_flags |= SMC_FLAGS_ENABLED; 1493 return (0); 1494 } 1495 1496 /* 1497 * Disable power on the interface. 1498 */ 1499 void 1500 smc91cxx_disable(struct smc91cxx_softc *sc) 1501 { 1502 1503 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1504 (*sc->sc_disable)(sc); 1505 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1506 } 1507 } 1508 1509 int 1510 smc91cxx_activate(device_t self, enum devact act) 1511 { 1512 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1513 int rv = 0, s; 1514 1515 s = splnet(); 1516 switch (act) { 1517 case DVACT_ACTIVATE: 1518 rv = EOPNOTSUPP; 1519 break; 1520 1521 case DVACT_DEACTIVATE: 1522 if_deactivate(&sc->sc_ec.ec_if); 1523 break; 1524 } 1525 splx(s); 1526 return (rv); 1527 } 1528 1529 int 1530 smc91cxx_detach(device_t self, int flags) 1531 { 1532 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1533 struct ifnet *ifp = &sc->sc_ec.ec_if; 1534 1535 /* Succeed now if there's no work to do. */ 1536 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1537 return (0); 1538 1539 1540 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1541 smc91cxx_disable(sc); 1542 1543 /* smc91cxx_attach() never fails */ 1544 1545 /* Delete all media. */ 1546 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1547 1548 #if NRND > 0 1549 rnd_detach_source(&sc->rnd_source); 1550 #endif 1551 ether_ifdetach(ifp); 1552 if_detach(ifp); 1553 1554 return (0); 1555 } 1556 1557 u_int32_t 1558 smc91cxx_mii_bitbang_read(device_t self) 1559 { 1560 struct smc91cxx_softc *sc = (void *) self; 1561 1562 /* We're already in bank 3. */ 1563 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1564 } 1565 1566 void 1567 smc91cxx_mii_bitbang_write(device_t self, u_int32_t val) 1568 { 1569 struct smc91cxx_softc *sc = (void *) self; 1570 1571 /* We're already in bank 3. */ 1572 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1573 } 1574 1575 int 1576 smc91cxx_mii_readreg(device_t self, int phy, int reg) 1577 { 1578 struct smc91cxx_softc *sc = (void *) self; 1579 int val; 1580 1581 SMC_SELECT_BANK(sc, 3); 1582 1583 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1584 1585 SMC_SELECT_BANK(sc, 2); 1586 1587 return (val); 1588 } 1589 1590 void 1591 smc91cxx_mii_writereg(device_t self, int phy, int reg, int val) 1592 { 1593 struct smc91cxx_softc *sc = (void *) self; 1594 1595 SMC_SELECT_BANK(sc, 3); 1596 1597 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1598 1599 SMC_SELECT_BANK(sc, 2); 1600 } 1601 1602 void 1603 smc91cxx_statchg(device_t self) 1604 { 1605 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1606 bus_space_tag_t bst = sc->sc_bst; 1607 bus_space_handle_t bsh = sc->sc_bsh; 1608 int mctl; 1609 1610 SMC_SELECT_BANK(sc, 0); 1611 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1612 if (sc->sc_mii.mii_media_active & IFM_FDX) 1613 mctl |= TCR_SWFDUP; 1614 else 1615 mctl &= ~TCR_SWFDUP; 1616 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1617 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1618 } 1619 1620 /* 1621 * One second timer, used to tick the MII. 1622 */ 1623 void 1624 smc91cxx_tick(void *arg) 1625 { 1626 struct smc91cxx_softc *sc = arg; 1627 int s; 1628 1629 #ifdef DIAGNOSTIC 1630 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1631 panic("smc91cxx_tick"); 1632 #endif 1633 1634 if (!device_is_active(&sc->sc_dev)) 1635 return; 1636 1637 s = splnet(); 1638 mii_tick(&sc->sc_mii); 1639 splx(s); 1640 1641 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1642 } 1643 1644
Indexes created Sun Sep 21 20:09:37 GMT 2025