smc91cxx.c revision 1.86
1 /* $NetBSD: smc91cxx.c,v 1.86 2013/09/08 14:27:39 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Gardner Buchanan <gbuchanan (at) shl.com> 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Gardner Buchanan. 48 * 4. The name of Gardner Buchanan may not be used to endorse or promote 49 * products derived from this software without specific prior written 50 * permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 64 */ 65 66 /* 67 * Core driver for the SMC 91Cxx family of Ethernet chips. 68 * 69 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 70 * written for NetBSD/amiga by Michael Hitch. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.86 2013/09/08 14:27:39 chs Exp $"); 75 76 #include "opt_inet.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/mbuf.h> 81 #include <sys/syslog.h> 82 #include <sys/socket.h> 83 #include <sys/device.h> 84 #include <sys/kernel.h> 85 #include <sys/malloc.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/rnd.h> 89 90 #include <sys/bus.h> 91 #include <sys/intr.h> 92 93 #include <net/if.h> 94 #include <net/if_dl.h> 95 #include <net/if_ether.h> 96 #include <net/if_media.h> 97 98 #ifdef INET 99 #include <netinet/in.h> 100 #include <netinet/if_inarp.h> 101 #include <netinet/in_systm.h> 102 #include <netinet/in_var.h> 103 #include <netinet/ip.h> 104 #endif 105 106 #include <net/bpf.h> 107 #include <net/bpfdesc.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 #include <dev/mii/mii_bitbang.h> 112 113 #include <dev/ic/smc91cxxreg.h> 114 #include <dev/ic/smc91cxxvar.h> 115 116 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 117 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 118 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 119 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 120 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 121 122 #define bus_space_write_stream_4 bus_space_write_4 123 #define bus_space_read_stream_4 bus_space_read_4 124 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 125 126 /* XXX Hardware padding doesn't work yet(?) */ 127 #define SMC91CXX_SW_PAD 128 129 const char *smc91cxx_idstrs[] = { 130 NULL, /* 0 */ 131 NULL, /* 1 */ 132 NULL, /* 2 */ 133 "SMC91C90/91C92", /* 3 */ 134 "SMC91C94/91C96", /* 4 */ 135 "SMC91C95", /* 5 */ 136 NULL, /* 6 */ 137 "SMC91C100", /* 7 */ 138 "SMC91C100FD", /* 8 */ 139 "SMC91C111", /* 9 */ 140 NULL, /* 10 */ 141 NULL, /* 11 */ 142 NULL, /* 12 */ 143 NULL, /* 13 */ 144 NULL, /* 14 */ 145 NULL, /* 15 */ 146 }; 147 148 /* Supported media types. */ 149 static const int smc91cxx_media[] = { 150 IFM_ETHER|IFM_10_T, 151 IFM_ETHER|IFM_10_5, 152 }; 153 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 154 155 /* 156 * MII bit-bang glue. 157 */ 158 u_int32_t smc91cxx_mii_bitbang_read(device_t); 159 void smc91cxx_mii_bitbang_write(device_t, u_int32_t); 160 161 static const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 162 smc91cxx_mii_bitbang_read, 163 smc91cxx_mii_bitbang_write, 164 { 165 MR_MDO, /* MII_BIT_MDO */ 166 MR_MDI, /* MII_BIT_MDI */ 167 MR_MCLK, /* MII_BIT_MDC */ 168 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 169 0, /* MII_BIT_DIR_PHY_HOST */ 170 } 171 }; 172 173 /* MII callbacks */ 174 int smc91cxx_mii_readreg(device_t, int, int); 175 void smc91cxx_mii_writereg(device_t, int, int, int); 176 void smc91cxx_statchg(struct ifnet *); 177 void smc91cxx_tick(void *); 178 179 int smc91cxx_mediachange(struct ifnet *); 180 void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *); 181 182 int smc91cxx_set_media(struct smc91cxx_softc *, int); 183 184 void smc91cxx_init(struct smc91cxx_softc *); 185 void smc91cxx_read(struct smc91cxx_softc *); 186 void smc91cxx_reset(struct smc91cxx_softc *); 187 void smc91cxx_start(struct ifnet *); 188 uint8_t smc91cxx_copy_tx_frame(struct smc91cxx_softc *, struct mbuf *); 189 void smc91cxx_resume(struct smc91cxx_softc *); 190 void smc91cxx_stop(struct smc91cxx_softc *); 191 void smc91cxx_watchdog(struct ifnet *); 192 int smc91cxx_ioctl(struct ifnet *, u_long, void *); 193 194 static inline int ether_cmp(const void *, const void *); 195 static inline int 196 ether_cmp(const void *va, const void *vb) 197 { 198 const u_int8_t *a = va; 199 const u_int8_t *b = vb; 200 201 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 202 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 203 } 204 205 static inline void 206 smc91cxx_intr_mask_write(bus_space_tag_t bst, bus_space_handle_t bsh, 207 uint8_t mask) 208 { 209 KDASSERT((mask & IM_ERCV_INT) == 0); 210 #ifdef SMC91CXX_NO_BYTE_WRITE 211 bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask << 8); 212 #else 213 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 214 #endif 215 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 216 } 217 218 static inline void 219 smc91cxx_intr_ack_write(bus_space_tag_t bst, bus_space_handle_t bsh, 220 uint8_t ack, uint8_t mask) 221 { 222 #ifdef SMC91CXX_NO_BYTE_WRITE 223 bus_space_write_2(bst, bsh, INTR_ACK_REG_B, ack | (mask << 8)); 224 #else 225 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, ack); 226 #endif 227 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 228 } 229 230 void 231 smc91cxx_attach(struct smc91cxx_softc *sc, u_int8_t *myea) 232 { 233 struct ifnet *ifp = &sc->sc_ec.ec_if; 234 bus_space_tag_t bst = sc->sc_bst; 235 bus_space_handle_t bsh = sc->sc_bsh; 236 struct ifmedia *ifm = &sc->sc_mii.mii_media; 237 const char *idstr; 238 u_int32_t miicapabilities; 239 u_int16_t tmp; 240 u_int8_t enaddr[ETHER_ADDR_LEN]; 241 int i, aui, mult, scale, memsize; 242 char pbuf[9]; 243 244 tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W); 245 /* check magic number */ 246 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 247 aprint_error_dev(sc->sc_dev, 248 "failed to detect chip, bsr=%04x\n", tmp); 249 return; 250 } 251 252 /* Make sure the chip is stopped. */ 253 smc91cxx_stop(sc); 254 255 SMC_SELECT_BANK(sc, 3); 256 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 257 sc->sc_chipid = RR_ID(tmp); 258 idstr = smc91cxx_idstrs[sc->sc_chipid]; 259 260 aprint_normal_dev(sc->sc_dev, ""); 261 if (idstr != NULL) 262 aprint_normal("%s, ", idstr); 263 else 264 aprint_normal("unknown chip id %d, ", sc->sc_chipid); 265 aprint_normal("revision %d, ", RR_REV(tmp)); 266 267 SMC_SELECT_BANK(sc, 0); 268 switch (sc->sc_chipid) { 269 default: 270 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 271 scale = MIR_SCALE_91C9x; 272 break; 273 274 case CHIP_91C111: 275 mult = MIR_MULT_91C111; 276 scale = MIR_SCALE_91C111; 277 } 278 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 279 if (memsize == 255) 280 memsize++; 281 memsize *= scale * mult; 282 283 format_bytes(pbuf, sizeof(pbuf), memsize); 284 aprint_normal("buffer size: %s\n", pbuf); 285 286 /* Read the station address from the chip. */ 287 SMC_SELECT_BANK(sc, 1); 288 if (myea == NULL) { 289 myea = enaddr; 290 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 291 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 292 myea[i + 1] = (tmp >> 8) & 0xff; 293 myea[i] = tmp & 0xff; 294 } 295 } 296 aprint_normal_dev(sc->sc_dev, "MAC address %s, ", 297 ether_sprintf(myea)); 298 299 /* Initialize the ifnet structure. */ 300 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 301 ifp->if_softc = sc; 302 ifp->if_start = smc91cxx_start; 303 ifp->if_ioctl = smc91cxx_ioctl; 304 ifp->if_watchdog = smc91cxx_watchdog; 305 ifp->if_flags = 306 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 307 IFQ_SET_READY(&ifp->if_snd); 308 309 /* Attach the interface. */ 310 if_attach(ifp); 311 ether_ifattach(ifp, myea); 312 313 /* 314 * Initialize our media structures and MII info. We will 315 * probe the MII if we are on the SMC91Cxx 316 */ 317 sc->sc_mii.mii_ifp = ifp; 318 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 319 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 320 sc->sc_mii.mii_statchg = smc91cxx_statchg; 321 ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, smc91cxx_mediastatus); 322 323 SMC_SELECT_BANK(sc, 1); 324 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 325 326 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 327 switch (sc->sc_chipid) { 328 case CHIP_91100: 329 /* 330 * The 91100 does not have full-duplex capabilities, 331 * even if the PHY does. 332 */ 333 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 334 case CHIP_91100FD: 335 case CHIP_91C111: 336 if (tmp & CR_MII_SELECT) { 337 aprint_normal("default media MII"); 338 if (sc->sc_chipid == CHIP_91C111) { 339 aprint_normal(" (%s PHY)\n", 340 (tmp & CR_AUI_SELECT) ? 341 "external" : "internal"); 342 sc->sc_internal_phy = !(tmp & CR_AUI_SELECT); 343 } else 344 aprint_normal("\n"); 345 mii_attach(sc->sc_dev, &sc->sc_mii, miicapabilities, 346 MII_PHY_ANY, MII_OFFSET_ANY, 0); 347 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 348 ifmedia_add(&sc->sc_mii.mii_media, 349 IFM_ETHER|IFM_NONE, 0, NULL); 350 ifmedia_set(&sc->sc_mii.mii_media, 351 IFM_ETHER|IFM_NONE); 352 } else { 353 ifmedia_set(&sc->sc_mii.mii_media, 354 IFM_ETHER|IFM_AUTO); 355 } 356 sc->sc_flags |= SMC_FLAGS_HAS_MII; 357 break; 358 } else 359 if (sc->sc_chipid == CHIP_91C111) { 360 /* 361 * XXX: Should bring it out of low-power mode 362 */ 363 aprint_normal("EPH interface in low power mode\n"); 364 sc->sc_internal_phy = 0; 365 return; 366 } 367 /*FALLTHROUGH*/ 368 default: 369 aprint_normal("default media %s\n", 370 (aui = (tmp & CR_AUI_SELECT)) ? 371 "AUI" : "UTP"); 372 for (i = 0; i < NSMC91CxxMEDIA; i++) 373 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 374 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 375 break; 376 } 377 378 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 379 RND_TYPE_NET, 0); 380 381 callout_init(&sc->sc_mii_callout, 0); 382 383 /* The attach is successful. */ 384 sc->sc_flags |= SMC_FLAGS_ATTACHED; 385 } 386 387 /* 388 * Change media according to request. 389 */ 390 int 391 smc91cxx_mediachange(struct ifnet *ifp) 392 { 393 struct smc91cxx_softc *sc = ifp->if_softc; 394 395 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 396 } 397 398 int 399 smc91cxx_set_media(struct smc91cxx_softc *sc, int media) 400 { 401 bus_space_tag_t bst = sc->sc_bst; 402 bus_space_handle_t bsh = sc->sc_bsh; 403 u_int16_t tmp; 404 int rc; 405 406 /* 407 * If the interface is not currently powered on, just return. 408 * When it is enabled later, smc91cxx_init() will properly set 409 * up the media for us. 410 */ 411 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 412 return (0); 413 414 if (IFM_TYPE(media) != IFM_ETHER) 415 return (EINVAL); 416 417 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0 || 418 (rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 419 rc = 0; 420 421 switch (IFM_SUBTYPE(media)) { 422 case IFM_10_T: 423 case IFM_10_5: 424 SMC_SELECT_BANK(sc, 1); 425 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 426 if (IFM_SUBTYPE(media) == IFM_10_5) 427 tmp |= CR_AUI_SELECT; 428 else 429 tmp &= ~CR_AUI_SELECT; 430 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 431 delay(20000); /* XXX is this needed? */ 432 break; 433 434 default: 435 return (EINVAL); 436 } 437 438 return rc; 439 } 440 441 /* 442 * Notify the world which media we're using. 443 */ 444 void 445 smc91cxx_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 446 { 447 struct smc91cxx_softc *sc = ifp->if_softc; 448 bus_space_tag_t bst = sc->sc_bst; 449 bus_space_handle_t bsh = sc->sc_bsh; 450 u_int16_t tmp; 451 452 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 453 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 454 ifmr->ifm_status = 0; 455 return; 456 } 457 458 /* 459 * If we have MII, go ask the PHY what's going on. 460 */ 461 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 462 mii_pollstat(&sc->sc_mii); 463 ifmr->ifm_active = sc->sc_mii.mii_media_active; 464 ifmr->ifm_status = sc->sc_mii.mii_media_status; 465 return; 466 } 467 468 SMC_SELECT_BANK(sc, 1); 469 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 470 ifmr->ifm_active = 471 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 472 } 473 474 /* 475 * Reset and initialize the chip. 476 */ 477 void 478 smc91cxx_init(struct smc91cxx_softc *sc) 479 { 480 struct ifnet *ifp = &sc->sc_ec.ec_if; 481 bus_space_tag_t bst = sc->sc_bst; 482 bus_space_handle_t bsh = sc->sc_bsh; 483 u_int16_t tmp; 484 const u_int8_t *enaddr; 485 int s, i; 486 487 s = splnet(); 488 489 /* 490 * This resets the registers mostly to defaults, but doesn't 491 * affect the EEPROM. The longest reset recovery time of those devices 492 * supported is the 91C111. Section 7.8 of its datasheet asks for 50ms. 493 */ 494 SMC_SELECT_BANK(sc, 0); 495 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 496 delay(5); 497 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 498 delay(50000); 499 500 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 501 502 /* Set the Ethernet address. */ 503 SMC_SELECT_BANK(sc, 1); 504 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 505 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 506 tmp = enaddr[i + 1] << 8 | enaddr[i]; 507 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 508 } 509 510 /* 511 * Set the control register to automatically release successfully 512 * transmitted packets (making the best use of our limited memory) 513 * and enable the EPH interrupt on certain TX errors. 514 */ 515 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 516 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 517 518 /* 519 * Reset the MMU and wait for it to be un-busy. 520 */ 521 SMC_SELECT_BANK(sc, 2); 522 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 523 sc->sc_txpacketno = ARR_FAILED; 524 for (;;) { 525 tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W); 526 if (tmp == 0xffff) /* card went away! */ 527 return; 528 if ((tmp & MMUCR_BUSY) == 0) 529 break; 530 } 531 532 /* 533 * Disable all interrupts. 534 */ 535 smc91cxx_intr_mask_write(bst, bsh, 0); 536 537 /* 538 * On the 91c111, enable auto-negotiation, and set the LED 539 * status pins to something sane. 540 * XXX: Should be some way for MD code to decide the latter. 541 */ 542 SMC_SELECT_BANK(sc, 0); 543 if (sc->sc_chipid == CHIP_91C111) { 544 bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W, 545 RPC_ANEG | 546 (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) | 547 (RPC_LS_TXRX << RPC_LSB_SHIFT)); 548 } 549 550 /* 551 * Set current media. 552 */ 553 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 554 555 /* 556 * Set the receive filter. We want receive enable and auto 557 * strip of CRC from received packet. If we are in promisc. mode, 558 * then set that bit as well. 559 * 560 * XXX Initialize multicast filter. For now, we just accept 561 * XXX all multicast. 562 */ 563 SMC_SELECT_BANK(sc, 0); 564 565 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 566 if (ifp->if_flags & IFF_PROMISC) 567 tmp |= RCR_PROMISC; 568 569 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 570 571 /* 572 * Set transmitter control to "enabled". 573 */ 574 tmp = TCR_ENABLE; 575 576 #ifndef SMC91CXX_SW_PAD 577 /* 578 * Enable hardware padding of transmitted packets. 579 * XXX doesn't work? 580 */ 581 tmp |= TCR_PAD_ENABLE; 582 #endif 583 584 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 585 586 /* 587 * Now, enable interrupts. 588 */ 589 SMC_SELECT_BANK(sc, 2); 590 591 sc->sc_intmask = IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT; 592 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) { 593 sc->sc_intmask |= IM_MD_INT; 594 } 595 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 596 597 /* Interface is now running, with no output active. */ 598 ifp->if_flags |= IFF_RUNNING; 599 ifp->if_flags &= ~IFF_OACTIVE; 600 601 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 602 /* Start the one second clock. */ 603 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 604 } 605 606 /* 607 * Attempt to start any pending transmission. 608 */ 609 smc91cxx_start(ifp); 610 611 splx(s); 612 } 613 614 /* 615 * Start output on an interface. 616 * Must be called at splnet or interrupt level. 617 */ 618 void 619 smc91cxx_start(struct ifnet *ifp) 620 { 621 struct smc91cxx_softc *sc = ifp->if_softc; 622 bus_space_tag_t bst = sc->sc_bst; 623 bus_space_handle_t bsh = sc->sc_bsh; 624 u_int len; 625 struct mbuf *m; 626 u_int16_t length, npages; 627 u_int16_t oddbyte; 628 u_int8_t packetno; 629 int timo, pad; 630 631 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 632 return; 633 634 again: 635 /* 636 * Peek at the next packet. 637 */ 638 IFQ_POLL(&ifp->if_snd, m); 639 if (m == NULL) 640 return; 641 642 /* 643 * Compute the frame length and set pad to give an overall even 644 * number of bytes. Below, we assume that the packet length 645 * is even. 646 */ 647 for (len = 0; m != NULL; m = m->m_next) 648 len += m->m_len; 649 650 /* 651 * We drop packets that are too large. Perhaps we should 652 * truncate them instead? 653 */ 654 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 655 printf("%s: large packet discarded\n", 656 device_xname(sc->sc_dev)); 657 ifp->if_oerrors++; 658 IFQ_DEQUEUE(&ifp->if_snd, m); 659 m_freem(m); 660 goto readcheck; 661 } 662 663 pad = 0; 664 #ifdef SMC91CXX_SW_PAD 665 /* 666 * Not using hardware padding; pad to ETHER_MIN_LEN. 667 */ 668 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 669 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 670 #endif 671 672 length = pad + len; 673 674 /* 675 * The MMU has a 256 byte page size. The MMU expects us to 676 * ask for "npages - 1". We include space for the status word, 677 * byte count, and control bytes in the allocation request. 678 */ 679 npages = ((length & ~1) + 6) >> 8; 680 681 /* 682 * Now allocate the memory. 683 */ 684 SMC_SELECT_BANK(sc, 2); 685 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 686 687 timo = MEMORY_WAIT_TIME; 688 if (__predict_false((sc->sc_txpacketno & ARR_FAILED) == 0)) { 689 packetno = sc->sc_txpacketno; 690 sc->sc_txpacketno = ARR_FAILED; 691 } else { 692 do { 693 if (bus_space_read_1(bst, bsh, 694 INTR_STAT_REG_B) & IM_ALLOC_INT) 695 break; 696 delay(1); 697 } while (--timo); 698 } 699 700 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 701 702 if (packetno & ARR_FAILED || timo == 0) { 703 /* 704 * No transmit memory is available. Record the number 705 * of requested pages and enable the allocation completion 706 * interrupt. Set up the watchdog timer in case we miss 707 * the interrupt. Mark the interface as active so that 708 * no one else attempts to transmit while we're allocating 709 * memory. 710 */ 711 sc->sc_intmask |= IM_ALLOC_INT; 712 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 713 ifp->if_timer = 5; 714 ifp->if_flags |= IFF_OACTIVE; 715 716 return; 717 } 718 719 /* 720 * We have a packet number - set the data window. 721 */ 722 bus_space_write_2(bst, bsh, PACKET_NUM_REG_B, packetno); 723 724 /* 725 * Point to the beginning of the packet. 726 */ 727 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 728 729 /* 730 * Send the packet length (+6 for stats, length, and control bytes) 731 * and the status word (set to zeros). 732 */ 733 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 734 bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff); 735 736 /* 737 * Get the packet from the kernel. This will include the Ethernet 738 * frame header, MAC address, etc. 739 */ 740 IFQ_DEQUEUE(&ifp->if_snd, m); 741 742 /* 743 * Push the packet out to the card. The copying function only does 744 * whole words and returns the straggling byte (if any). 745 */ 746 oddbyte = smc91cxx_copy_tx_frame(sc, m); 747 748 #ifdef SMC91CXX_SW_PAD 749 if (pad > 1 && (pad & 1)) { 750 bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte); 751 oddbyte = 0; 752 pad -= 1; 753 } 754 755 /* 756 * Push out padding. 757 */ 758 while (pad > 1) { 759 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 760 pad -= 2; 761 } 762 #endif 763 764 /* 765 * Push out control byte and unused packet byte. The control byte 766 * denotes whether this is an odd or even length packet, and that 767 * no special CRC handling is necessary. 768 */ 769 bus_space_write_2(bst, bsh, DATA_REG_W, 770 oddbyte | ((length & 1) ? (CTLB_ODD << 8) : 0)); 771 772 /* 773 * Enable transmit interrupts and let the chip go. Set a watchdog 774 * in case we miss the interrupt. 775 */ 776 sc->sc_intmask |= IM_TX_INT | IM_TX_EMPTY_INT; 777 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 778 779 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 780 781 ifp->if_timer = 5; 782 783 /* Hand off a copy to the bpf. */ 784 bpf_mtap(ifp, m); 785 786 ifp->if_opackets++; 787 m_freem(m); 788 789 readcheck: 790 /* 791 * Check for incoming packets. We don't want to overflow the small 792 * RX FIFO. If nothing has arrived, attempt to queue another 793 * transmit packet. 794 */ 795 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 796 goto again; 797 } 798 799 /* 800 * Squirt a (possibly misaligned) mbuf to the device 801 */ 802 uint8_t 803 smc91cxx_copy_tx_frame(struct smc91cxx_softc *sc, struct mbuf *m0) 804 { 805 bus_space_tag_t bst = sc->sc_bst; 806 bus_space_handle_t bsh = sc->sc_bsh; 807 struct mbuf *m; 808 int len, leftover; 809 u_int16_t dbuf; 810 u_int8_t *p; 811 #ifdef DIAGNOSTIC 812 u_int8_t *lim; 813 #endif 814 815 /* start out with no leftover data */ 816 leftover = 0; 817 dbuf = 0; 818 819 /* Process the chain of mbufs */ 820 for (m = m0; m != NULL; m = m->m_next) { 821 /* 822 * Process all of the data in a single mbuf. 823 */ 824 p = mtod(m, u_int8_t *); 825 len = m->m_len; 826 #ifdef DIAGNOSTIC 827 lim = p + len; 828 #endif 829 830 while (len > 0) { 831 if (leftover) { 832 /* 833 * Data left over (from mbuf or realignment). 834 * Buffer the next byte, and write it and 835 * the leftover data out. 836 */ 837 dbuf |= *p++ << 8; 838 len--; 839 bus_space_write_2(bst, bsh, DATA_REG_W, dbuf); 840 leftover = 0; 841 } else if ((long) p & 1) { 842 /* 843 * Misaligned data. Buffer the next byte. 844 */ 845 dbuf = *p++; 846 len--; 847 leftover = 1; 848 } else { 849 /* 850 * Aligned data. This is the case we like. 851 * 852 * Write-region out as much as we can, then 853 * buffer the remaining byte (if any). 854 */ 855 leftover = len & 1; 856 len &= ~1; 857 bus_space_write_multi_stream_2(bst, bsh, 858 DATA_REG_W, (u_int16_t *)p, len >> 1); 859 p += len; 860 861 if (leftover) 862 dbuf = *p++; 863 len = 0; 864 } 865 } 866 if (len < 0) 867 panic("smc91cxx_copy_tx_frame: negative len"); 868 #ifdef DIAGNOSTIC 869 if (p != lim) 870 panic("smc91cxx_copy_tx_frame: p != lim"); 871 #endif 872 } 873 874 return dbuf; 875 } 876 877 /* 878 * Interrupt service routine. 879 */ 880 int 881 smc91cxx_intr(void *arg) 882 { 883 struct smc91cxx_softc *sc = arg; 884 struct ifnet *ifp = &sc->sc_ec.ec_if; 885 bus_space_tag_t bst = sc->sc_bst; 886 bus_space_handle_t bsh = sc->sc_bsh; 887 u_int8_t mask, interrupts, status; 888 u_int16_t packetno, tx_status, card_stats; 889 u_int16_t v; 890 891 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 892 !device_is_active(sc->sc_dev)) 893 return (0); 894 895 SMC_SELECT_BANK(sc, 2); 896 897 /* 898 * Obtain the current interrupt status and mask. 899 */ 900 v = bus_space_read_2(bst, bsh, INTR_STAT_REG_B); 901 902 /* 903 * Get the set of interrupt which occurred and eliminate any 904 * which are not enabled. 905 */ 906 mask = v >> 8; 907 interrupts = v & 0xff; 908 KDASSERT(mask == sc->sc_intmask); 909 status = interrupts & mask; 910 911 /* Ours? */ 912 if (status == 0) 913 return (0); 914 915 /* 916 * It's ours; disable all interrupts while we process them. 917 */ 918 smc91cxx_intr_mask_write(bst, bsh, 0); 919 920 /* 921 * Receive overrun interrupts. 922 */ 923 if (status & IM_RX_OVRN_INT) { 924 smc91cxx_intr_ack_write(bst, bsh, IM_RX_OVRN_INT, 0); 925 ifp->if_ierrors++; 926 } 927 928 /* 929 * Receive interrupts. 930 */ 931 if (status & IM_RCV_INT) { 932 smc91cxx_read(sc); 933 } 934 935 /* 936 * Memory allocation interrupts. 937 */ 938 if (status & IM_ALLOC_INT) { 939 /* Disable this interrupt. */ 940 mask &= ~IM_ALLOC_INT; 941 sc->sc_intmask &= ~IM_ALLOC_INT; 942 943 /* 944 * Save allocated packet number for use in start 945 */ 946 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 947 KASSERT(sc->sc_txpacketno & ARR_FAILED); 948 sc->sc_txpacketno = packetno; 949 950 /* 951 * We can transmit again! 952 */ 953 ifp->if_flags &= ~IFF_OACTIVE; 954 ifp->if_timer = 0; 955 } 956 957 /* 958 * Transmit complete interrupt. Handle transmission error messages. 959 * This will only be called on error condition because of AUTO RELEASE 960 * mode. 961 */ 962 if (status & IM_TX_INT) { 963 smc91cxx_intr_ack_write(bst, bsh, IM_TX_INT, 0); 964 965 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 966 FIFO_TX_MASK; 967 968 /* 969 * Select this as the packet to read from. 970 */ 971 bus_space_write_2(bst, bsh, PACKET_NUM_REG_B, packetno); 972 973 /* 974 * Position the pointer to the beginning of the packet, wait 975 * for preload. 976 */ 977 bus_space_write_2(bst, bsh, POINTER_REG_W, 978 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 979 delay(1); 980 981 /* 982 * Fetch the TX status word. This will be a copy of 983 * the EPH_STATUS_REG_W at the time of the transmission 984 * failure. 985 */ 986 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 987 988 if (tx_status & EPHSR_TX_SUC) { 989 static struct timeval txsuc_last; 990 static int txsuc_count; 991 if (ppsratecheck(&txsuc_last, &txsuc_count, 1)) 992 printf("%s: successful packet caused TX" 993 " interrupt?!\n", device_xname(sc->sc_dev)); 994 } else 995 ifp->if_oerrors++; 996 997 if (tx_status & EPHSR_LATCOL) 998 ifp->if_collisions++; 999 1000 /* Disable this interrupt (start will reenable if needed). */ 1001 mask &= ~IM_TX_INT; 1002 sc->sc_intmask &= ~IM_TX_INT; 1003 1004 /* 1005 * Some of these errors disable the transmitter; reenable it. 1006 */ 1007 SMC_SELECT_BANK(sc, 0); 1008 #ifdef SMC91CXX_SW_PAD 1009 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 1010 #else 1011 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 1012 TCR_ENABLE | TCR_PAD_ENABLE); 1013 #endif 1014 1015 /* 1016 * Kill the failed packet and wait for the MMU to unbusy. 1017 */ 1018 SMC_SELECT_BANK(sc, 2); 1019 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1020 /* XXX bound this loop! */ ; 1021 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 1022 1023 ifp->if_timer = 0; 1024 } 1025 1026 /* 1027 * Transmit underrun interrupts. We use this opportunity to 1028 * update transmit statistics from the card. 1029 */ 1030 if (status & IM_TX_EMPTY_INT) { 1031 smc91cxx_intr_ack_write(bst, bsh, IM_TX_EMPTY_INT, 0); 1032 1033 /* Disable this interrupt. */ 1034 mask &= ~IM_TX_EMPTY_INT; 1035 sc->sc_intmask &= ~IM_TX_EMPTY_INT; 1036 1037 SMC_SELECT_BANK(sc, 0); 1038 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 1039 1040 /* Single collisions. */ 1041 ifp->if_collisions += card_stats & ECR_COLN_MASK; 1042 1043 /* Multiple collisions. */ 1044 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 1045 1046 SMC_SELECT_BANK(sc, 2); 1047 1048 ifp->if_timer = 0; 1049 } 1050 1051 /* 1052 * Internal PHY status change 1053 */ 1054 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy && 1055 (status & IM_MD_INT)) { 1056 1057 /* 1058 * Internal PHY status change 1059 */ 1060 smc91cxx_intr_ack_write(bst, bsh, IM_MD_INT, 0); 1061 mii_pollstat(&sc->sc_mii); 1062 } 1063 1064 /* 1065 * Other errors. Reset the interface. 1066 */ 1067 if (status & IM_EPH_INT) { 1068 smc91cxx_stop(sc); 1069 smc91cxx_init(sc); 1070 } 1071 1072 /* 1073 * Attempt to queue more packets for transmission. 1074 */ 1075 smc91cxx_start(ifp); 1076 1077 /* 1078 * Reenable the interrupts we wish to receive now that processing 1079 * is complete. 1080 */ 1081 mask |= sc->sc_intmask; 1082 smc91cxx_intr_mask_write(bst, bsh, mask); 1083 1084 if (status) 1085 rnd_add_uint32(&sc->rnd_source, status); 1086 1087 return (1); 1088 } 1089 1090 /* 1091 * Read a packet from the card and pass it up to the kernel. 1092 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 1093 */ 1094 void 1095 smc91cxx_read(struct smc91cxx_softc *sc) 1096 { 1097 struct ifnet *ifp = &sc->sc_ec.ec_if; 1098 bus_space_tag_t bst = sc->sc_bst; 1099 bus_space_handle_t bsh = sc->sc_bsh; 1100 struct ether_header *eh; 1101 struct mbuf *m; 1102 u_int16_t status, packetno, packetlen; 1103 u_int8_t *data; 1104 u_int32_t dr; 1105 bool first = true; 1106 1107 again: 1108 /* 1109 * Set data pointer to the beginning of the packet. Since 1110 * PTR_RCV is set, the packet number will be found automatically 1111 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1112 */ 1113 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1114 if (packetno & FIFO_REMPTY) { 1115 if (first) { 1116 aprint_error_dev(sc->sc_dev, 1117 "receive interrupt on empty fifo\n"); 1118 } 1119 return; 1120 } 1121 first = false; 1122 1123 bus_space_write_2(bst, bsh, POINTER_REG_W, 1124 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 1125 delay(1); 1126 1127 /* 1128 * First two words are status and packet length. 1129 */ 1130 dr = bus_space_read_4(bst, bsh, DATA_REG_W); 1131 status = (u_int16_t)dr; 1132 packetlen = (u_int16_t)(dr >> 16); 1133 1134 packetlen &= RLEN_MASK; 1135 if (packetlen < ETHER_MIN_LEN - ETHER_CRC_LEN + 6 || packetlen > 1534) { 1136 ifp->if_ierrors++; 1137 goto out; 1138 } 1139 1140 /* 1141 * The packet length includes 3 extra words: status, length, 1142 * and an extra word that includes the control byte. 1143 */ 1144 packetlen -= 6; 1145 1146 /* 1147 * Account for receive errors and discard. 1148 */ 1149 if (status & RS_ERRORS) { 1150 ifp->if_ierrors++; 1151 goto out; 1152 } 1153 1154 /* 1155 * Adjust for odd-length packet. 1156 */ 1157 if (status & RS_ODDFRAME) 1158 packetlen++; 1159 1160 /* 1161 * Allocate a header mbuf. 1162 */ 1163 MGETHDR(m, M_DONTWAIT, MT_DATA); 1164 if (m == NULL) 1165 goto out; 1166 m->m_pkthdr.rcvif = ifp; 1167 m->m_pkthdr.len = packetlen; 1168 1169 /* 1170 * Always put the packet in a cluster. 1171 * XXX should chain small mbufs if less than threshold. 1172 */ 1173 MCLGET(m, M_DONTWAIT); 1174 if ((m->m_flags & M_EXT) == 0) { 1175 m_freem(m); 1176 ifp->if_ierrors++; 1177 aprint_error_dev(sc->sc_dev, 1178 "can't allocate cluster for incoming packet\n"); 1179 goto out; 1180 } 1181 1182 /* 1183 * Pull the packet off the interface. Make sure the payload 1184 * is aligned. 1185 */ 1186 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1187 m->m_data = (char *) ALIGN(mtod(m, char *) + 1188 sizeof(struct ether_header)) - sizeof(struct ether_header); 1189 1190 eh = mtod(m, struct ether_header *); 1191 data = mtod(m, u_int8_t *); 1192 KASSERT(trunc_page((uintptr_t)data) == 1193 trunc_page((uintptr_t)data + packetlen - 1)); 1194 if (packetlen > 1) 1195 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 1196 (u_int16_t *)data, packetlen >> 1); 1197 if (packetlen & 1) { 1198 data += packetlen & ~1; 1199 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1200 } 1201 } else { 1202 m->m_data = (void *) ALIGN(mtod(m, void *)); 1203 eh = mtod(m, struct ether_header *); 1204 data = mtod(m, u_int8_t *); 1205 KASSERT(trunc_page((uintptr_t)data) == 1206 trunc_page((uintptr_t)data + packetlen - 1)); 1207 if (packetlen > 3) 1208 bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W, 1209 (u_int32_t *)data, packetlen >> 2); 1210 if (packetlen & 3) { 1211 data += packetlen & ~3; 1212 *((u_int32_t *)data) = 1213 bus_space_read_stream_4(bst, bsh, DATA_REG_W); 1214 } 1215 } 1216 1217 ifp->if_ipackets++; 1218 1219 /* 1220 * Make sure to behave as IFF_SIMPLEX in all cases. 1221 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1222 * loops back packets to itself on promiscuous mode. 1223 * (should be ensured by chipset configuration) 1224 */ 1225 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1226 /* 1227 * Drop packet looped back from myself. 1228 */ 1229 if (ether_cmp(eh->ether_shost, CLLADDR(ifp->if_sadl)) == 0) { 1230 m_freem(m); 1231 goto out; 1232 } 1233 } 1234 1235 m->m_pkthdr.len = m->m_len = packetlen; 1236 1237 /* 1238 * Hand the packet off to bpf listeners. 1239 */ 1240 bpf_mtap(ifp, m); 1241 1242 (*ifp->if_input)(ifp, m); 1243 1244 out: 1245 /* 1246 * Tell the card to free the memory occupied by this packet. 1247 */ 1248 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1249 /* XXX bound this loop! */ ; 1250 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1251 1252 /* 1253 * Check for another packet. 1254 */ 1255 goto again; 1256 } 1257 1258 /* 1259 * Process an ioctl request. 1260 */ 1261 int 1262 smc91cxx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1263 { 1264 struct smc91cxx_softc *sc = ifp->if_softc; 1265 struct ifaddr *ifa = (struct ifaddr *)data; 1266 struct ifreq *ifr = (struct ifreq *)data; 1267 int s, error = 0; 1268 1269 s = splnet(); 1270 1271 switch (cmd) { 1272 case SIOCINITIFADDR: 1273 if ((error = smc91cxx_enable(sc)) != 0) 1274 break; 1275 ifp->if_flags |= IFF_UP; 1276 smc91cxx_init(sc); 1277 switch (ifa->ifa_addr->sa_family) { 1278 #ifdef INET 1279 case AF_INET: 1280 arp_ifinit(ifp, ifa); 1281 break; 1282 #endif 1283 default: 1284 break; 1285 } 1286 break; 1287 1288 1289 case SIOCSIFFLAGS: 1290 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1291 break; 1292 /* XXX re-use ether_ioctl() */ 1293 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1294 case IFF_RUNNING: 1295 /* 1296 * If interface is marked down and it is running, 1297 * stop it. 1298 */ 1299 smc91cxx_stop(sc); 1300 ifp->if_flags &= ~IFF_RUNNING; 1301 smc91cxx_disable(sc); 1302 break; 1303 case IFF_UP: 1304 /* 1305 * If interface is marked up and it is stopped, 1306 * start it. 1307 */ 1308 if ((error = smc91cxx_enable(sc)) != 0) 1309 break; 1310 smc91cxx_init(sc); 1311 break; 1312 case IFF_UP|IFF_RUNNING: 1313 /* 1314 * Reset the interface to pick up changes in any 1315 * other flags that affect hardware registers. 1316 */ 1317 smc91cxx_reset(sc); 1318 break; 1319 case 0: 1320 break; 1321 } 1322 break; 1323 1324 case SIOCADDMULTI: 1325 case SIOCDELMULTI: 1326 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1327 error = EIO; 1328 break; 1329 } 1330 1331 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1332 /* 1333 * Multicast list has changed; set the hardware 1334 * filter accordingly. 1335 */ 1336 if (ifp->if_flags & IFF_RUNNING) 1337 smc91cxx_reset(sc); 1338 error = 0; 1339 } 1340 break; 1341 1342 case SIOCGIFMEDIA: 1343 case SIOCSIFMEDIA: 1344 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1345 break; 1346 1347 default: 1348 error = ether_ioctl(ifp, cmd, data); 1349 break; 1350 } 1351 1352 splx(s); 1353 return (error); 1354 } 1355 1356 /* 1357 * Reset the interface. 1358 */ 1359 void 1360 smc91cxx_reset(struct smc91cxx_softc *sc) 1361 { 1362 int s; 1363 1364 s = splnet(); 1365 smc91cxx_stop(sc); 1366 smc91cxx_init(sc); 1367 splx(s); 1368 } 1369 1370 /* 1371 * Watchdog timer. 1372 */ 1373 void 1374 smc91cxx_watchdog(struct ifnet *ifp) 1375 { 1376 struct smc91cxx_softc *sc = ifp->if_softc; 1377 1378 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1379 ifp->if_oerrors++; 1380 smc91cxx_reset(sc); 1381 } 1382 1383 /* 1384 * Stop output on the interface. 1385 */ 1386 void 1387 smc91cxx_stop(struct smc91cxx_softc *sc) 1388 { 1389 bus_space_tag_t bst = sc->sc_bst; 1390 bus_space_handle_t bsh = sc->sc_bsh; 1391 1392 /* 1393 * Clear interrupt mask; disable all interrupts. 1394 */ 1395 SMC_SELECT_BANK(sc, 2); 1396 smc91cxx_intr_mask_write(bst, bsh, 0); 1397 1398 /* 1399 * Disable transmitter and receiver. 1400 */ 1401 SMC_SELECT_BANK(sc, 0); 1402 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1403 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1404 1405 /* 1406 * Cancel watchdog timer. 1407 */ 1408 sc->sc_ec.ec_if.if_timer = 0; 1409 } 1410 1411 /* 1412 * Enable power on the interface. 1413 */ 1414 int 1415 smc91cxx_enable(struct smc91cxx_softc *sc) 1416 { 1417 1418 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1419 if ((*sc->sc_enable)(sc) != 0) { 1420 aprint_error_dev(sc->sc_dev, "device enable failed\n"); 1421 return (EIO); 1422 } 1423 } 1424 1425 sc->sc_flags |= SMC_FLAGS_ENABLED; 1426 return (0); 1427 } 1428 1429 /* 1430 * Disable power on the interface. 1431 */ 1432 void 1433 smc91cxx_disable(struct smc91cxx_softc *sc) 1434 { 1435 1436 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1437 (*sc->sc_disable)(sc); 1438 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1439 } 1440 } 1441 1442 int 1443 smc91cxx_activate(device_t self, enum devact act) 1444 { 1445 struct smc91cxx_softc *sc = device_private(self); 1446 1447 switch (act) { 1448 case DVACT_DEACTIVATE: 1449 if_deactivate(&sc->sc_ec.ec_if); 1450 return 0; 1451 default: 1452 return EOPNOTSUPP; 1453 } 1454 } 1455 1456 int 1457 smc91cxx_detach(device_t self, int flags) 1458 { 1459 struct smc91cxx_softc *sc = device_private(self); 1460 struct ifnet *ifp = &sc->sc_ec.ec_if; 1461 1462 /* Succeed now if there's no work to do. */ 1463 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1464 return (0); 1465 1466 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1467 smc91cxx_disable(sc); 1468 1469 /* smc91cxx_attach() never fails */ 1470 1471 /* Delete all media. */ 1472 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1473 1474 rnd_detach_source(&sc->rnd_source); 1475 1476 ether_ifdetach(ifp); 1477 if_detach(ifp); 1478 1479 return (0); 1480 } 1481 1482 u_int32_t 1483 smc91cxx_mii_bitbang_read(device_t self) 1484 { 1485 struct smc91cxx_softc *sc = device_private(self); 1486 1487 /* We're already in bank 3. */ 1488 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1489 } 1490 1491 void 1492 smc91cxx_mii_bitbang_write(device_t self, u_int32_t val) 1493 { 1494 struct smc91cxx_softc *sc = device_private(self); 1495 1496 /* We're already in bank 3. */ 1497 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1498 } 1499 1500 int 1501 smc91cxx_mii_readreg(device_t self, int phy, int reg) 1502 { 1503 struct smc91cxx_softc *sc = device_private(self); 1504 int val; 1505 1506 SMC_SELECT_BANK(sc, 3); 1507 1508 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1509 1510 SMC_SELECT_BANK(sc, 2); 1511 1512 return (val); 1513 } 1514 1515 void 1516 smc91cxx_mii_writereg(device_t self, int phy, int reg, int val) 1517 { 1518 struct smc91cxx_softc *sc = device_private(self); 1519 1520 SMC_SELECT_BANK(sc, 3); 1521 1522 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1523 1524 SMC_SELECT_BANK(sc, 2); 1525 } 1526 1527 void 1528 smc91cxx_statchg(struct ifnet *ifp) 1529 { 1530 struct smc91cxx_softc *sc = ifp->if_softc; 1531 bus_space_tag_t bst = sc->sc_bst; 1532 bus_space_handle_t bsh = sc->sc_bsh; 1533 int mctl; 1534 1535 SMC_SELECT_BANK(sc, 0); 1536 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1537 if (sc->sc_mii.mii_media_active & IFM_FDX) 1538 mctl |= TCR_SWFDUP; 1539 else 1540 mctl &= ~TCR_SWFDUP; 1541 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1542 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1543 } 1544 1545 /* 1546 * One second timer, used to tick the MII. 1547 */ 1548 void 1549 smc91cxx_tick(void *arg) 1550 { 1551 struct smc91cxx_softc *sc = arg; 1552 int s; 1553 1554 #ifdef DIAGNOSTIC 1555 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1556 panic("smc91cxx_tick"); 1557 #endif 1558 1559 if (!device_is_active(sc->sc_dev)) 1560 return; 1561 1562 s = splnet(); 1563 mii_tick(&sc->sc_mii); 1564 splx(s); 1565 1566 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1567 } 1568
Indexes created Tue Sep 23 02:09:52 GMT 2025