smc91cxx.c revision 1.95
1 /* $NetBSD: smc91cxx.c,v 1.95 2017/05/23 02:19:14 ozaki-r Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Gardner Buchanan <gbuchanan (at) shl.com> 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Gardner Buchanan. 48 * 4. The name of Gardner Buchanan may not be used to endorse or promote 49 * products derived from this software without specific prior written 50 * permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 64 */ 65 66 /* 67 * Core driver for the SMC 91Cxx family of Ethernet chips. 68 * 69 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 70 * written for NetBSD/amiga by Michael Hitch. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.95 2017/05/23 02:19:14 ozaki-r Exp $"); 75 76 #include "opt_inet.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/mbuf.h> 81 #include <sys/syslog.h> 82 #include <sys/socket.h> 83 #include <sys/device.h> 84 #include <sys/kernel.h> 85 #include <sys/malloc.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/rndsource.h> 89 90 #include <sys/bus.h> 91 #include <sys/intr.h> 92 93 #include <net/if.h> 94 #include <net/if_dl.h> 95 #include <net/if_ether.h> 96 #include <net/if_media.h> 97 98 #ifdef INET 99 #include <netinet/in.h> 100 #include <netinet/if_inarp.h> 101 #include <netinet/in_systm.h> 102 #include <netinet/in_var.h> 103 #include <netinet/ip.h> 104 #endif 105 106 #include <net/bpf.h> 107 #include <net/bpfdesc.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 #include <dev/mii/mii_bitbang.h> 112 113 #include <dev/ic/smc91cxxreg.h> 114 #include <dev/ic/smc91cxxvar.h> 115 116 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 117 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 118 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 119 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 120 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 121 122 #define bus_space_write_stream_4 bus_space_write_4 123 #define bus_space_read_stream_4 bus_space_read_4 124 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 125 126 /* XXX Hardware padding doesn't work yet(?) */ 127 #define SMC91CXX_SW_PAD 128 129 const char *smc91cxx_idstrs[] = { 130 NULL, /* 0 */ 131 NULL, /* 1 */ 132 NULL, /* 2 */ 133 "SMC91C90/91C92", /* 3 */ 134 "SMC91C94/91C96", /* 4 */ 135 "SMC91C95", /* 5 */ 136 NULL, /* 6 */ 137 "SMC91C100", /* 7 */ 138 "SMC91C100FD", /* 8 */ 139 "SMC91C111", /* 9 */ 140 NULL, /* 10 */ 141 NULL, /* 11 */ 142 NULL, /* 12 */ 143 NULL, /* 13 */ 144 NULL, /* 14 */ 145 NULL, /* 15 */ 146 }; 147 148 /* Supported media types. */ 149 static const int smc91cxx_media[] = { 150 IFM_ETHER|IFM_10_T, 151 IFM_ETHER|IFM_10_5, 152 }; 153 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 154 155 /* 156 * MII bit-bang glue. 157 */ 158 u_int32_t smc91cxx_mii_bitbang_read(device_t); 159 void smc91cxx_mii_bitbang_write(device_t, u_int32_t); 160 161 static const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 162 smc91cxx_mii_bitbang_read, 163 smc91cxx_mii_bitbang_write, 164 { 165 MR_MDO, /* MII_BIT_MDO */ 166 MR_MDI, /* MII_BIT_MDI */ 167 MR_MCLK, /* MII_BIT_MDC */ 168 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 169 0, /* MII_BIT_DIR_PHY_HOST */ 170 } 171 }; 172 173 /* MII callbacks */ 174 int smc91cxx_mii_readreg(device_t, int, int); 175 void smc91cxx_mii_writereg(device_t, int, int, int); 176 void smc91cxx_statchg(struct ifnet *); 177 void smc91cxx_tick(void *); 178 179 int smc91cxx_mediachange(struct ifnet *); 180 void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *); 181 182 int smc91cxx_set_media(struct smc91cxx_softc *, int); 183 184 void smc91cxx_init(struct smc91cxx_softc *); 185 void smc91cxx_read(struct smc91cxx_softc *); 186 void smc91cxx_reset(struct smc91cxx_softc *); 187 void smc91cxx_start(struct ifnet *); 188 uint8_t smc91cxx_copy_tx_frame(struct smc91cxx_softc *, struct mbuf *); 189 void smc91cxx_resume(struct smc91cxx_softc *); 190 void smc91cxx_stop(struct smc91cxx_softc *); 191 void smc91cxx_watchdog(struct ifnet *); 192 int smc91cxx_ioctl(struct ifnet *, u_long, void *); 193 194 static inline int ether_cmp(const void *, const void *); 195 static inline int 196 ether_cmp(const void *va, const void *vb) 197 { 198 const u_int8_t *a = va; 199 const u_int8_t *b = vb; 200 201 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 202 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 203 } 204 205 static inline void 206 smc91cxx_intr_mask_write(bus_space_tag_t bst, bus_space_handle_t bsh, 207 uint8_t mask) 208 { 209 KDASSERT((mask & IM_ERCV_INT) == 0); 210 #ifdef SMC91CXX_NO_BYTE_WRITE 211 bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask << 8); 212 #else 213 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 214 #endif 215 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 216 } 217 218 static inline void 219 smc91cxx_intr_ack_write(bus_space_tag_t bst, bus_space_handle_t bsh, 220 uint8_t ack, uint8_t mask) 221 { 222 #ifdef SMC91CXX_NO_BYTE_WRITE 223 bus_space_write_2(bst, bsh, INTR_ACK_REG_B, ack | (mask << 8)); 224 #else 225 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, ack); 226 #endif 227 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 228 } 229 230 void 231 smc91cxx_attach(struct smc91cxx_softc *sc, u_int8_t *myea) 232 { 233 struct ifnet *ifp = &sc->sc_ec.ec_if; 234 bus_space_tag_t bst = sc->sc_bst; 235 bus_space_handle_t bsh = sc->sc_bsh; 236 struct ifmedia *ifm = &sc->sc_mii.mii_media; 237 const char *idstr; 238 u_int32_t miicapabilities; 239 u_int16_t tmp; 240 u_int8_t enaddr[ETHER_ADDR_LEN]; 241 int i, aui, mult, scale, memsize; 242 char pbuf[9]; 243 244 tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W); 245 /* check magic number */ 246 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 247 aprint_error_dev(sc->sc_dev, 248 "failed to detect chip, bsr=%04x\n", tmp); 249 return; 250 } 251 252 /* Make sure the chip is stopped. */ 253 smc91cxx_stop(sc); 254 255 SMC_SELECT_BANK(sc, 3); 256 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 257 sc->sc_chipid = RR_ID(tmp); 258 idstr = smc91cxx_idstrs[sc->sc_chipid]; 259 260 aprint_normal_dev(sc->sc_dev, ""); 261 if (idstr != NULL) 262 aprint_normal("%s, ", idstr); 263 else 264 aprint_normal("unknown chip id %d, ", sc->sc_chipid); 265 aprint_normal("revision %d, ", RR_REV(tmp)); 266 267 SMC_SELECT_BANK(sc, 0); 268 switch (sc->sc_chipid) { 269 default: 270 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 271 scale = MIR_SCALE_91C9x; 272 break; 273 274 case CHIP_91C111: 275 mult = MIR_MULT_91C111; 276 scale = MIR_SCALE_91C111; 277 } 278 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 279 if (memsize == 255) 280 memsize++; 281 memsize *= scale * mult; 282 283 format_bytes(pbuf, sizeof(pbuf), memsize); 284 aprint_normal("buffer size: %s\n", pbuf); 285 286 /* Read the station address from the chip. */ 287 SMC_SELECT_BANK(sc, 1); 288 if (myea == NULL) { 289 myea = enaddr; 290 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 291 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 292 myea[i + 1] = (tmp >> 8) & 0xff; 293 myea[i] = tmp & 0xff; 294 } 295 } 296 aprint_normal_dev(sc->sc_dev, "MAC address %s, ", 297 ether_sprintf(myea)); 298 299 /* Initialize the ifnet structure. */ 300 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 301 ifp->if_softc = sc; 302 ifp->if_start = smc91cxx_start; 303 ifp->if_ioctl = smc91cxx_ioctl; 304 ifp->if_watchdog = smc91cxx_watchdog; 305 ifp->if_flags = 306 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 307 IFQ_SET_READY(&ifp->if_snd); 308 309 /* Attach the interface. */ 310 if_attach(ifp); 311 if_deferred_start_init(ifp, NULL); 312 ether_ifattach(ifp, myea); 313 314 /* 315 * Initialize our media structures and MII info. We will 316 * probe the MII if we are on the SMC91Cxx 317 */ 318 sc->sc_mii.mii_ifp = ifp; 319 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 320 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 321 sc->sc_mii.mii_statchg = smc91cxx_statchg; 322 ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, 323 smc91cxx_mediastatus); 324 325 SMC_SELECT_BANK(sc, 1); 326 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 327 328 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 329 switch (sc->sc_chipid) { 330 case CHIP_91100: 331 /* 332 * The 91100 does not have full-duplex capabilities, 333 * even if the PHY does. 334 */ 335 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 336 /*FALLTHROUGH*/ 337 case CHIP_91100FD: 338 case CHIP_91C111: 339 if (tmp & CR_MII_SELECT) { 340 aprint_normal("default media MII"); 341 if (sc->sc_chipid == CHIP_91C111) { 342 aprint_normal(" (%s PHY)\n", 343 (tmp & CR_AUI_SELECT) ? 344 "external" : "internal"); 345 sc->sc_internal_phy = !(tmp & CR_AUI_SELECT); 346 } else 347 aprint_normal("\n"); 348 mii_attach(sc->sc_dev, &sc->sc_mii, miicapabilities, 349 MII_PHY_ANY, MII_OFFSET_ANY, 0); 350 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 351 ifmedia_add(&sc->sc_mii.mii_media, 352 IFM_ETHER|IFM_NONE, 0, NULL); 353 ifmedia_set(&sc->sc_mii.mii_media, 354 IFM_ETHER|IFM_NONE); 355 } else { 356 ifmedia_set(&sc->sc_mii.mii_media, 357 IFM_ETHER|IFM_AUTO); 358 } 359 sc->sc_flags |= SMC_FLAGS_HAS_MII; 360 break; 361 } else 362 if (sc->sc_chipid == CHIP_91C111) { 363 /* 364 * XXX: Should bring it out of low-power mode 365 */ 366 aprint_normal("EPH interface in low power mode\n"); 367 sc->sc_internal_phy = 0; 368 return; 369 } 370 /*FALLTHROUGH*/ 371 default: 372 aprint_normal("default media %s\n", 373 (aui = (tmp & CR_AUI_SELECT)) ? 374 "AUI" : "UTP"); 375 for (i = 0; i < NSMC91CxxMEDIA; i++) 376 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 377 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 378 break; 379 } 380 381 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 382 RND_TYPE_NET, RND_FLAG_DEFAULT); 383 384 callout_init(&sc->sc_mii_callout, 0); 385 386 /* The attach is successful. */ 387 sc->sc_flags |= SMC_FLAGS_ATTACHED; 388 } 389 390 /* 391 * Change media according to request. 392 */ 393 int 394 smc91cxx_mediachange(struct ifnet *ifp) 395 { 396 struct smc91cxx_softc *sc = ifp->if_softc; 397 398 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 399 } 400 401 int 402 smc91cxx_set_media(struct smc91cxx_softc *sc, int media) 403 { 404 bus_space_tag_t bst = sc->sc_bst; 405 bus_space_handle_t bsh = sc->sc_bsh; 406 u_int16_t tmp; 407 int rc; 408 409 /* 410 * If the interface is not currently powered on, just return. 411 * When it is enabled later, smc91cxx_init() will properly set 412 * up the media for us. 413 */ 414 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 415 return (0); 416 417 if (IFM_TYPE(media) != IFM_ETHER) 418 return (EINVAL); 419 420 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0 || 421 (rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 422 rc = 0; 423 424 switch (IFM_SUBTYPE(media)) { 425 case IFM_10_T: 426 case IFM_10_5: 427 SMC_SELECT_BANK(sc, 1); 428 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 429 if (IFM_SUBTYPE(media) == IFM_10_5) 430 tmp |= CR_AUI_SELECT; 431 else 432 tmp &= ~CR_AUI_SELECT; 433 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 434 delay(20000); /* XXX is this needed? */ 435 break; 436 437 default: 438 return (EINVAL); 439 } 440 441 return rc; 442 } 443 444 /* 445 * Notify the world which media we're using. 446 */ 447 void 448 smc91cxx_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 449 { 450 struct smc91cxx_softc *sc = ifp->if_softc; 451 bus_space_tag_t bst = sc->sc_bst; 452 bus_space_handle_t bsh = sc->sc_bsh; 453 u_int16_t tmp; 454 455 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 456 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 457 ifmr->ifm_status = 0; 458 return; 459 } 460 461 /* 462 * If we have MII, go ask the PHY what's going on. 463 */ 464 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 465 mii_pollstat(&sc->sc_mii); 466 ifmr->ifm_active = sc->sc_mii.mii_media_active; 467 ifmr->ifm_status = sc->sc_mii.mii_media_status; 468 return; 469 } 470 471 SMC_SELECT_BANK(sc, 1); 472 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 473 ifmr->ifm_active = 474 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 475 } 476 477 /* 478 * Reset and initialize the chip. 479 */ 480 void 481 smc91cxx_init(struct smc91cxx_softc *sc) 482 { 483 struct ifnet *ifp = &sc->sc_ec.ec_if; 484 bus_space_tag_t bst = sc->sc_bst; 485 bus_space_handle_t bsh = sc->sc_bsh; 486 u_int16_t tmp; 487 const u_int8_t *enaddr; 488 int s, i; 489 490 s = splnet(); 491 492 /* 493 * This resets the registers mostly to defaults, but doesn't 494 * affect the EEPROM. The longest reset recovery time of those devices 495 * supported is the 91C111. Section 7.8 of its datasheet asks for 50ms. 496 */ 497 SMC_SELECT_BANK(sc, 0); 498 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 499 delay(5); 500 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 501 delay(50000); 502 503 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 504 505 /* Set the Ethernet address. */ 506 SMC_SELECT_BANK(sc, 1); 507 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 508 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 509 tmp = enaddr[i + 1] << 8 | enaddr[i]; 510 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 511 } 512 513 /* 514 * Set the control register to automatically release successfully 515 * transmitted packets (making the best use of our limited memory) 516 * and enable the EPH interrupt on certain TX errors. 517 */ 518 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 519 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 520 521 /* 522 * Reset the MMU and wait for it to be un-busy. 523 */ 524 SMC_SELECT_BANK(sc, 2); 525 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 526 sc->sc_txpacketno = ARR_FAILED; 527 for (;;) { 528 tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W); 529 if (tmp == 0xffff) { 530 /* card went away! */ 531 splx(s); 532 return; 533 } 534 if ((tmp & MMUCR_BUSY) == 0) 535 break; 536 } 537 538 /* 539 * Disable all interrupts. 540 */ 541 smc91cxx_intr_mask_write(bst, bsh, 0); 542 543 /* 544 * On the 91c111, enable auto-negotiation, and set the LED 545 * status pins to something sane. 546 * XXX: Should be some way for MD code to decide the latter. 547 */ 548 SMC_SELECT_BANK(sc, 0); 549 if (sc->sc_chipid == CHIP_91C111) { 550 bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W, 551 RPC_ANEG | 552 (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) | 553 (RPC_LS_TXRX << RPC_LSB_SHIFT)); 554 } 555 556 /* 557 * Set current media. 558 */ 559 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 560 561 /* 562 * Set the receive filter. We want receive enable and auto 563 * strip of CRC from received packet. If we are in promisc. mode, 564 * then set that bit as well. 565 * 566 * XXX Initialize multicast filter. For now, we just accept 567 * XXX all multicast. 568 */ 569 SMC_SELECT_BANK(sc, 0); 570 571 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 572 if (ifp->if_flags & IFF_PROMISC) 573 tmp |= RCR_PROMISC; 574 575 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 576 577 /* 578 * Set transmitter control to "enabled". 579 */ 580 tmp = TCR_ENABLE; 581 582 #ifndef SMC91CXX_SW_PAD 583 /* 584 * Enable hardware padding of transmitted packets. 585 * XXX doesn't work? 586 */ 587 tmp |= TCR_PAD_ENABLE; 588 #endif 589 590 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 591 592 /* 593 * Now, enable interrupts. 594 */ 595 SMC_SELECT_BANK(sc, 2); 596 597 sc->sc_intmask = IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT; 598 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) { 599 sc->sc_intmask |= IM_MD_INT; 600 } 601 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 602 603 /* Interface is now running, with no output active. */ 604 ifp->if_flags |= IFF_RUNNING; 605 ifp->if_flags &= ~IFF_OACTIVE; 606 607 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 608 /* Start the one second clock. */ 609 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 610 } 611 612 /* 613 * Attempt to start any pending transmission. 614 */ 615 smc91cxx_start(ifp); 616 617 splx(s); 618 } 619 620 /* 621 * Start output on an interface. 622 * Must be called at splnet or interrupt level. 623 */ 624 void 625 smc91cxx_start(struct ifnet *ifp) 626 { 627 struct smc91cxx_softc *sc = ifp->if_softc; 628 bus_space_tag_t bst = sc->sc_bst; 629 bus_space_handle_t bsh = sc->sc_bsh; 630 u_int len; 631 struct mbuf *m; 632 u_int16_t length, npages; 633 u_int16_t oddbyte; 634 u_int8_t packetno; 635 int timo, pad; 636 637 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 638 return; 639 640 again: 641 /* 642 * Peek at the next packet. 643 */ 644 IFQ_POLL(&ifp->if_snd, m); 645 if (m == NULL) 646 return; 647 648 /* 649 * Compute the frame length and set pad to give an overall even 650 * number of bytes. Below, we assume that the packet length 651 * is even. 652 */ 653 for (len = 0; m != NULL; m = m->m_next) 654 len += m->m_len; 655 656 /* 657 * We drop packets that are too large. Perhaps we should 658 * truncate them instead? 659 */ 660 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 661 printf("%s: large packet discarded\n", 662 device_xname(sc->sc_dev)); 663 ifp->if_oerrors++; 664 IFQ_DEQUEUE(&ifp->if_snd, m); 665 m_freem(m); 666 goto readcheck; 667 } 668 669 pad = 0; 670 #ifdef SMC91CXX_SW_PAD 671 /* 672 * Not using hardware padding; pad to ETHER_MIN_LEN. 673 */ 674 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 675 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 676 #endif 677 678 length = pad + len; 679 680 /* 681 * The MMU has a 256 byte page size. The MMU expects us to 682 * ask for "npages - 1". We include space for the status word, 683 * byte count, and control bytes in the allocation request. 684 */ 685 npages = ((length & ~1) + 6) >> 8; 686 687 /* 688 * Now allocate the memory. 689 */ 690 SMC_SELECT_BANK(sc, 2); 691 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 692 693 timo = MEMORY_WAIT_TIME; 694 if (__predict_false((sc->sc_txpacketno & ARR_FAILED) == 0)) { 695 packetno = sc->sc_txpacketno; 696 sc->sc_txpacketno = ARR_FAILED; 697 } else { 698 do { 699 if (bus_space_read_1(bst, bsh, 700 INTR_STAT_REG_B) & IM_ALLOC_INT) 701 break; 702 delay(1); 703 } while (--timo); 704 } 705 706 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 707 708 if (packetno & ARR_FAILED || timo == 0) { 709 /* 710 * No transmit memory is available. Record the number 711 * of requested pages and enable the allocation completion 712 * interrupt. Set up the watchdog timer in case we miss 713 * the interrupt. Mark the interface as active so that 714 * no one else attempts to transmit while we're allocating 715 * memory. 716 */ 717 sc->sc_intmask |= IM_ALLOC_INT; 718 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 719 ifp->if_timer = 5; 720 ifp->if_flags |= IFF_OACTIVE; 721 722 return; 723 } 724 725 /* 726 * We have a packet number - set the data window. 727 */ 728 bus_space_write_2(bst, bsh, PACKET_NUM_REG_B, packetno); 729 730 /* 731 * Point to the beginning of the packet. 732 */ 733 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 734 735 /* 736 * Send the packet length (+6 for stats, length, and control bytes) 737 * and the status word (set to zeros). 738 */ 739 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 740 bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff); 741 742 /* 743 * Get the packet from the kernel. This will include the Ethernet 744 * frame header, MAC address, etc. 745 */ 746 IFQ_DEQUEUE(&ifp->if_snd, m); 747 748 /* 749 * Push the packet out to the card. The copying function only does 750 * whole words and returns the straggling byte (if any). 751 */ 752 oddbyte = smc91cxx_copy_tx_frame(sc, m); 753 754 #ifdef SMC91CXX_SW_PAD 755 if (pad > 1 && (pad & 1)) { 756 bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte); 757 oddbyte = 0; 758 pad -= 1; 759 } 760 761 /* 762 * Push out padding. 763 */ 764 while (pad > 1) { 765 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 766 pad -= 2; 767 } 768 #endif 769 770 /* 771 * Push out control byte and unused packet byte. The control byte 772 * denotes whether this is an odd or even length packet, and that 773 * no special CRC handling is necessary. 774 */ 775 bus_space_write_2(bst, bsh, DATA_REG_W, 776 oddbyte | ((length & 1) ? (CTLB_ODD << 8) : 0)); 777 778 /* 779 * Enable transmit interrupts and let the chip go. Set a watchdog 780 * in case we miss the interrupt. 781 */ 782 sc->sc_intmask |= IM_TX_INT | IM_TX_EMPTY_INT; 783 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 784 785 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 786 787 ifp->if_timer = 5; 788 789 /* Hand off a copy to the bpf. */ 790 bpf_mtap(ifp, m); 791 792 ifp->if_opackets++; 793 m_freem(m); 794 795 readcheck: 796 /* 797 * Check for incoming packets. We don't want to overflow the small 798 * RX FIFO. If nothing has arrived, attempt to queue another 799 * transmit packet. 800 */ 801 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 802 goto again; 803 } 804 805 /* 806 * Squirt a (possibly misaligned) mbuf to the device 807 */ 808 uint8_t 809 smc91cxx_copy_tx_frame(struct smc91cxx_softc *sc, struct mbuf *m0) 810 { 811 bus_space_tag_t bst = sc->sc_bst; 812 bus_space_handle_t bsh = sc->sc_bsh; 813 struct mbuf *m; 814 int len, leftover; 815 u_int16_t dbuf; 816 u_int8_t *p; 817 #ifdef DIAGNOSTIC 818 u_int8_t *lim; 819 #endif 820 821 /* start out with no leftover data */ 822 leftover = 0; 823 dbuf = 0; 824 825 /* Process the chain of mbufs */ 826 for (m = m0; m != NULL; m = m->m_next) { 827 /* 828 * Process all of the data in a single mbuf. 829 */ 830 p = mtod(m, u_int8_t *); 831 len = m->m_len; 832 #ifdef DIAGNOSTIC 833 lim = p + len; 834 #endif 835 836 while (len > 0) { 837 if (leftover) { 838 /* 839 * Data left over (from mbuf or realignment). 840 * Buffer the next byte, and write it and 841 * the leftover data out. 842 */ 843 dbuf |= *p++ << 8; 844 len--; 845 bus_space_write_2(bst, bsh, DATA_REG_W, dbuf); 846 leftover = 0; 847 } else if ((long) p & 1) { 848 /* 849 * Misaligned data. Buffer the next byte. 850 */ 851 dbuf = *p++; 852 len--; 853 leftover = 1; 854 } else { 855 /* 856 * Aligned data. This is the case we like. 857 * 858 * Write-region out as much as we can, then 859 * buffer the remaining byte (if any). 860 */ 861 leftover = len & 1; 862 len &= ~1; 863 bus_space_write_multi_stream_2(bst, bsh, 864 DATA_REG_W, (u_int16_t *)p, len >> 1); 865 p += len; 866 867 if (leftover) 868 dbuf = *p++; 869 len = 0; 870 } 871 } 872 if (len < 0) 873 panic("smc91cxx_copy_tx_frame: negative len"); 874 #ifdef DIAGNOSTIC 875 if (p != lim) 876 panic("smc91cxx_copy_tx_frame: p != lim"); 877 #endif 878 } 879 880 return dbuf; 881 } 882 883 /* 884 * Interrupt service routine. 885 */ 886 int 887 smc91cxx_intr(void *arg) 888 { 889 struct smc91cxx_softc *sc = arg; 890 struct ifnet *ifp = &sc->sc_ec.ec_if; 891 bus_space_tag_t bst = sc->sc_bst; 892 bus_space_handle_t bsh = sc->sc_bsh; 893 u_int8_t mask, interrupts, status; 894 u_int16_t packetno, tx_status, card_stats; 895 u_int16_t v; 896 897 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 898 !device_is_active(sc->sc_dev)) 899 return (0); 900 901 SMC_SELECT_BANK(sc, 2); 902 903 /* 904 * Obtain the current interrupt status and mask. 905 */ 906 v = bus_space_read_2(bst, bsh, INTR_STAT_REG_B); 907 908 /* 909 * Get the set of interrupt which occurred and eliminate any 910 * which are not enabled. 911 */ 912 mask = v >> 8; 913 interrupts = v & 0xff; 914 KDASSERT(mask == sc->sc_intmask); 915 status = interrupts & mask; 916 917 /* Ours? */ 918 if (status == 0) 919 return (0); 920 921 /* 922 * It's ours; disable all interrupts while we process them. 923 */ 924 smc91cxx_intr_mask_write(bst, bsh, 0); 925 926 /* 927 * Receive overrun interrupts. 928 */ 929 if (status & IM_RX_OVRN_INT) { 930 smc91cxx_intr_ack_write(bst, bsh, IM_RX_OVRN_INT, 0); 931 ifp->if_ierrors++; 932 } 933 934 /* 935 * Receive interrupts. 936 */ 937 if (status & IM_RCV_INT) { 938 smc91cxx_read(sc); 939 } 940 941 /* 942 * Memory allocation interrupts. 943 */ 944 if (status & IM_ALLOC_INT) { 945 /* Disable this interrupt. */ 946 mask &= ~IM_ALLOC_INT; 947 sc->sc_intmask &= ~IM_ALLOC_INT; 948 949 /* 950 * Save allocated packet number for use in start 951 */ 952 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 953 KASSERT(sc->sc_txpacketno & ARR_FAILED); 954 sc->sc_txpacketno = packetno; 955 956 /* 957 * We can transmit again! 958 */ 959 ifp->if_flags &= ~IFF_OACTIVE; 960 ifp->if_timer = 0; 961 } 962 963 /* 964 * Transmit complete interrupt. Handle transmission error messages. 965 * This will only be called on error condition because of AUTO RELEASE 966 * mode. 967 */ 968 if (status & IM_TX_INT) { 969 smc91cxx_intr_ack_write(bst, bsh, IM_TX_INT, 0); 970 971 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 972 FIFO_TX_MASK; 973 974 /* 975 * Select this as the packet to read from. 976 */ 977 bus_space_write_2(bst, bsh, PACKET_NUM_REG_B, packetno); 978 979 /* 980 * Position the pointer to the beginning of the packet, wait 981 * for preload. 982 */ 983 bus_space_write_2(bst, bsh, POINTER_REG_W, 984 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 985 delay(1); 986 987 /* 988 * Fetch the TX status word. This will be a copy of 989 * the EPH_STATUS_REG_W at the time of the transmission 990 * failure. 991 */ 992 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 993 994 if (tx_status & EPHSR_TX_SUC) { 995 static struct timeval txsuc_last; 996 static int txsuc_count; 997 if (ppsratecheck(&txsuc_last, &txsuc_count, 1)) 998 printf("%s: successful packet caused TX" 999 " interrupt?!\n", device_xname(sc->sc_dev)); 1000 } else 1001 ifp->if_oerrors++; 1002 1003 if (tx_status & EPHSR_LATCOL) 1004 ifp->if_collisions++; 1005 1006 /* Disable this interrupt (start will reenable if needed). */ 1007 mask &= ~IM_TX_INT; 1008 sc->sc_intmask &= ~IM_TX_INT; 1009 1010 /* 1011 * Some of these errors disable the transmitter; reenable it. 1012 */ 1013 SMC_SELECT_BANK(sc, 0); 1014 #ifdef SMC91CXX_SW_PAD 1015 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 1016 #else 1017 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 1018 TCR_ENABLE | TCR_PAD_ENABLE); 1019 #endif 1020 1021 /* 1022 * Kill the failed packet and wait for the MMU to unbusy. 1023 */ 1024 SMC_SELECT_BANK(sc, 2); 1025 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1026 /* XXX bound this loop! */ ; 1027 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 1028 1029 ifp->if_timer = 0; 1030 } 1031 1032 /* 1033 * Transmit underrun interrupts. We use this opportunity to 1034 * update transmit statistics from the card. 1035 */ 1036 if (status & IM_TX_EMPTY_INT) { 1037 smc91cxx_intr_ack_write(bst, bsh, IM_TX_EMPTY_INT, 0); 1038 1039 /* Disable this interrupt. */ 1040 mask &= ~IM_TX_EMPTY_INT; 1041 sc->sc_intmask &= ~IM_TX_EMPTY_INT; 1042 1043 SMC_SELECT_BANK(sc, 0); 1044 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 1045 1046 /* Single collisions. */ 1047 ifp->if_collisions += card_stats & ECR_COLN_MASK; 1048 1049 /* Multiple collisions. */ 1050 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 1051 1052 SMC_SELECT_BANK(sc, 2); 1053 1054 ifp->if_timer = 0; 1055 } 1056 1057 /* 1058 * Internal PHY status change 1059 */ 1060 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy && 1061 (status & IM_MD_INT)) { 1062 1063 /* 1064 * Internal PHY status change 1065 */ 1066 smc91cxx_intr_ack_write(bst, bsh, IM_MD_INT, 0); 1067 mii_pollstat(&sc->sc_mii); 1068 } 1069 1070 /* 1071 * Other errors. Reset the interface. 1072 */ 1073 if (status & IM_EPH_INT) { 1074 smc91cxx_stop(sc); 1075 smc91cxx_init(sc); 1076 } 1077 1078 /* 1079 * Attempt to queue more packets for transmission. 1080 */ 1081 if_schedule_deferred_start(ifp); 1082 1083 /* 1084 * Reenable the interrupts we wish to receive now that processing 1085 * is complete. 1086 */ 1087 mask |= sc->sc_intmask; 1088 smc91cxx_intr_mask_write(bst, bsh, mask); 1089 1090 if (status) 1091 rnd_add_uint32(&sc->rnd_source, status); 1092 1093 return (1); 1094 } 1095 1096 /* 1097 * Read a packet from the card and pass it up to the kernel. 1098 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 1099 */ 1100 void 1101 smc91cxx_read(struct smc91cxx_softc *sc) 1102 { 1103 struct ifnet *ifp = &sc->sc_ec.ec_if; 1104 bus_space_tag_t bst = sc->sc_bst; 1105 bus_space_handle_t bsh = sc->sc_bsh; 1106 struct ether_header *eh; 1107 struct mbuf *m; 1108 u_int16_t status, packetno, packetlen; 1109 u_int8_t *data; 1110 u_int32_t dr; 1111 bool first = true; 1112 1113 again: 1114 /* 1115 * Set data pointer to the beginning of the packet. Since 1116 * PTR_RCV is set, the packet number will be found automatically 1117 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1118 */ 1119 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1120 if (packetno & FIFO_REMPTY) { 1121 if (first) { 1122 aprint_error_dev(sc->sc_dev, 1123 "receive interrupt on empty fifo\n"); 1124 } 1125 return; 1126 } 1127 first = false; 1128 1129 bus_space_write_2(bst, bsh, POINTER_REG_W, 1130 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 1131 delay(1); 1132 1133 /* 1134 * First two words are status and packet length. 1135 */ 1136 dr = bus_space_read_4(bst, bsh, DATA_REG_W); 1137 status = (u_int16_t)dr; 1138 packetlen = (u_int16_t)(dr >> 16); 1139 1140 packetlen &= RLEN_MASK; 1141 if (packetlen < ETHER_MIN_LEN - ETHER_CRC_LEN + 6 || packetlen > 1534) { 1142 ifp->if_ierrors++; 1143 goto out; 1144 } 1145 1146 /* 1147 * The packet length includes 3 extra words: status, length, 1148 * and an extra word that includes the control byte. 1149 */ 1150 packetlen -= 6; 1151 1152 /* 1153 * Account for receive errors and discard. 1154 */ 1155 if (status & RS_ERRORS) { 1156 ifp->if_ierrors++; 1157 goto out; 1158 } 1159 1160 /* 1161 * Adjust for odd-length packet. 1162 */ 1163 if (status & RS_ODDFRAME) 1164 packetlen++; 1165 1166 /* 1167 * Allocate a header mbuf. 1168 */ 1169 MGETHDR(m, M_DONTWAIT, MT_DATA); 1170 if (m == NULL) 1171 goto out; 1172 m_set_rcvif(m, ifp); 1173 m->m_pkthdr.len = packetlen; 1174 1175 /* 1176 * Always put the packet in a cluster. 1177 * XXX should chain small mbufs if less than threshold. 1178 */ 1179 MCLGET(m, M_DONTWAIT); 1180 if ((m->m_flags & M_EXT) == 0) { 1181 m_freem(m); 1182 ifp->if_ierrors++; 1183 aprint_error_dev(sc->sc_dev, 1184 "can't allocate cluster for incoming packet\n"); 1185 goto out; 1186 } 1187 1188 /* 1189 * Pull the packet off the interface. Make sure the payload 1190 * is aligned. 1191 */ 1192 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1193 m->m_data = (char *) ALIGN(mtod(m, char *) + 1194 sizeof(struct ether_header)) - sizeof(struct ether_header); 1195 1196 eh = mtod(m, struct ether_header *); 1197 data = mtod(m, u_int8_t *); 1198 KASSERT(trunc_page((uintptr_t)data) == 1199 trunc_page((uintptr_t)data + packetlen - 1)); 1200 if (packetlen > 1) 1201 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 1202 (u_int16_t *)data, packetlen >> 1); 1203 if (packetlen & 1) { 1204 data += packetlen & ~1; 1205 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1206 } 1207 } else { 1208 m->m_data = (void *) ALIGN(mtod(m, void *)); 1209 eh = mtod(m, struct ether_header *); 1210 data = mtod(m, u_int8_t *); 1211 KASSERT(trunc_page((uintptr_t)data) == 1212 trunc_page((uintptr_t)data + packetlen - 1)); 1213 if (packetlen > 3) 1214 bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W, 1215 (u_int32_t *)data, packetlen >> 2); 1216 if (packetlen & 3) { 1217 data += packetlen & ~3; 1218 *((u_int32_t *)data) = 1219 bus_space_read_stream_4(bst, bsh, DATA_REG_W); 1220 } 1221 } 1222 1223 /* 1224 * Make sure to behave as IFF_SIMPLEX in all cases. 1225 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1226 * loops back packets to itself on promiscuous mode. 1227 * (should be ensured by chipset configuration) 1228 */ 1229 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1230 /* 1231 * Drop packet looped back from myself. 1232 */ 1233 if (ether_cmp(eh->ether_shost, CLLADDR(ifp->if_sadl)) == 0) { 1234 m_freem(m); 1235 goto out; 1236 } 1237 } 1238 1239 m->m_pkthdr.len = m->m_len = packetlen; 1240 1241 if_percpuq_enqueue(ifp->if_percpuq, m); 1242 1243 out: 1244 /* 1245 * Tell the card to free the memory occupied by this packet. 1246 */ 1247 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1248 /* XXX bound this loop! */ ; 1249 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1250 1251 /* 1252 * Check for another packet. 1253 */ 1254 goto again; 1255 } 1256 1257 /* 1258 * Process an ioctl request. 1259 */ 1260 int 1261 smc91cxx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1262 { 1263 struct smc91cxx_softc *sc = ifp->if_softc; 1264 struct ifaddr *ifa = (struct ifaddr *)data; 1265 struct ifreq *ifr = (struct ifreq *)data; 1266 int s, error = 0; 1267 1268 s = splnet(); 1269 1270 switch (cmd) { 1271 case SIOCINITIFADDR: 1272 if ((error = smc91cxx_enable(sc)) != 0) 1273 break; 1274 ifp->if_flags |= IFF_UP; 1275 smc91cxx_init(sc); 1276 switch (ifa->ifa_addr->sa_family) { 1277 #ifdef INET 1278 case AF_INET: 1279 arp_ifinit(ifp, ifa); 1280 break; 1281 #endif 1282 default: 1283 break; 1284 } 1285 break; 1286 1287 1288 case SIOCSIFFLAGS: 1289 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1290 break; 1291 /* XXX re-use ether_ioctl() */ 1292 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1293 case IFF_RUNNING: 1294 /* 1295 * If interface is marked down and it is running, 1296 * stop it. 1297 */ 1298 smc91cxx_stop(sc); 1299 ifp->if_flags &= ~IFF_RUNNING; 1300 smc91cxx_disable(sc); 1301 break; 1302 case IFF_UP: 1303 /* 1304 * If interface is marked up and it is stopped, 1305 * start it. 1306 */ 1307 if ((error = smc91cxx_enable(sc)) != 0) 1308 break; 1309 smc91cxx_init(sc); 1310 break; 1311 case IFF_UP|IFF_RUNNING: 1312 /* 1313 * Reset the interface to pick up changes in any 1314 * other flags that affect hardware registers. 1315 */ 1316 smc91cxx_reset(sc); 1317 break; 1318 case 0: 1319 break; 1320 } 1321 break; 1322 1323 case SIOCADDMULTI: 1324 case SIOCDELMULTI: 1325 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1326 error = EIO; 1327 break; 1328 } 1329 1330 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1331 /* 1332 * Multicast list has changed; set the hardware 1333 * filter accordingly. 1334 */ 1335 if (ifp->if_flags & IFF_RUNNING) 1336 smc91cxx_reset(sc); 1337 error = 0; 1338 } 1339 break; 1340 1341 case SIOCGIFMEDIA: 1342 case SIOCSIFMEDIA: 1343 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1344 break; 1345 1346 default: 1347 error = ether_ioctl(ifp, cmd, data); 1348 break; 1349 } 1350 1351 splx(s); 1352 return (error); 1353 } 1354 1355 /* 1356 * Reset the interface. 1357 */ 1358 void 1359 smc91cxx_reset(struct smc91cxx_softc *sc) 1360 { 1361 int s; 1362 1363 s = splnet(); 1364 smc91cxx_stop(sc); 1365 smc91cxx_init(sc); 1366 splx(s); 1367 } 1368 1369 /* 1370 * Watchdog timer. 1371 */ 1372 void 1373 smc91cxx_watchdog(struct ifnet *ifp) 1374 { 1375 struct smc91cxx_softc *sc = ifp->if_softc; 1376 1377 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1378 ifp->if_oerrors++; 1379 smc91cxx_reset(sc); 1380 } 1381 1382 /* 1383 * Stop output on the interface. 1384 */ 1385 void 1386 smc91cxx_stop(struct smc91cxx_softc *sc) 1387 { 1388 bus_space_tag_t bst = sc->sc_bst; 1389 bus_space_handle_t bsh = sc->sc_bsh; 1390 1391 /* 1392 * Clear interrupt mask; disable all interrupts. 1393 */ 1394 SMC_SELECT_BANK(sc, 2); 1395 smc91cxx_intr_mask_write(bst, bsh, 0); 1396 1397 /* 1398 * Disable transmitter and receiver. 1399 */ 1400 SMC_SELECT_BANK(sc, 0); 1401 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1402 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1403 1404 /* 1405 * Cancel watchdog timer. 1406 */ 1407 sc->sc_ec.ec_if.if_timer = 0; 1408 } 1409 1410 /* 1411 * Enable power on the interface. 1412 */ 1413 int 1414 smc91cxx_enable(struct smc91cxx_softc *sc) 1415 { 1416 1417 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1418 if ((*sc->sc_enable)(sc) != 0) { 1419 aprint_error_dev(sc->sc_dev, "device enable failed\n"); 1420 return (EIO); 1421 } 1422 } 1423 1424 sc->sc_flags |= SMC_FLAGS_ENABLED; 1425 return (0); 1426 } 1427 1428 /* 1429 * Disable power on the interface. 1430 */ 1431 void 1432 smc91cxx_disable(struct smc91cxx_softc *sc) 1433 { 1434 1435 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1436 (*sc->sc_disable)(sc); 1437 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1438 } 1439 } 1440 1441 int 1442 smc91cxx_activate(device_t self, enum devact act) 1443 { 1444 struct smc91cxx_softc *sc = device_private(self); 1445 1446 switch (act) { 1447 case DVACT_DEACTIVATE: 1448 if_deactivate(&sc->sc_ec.ec_if); 1449 return 0; 1450 default: 1451 return EOPNOTSUPP; 1452 } 1453 } 1454 1455 int 1456 smc91cxx_detach(device_t self, int flags) 1457 { 1458 struct smc91cxx_softc *sc = device_private(self); 1459 struct ifnet *ifp = &sc->sc_ec.ec_if; 1460 1461 /* Succeed now if there's no work to do. */ 1462 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1463 return (0); 1464 1465 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1466 smc91cxx_disable(sc); 1467 1468 /* smc91cxx_attach() never fails */ 1469 1470 /* Delete all media. */ 1471 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1472 1473 rnd_detach_source(&sc->rnd_source); 1474 1475 ether_ifdetach(ifp); 1476 if_detach(ifp); 1477 1478 return (0); 1479 } 1480 1481 u_int32_t 1482 smc91cxx_mii_bitbang_read(device_t self) 1483 { 1484 struct smc91cxx_softc *sc = device_private(self); 1485 1486 /* We're already in bank 3. */ 1487 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1488 } 1489 1490 void 1491 smc91cxx_mii_bitbang_write(device_t self, u_int32_t val) 1492 { 1493 struct smc91cxx_softc *sc = device_private(self); 1494 1495 /* We're already in bank 3. */ 1496 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1497 } 1498 1499 int 1500 smc91cxx_mii_readreg(device_t self, int phy, int reg) 1501 { 1502 struct smc91cxx_softc *sc = device_private(self); 1503 int val; 1504 1505 SMC_SELECT_BANK(sc, 3); 1506 1507 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1508 1509 SMC_SELECT_BANK(sc, 2); 1510 1511 return (val); 1512 } 1513 1514 void 1515 smc91cxx_mii_writereg(device_t self, int phy, int reg, int val) 1516 { 1517 struct smc91cxx_softc *sc = device_private(self); 1518 1519 SMC_SELECT_BANK(sc, 3); 1520 1521 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1522 1523 SMC_SELECT_BANK(sc, 2); 1524 } 1525 1526 void 1527 smc91cxx_statchg(struct ifnet *ifp) 1528 { 1529 struct smc91cxx_softc *sc = ifp->if_softc; 1530 bus_space_tag_t bst = sc->sc_bst; 1531 bus_space_handle_t bsh = sc->sc_bsh; 1532 int mctl; 1533 1534 SMC_SELECT_BANK(sc, 0); 1535 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1536 if (sc->sc_mii.mii_media_active & IFM_FDX) 1537 mctl |= TCR_SWFDUP; 1538 else 1539 mctl &= ~TCR_SWFDUP; 1540 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1541 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1542 } 1543 1544 /* 1545 * One second timer, used to tick the MII. 1546 */ 1547 void 1548 smc91cxx_tick(void *arg) 1549 { 1550 struct smc91cxx_softc *sc = arg; 1551 int s; 1552 1553 #ifdef DIAGNOSTIC 1554 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1555 panic("smc91cxx_tick"); 1556 #endif 1557 1558 if (!device_is_active(sc->sc_dev)) 1559 return; 1560 1561 s = splnet(); 1562 mii_tick(&sc->sc_mii); 1563 splx(s); 1564 1565 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1566 } 1567
Indexes created Wed Sep 24 05:09:52 GMT 2025