smc91cxx.c revision 1.98
1 /* $NetBSD: smc91cxx.c,v 1.98 2019/01/22 03:42:26 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Gardner Buchanan <gbuchanan (at) shl.com> 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Gardner Buchanan. 48 * 4. The name of Gardner Buchanan may not be used to endorse or promote 49 * products derived from this software without specific prior written 50 * permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 64 */ 65 66 /* 67 * Core driver for the SMC 91Cxx family of Ethernet chips. 68 * 69 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 70 * written for NetBSD/amiga by Michael Hitch. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.98 2019/01/22 03:42:26 msaitoh Exp $"); 75 76 #include "opt_inet.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/mbuf.h> 81 #include <sys/syslog.h> 82 #include <sys/socket.h> 83 #include <sys/device.h> 84 #include <sys/kernel.h> 85 #include <sys/malloc.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/rndsource.h> 89 90 #include <sys/bus.h> 91 #include <sys/intr.h> 92 93 #include <net/if.h> 94 #include <net/if_dl.h> 95 #include <net/if_ether.h> 96 #include <net/if_media.h> 97 #include <net/bpf.h> 98 99 #ifdef INET 100 #include <netinet/in.h> 101 #include <netinet/if_inarp.h> 102 #include <netinet/in_systm.h> 103 #include <netinet/in_var.h> 104 #include <netinet/ip.h> 105 #endif 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 #include <dev/mii/mii_bitbang.h> 110 111 #include <dev/ic/smc91cxxreg.h> 112 #include <dev/ic/smc91cxxvar.h> 113 114 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 115 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 116 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 117 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 118 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 119 120 #define bus_space_write_stream_4 bus_space_write_4 121 #define bus_space_read_stream_4 bus_space_read_4 122 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 123 124 /* XXX Hardware padding doesn't work yet(?) */ 125 #define SMC91CXX_SW_PAD 126 127 const char *smc91cxx_idstrs[] = { 128 NULL, /* 0 */ 129 NULL, /* 1 */ 130 NULL, /* 2 */ 131 "SMC91C90/91C92", /* 3 */ 132 "SMC91C94/91C96", /* 4 */ 133 "SMC91C95", /* 5 */ 134 NULL, /* 6 */ 135 "SMC91C100", /* 7 */ 136 "SMC91C100FD", /* 8 */ 137 "SMC91C111", /* 9 */ 138 NULL, /* 10 */ 139 NULL, /* 11 */ 140 NULL, /* 12 */ 141 NULL, /* 13 */ 142 NULL, /* 14 */ 143 NULL, /* 15 */ 144 }; 145 146 /* Supported media types. */ 147 static const int smc91cxx_media[] = { 148 IFM_ETHER|IFM_10_T, 149 IFM_ETHER|IFM_10_5, 150 }; 151 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 152 153 /* 154 * MII bit-bang glue. 155 */ 156 u_int32_t smc91cxx_mii_bitbang_read(device_t); 157 void smc91cxx_mii_bitbang_write(device_t, u_int32_t); 158 159 static const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 160 smc91cxx_mii_bitbang_read, 161 smc91cxx_mii_bitbang_write, 162 { 163 MR_MDO, /* MII_BIT_MDO */ 164 MR_MDI, /* MII_BIT_MDI */ 165 MR_MCLK, /* MII_BIT_MDC */ 166 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 167 0, /* MII_BIT_DIR_PHY_HOST */ 168 } 169 }; 170 171 /* MII callbacks */ 172 int smc91cxx_mii_readreg(device_t, int, int, uint16_t *); 173 int smc91cxx_mii_writereg(device_t, int, int, uint16_t); 174 void smc91cxx_statchg(struct ifnet *); 175 void smc91cxx_tick(void *); 176 177 int smc91cxx_mediachange(struct ifnet *); 178 void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 int smc91cxx_set_media(struct smc91cxx_softc *, int); 181 182 void smc91cxx_init(struct smc91cxx_softc *); 183 void smc91cxx_read(struct smc91cxx_softc *); 184 void smc91cxx_reset(struct smc91cxx_softc *); 185 void smc91cxx_start(struct ifnet *); 186 uint8_t smc91cxx_copy_tx_frame(struct smc91cxx_softc *, struct mbuf *); 187 void smc91cxx_resume(struct smc91cxx_softc *); 188 void smc91cxx_stop(struct smc91cxx_softc *); 189 void smc91cxx_watchdog(struct ifnet *); 190 int smc91cxx_ioctl(struct ifnet *, u_long, void *); 191 192 static inline int ether_cmp(const void *, const void *); 193 static inline int 194 ether_cmp(const void *va, const void *vb) 195 { 196 const u_int8_t *a = va; 197 const u_int8_t *b = vb; 198 199 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 200 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 201 } 202 203 static inline void 204 smc91cxx_intr_mask_write(bus_space_tag_t bst, bus_space_handle_t bsh, 205 uint8_t mask) 206 { 207 KDASSERT((mask & IM_ERCV_INT) == 0); 208 #ifdef SMC91CXX_NO_BYTE_WRITE 209 bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask << 8); 210 #else 211 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 212 #endif 213 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 214 } 215 216 static inline void 217 smc91cxx_intr_ack_write(bus_space_tag_t bst, bus_space_handle_t bsh, 218 uint8_t ack, uint8_t mask) 219 { 220 #ifdef SMC91CXX_NO_BYTE_WRITE 221 bus_space_write_2(bst, bsh, INTR_ACK_REG_B, ack | (mask << 8)); 222 #else 223 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, ack); 224 #endif 225 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 226 } 227 228 void 229 smc91cxx_attach(struct smc91cxx_softc *sc, u_int8_t *myea) 230 { 231 struct ifnet *ifp = &sc->sc_ec.ec_if; 232 bus_space_tag_t bst = sc->sc_bst; 233 bus_space_handle_t bsh = sc->sc_bsh; 234 struct ifmedia *ifm = &sc->sc_mii.mii_media; 235 const char *idstr; 236 u_int32_t miicapabilities; 237 u_int16_t tmp; 238 u_int8_t enaddr[ETHER_ADDR_LEN]; 239 int i, aui, mult, scale, memsize; 240 char pbuf[9]; 241 242 tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W); 243 /* check magic number */ 244 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 245 aprint_error_dev(sc->sc_dev, 246 "failed to detect chip, bsr=%04x\n", tmp); 247 return; 248 } 249 250 /* Make sure the chip is stopped. */ 251 smc91cxx_stop(sc); 252 253 SMC_SELECT_BANK(sc, 3); 254 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 255 sc->sc_chipid = RR_ID(tmp); 256 idstr = smc91cxx_idstrs[sc->sc_chipid]; 257 258 aprint_normal_dev(sc->sc_dev, ""); 259 if (idstr != NULL) 260 aprint_normal("%s, ", idstr); 261 else 262 aprint_normal("unknown chip id %d, ", sc->sc_chipid); 263 aprint_normal("revision %d, ", RR_REV(tmp)); 264 265 SMC_SELECT_BANK(sc, 0); 266 switch (sc->sc_chipid) { 267 default: 268 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 269 scale = MIR_SCALE_91C9x; 270 break; 271 272 case CHIP_91C111: 273 mult = MIR_MULT_91C111; 274 scale = MIR_SCALE_91C111; 275 } 276 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 277 if (memsize == 255) 278 memsize++; 279 memsize *= scale * mult; 280 281 format_bytes(pbuf, sizeof(pbuf), memsize); 282 aprint_normal("buffer size: %s\n", pbuf); 283 284 /* Read the station address from the chip. */ 285 SMC_SELECT_BANK(sc, 1); 286 if (myea == NULL) { 287 myea = enaddr; 288 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 289 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 290 myea[i + 1] = (tmp >> 8) & 0xff; 291 myea[i] = tmp & 0xff; 292 } 293 } 294 aprint_normal_dev(sc->sc_dev, "MAC address %s, ", 295 ether_sprintf(myea)); 296 297 /* Initialize the ifnet structure. */ 298 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 299 ifp->if_softc = sc; 300 ifp->if_start = smc91cxx_start; 301 ifp->if_ioctl = smc91cxx_ioctl; 302 ifp->if_watchdog = smc91cxx_watchdog; 303 ifp->if_flags = 304 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 305 IFQ_SET_READY(&ifp->if_snd); 306 307 /* Attach the interface. */ 308 if_attach(ifp); 309 if_deferred_start_init(ifp, NULL); 310 ether_ifattach(ifp, myea); 311 312 /* 313 * Initialize our media structures and MII info. We will 314 * probe the MII if we are on the SMC91Cxx 315 */ 316 sc->sc_mii.mii_ifp = ifp; 317 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 318 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 319 sc->sc_mii.mii_statchg = smc91cxx_statchg; 320 ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, 321 smc91cxx_mediastatus); 322 323 SMC_SELECT_BANK(sc, 1); 324 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 325 326 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 327 switch (sc->sc_chipid) { 328 case CHIP_91100: 329 /* 330 * The 91100 does not have full-duplex capabilities, 331 * even if the PHY does. 332 */ 333 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 334 /*FALLTHROUGH*/ 335 case CHIP_91100FD: 336 case CHIP_91C111: 337 if (tmp & CR_MII_SELECT) { 338 aprint_normal("default media MII"); 339 if (sc->sc_chipid == CHIP_91C111) { 340 aprint_normal(" (%s PHY)\n", 341 (tmp & CR_AUI_SELECT) ? 342 "external" : "internal"); 343 sc->sc_internal_phy = !(tmp & CR_AUI_SELECT); 344 } else 345 aprint_normal("\n"); 346 mii_attach(sc->sc_dev, &sc->sc_mii, miicapabilities, 347 MII_PHY_ANY, MII_OFFSET_ANY, 0); 348 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 349 ifmedia_add(&sc->sc_mii.mii_media, 350 IFM_ETHER|IFM_NONE, 0, NULL); 351 ifmedia_set(&sc->sc_mii.mii_media, 352 IFM_ETHER|IFM_NONE); 353 } else { 354 ifmedia_set(&sc->sc_mii.mii_media, 355 IFM_ETHER|IFM_AUTO); 356 } 357 sc->sc_flags |= SMC_FLAGS_HAS_MII; 358 break; 359 } else 360 if (sc->sc_chipid == CHIP_91C111) { 361 /* 362 * XXX: Should bring it out of low-power mode 363 */ 364 aprint_normal("EPH interface in low power mode\n"); 365 sc->sc_internal_phy = 0; 366 return; 367 } 368 /*FALLTHROUGH*/ 369 default: 370 aprint_normal("default media %s\n", 371 (aui = (tmp & CR_AUI_SELECT)) ? 372 "AUI" : "UTP"); 373 for (i = 0; i < NSMC91CxxMEDIA; i++) 374 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 375 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 376 break; 377 } 378 379 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 380 RND_TYPE_NET, RND_FLAG_DEFAULT); 381 382 callout_init(&sc->sc_mii_callout, 0); 383 384 /* The attach is successful. */ 385 sc->sc_flags |= SMC_FLAGS_ATTACHED; 386 } 387 388 /* 389 * Change media according to request. 390 */ 391 int 392 smc91cxx_mediachange(struct ifnet *ifp) 393 { 394 struct smc91cxx_softc *sc = ifp->if_softc; 395 396 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 397 } 398 399 int 400 smc91cxx_set_media(struct smc91cxx_softc *sc, int media) 401 { 402 bus_space_tag_t bst = sc->sc_bst; 403 bus_space_handle_t bsh = sc->sc_bsh; 404 u_int16_t tmp; 405 int rc; 406 407 /* 408 * If the interface is not currently powered on, just return. 409 * When it is enabled later, smc91cxx_init() will properly set 410 * up the media for us. 411 */ 412 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 413 return (0); 414 415 if (IFM_TYPE(media) != IFM_ETHER) 416 return (EINVAL); 417 418 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0 || 419 (rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 420 rc = 0; 421 422 switch (IFM_SUBTYPE(media)) { 423 case IFM_10_T: 424 case IFM_10_5: 425 SMC_SELECT_BANK(sc, 1); 426 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 427 if (IFM_SUBTYPE(media) == IFM_10_5) 428 tmp |= CR_AUI_SELECT; 429 else 430 tmp &= ~CR_AUI_SELECT; 431 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 432 delay(20000); /* XXX is this needed? */ 433 break; 434 435 default: 436 return (EINVAL); 437 } 438 439 return rc; 440 } 441 442 /* 443 * Notify the world which media we're using. 444 */ 445 void 446 smc91cxx_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 447 { 448 struct smc91cxx_softc *sc = ifp->if_softc; 449 bus_space_tag_t bst = sc->sc_bst; 450 bus_space_handle_t bsh = sc->sc_bsh; 451 u_int16_t tmp; 452 453 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 454 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 455 ifmr->ifm_status = 0; 456 return; 457 } 458 459 /* 460 * If we have MII, go ask the PHY what's going on. 461 */ 462 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 463 mii_pollstat(&sc->sc_mii); 464 ifmr->ifm_active = sc->sc_mii.mii_media_active; 465 ifmr->ifm_status = sc->sc_mii.mii_media_status; 466 return; 467 } 468 469 SMC_SELECT_BANK(sc, 1); 470 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 471 ifmr->ifm_active = 472 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 473 } 474 475 /* 476 * Reset and initialize the chip. 477 */ 478 void 479 smc91cxx_init(struct smc91cxx_softc *sc) 480 { 481 struct ifnet *ifp = &sc->sc_ec.ec_if; 482 bus_space_tag_t bst = sc->sc_bst; 483 bus_space_handle_t bsh = sc->sc_bsh; 484 u_int16_t tmp; 485 const u_int8_t *enaddr; 486 int s, i; 487 488 s = splnet(); 489 490 /* 491 * This resets the registers mostly to defaults, but doesn't 492 * affect the EEPROM. The longest reset recovery time of those devices 493 * supported is the 91C111. Section 7.8 of its datasheet asks for 50ms. 494 */ 495 SMC_SELECT_BANK(sc, 0); 496 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 497 delay(5); 498 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 499 delay(50000); 500 501 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 502 503 /* Set the Ethernet address. */ 504 SMC_SELECT_BANK(sc, 1); 505 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 506 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 507 tmp = enaddr[i + 1] << 8 | enaddr[i]; 508 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 509 } 510 511 /* 512 * Set the control register to automatically release successfully 513 * transmitted packets (making the best use of our limited memory) 514 * and enable the EPH interrupt on certain TX errors. 515 */ 516 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 517 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 518 519 /* 520 * Reset the MMU and wait for it to be un-busy. 521 */ 522 SMC_SELECT_BANK(sc, 2); 523 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 524 sc->sc_txpacketno = ARR_FAILED; 525 for (;;) { 526 tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W); 527 if (tmp == 0xffff) { 528 /* card went away! */ 529 splx(s); 530 return; 531 } 532 if ((tmp & MMUCR_BUSY) == 0) 533 break; 534 } 535 536 /* 537 * Disable all interrupts. 538 */ 539 smc91cxx_intr_mask_write(bst, bsh, 0); 540 541 /* 542 * On the 91c111, enable auto-negotiation, and set the LED 543 * status pins to something sane. 544 * XXX: Should be some way for MD code to decide the latter. 545 */ 546 SMC_SELECT_BANK(sc, 0); 547 if (sc->sc_chipid == CHIP_91C111) { 548 bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W, 549 RPC_ANEG | 550 (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) | 551 (RPC_LS_TXRX << RPC_LSB_SHIFT)); 552 } 553 554 /* 555 * Set current media. 556 */ 557 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 558 559 /* 560 * Set the receive filter. We want receive enable and auto 561 * strip of CRC from received packet. If we are in promisc. mode, 562 * then set that bit as well. 563 * 564 * XXX Initialize multicast filter. For now, we just accept 565 * XXX all multicast. 566 */ 567 SMC_SELECT_BANK(sc, 0); 568 569 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 570 if (ifp->if_flags & IFF_PROMISC) 571 tmp |= RCR_PROMISC; 572 573 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 574 575 /* 576 * Set transmitter control to "enabled". 577 */ 578 tmp = TCR_ENABLE; 579 580 #ifndef SMC91CXX_SW_PAD 581 /* 582 * Enable hardware padding of transmitted packets. 583 * XXX doesn't work? 584 */ 585 tmp |= TCR_PAD_ENABLE; 586 #endif 587 588 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 589 590 /* 591 * Now, enable interrupts. 592 */ 593 SMC_SELECT_BANK(sc, 2); 594 595 sc->sc_intmask = IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT; 596 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) { 597 sc->sc_intmask |= IM_MD_INT; 598 } 599 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 600 601 /* Interface is now running, with no output active. */ 602 ifp->if_flags |= IFF_RUNNING; 603 ifp->if_flags &= ~IFF_OACTIVE; 604 605 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 606 /* Start the one second clock. */ 607 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 608 } 609 610 /* 611 * Attempt to start any pending transmission. 612 */ 613 smc91cxx_start(ifp); 614 615 splx(s); 616 } 617 618 /* 619 * Start output on an interface. 620 * Must be called at splnet or interrupt level. 621 */ 622 void 623 smc91cxx_start(struct ifnet *ifp) 624 { 625 struct smc91cxx_softc *sc = ifp->if_softc; 626 bus_space_tag_t bst = sc->sc_bst; 627 bus_space_handle_t bsh = sc->sc_bsh; 628 u_int len; 629 struct mbuf *m; 630 u_int16_t length, npages; 631 u_int16_t oddbyte; 632 u_int8_t packetno; 633 int timo, pad; 634 635 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 636 return; 637 638 again: 639 /* 640 * Peek at the next packet. 641 */ 642 IFQ_POLL(&ifp->if_snd, m); 643 if (m == NULL) 644 return; 645 646 /* 647 * Compute the frame length and set pad to give an overall even 648 * number of bytes. Below, we assume that the packet length 649 * is even. 650 */ 651 for (len = 0; m != NULL; m = m->m_next) 652 len += m->m_len; 653 654 /* 655 * We drop packets that are too large. Perhaps we should 656 * truncate them instead? 657 */ 658 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 659 printf("%s: large packet discarded\n", 660 device_xname(sc->sc_dev)); 661 ifp->if_oerrors++; 662 IFQ_DEQUEUE(&ifp->if_snd, m); 663 m_freem(m); 664 goto readcheck; 665 } 666 667 pad = 0; 668 #ifdef SMC91CXX_SW_PAD 669 /* 670 * Not using hardware padding; pad to ETHER_MIN_LEN. 671 */ 672 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 673 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 674 #endif 675 676 length = pad + len; 677 678 /* 679 * The MMU has a 256 byte page size. The MMU expects us to 680 * ask for "npages - 1". We include space for the status word, 681 * byte count, and control bytes in the allocation request. 682 */ 683 npages = ((length & ~1) + 6) >> 8; 684 685 /* 686 * Now allocate the memory. 687 */ 688 SMC_SELECT_BANK(sc, 2); 689 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 690 691 timo = MEMORY_WAIT_TIME; 692 if (__predict_false((sc->sc_txpacketno & ARR_FAILED) == 0)) { 693 packetno = sc->sc_txpacketno; 694 sc->sc_txpacketno = ARR_FAILED; 695 } else { 696 do { 697 if (bus_space_read_1(bst, bsh, 698 INTR_STAT_REG_B) & IM_ALLOC_INT) 699 break; 700 delay(1); 701 } while (--timo); 702 } 703 704 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 705 706 if (packetno & ARR_FAILED || timo == 0) { 707 /* 708 * No transmit memory is available. Record the number 709 * of requested pages and enable the allocation completion 710 * interrupt. Set up the watchdog timer in case we miss 711 * the interrupt. Mark the interface as active so that 712 * no one else attempts to transmit while we're allocating 713 * memory. 714 */ 715 sc->sc_intmask |= IM_ALLOC_INT; 716 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 717 ifp->if_timer = 5; 718 ifp->if_flags |= IFF_OACTIVE; 719 720 return; 721 } 722 723 /* 724 * We have a packet number - set the data window. 725 */ 726 bus_space_write_2(bst, bsh, PACKET_NUM_REG_B, packetno); 727 728 /* 729 * Point to the beginning of the packet. 730 */ 731 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 732 733 /* 734 * Send the packet length (+6 for stats, length, and control bytes) 735 * and the status word (set to zeros). 736 */ 737 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 738 bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff); 739 740 /* 741 * Get the packet from the kernel. This will include the Ethernet 742 * frame header, MAC address, etc. 743 */ 744 IFQ_DEQUEUE(&ifp->if_snd, m); 745 746 /* 747 * Push the packet out to the card. The copying function only does 748 * whole words and returns the straggling byte (if any). 749 */ 750 oddbyte = smc91cxx_copy_tx_frame(sc, m); 751 752 #ifdef SMC91CXX_SW_PAD 753 if (pad > 1 && (pad & 1)) { 754 bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte); 755 oddbyte = 0; 756 pad -= 1; 757 } 758 759 /* 760 * Push out padding. 761 */ 762 while (pad > 1) { 763 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 764 pad -= 2; 765 } 766 #endif 767 768 /* 769 * Push out control byte and unused packet byte. The control byte 770 * denotes whether this is an odd or even length packet, and that 771 * no special CRC handling is necessary. 772 */ 773 bus_space_write_2(bst, bsh, DATA_REG_W, 774 oddbyte | ((length & 1) ? (CTLB_ODD << 8) : 0)); 775 776 /* 777 * Enable transmit interrupts and let the chip go. Set a watchdog 778 * in case we miss the interrupt. 779 */ 780 sc->sc_intmask |= IM_TX_INT | IM_TX_EMPTY_INT; 781 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 782 783 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 784 785 ifp->if_timer = 5; 786 787 /* Hand off a copy to the bpf. */ 788 bpf_mtap(ifp, m, BPF_D_OUT); 789 790 ifp->if_opackets++; 791 m_freem(m); 792 793 readcheck: 794 /* 795 * Check for incoming packets. We don't want to overflow the small 796 * RX FIFO. If nothing has arrived, attempt to queue another 797 * transmit packet. 798 */ 799 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 800 goto again; 801 } 802 803 /* 804 * Squirt a (possibly misaligned) mbuf to the device 805 */ 806 uint8_t 807 smc91cxx_copy_tx_frame(struct smc91cxx_softc *sc, struct mbuf *m0) 808 { 809 bus_space_tag_t bst = sc->sc_bst; 810 bus_space_handle_t bsh = sc->sc_bsh; 811 struct mbuf *m; 812 int len, leftover; 813 u_int16_t dbuf; 814 u_int8_t *p; 815 #ifdef DIAGNOSTIC 816 u_int8_t *lim; 817 #endif 818 819 /* start out with no leftover data */ 820 leftover = 0; 821 dbuf = 0; 822 823 /* Process the chain of mbufs */ 824 for (m = m0; m != NULL; m = m->m_next) { 825 /* 826 * Process all of the data in a single mbuf. 827 */ 828 p = mtod(m, u_int8_t *); 829 len = m->m_len; 830 #ifdef DIAGNOSTIC 831 lim = p + len; 832 #endif 833 834 while (len > 0) { 835 if (leftover) { 836 /* 837 * Data left over (from mbuf or realignment). 838 * Buffer the next byte, and write it and 839 * the leftover data out. 840 */ 841 dbuf |= *p++ << 8; 842 len--; 843 bus_space_write_2(bst, bsh, DATA_REG_W, dbuf); 844 leftover = 0; 845 } else if ((long) p & 1) { 846 /* 847 * Misaligned data. Buffer the next byte. 848 */ 849 dbuf = *p++; 850 len--; 851 leftover = 1; 852 } else { 853 /* 854 * Aligned data. This is the case we like. 855 * 856 * Write-region out as much as we can, then 857 * buffer the remaining byte (if any). 858 */ 859 leftover = len & 1; 860 len &= ~1; 861 bus_space_write_multi_stream_2(bst, bsh, 862 DATA_REG_W, (u_int16_t *)p, len >> 1); 863 p += len; 864 865 if (leftover) 866 dbuf = *p++; 867 len = 0; 868 } 869 } 870 if (len < 0) 871 panic("smc91cxx_copy_tx_frame: negative len"); 872 #ifdef DIAGNOSTIC 873 if (p != lim) 874 panic("smc91cxx_copy_tx_frame: p != lim"); 875 #endif 876 } 877 878 return dbuf; 879 } 880 881 /* 882 * Interrupt service routine. 883 */ 884 int 885 smc91cxx_intr(void *arg) 886 { 887 struct smc91cxx_softc *sc = arg; 888 struct ifnet *ifp = &sc->sc_ec.ec_if; 889 bus_space_tag_t bst = sc->sc_bst; 890 bus_space_handle_t bsh = sc->sc_bsh; 891 u_int8_t mask, interrupts, status; 892 u_int16_t packetno, tx_status, card_stats; 893 u_int16_t v; 894 895 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 896 !device_is_active(sc->sc_dev)) 897 return (0); 898 899 SMC_SELECT_BANK(sc, 2); 900 901 /* 902 * Obtain the current interrupt status and mask. 903 */ 904 v = bus_space_read_2(bst, bsh, INTR_STAT_REG_B); 905 906 /* 907 * Get the set of interrupt which occurred and eliminate any 908 * which are not enabled. 909 */ 910 mask = v >> 8; 911 interrupts = v & 0xff; 912 KDASSERT(mask == sc->sc_intmask); 913 status = interrupts & mask; 914 915 /* Ours? */ 916 if (status == 0) 917 return (0); 918 919 /* 920 * It's ours; disable all interrupts while we process them. 921 */ 922 smc91cxx_intr_mask_write(bst, bsh, 0); 923 924 /* 925 * Receive overrun interrupts. 926 */ 927 if (status & IM_RX_OVRN_INT) { 928 smc91cxx_intr_ack_write(bst, bsh, IM_RX_OVRN_INT, 0); 929 ifp->if_ierrors++; 930 } 931 932 /* 933 * Receive interrupts. 934 */ 935 if (status & IM_RCV_INT) { 936 smc91cxx_read(sc); 937 } 938 939 /* 940 * Memory allocation interrupts. 941 */ 942 if (status & IM_ALLOC_INT) { 943 /* Disable this interrupt. */ 944 mask &= ~IM_ALLOC_INT; 945 sc->sc_intmask &= ~IM_ALLOC_INT; 946 947 /* 948 * Save allocated packet number for use in start 949 */ 950 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 951 KASSERT(sc->sc_txpacketno & ARR_FAILED); 952 sc->sc_txpacketno = packetno; 953 954 /* 955 * We can transmit again! 956 */ 957 ifp->if_flags &= ~IFF_OACTIVE; 958 ifp->if_timer = 0; 959 } 960 961 /* 962 * Transmit complete interrupt. Handle transmission error messages. 963 * This will only be called on error condition because of AUTO RELEASE 964 * mode. 965 */ 966 if (status & IM_TX_INT) { 967 smc91cxx_intr_ack_write(bst, bsh, IM_TX_INT, 0); 968 969 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 970 FIFO_TX_MASK; 971 972 /* 973 * Select this as the packet to read from. 974 */ 975 bus_space_write_2(bst, bsh, PACKET_NUM_REG_B, packetno); 976 977 /* 978 * Position the pointer to the beginning of the packet, wait 979 * for preload. 980 */ 981 bus_space_write_2(bst, bsh, POINTER_REG_W, 982 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 983 delay(1); 984 985 /* 986 * Fetch the TX status word. This will be a copy of 987 * the EPH_STATUS_REG_W at the time of the transmission 988 * failure. 989 */ 990 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 991 992 if (tx_status & EPHSR_TX_SUC) { 993 static struct timeval txsuc_last; 994 static int txsuc_count; 995 if (ppsratecheck(&txsuc_last, &txsuc_count, 1)) 996 printf("%s: successful packet caused TX" 997 " interrupt?!\n", device_xname(sc->sc_dev)); 998 } else 999 ifp->if_oerrors++; 1000 1001 if (tx_status & EPHSR_LATCOL) 1002 ifp->if_collisions++; 1003 1004 /* Disable this interrupt (start will reenable if needed). */ 1005 mask &= ~IM_TX_INT; 1006 sc->sc_intmask &= ~IM_TX_INT; 1007 1008 /* 1009 * Some of these errors disable the transmitter; reenable it. 1010 */ 1011 SMC_SELECT_BANK(sc, 0); 1012 #ifdef SMC91CXX_SW_PAD 1013 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 1014 #else 1015 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 1016 TCR_ENABLE | TCR_PAD_ENABLE); 1017 #endif 1018 1019 /* 1020 * Kill the failed packet and wait for the MMU to unbusy. 1021 */ 1022 SMC_SELECT_BANK(sc, 2); 1023 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1024 /* XXX bound this loop! */ ; 1025 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 1026 1027 ifp->if_timer = 0; 1028 } 1029 1030 /* 1031 * Transmit underrun interrupts. We use this opportunity to 1032 * update transmit statistics from the card. 1033 */ 1034 if (status & IM_TX_EMPTY_INT) { 1035 smc91cxx_intr_ack_write(bst, bsh, IM_TX_EMPTY_INT, 0); 1036 1037 /* Disable this interrupt. */ 1038 mask &= ~IM_TX_EMPTY_INT; 1039 sc->sc_intmask &= ~IM_TX_EMPTY_INT; 1040 1041 SMC_SELECT_BANK(sc, 0); 1042 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 1043 1044 /* Single collisions. */ 1045 ifp->if_collisions += card_stats & ECR_COLN_MASK; 1046 1047 /* Multiple collisions. */ 1048 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 1049 1050 SMC_SELECT_BANK(sc, 2); 1051 1052 ifp->if_timer = 0; 1053 } 1054 1055 /* 1056 * Internal PHY status change 1057 */ 1058 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy && 1059 (status & IM_MD_INT)) { 1060 1061 /* 1062 * Internal PHY status change 1063 */ 1064 smc91cxx_intr_ack_write(bst, bsh, IM_MD_INT, 0); 1065 mii_pollstat(&sc->sc_mii); 1066 } 1067 1068 /* 1069 * Other errors. Reset the interface. 1070 */ 1071 if (status & IM_EPH_INT) { 1072 smc91cxx_stop(sc); 1073 smc91cxx_init(sc); 1074 } 1075 1076 /* 1077 * Attempt to queue more packets for transmission. 1078 */ 1079 if_schedule_deferred_start(ifp); 1080 1081 /* 1082 * Reenable the interrupts we wish to receive now that processing 1083 * is complete. 1084 */ 1085 mask |= sc->sc_intmask; 1086 smc91cxx_intr_mask_write(bst, bsh, mask); 1087 1088 if (status) 1089 rnd_add_uint32(&sc->rnd_source, status); 1090 1091 return (1); 1092 } 1093 1094 /* 1095 * Read a packet from the card and pass it up to the kernel. 1096 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 1097 */ 1098 void 1099 smc91cxx_read(struct smc91cxx_softc *sc) 1100 { 1101 struct ifnet *ifp = &sc->sc_ec.ec_if; 1102 bus_space_tag_t bst = sc->sc_bst; 1103 bus_space_handle_t bsh = sc->sc_bsh; 1104 struct ether_header *eh; 1105 struct mbuf *m; 1106 u_int16_t status, packetno, packetlen; 1107 u_int8_t *data; 1108 u_int32_t dr; 1109 bool first = true; 1110 1111 again: 1112 /* 1113 * Set data pointer to the beginning of the packet. Since 1114 * PTR_RCV is set, the packet number will be found automatically 1115 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1116 */ 1117 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1118 if (packetno & FIFO_REMPTY) { 1119 if (first) { 1120 aprint_error_dev(sc->sc_dev, 1121 "receive interrupt on empty fifo\n"); 1122 } 1123 return; 1124 } 1125 first = false; 1126 1127 bus_space_write_2(bst, bsh, POINTER_REG_W, 1128 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 1129 delay(1); 1130 1131 /* 1132 * First two words are status and packet length. 1133 */ 1134 dr = bus_space_read_4(bst, bsh, DATA_REG_W); 1135 status = (u_int16_t)dr; 1136 packetlen = (u_int16_t)(dr >> 16); 1137 1138 packetlen &= RLEN_MASK; 1139 if (packetlen < ETHER_MIN_LEN - ETHER_CRC_LEN + 6 || packetlen > 1534) { 1140 ifp->if_ierrors++; 1141 goto out; 1142 } 1143 1144 /* 1145 * The packet length includes 3 extra words: status, length, 1146 * and an extra word that includes the control byte. 1147 */ 1148 packetlen -= 6; 1149 1150 /* 1151 * Account for receive errors and discard. 1152 */ 1153 if (status & RS_ERRORS) { 1154 ifp->if_ierrors++; 1155 goto out; 1156 } 1157 1158 /* 1159 * Adjust for odd-length packet. 1160 */ 1161 if (status & RS_ODDFRAME) 1162 packetlen++; 1163 1164 /* 1165 * Allocate a header mbuf. 1166 */ 1167 MGETHDR(m, M_DONTWAIT, MT_DATA); 1168 if (m == NULL) 1169 goto out; 1170 m_set_rcvif(m, ifp); 1171 m->m_pkthdr.len = packetlen; 1172 1173 /* 1174 * Always put the packet in a cluster. 1175 * XXX should chain small mbufs if less than threshold. 1176 */ 1177 MCLGET(m, M_DONTWAIT); 1178 if ((m->m_flags & M_EXT) == 0) { 1179 m_freem(m); 1180 ifp->if_ierrors++; 1181 aprint_error_dev(sc->sc_dev, 1182 "can't allocate cluster for incoming packet\n"); 1183 goto out; 1184 } 1185 1186 /* 1187 * Pull the packet off the interface. Make sure the payload 1188 * is aligned. 1189 */ 1190 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1191 m->m_data = (char *) ALIGN(mtod(m, char *) + 1192 sizeof(struct ether_header)) - sizeof(struct ether_header); 1193 1194 eh = mtod(m, struct ether_header *); 1195 data = mtod(m, u_int8_t *); 1196 KASSERT(trunc_page((uintptr_t)data) == 1197 trunc_page((uintptr_t)data + packetlen - 1)); 1198 if (packetlen > 1) 1199 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 1200 (u_int16_t *)data, packetlen >> 1); 1201 if (packetlen & 1) { 1202 data += packetlen & ~1; 1203 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1204 } 1205 } else { 1206 m->m_data = (void *) ALIGN(mtod(m, void *)); 1207 eh = mtod(m, struct ether_header *); 1208 data = mtod(m, u_int8_t *); 1209 KASSERT(trunc_page((uintptr_t)data) == 1210 trunc_page((uintptr_t)data + packetlen - 1)); 1211 if (packetlen > 3) 1212 bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W, 1213 (u_int32_t *)data, packetlen >> 2); 1214 if (packetlen & 3) { 1215 data += packetlen & ~3; 1216 *((u_int32_t *)data) = 1217 bus_space_read_stream_4(bst, bsh, DATA_REG_W); 1218 } 1219 } 1220 1221 /* 1222 * Make sure to behave as IFF_SIMPLEX in all cases. 1223 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1224 * loops back packets to itself on promiscuous mode. 1225 * (should be ensured by chipset configuration) 1226 */ 1227 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1228 /* 1229 * Drop packet looped back from myself. 1230 */ 1231 if (ether_cmp(eh->ether_shost, CLLADDR(ifp->if_sadl)) == 0) { 1232 m_freem(m); 1233 goto out; 1234 } 1235 } 1236 1237 m->m_pkthdr.len = m->m_len = packetlen; 1238 1239 if_percpuq_enqueue(ifp->if_percpuq, m); 1240 1241 out: 1242 /* 1243 * Tell the card to free the memory occupied by this packet. 1244 */ 1245 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1246 /* XXX bound this loop! */ ; 1247 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1248 1249 /* 1250 * Check for another packet. 1251 */ 1252 goto again; 1253 } 1254 1255 /* 1256 * Process an ioctl request. 1257 */ 1258 int 1259 smc91cxx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1260 { 1261 struct smc91cxx_softc *sc = ifp->if_softc; 1262 struct ifaddr *ifa = (struct ifaddr *)data; 1263 struct ifreq *ifr = (struct ifreq *)data; 1264 int s, error = 0; 1265 1266 s = splnet(); 1267 1268 switch (cmd) { 1269 case SIOCINITIFADDR: 1270 if ((error = smc91cxx_enable(sc)) != 0) 1271 break; 1272 ifp->if_flags |= IFF_UP; 1273 smc91cxx_init(sc); 1274 switch (ifa->ifa_addr->sa_family) { 1275 #ifdef INET 1276 case AF_INET: 1277 arp_ifinit(ifp, ifa); 1278 break; 1279 #endif 1280 default: 1281 break; 1282 } 1283 break; 1284 1285 1286 case SIOCSIFFLAGS: 1287 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1288 break; 1289 /* XXX re-use ether_ioctl() */ 1290 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1291 case IFF_RUNNING: 1292 /* 1293 * If interface is marked down and it is running, 1294 * stop it. 1295 */ 1296 smc91cxx_stop(sc); 1297 ifp->if_flags &= ~IFF_RUNNING; 1298 smc91cxx_disable(sc); 1299 break; 1300 case IFF_UP: 1301 /* 1302 * If interface is marked up and it is stopped, 1303 * start it. 1304 */ 1305 if ((error = smc91cxx_enable(sc)) != 0) 1306 break; 1307 smc91cxx_init(sc); 1308 break; 1309 case IFF_UP|IFF_RUNNING: 1310 /* 1311 * Reset the interface to pick up changes in any 1312 * other flags that affect hardware registers. 1313 */ 1314 smc91cxx_reset(sc); 1315 break; 1316 case 0: 1317 break; 1318 } 1319 break; 1320 1321 case SIOCADDMULTI: 1322 case SIOCDELMULTI: 1323 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1324 error = EIO; 1325 break; 1326 } 1327 1328 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1329 /* 1330 * Multicast list has changed; set the hardware 1331 * filter accordingly. 1332 */ 1333 if (ifp->if_flags & IFF_RUNNING) 1334 smc91cxx_reset(sc); 1335 error = 0; 1336 } 1337 break; 1338 1339 case SIOCGIFMEDIA: 1340 case SIOCSIFMEDIA: 1341 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1342 break; 1343 1344 default: 1345 error = ether_ioctl(ifp, cmd, data); 1346 break; 1347 } 1348 1349 splx(s); 1350 return (error); 1351 } 1352 1353 /* 1354 * Reset the interface. 1355 */ 1356 void 1357 smc91cxx_reset(struct smc91cxx_softc *sc) 1358 { 1359 int s; 1360 1361 s = splnet(); 1362 smc91cxx_stop(sc); 1363 smc91cxx_init(sc); 1364 splx(s); 1365 } 1366 1367 /* 1368 * Watchdog timer. 1369 */ 1370 void 1371 smc91cxx_watchdog(struct ifnet *ifp) 1372 { 1373 struct smc91cxx_softc *sc = ifp->if_softc; 1374 1375 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1376 ifp->if_oerrors++; 1377 smc91cxx_reset(sc); 1378 } 1379 1380 /* 1381 * Stop output on the interface. 1382 */ 1383 void 1384 smc91cxx_stop(struct smc91cxx_softc *sc) 1385 { 1386 bus_space_tag_t bst = sc->sc_bst; 1387 bus_space_handle_t bsh = sc->sc_bsh; 1388 1389 /* 1390 * Clear interrupt mask; disable all interrupts. 1391 */ 1392 SMC_SELECT_BANK(sc, 2); 1393 smc91cxx_intr_mask_write(bst, bsh, 0); 1394 1395 /* 1396 * Disable transmitter and receiver. 1397 */ 1398 SMC_SELECT_BANK(sc, 0); 1399 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1400 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1401 1402 /* 1403 * Cancel watchdog timer. 1404 */ 1405 sc->sc_ec.ec_if.if_timer = 0; 1406 } 1407 1408 /* 1409 * Enable power on the interface. 1410 */ 1411 int 1412 smc91cxx_enable(struct smc91cxx_softc *sc) 1413 { 1414 1415 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1416 if ((*sc->sc_enable)(sc) != 0) { 1417 aprint_error_dev(sc->sc_dev, "device enable failed\n"); 1418 return (EIO); 1419 } 1420 } 1421 1422 sc->sc_flags |= SMC_FLAGS_ENABLED; 1423 return (0); 1424 } 1425 1426 /* 1427 * Disable power on the interface. 1428 */ 1429 void 1430 smc91cxx_disable(struct smc91cxx_softc *sc) 1431 { 1432 1433 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1434 (*sc->sc_disable)(sc); 1435 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1436 } 1437 } 1438 1439 int 1440 smc91cxx_activate(device_t self, enum devact act) 1441 { 1442 struct smc91cxx_softc *sc = device_private(self); 1443 1444 switch (act) { 1445 case DVACT_DEACTIVATE: 1446 if_deactivate(&sc->sc_ec.ec_if); 1447 return 0; 1448 default: 1449 return EOPNOTSUPP; 1450 } 1451 } 1452 1453 int 1454 smc91cxx_detach(device_t self, int flags) 1455 { 1456 struct smc91cxx_softc *sc = device_private(self); 1457 struct ifnet *ifp = &sc->sc_ec.ec_if; 1458 1459 /* Succeed now if there's no work to do. */ 1460 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1461 return (0); 1462 1463 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1464 smc91cxx_disable(sc); 1465 1466 /* smc91cxx_attach() never fails */ 1467 1468 /* Delete all media. */ 1469 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1470 1471 rnd_detach_source(&sc->rnd_source); 1472 1473 ether_ifdetach(ifp); 1474 if_detach(ifp); 1475 1476 return (0); 1477 } 1478 1479 u_int32_t 1480 smc91cxx_mii_bitbang_read(device_t self) 1481 { 1482 struct smc91cxx_softc *sc = device_private(self); 1483 1484 /* We're already in bank 3. */ 1485 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1486 } 1487 1488 void 1489 smc91cxx_mii_bitbang_write(device_t self, u_int32_t val) 1490 { 1491 struct smc91cxx_softc *sc = device_private(self); 1492 1493 /* We're already in bank 3. */ 1494 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1495 } 1496 1497 int 1498 smc91cxx_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1499 { 1500 struct smc91cxx_softc *sc = device_private(self); 1501 int rv; 1502 1503 SMC_SELECT_BANK(sc, 3); 1504 1505 rv = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg, 1506 val); 1507 1508 SMC_SELECT_BANK(sc, 2); 1509 1510 return rv; 1511 } 1512 1513 int 1514 smc91cxx_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1515 { 1516 struct smc91cxx_softc *sc = device_private(self); 1517 int rv; 1518 1519 SMC_SELECT_BANK(sc, 3); 1520 1521 rv = mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, 1522 val); 1523 1524 SMC_SELECT_BANK(sc, 2); 1525 1526 return rv; 1527 } 1528 1529 void 1530 smc91cxx_statchg(struct ifnet *ifp) 1531 { 1532 struct smc91cxx_softc *sc = ifp->if_softc; 1533 bus_space_tag_t bst = sc->sc_bst; 1534 bus_space_handle_t bsh = sc->sc_bsh; 1535 int mctl; 1536 1537 SMC_SELECT_BANK(sc, 0); 1538 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1539 if (sc->sc_mii.mii_media_active & IFM_FDX) 1540 mctl |= TCR_SWFDUP; 1541 else 1542 mctl &= ~TCR_SWFDUP; 1543 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1544 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1545 } 1546 1547 /* 1548 * One second timer, used to tick the MII. 1549 */ 1550 void 1551 smc91cxx_tick(void *arg) 1552 { 1553 struct smc91cxx_softc *sc = arg; 1554 int s; 1555 1556 #ifdef DIAGNOSTIC 1557 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1558 panic("smc91cxx_tick"); 1559 #endif 1560 1561 if (!device_is_active(sc->sc_dev)) 1562 return; 1563 1564 s = splnet(); 1565 mii_tick(&sc->sc_mii); 1566 splx(s); 1567 1568 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1569 } 1570
Indexes created Wed Sep 24 05:09:52 GMT 2025