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smc93cx6.c revision 1.11.2.2
      1  1.11.2.2      yamt /*	$NetBSD: smc93cx6.c,v 1.11.2.2 2007/10/27 11:31:05 yamt Exp $	*/
      2       1.1   mycroft 
      3       1.1   mycroft /*
      4       1.6      fvdl  * Interface for the 93C66/56/46/26/06 serial eeprom parts.
      5       1.1   mycroft  *
      6       1.6      fvdl  * Copyright (c) 1995, 1996 Daniel M. Eischen
      7       1.1   mycroft  * All rights reserved.
      8       1.1   mycroft  *
      9       1.1   mycroft  * Redistribution and use in source and binary forms, with or without
     10       1.1   mycroft  * modification, are permitted provided that the following conditions
     11       1.1   mycroft  * are met:
     12       1.1   mycroft  * 1. Redistributions of source code must retain the above copyright
     13       1.1   mycroft  *    notice immediately at the beginning of the file, without modification,
     14       1.1   mycroft  *    this list of conditions, and the following disclaimer.
     15       1.1   mycroft  * 2. Redistributions in binary form must reproduce the above copyright
     16       1.1   mycroft  *    notice, this list of conditions and the following disclaimer in the
     17       1.1   mycroft  *    documentation and/or other materials provided with the distribution.
     18       1.1   mycroft  * 3. Absolutely no warranty of function or purpose is made by the author
     19       1.1   mycroft  *    Daniel M. Eischen.
     20       1.1   mycroft  * 4. Modifications may be freely made to this file if the above conditions
     21       1.1   mycroft  *    are met.
     22       1.2  explorer  *
     23       1.6      fvdl  * $FreeBSD: src/sys/dev/aic7xxx/93cx6.c,v 1.5 2000/01/07 23:08:17 gibbs Exp $
     24       1.1   mycroft  */
     25       1.1   mycroft 
     26       1.1   mycroft /*
     27       1.6      fvdl  *   The instruction set of the 93C66/56/46/26/06 chips are as follows:
     28       1.1   mycroft  *
     29       1.6      fvdl  *               Start  OP	    *
     30       1.6      fvdl  *     Function   Bit  Code  Address**  Data     Description
     31       1.1   mycroft  *     -------------------------------------------------------------------
     32       1.1   mycroft  *     READ        1    10   A5 - A0             Reads data stored in memory,
     33       1.1   mycroft  *                                               starting at specified address
     34       1.8       wiz  *     EWEN        1    00   11XXXX              Write enable must precede
     35       1.1   mycroft  *                                               all programming modes
     36       1.1   mycroft  *     ERASE       1    11   A5 - A0             Erase register A5A4A3A2A1A0
     37       1.1   mycroft  *     WRITE       1    01   A5 - A0   D15 - D0  Writes register
     38       1.1   mycroft  *     ERAL        1    00   10XXXX              Erase all registers
     39       1.1   mycroft  *     WRAL        1    00   01XXXX    D15 - D0  Writes to all registers
     40       1.1   mycroft  *     EWDS        1    00   00XXXX              Disables all programming
     41       1.1   mycroft  *                                               instructions
     42       1.1   mycroft  *     *Note: A value of X for address is a don't care condition.
     43       1.6      fvdl  *    **Note: There are 8 address bits for the 93C56/66 chips unlike
     44       1.6      fvdl  *	      the 93C46/26/06 chips which have 6 address bits.
     45       1.1   mycroft  *
     46       1.1   mycroft  *   The 93C46 has a four wire interface: clock, chip select, data in, and
     47       1.1   mycroft  *   data out.  In order to perform one of the above functions, you need
     48       1.1   mycroft  *   to enable the chip select for a clock period (typically a minimum of
     49       1.1   mycroft  *   1 usec, with the clock high and low a minimum of 750 and 250 nsec
     50       1.6      fvdl  *   respectively).  While the chip select remains high, you can clock in
     51       1.1   mycroft  *   the instructions (above) starting with the start bit, followed by the
     52       1.1   mycroft  *   OP code, Address, and Data (if needed).  For the READ instruction, the
     53       1.1   mycroft  *   requested 16-bit register contents is read from the data out line but
     54       1.1   mycroft  *   is preceded by an initial zero (leading 0, followed by 16-bits, MSB
     55       1.1   mycroft  *   first).  The clock cycling from low to high initiates the next data
     56       1.1   mycroft  *   bit to be sent from the chip.
     57       1.1   mycroft  *
     58       1.1   mycroft  */
     59       1.9     lukem 
     60       1.9     lukem #include <sys/cdefs.h>
     61  1.11.2.2      yamt __KERNEL_RCSID(0, "$NetBSD: smc93cx6.c,v 1.11.2.2 2007/10/27 11:31:05 yamt Exp $");
     62       1.1   mycroft 
     63       1.6      fvdl #ifndef __NetBSD__
     64       1.6      fvdl #include "opt_aic7xxx.h"
     65       1.6      fvdl #endif
     66       1.6      fvdl 
     67       1.1   mycroft #include <sys/param.h>
     68       1.1   mycroft #include <sys/systm.h>
     69  1.11.2.2      yamt #include <sys/bus.h>
     70  1.11.2.1      yamt #ifdef __NetBSD__
     71       1.1   mycroft #include <dev/ic/smc93cx6var.h>
     72       1.6      fvdl #else
     73       1.6      fvdl #include <machine/bus_memio.h>
     74       1.6      fvdl #include <machine/bus_pio.h>
     75       1.6      fvdl #include <dev/aic7xxx/93cx6.h>
     76       1.1   mycroft #endif
     77       1.1   mycroft 
     78       1.1   mycroft /*
     79       1.1   mycroft  * Right now, we only have to read the SEEPROM.  But we make it easier to
     80       1.1   mycroft  * add other 93Cx6 functions.
     81       1.1   mycroft  */
     82       1.1   mycroft static struct seeprom_cmd {
     83       1.1   mycroft   	unsigned char len;
     84       1.1   mycroft  	unsigned char bits[3];
     85       1.1   mycroft } seeprom_read = {3, {1, 1, 0}};
     86       1.1   mycroft 
     87      1.11    dyoung /* XXX bus barriers */
     88      1.10    dyoung #define CLOCK_PULSE(sd, rdy)	do {					\
     89      1.10    dyoung 	/*								\
     90      1.10    dyoung 	 * Wait for the SEERDY to go high; about 800 ns.		\
     91      1.10    dyoung 	 */								\
     92       1.7     lukem 	int cpi = 1000;							\
     93      1.10    dyoung 	if (rdy == 0) {							\
     94      1.10    dyoung 		DELAY(4); /* more than long enough */			\
     95      1.10    dyoung 		break;							\
     96      1.10    dyoung 	}								\
     97       1.7     lukem 	while ((SEEPROM_STATUS_INB(sd) & rdy) == 0 && cpi-- > 0) {	\
     98       1.6      fvdl 		;  /* Do nothing */					\
     99       1.6      fvdl 	}								\
    100       1.6      fvdl 	(void)SEEPROM_INB(sd);	/* Clear clock */			\
    101      1.10    dyoung } while (0)
    102       1.1   mycroft 
    103       1.1   mycroft /*
    104       1.1   mycroft  * Read the serial EEPROM and returns 1 if successful and 0 if
    105       1.1   mycroft  * not successful.
    106       1.1   mycroft  */
    107       1.1   mycroft int
    108       1.1   mycroft read_seeprom(sd, buf, start_addr, count)
    109       1.1   mycroft 	struct seeprom_descriptor *sd;
    110       1.1   mycroft 	u_int16_t *buf;
    111       1.5   thorpej 	bus_size_t start_addr;
    112       1.5   thorpej 	bus_size_t count;
    113       1.1   mycroft {
    114       1.6      fvdl 	int i = 0;
    115       1.6      fvdl 	u_int k = 0;
    116       1.1   mycroft 	u_int16_t v;
    117      1.10    dyoung 	u_int32_t temp;
    118       1.1   mycroft 
    119       1.1   mycroft 	/*
    120       1.1   mycroft 	 * Read the requested registers of the seeprom.  The loop
    121       1.1   mycroft 	 * will range from 0 to count-1.
    122       1.1   mycroft 	 */
    123       1.1   mycroft 	for (k = start_addr; k < count + start_addr; k++) {
    124       1.1   mycroft 		/* Send chip select for one clock cycle. */
    125       1.1   mycroft 		temp = sd->sd_MS ^ sd->sd_CS;
    126       1.1   mycroft 		SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
    127       1.1   mycroft 		CLOCK_PULSE(sd, sd->sd_RDY);
    128       1.1   mycroft 
    129       1.1   mycroft 		/*
    130       1.1   mycroft 		 * Now we're ready to send the read command followed by the
    131       1.1   mycroft 		 * address of the 16-bit register we want to read.
    132       1.1   mycroft 		 */
    133       1.1   mycroft 		for (i = 0; i < seeprom_read.len; i++) {
    134       1.1   mycroft 			if (seeprom_read.bits[i] != 0)
    135       1.1   mycroft 				temp ^= sd->sd_DO;
    136       1.1   mycroft 			SEEPROM_OUTB(sd, temp);
    137       1.1   mycroft 			CLOCK_PULSE(sd, sd->sd_RDY);
    138       1.1   mycroft 			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
    139       1.1   mycroft 			CLOCK_PULSE(sd, sd->sd_RDY);
    140       1.1   mycroft 			if (seeprom_read.bits[i] != 0)
    141       1.1   mycroft 				temp ^= sd->sd_DO;
    142       1.1   mycroft 		}
    143       1.6      fvdl 		/* Send the 6 or 8 bit address (MSB first, LSB last). */
    144       1.6      fvdl 		for (i = (sd->sd_chip - 1); i >= 0; i--) {
    145       1.1   mycroft 			if ((k & (1 << i)) != 0)
    146       1.1   mycroft 				temp ^= sd->sd_DO;
    147       1.1   mycroft 			SEEPROM_OUTB(sd, temp);
    148       1.1   mycroft 			CLOCK_PULSE(sd, sd->sd_RDY);
    149       1.1   mycroft 			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
    150       1.1   mycroft 			CLOCK_PULSE(sd, sd->sd_RDY);
    151       1.1   mycroft 			if ((k & (1 << i)) != 0)
    152       1.1   mycroft 				temp ^= sd->sd_DO;
    153       1.1   mycroft 		}
    154       1.1   mycroft 
    155       1.1   mycroft 		/*
    156       1.1   mycroft 		 * Now read the 16 bit register.  An initial 0 precedes the
    157       1.1   mycroft 		 * register contents which begins with bit 15 (MSB) and ends
    158       1.1   mycroft 		 * with bit 0 (LSB).  The initial 0 will be shifted off the
    159       1.1   mycroft 		 * top of our word as we let the loop run from 0 to 16.
    160       1.1   mycroft 		 */
    161       1.1   mycroft 		v = 0;
    162       1.1   mycroft 		for (i = 16; i >= 0; i--) {
    163       1.1   mycroft 			SEEPROM_OUTB(sd, temp);
    164       1.1   mycroft 			CLOCK_PULSE(sd, sd->sd_RDY);
    165       1.1   mycroft 			v <<= 1;
    166       1.6      fvdl 			if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
    167       1.1   mycroft 				v |= 1;
    168       1.1   mycroft 			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
    169       1.1   mycroft 			CLOCK_PULSE(sd, sd->sd_RDY);
    170       1.1   mycroft 		}
    171       1.1   mycroft 
    172       1.1   mycroft 		buf[k - start_addr] = v;
    173       1.1   mycroft 
    174       1.1   mycroft 		/* Reset the chip select for the next command cycle. */
    175       1.1   mycroft 		temp = sd->sd_MS;
    176       1.1   mycroft 		SEEPROM_OUTB(sd, temp);
    177       1.1   mycroft 		CLOCK_PULSE(sd, sd->sd_RDY);
    178       1.1   mycroft 		SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
    179       1.1   mycroft 		CLOCK_PULSE(sd, sd->sd_RDY);
    180       1.1   mycroft 		SEEPROM_OUTB(sd, temp);
    181       1.1   mycroft 		CLOCK_PULSE(sd, sd->sd_RDY);
    182       1.1   mycroft 	}
    183       1.6      fvdl #ifdef AHC_DUMP_EEPROM
    184       1.6      fvdl 	printf("\nSerial EEPROM:\n\t");
    185       1.1   mycroft 	for (k = 0; k < count; k = k + 1) {
    186       1.6      fvdl 		if (((k % 8) == 0) && (k != 0)) {
    187       1.6      fvdl 			printf ("\n\t");
    188       1.1   mycroft 		}
    189       1.4  christos 		printf (" 0x%x", buf[k]);
    190       1.1   mycroft 	}
    191       1.4  christos 	printf ("\n");
    192       1.1   mycroft #endif
    193       1.1   mycroft 	return (1);
    194       1.1   mycroft }
    195