spdmem.c revision 1.2
1 /* $NetBSD: spdmem.c,v 1.2 2010/06/29 04:42:30 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Nicolas Joly 5 * Copyright (c) 2007 Paul Goyette 6 * Copyright (c) 2007 Tobias Nygren 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Serial Presence Detect (SPD) memory identification 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.2 2010/06/29 04:42:30 pgoyette Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/device.h> 42 #include <sys/endian.h> 43 #include <sys/sysctl.h> 44 #include <machine/bswap.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/ic/spdmemreg.h> 48 #include <dev/ic/spdmemvar.h> 49 50 SYSCTL_SETUP_PROTO(sysctl_spdmem_setup); 51 52 /* Routines for decoding spd data */ 53 static void decode_edofpm(const struct sysctlnode *, device_t, struct spdmem *); 54 static void decode_rom(const struct sysctlnode *, device_t, struct spdmem *); 55 static void decode_sdram(const struct sysctlnode *, device_t, struct spdmem *, 56 int); 57 static void decode_ddr(const struct sysctlnode *, device_t, struct spdmem *); 58 static void decode_ddr2(const struct sysctlnode *, device_t, struct spdmem *); 59 static void decode_ddr3(const struct sysctlnode *, device_t, struct spdmem *); 60 static void decode_fbdimm(const struct sysctlnode *, device_t, struct spdmem *); 61 62 static void decode_size_speed(const struct sysctlnode *, int, int, int, int, 63 bool, const char *, int); 64 static void decode_voltage_refresh(device_t, struct spdmem *); 65 66 #define IS_RAMBUS_TYPE (s->sm_len < 4) 67 68 static const char* spdmem_basic_types[] = { 69 "unknown", 70 "FPM", 71 "EDO", 72 "Pipelined Nibble", 73 "SDRAM", 74 "ROM", 75 "DDR SGRAM", 76 "DDR SDRAM", 77 "DDR2 SDRAM", 78 "DDR2 SDRAM FB", 79 "DDR2 SDRAM FB Probe", 80 "DDR3 SDRAM" 81 }; 82 83 static const char* spdmem_superset_types[] = { 84 "unknown", 85 "ESDRAM", 86 "DDR ESDRAM", 87 "PEM EDO", 88 "PEM SDRAM" 89 }; 90 91 static const char* spdmem_voltage_types[] = { 92 "TTL (5V tolerant)", 93 "LvTTL (not 5V tolerant)", 94 "HSTL 1.5V", 95 "SSTL 3.3V", 96 "SSTL 2.5V", 97 "SSTL 1.8V" 98 }; 99 100 static const char* spdmem_refresh_types[] = { 101 "15.625us", 102 "3.9us", 103 "7.8us", 104 "31.3us", 105 "62.5us", 106 "125us" 107 }; 108 109 static const char* spdmem_parity_types[] = { 110 "no parity or ECC", 111 "data parity", 112 "data ECC", 113 "data parity and ECC", 114 "cmd/addr parity", 115 "cmd/addr/data parity", 116 "cmd/addr parity, data ECC", 117 "cmd/addr/data parity, data ECC" 118 }; 119 120 /* Cycle time fractional values (units of .001 ns) for DDR2 SDRAM */ 121 static const uint16_t spdmem_cycle_frac[] = { 122 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 123 250, 333, 667, 750, 999, 999 124 }; 125 126 /* Format string for timing info */ 127 static const char* latency="tAA-tRCD-tRP-tRAS: %d-%d-%d-%d\n"; 128 129 /* sysctl stuff */ 130 static int hw_node = CTL_EOL; 131 132 /* CRC functions used for certain memory types */ 133 134 static uint16_t spdcrc16 (struct spdmem_softc *sc, int count) 135 { 136 uint16_t crc; 137 int i, j; 138 uint8_t val; 139 crc = 0; 140 for (j = 0; j <= count; j++) { 141 val = (sc->sc_read)(sc, j); 142 crc = crc ^ val << 8; 143 for (i = 0; i < 8; ++i) 144 if (crc & 0x8000) 145 crc = crc << 1 ^ 0x1021; 146 else 147 crc = crc << 1; 148 } 149 return (crc & 0xFFFF); 150 } 151 152 int 153 spdmem_common_probe(struct spdmem_softc *sc) 154 { 155 int cksum = 0; 156 uint8_t i, val, spd_type; 157 int spd_len, spd_crc_cover; 158 uint16_t crc_calc, crc_spd; 159 160 spd_type = (sc->sc_read)(sc, 2); 161 162 /* For older memory types, validate the checksum over 1st 63 bytes */ 163 if (spd_type <= SPDMEM_MEMTYPE_DDR2SDRAM) { 164 for (i = 0; i < 63; i++) 165 cksum += (sc->sc_read)(sc, i); 166 167 val = (sc->sc_read)(sc, 63); 168 169 if (cksum == 0 || (cksum & 0xff) != val) { 170 aprint_debug("spd checksum failed, calc = 0x%02x, " 171 "spd = 0x%02x\n", cksum, val); 172 return 0; 173 } else 174 return 1; 175 } 176 177 /* For DDR3 and FBDIMM, verify the CRC */ 178 else if (spd_type <= SPDMEM_MEMTYPE_DDR3SDRAM) { 179 spd_len = (sc->sc_read)(sc, 0); 180 if (spd_len & SPDMEM_SPDCRC_116) 181 spd_crc_cover = 116; 182 else 183 spd_crc_cover = 125; 184 switch (spd_len & SPDMEM_SPDLEN_MASK) { 185 case SPDMEM_SPDLEN_128: 186 spd_len = 128; 187 break; 188 case SPDMEM_SPDLEN_176: 189 spd_len = 176; 190 break; 191 case SPDMEM_SPDLEN_256: 192 spd_len = 256; 193 break; 194 default: 195 return 0; 196 } 197 if (spd_crc_cover > spd_len) 198 return 0; 199 crc_calc = spdcrc16(sc, spd_crc_cover); 200 crc_spd = (sc->sc_read)(sc, 127) << 8; 201 crc_spd |= (sc->sc_read)(sc, 126); 202 if (crc_calc != crc_spd) { 203 aprint_debug("crc16 failed, covers %d bytes, " 204 "calc = 0x%04x, spd = 0x%04x\n", 205 spd_crc_cover, crc_calc, crc_spd); 206 return 0; 207 } 208 return 1; 209 } 210 211 /* For unrecognized memory types, don't match at all */ 212 return 0; 213 } 214 215 void 216 spdmem_common_attach(struct spdmem_softc *sc, device_t self) 217 { 218 struct spdmem *s = &(sc->sc_spd_data); 219 const char *type; 220 const char *rambus_rev = "Reserved"; 221 int dimm_size; 222 int i; 223 unsigned int spd_len, spd_size; 224 const struct sysctlnode *node = NULL; 225 226 /* 227 * FBDIMM and DDR3 (and probably all newer) have a different 228 * encoding of the SPD EEPROM used/total sizes 229 */ 230 s->sm_len = (sc->sc_read)(sc, 0); 231 s->sm_size = (sc->sc_read)(sc, 1); 232 s->sm_type = (sc->sc_read)(sc, 2); 233 234 if (s->sm_type >= SPDMEM_MEMTYPE_FBDIMM) { 235 spd_size = 64 << (s->sm_len & SPDMEM_SPDSIZE_MASK); 236 switch (s->sm_len & SPDMEM_SPDLEN_MASK) { 237 case SPDMEM_SPDLEN_128: 238 spd_len = 128; 239 break; 240 case SPDMEM_SPDLEN_176: 241 spd_len = 176; 242 break; 243 case SPDMEM_SPDLEN_256: 244 spd_len = 256; 245 break; 246 default: 247 spd_len = 64; 248 break; 249 } 250 } else { 251 spd_size = 1 << s->sm_size; 252 spd_len = s->sm_len; 253 if (spd_len < 64) 254 spd_len = 64; 255 } 256 if (spd_len > spd_size) 257 spd_len = spd_size; 258 if (spd_len > sizeof(struct spdmem)) 259 spd_len = sizeof(struct spdmem); 260 for (i = 3; i < spd_len; i++) 261 ((uint8_t *)s)[i] = (sc->sc_read)(sc, i); 262 263 #ifdef DEBUG 264 for (i = 0; i < spd_len; i += 16) { 265 int j, k; 266 aprint_debug("\n"); 267 aprint_debug_dev(self, "0x%02x:", i); 268 k = (spd_len > i + 16) ? spd_len : i + 16; 269 for (j = i; j < k; j++) 270 aprint_debug(" %02x", ((uint8_t *)s)[j]); 271 } 272 aprint_debug("\n"); 273 aprint_debug_dev(self, ""); 274 #endif 275 276 /* 277 * Setup our sysctl subtree, hw.spdmemN 278 */ 279 if (hw_node != CTL_EOL) 280 sysctl_createv(NULL, 0, NULL, &node, 281 0, CTLTYPE_NODE, 282 device_xname(self), NULL, NULL, 0, NULL, 0, 283 CTL_HW, CTL_CREATE, CTL_EOL); 284 if (node != NULL && spd_len != 0) 285 sysctl_createv(NULL, 0, NULL, NULL, 286 0, 287 CTLTYPE_STRUCT, "spd_data", 288 SYSCTL_DESCR("raw spd data"), NULL, 289 0, s, spd_len, 290 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 291 292 /* 293 * Decode and print key SPD contents 294 */ 295 if (IS_RAMBUS_TYPE) { 296 if (s->sm_type == SPDMEM_MEMTYPE_RAMBUS) 297 type = "Rambus"; 298 else if (s->sm_type == SPDMEM_MEMTYPE_DIRECTRAMBUS) 299 type = "Direct Rambus"; 300 else 301 type = "Rambus (unknown)"; 302 303 switch (s->sm_len) { 304 case 0: 305 rambus_rev = "Invalid"; 306 break; 307 case 1: 308 rambus_rev = "0.7"; 309 break; 310 case 2: 311 rambus_rev = "1.0"; 312 break; 313 default: 314 rambus_rev = "Reserved"; 315 break; 316 } 317 } else { 318 if (s->sm_type < __arraycount(spdmem_basic_types)) 319 type = spdmem_basic_types[s->sm_type]; 320 else 321 type = "unknown memory type"; 322 323 if (s->sm_type == SPDMEM_MEMTYPE_EDO && 324 s->sm_fpm.fpm_superset == SPDMEM_SUPERSET_EDO_PEM) 325 type = spdmem_superset_types[SPDMEM_SUPERSET_EDO_PEM]; 326 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 327 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_SDRAM_PEM) 328 type = spdmem_superset_types[SPDMEM_SUPERSET_SDRAM_PEM]; 329 if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM && 330 s->sm_ddr.ddr_superset == SPDMEM_SUPERSET_DDR_ESDRAM) 331 type = 332 spdmem_superset_types[SPDMEM_SUPERSET_DDR_ESDRAM]; 333 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 334 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_ESDRAM) { 335 type = spdmem_superset_types[SPDMEM_SUPERSET_ESDRAM]; 336 } 337 } 338 339 aprint_naive("\n"); 340 aprint_normal("\n"); 341 aprint_normal_dev(self, "%s", type); 342 strlcpy(sc->sc_type, type, SPDMEM_TYPE_MAXLEN); 343 if (node != NULL) 344 sysctl_createv(NULL, 0, NULL, NULL, 345 0, 346 CTLTYPE_STRING, "mem_type", 347 SYSCTL_DESCR("memory module type"), NULL, 348 0, sc->sc_type, 0, 349 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 350 351 if (IS_RAMBUS_TYPE) { 352 aprint_normal(", SPD Revision %s", rambus_rev); 353 dimm_size = 1 << (s->sm_rdr.rdr_rows + s->sm_rdr.rdr_cols - 13); 354 if (dimm_size >= 1024) 355 aprint_normal(", %dGB\n", dimm_size / 1024); 356 else 357 aprint_normal(", %dMB\n", dimm_size); 358 359 /* No further decode for RAMBUS memory */ 360 return; 361 } 362 switch (s->sm_type) { 363 case SPDMEM_MEMTYPE_EDO: 364 case SPDMEM_MEMTYPE_FPM: 365 decode_edofpm(node, self, s); 366 break; 367 case SPDMEM_MEMTYPE_ROM: 368 decode_rom(node, self, s); 369 break; 370 case SPDMEM_MEMTYPE_SDRAM: 371 decode_sdram(node, self, s, spd_len); 372 break; 373 case SPDMEM_MEMTYPE_DDRSDRAM: 374 decode_ddr(node, self, s); 375 break; 376 case SPDMEM_MEMTYPE_DDR2SDRAM: 377 decode_ddr2(node, self, s); 378 break; 379 case SPDMEM_MEMTYPE_DDR3SDRAM: 380 decode_ddr3(node, self, s); 381 break; 382 case SPDMEM_MEMTYPE_FBDIMM: 383 case SPDMEM_MEMTYPE_FBDIMM_PROBE: 384 decode_fbdimm(node, self, s); 385 break; 386 } 387 } 388 389 SYSCTL_SETUP(sysctl_spdmem_setup, "sysctl hw.spdmem subtree setup") 390 { 391 const struct sysctlnode *node; 392 393 if (sysctl_createv(clog, 0, NULL, &node, 394 CTLFLAG_PERMANENT, 395 CTLTYPE_NODE, "hw", NULL, 396 NULL, 0, NULL, 0, 397 CTL_HW, CTL_EOL) != 0) 398 return; 399 400 hw_node = node->sysctl_num; 401 } 402 403 static void 404 decode_size_speed(const struct sysctlnode *node, int dimm_size, int cycle_time, 405 int d_clk, int bits, bool round, const char *ddr_type_string, 406 int speed) 407 { 408 int p_clk; 409 410 if (dimm_size < 1024) 411 aprint_normal("%dMB", dimm_size); 412 else 413 aprint_normal("%dGB", dimm_size / 1024); 414 if (node != NULL) 415 sysctl_createv(NULL, 0, NULL, NULL, 416 CTLFLAG_IMMEDIATE, 417 CTLTYPE_INT, "size", 418 SYSCTL_DESCR("module size in MB"), NULL, 419 dimm_size, NULL, 0, 420 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 421 422 if (cycle_time == 0) { 423 aprint_normal("\n"); 424 return; 425 } 426 427 /* 428 * Calculate p_clk first, since for DDR3 we need maximum significance. 429 * DDR3 rating is not rounded to a multiple of 100. This results in 430 * cycle_time of 1.5ns displayed as PC3-10666. 431 * 432 * For SDRAM, the speed is provided by the caller so we use it. 433 */ 434 d_clk *= 1000 * 1000; 435 if (speed) 436 p_clk = speed; 437 else 438 p_clk = (d_clk * bits) / 8 / cycle_time; 439 d_clk = ((d_clk + cycle_time / 2) ) / cycle_time; 440 if (round) { 441 if ((p_clk % 100) >= 50) 442 p_clk += 50; 443 p_clk -= p_clk % 100; 444 } 445 aprint_normal(", %dMHz (%s-%d)\n", 446 d_clk, ddr_type_string, p_clk); 447 if (node != NULL) 448 sysctl_createv(NULL, 0, NULL, NULL, 449 CTLFLAG_IMMEDIATE, 450 CTLTYPE_INT, "speed", 451 SYSCTL_DESCR("memory speed in MHz"), 452 NULL, d_clk, NULL, 0, 453 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 454 } 455 456 static void 457 decode_voltage_refresh(device_t self, struct spdmem *s) 458 { 459 const char *voltage, *refresh; 460 461 if (s->sm_voltage < __arraycount(spdmem_voltage_types)) 462 voltage = spdmem_voltage_types[s->sm_voltage]; 463 else 464 voltage = "unknown"; 465 466 if (s->sm_refresh < __arraycount(spdmem_refresh_types)) 467 refresh = spdmem_refresh_types[s->sm_refresh]; 468 else 469 refresh = "unknown"; 470 471 aprint_verbose_dev(self, "voltage %s, refresh time %s%s\n", 472 voltage, refresh, 473 s->sm_selfrefresh?" (self-refreshing)":""); 474 } 475 476 static void 477 decode_edofpm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 478 aprint_normal("\n"); 479 aprint_verbose_dev(self, 480 "%d rows, %d cols, %d banks, %dns tRAC, %dns tCAC\n", 481 s->sm_fpm.fpm_rows, s->sm_fpm.fpm_cols, s->sm_fpm.fpm_banks, 482 s->sm_fpm.fpm_tRAC, s->sm_fpm.fpm_tCAC); 483 } 484 485 static void 486 decode_rom(const struct sysctlnode *node, device_t self, struct spdmem *s) { 487 aprint_normal("\n"); 488 aprint_verbose_dev(self, "%d rows, %d cols, %d banks\n", 489 s->sm_rom.rom_rows, s->sm_rom.rom_cols, s->sm_rom.rom_banks); 490 } 491 492 static void 493 decode_sdram(const struct sysctlnode *node, device_t self, struct spdmem *s, 494 int spd_len) { 495 int dimm_size, cycle_time, bits, tAA, i, speed, freq; 496 497 aprint_normal("%s, %s, ", 498 (s->sm_sdr.sdr_mod_attrs & SPDMEM_SDR_MASK_REG)? 499 " (registered)":"", 500 (s->sm_config < __arraycount(spdmem_parity_types))? 501 spdmem_parity_types[s->sm_config]:"invalid parity"); 502 503 dimm_size = 1 << (s->sm_sdr.sdr_rows + s->sm_sdr.sdr_cols - 17); 504 dimm_size *= s->sm_sdr.sdr_banks * s->sm_sdr.sdr_banks_per_chip; 505 506 cycle_time = s->sm_sdr.sdr_cycle_whole * 1000 + 507 s->sm_sdr.sdr_cycle_tenths * 100; 508 bits = le16toh(s->sm_sdr.sdr_datawidth); 509 if (s->sm_config == 1 || s->sm_config == 2) 510 bits -= 8; 511 512 /* Calculate speed here - from OpenBSD */ 513 if (spd_len >= 128) 514 freq = ((uint8_t *)s)[126]; 515 else 516 freq = 0; 517 switch (freq) { 518 /* 519 * Must check cycle time since some PC-133 DIMMs 520 * actually report PC-100 521 */ 522 case 100: 523 case 133: 524 if (cycle_time < 8000) 525 speed = 133; 526 else 527 speed = 100; 528 break; 529 case 0x66: /* Legacy DIMMs use _hex_ 66! */ 530 default: 531 speed = 66; 532 } 533 decode_size_speed(node, dimm_size, cycle_time, 1, bits, FALSE, "PC", 534 speed); 535 536 aprint_verbose_dev(self, 537 "%d rows, %d cols, %d banks, %d banks/chip, %d.%dns cycle time\n", 538 s->sm_sdr.sdr_rows, s->sm_sdr.sdr_cols, s->sm_sdr.sdr_banks, 539 s->sm_sdr.sdr_banks_per_chip, cycle_time/1000, 540 (cycle_time % 1000) / 100); 541 542 tAA = 0; 543 for (i = 0; i < 8; i++) 544 if (s->sm_sdr.sdr_tCAS & (1 << i)) 545 tAA = i; 546 tAA++; 547 aprint_verbose_dev(self, latency, tAA, s->sm_sdr.sdr_tRCD, 548 s->sm_sdr.sdr_tRP, s->sm_sdr.sdr_tRAS); 549 550 decode_voltage_refresh(self, s); 551 } 552 553 static void 554 decode_ddr(const struct sysctlnode *node, device_t self, struct spdmem *s) { 555 int dimm_size, cycle_time, bits, tAA, i; 556 557 aprint_normal("%s, %s, ", 558 (s->sm_ddr.ddr_mod_attrs & SPDMEM_DDR_MASK_REG)? 559 " (registered)":"", 560 (s->sm_config < __arraycount(spdmem_parity_types))? 561 spdmem_parity_types[s->sm_config]:"invalid parity"); 562 563 dimm_size = 1 << (s->sm_ddr.ddr_rows + s->sm_ddr.ddr_cols - 17); 564 dimm_size *= s->sm_ddr.ddr_ranks * s->sm_ddr.ddr_banks_per_chip; 565 566 cycle_time = s->sm_ddr.ddr_cycle_whole * 1000 + 567 spdmem_cycle_frac[s->sm_ddr.ddr_cycle_tenths]; 568 bits = le16toh(s->sm_ddr.ddr_datawidth); 569 if (s->sm_config == 1 || s->sm_config == 2) 570 bits -= 8; 571 decode_size_speed(node, dimm_size, cycle_time, 2, bits, TRUE, "PC", 0); 572 573 aprint_verbose_dev(self, 574 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%dns cycle time\n", 575 s->sm_ddr.ddr_rows, s->sm_ddr.ddr_cols, s->sm_ddr.ddr_ranks, 576 s->sm_ddr.ddr_banks_per_chip, cycle_time/1000, 577 (cycle_time % 1000 + 50) / 100); 578 579 tAA = 0; 580 for (i = 2; i < 8; i++) 581 if (s->sm_ddr.ddr_tCAS & (1 << i)) 582 tAA = i; 583 tAA /= 2; 584 585 #define __DDR_ROUND(scale, field) \ 586 ((scale * s->sm_ddr.field + cycle_time - 1) / cycle_time) 587 588 aprint_verbose_dev(self, latency, tAA, __DDR_ROUND(250, ddr_tRCD), 589 __DDR_ROUND(250, ddr_tRP), __DDR_ROUND(1000, ddr_tRAS)); 590 591 #undef __DDR_ROUND 592 593 decode_voltage_refresh(self, s); 594 } 595 596 static void 597 decode_ddr2(const struct sysctlnode *node, device_t self, struct spdmem *s) { 598 int dimm_size, cycle_time, bits, tAA, i; 599 600 aprint_normal("%s, %s, ", 601 (s->sm_ddr2.ddr2_mod_attrs & SPDMEM_DDR2_MASK_REG)? 602 " (registered)":"", 603 (s->sm_config < __arraycount(spdmem_parity_types))? 604 spdmem_parity_types[s->sm_config]:"invalid parity"); 605 606 dimm_size = 1 << (s->sm_ddr2.ddr2_rows + s->sm_ddr2.ddr2_cols - 17); 607 dimm_size *= (s->sm_ddr2.ddr2_ranks + 1) * 608 s->sm_ddr2.ddr2_banks_per_chip; 609 610 cycle_time = s->sm_ddr2.ddr2_cycle_whole * 1000 + 611 spdmem_cycle_frac[s->sm_ddr2.ddr2_cycle_frac]; 612 bits = s->sm_ddr2.ddr2_datawidth; 613 if ((s->sm_config & 0x03) != 0) 614 bits -= 8; 615 decode_size_speed(node, dimm_size, cycle_time, 2, bits, TRUE, "PC2", 0); 616 617 aprint_verbose_dev(self, 618 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%02dns cycle time\n", 619 s->sm_ddr2.ddr2_rows, s->sm_ddr2.ddr2_cols, 620 s->sm_ddr2.ddr2_ranks + 1, s->sm_ddr2.ddr2_banks_per_chip, 621 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 622 623 tAA = 0; 624 for (i = 2; i < 8; i++) 625 if (s->sm_ddr2.ddr2_tCAS & (1 << i)) 626 tAA = i; 627 628 #define __DDR2_ROUND(scale, field) \ 629 ((scale * s->sm_ddr2.field + cycle_time - 1) / cycle_time) 630 631 aprint_verbose_dev(self, latency, tAA, __DDR2_ROUND(250, ddr2_tRCD), 632 __DDR2_ROUND(250, ddr2_tRP), __DDR2_ROUND(1000, ddr2_tRAS)); 633 634 #undef __DDR_ROUND 635 636 decode_voltage_refresh(self, s); 637 } 638 639 static void 640 decode_ddr3(const struct sysctlnode *node, device_t self, struct spdmem *s) { 641 int dimm_size, cycle_time, bits; 642 643 if (s->sm_ddr3.ddr3_mod_type == 644 SPDMEM_DDR3_TYPE_MINI_RDIMM || 645 s->sm_ddr3.ddr3_mod_type == SPDMEM_DDR3_TYPE_RDIMM) 646 aprint_normal(" (registered)"); 647 aprint_normal(", %sECC, %stemp-sensor, ", 648 (s->sm_ddr3.ddr3_hasECC)?"":"no ", 649 (s->sm_ddr3.ddr3_has_therm_sensor)?"":"no "); 650 651 /* 652 * DDR3 size specification is quite different from others 653 * 654 * Module capacity is defined as 655 * Chip_Capacity_in_bits / 8bits-per-byte * 656 * external_bus_width / internal_bus_width 657 * We further divide by 2**20 to get our answer in MB 658 */ 659 dimm_size = (s->sm_ddr3.ddr3_chipsize + 28 - 20) - 3 + 660 (s->sm_ddr3.ddr3_datawidth + 3) - 661 (s->sm_ddr3.ddr3_chipwidth + 2); 662 dimm_size = (1 << dimm_size) * (s->sm_ddr3.ddr3_physbanks + 1); 663 664 cycle_time = (1000 * s->sm_ddr3.ddr3_mtb_dividend + 665 (s->sm_ddr3.ddr3_mtb_divisor / 2)) / 666 s->sm_ddr3.ddr3_mtb_divisor; 667 cycle_time *= s->sm_ddr3.ddr3_tCKmin; 668 bits = 1 << (s->sm_ddr3.ddr3_datawidth + 3); 669 decode_size_speed(node, dimm_size, cycle_time, 2, bits, FALSE, "PC3", 0); 670 671 aprint_verbose_dev(self, 672 "%d rows, %d cols, %d log. banks, %d phys. banks, " 673 "%d.%03dns cycle time\n", 674 s->sm_ddr3.ddr3_rows + 9, s->sm_ddr3.ddr3_cols + 12, 675 1 << (s->sm_ddr3.ddr3_logbanks + 3), 676 s->sm_ddr3.ddr3_physbanks + 1, 677 cycle_time/1000, cycle_time % 1000); 678 679 #define __DDR3_CYCLES(field) (s->sm_ddr3.field / s->sm_ddr3.ddr3_tCKmin) 680 681 aprint_verbose_dev(self, latency, __DDR3_CYCLES(ddr3_tAAmin), 682 __DDR3_CYCLES(ddr3_tRCDmin), __DDR3_CYCLES(ddr3_tRPmin), 683 (s->sm_ddr3.ddr3_tRAS_msb * 256 + s->sm_ddr3.ddr3_tRAS_lsb) / 684 s->sm_ddr3.ddr3_tCKmin); 685 686 #undef __DDR3_CYCLES 687 } 688 689 static void 690 decode_fbdimm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 691 int dimm_size, cycle_time, bits; 692 693 /* 694 * FB-DIMM module size calculation is very much like DDR3 695 */ 696 dimm_size = s->sm_fbd.fbdimm_rows + 12 + 697 s->sm_fbd.fbdimm_cols + 9 - 20 - 3; 698 dimm_size = (1 << dimm_size) * (1 << (s->sm_fbd.fbdimm_banks + 2)); 699 700 cycle_time = (1000 * s->sm_fbd.fbdimm_mtb_dividend + 701 (s->sm_fbd.fbdimm_mtb_divisor / 2)) / 702 s->sm_fbd.fbdimm_mtb_divisor; 703 bits = 1 << (s->sm_fbd.fbdimm_dev_width + 2); 704 decode_size_speed(node, dimm_size, cycle_time, 2, bits, TRUE, "PC2", 0); 705 706 aprint_verbose_dev(self, 707 "%d rows, %d cols, %d banks, %d.%02dns cycle time\n", 708 s->sm_fbd.fbdimm_rows, s->sm_fbd.fbdimm_cols, 709 1 << (s->sm_fbd.fbdimm_banks + 2), 710 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 711 712 #define __FBDIMM_CYCLES(field) (s->sm_fbd.field / s->sm_fbd.fbdimm_tCKmin) 713 714 aprint_verbose_dev(self, latency, __FBDIMM_CYCLES(fbdimm_tAAmin), 715 __FBDIMM_CYCLES(fbdimm_tRCDmin), __FBDIMM_CYCLES(fbdimm_tRPmin), 716 (s->sm_fbd.fbdimm_tRAS_msb * 256 + 717 s->sm_fbd.fbdimm_tRAS_lsb) / 718 s->sm_fbd.fbdimm_tCKmin); 719 720 #undef __FBDIMM_CYCLES 721 722 decode_voltage_refresh(self, s); 723 } 724
Indexes created Wed Oct 01 13:09:50 GMT 2025