spdmem.c revision 1.4
1 /* $NetBSD: spdmem.c,v 1.4 2011/08/19 08:25:07 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Nicolas Joly 5 * Copyright (c) 2007 Paul Goyette 6 * Copyright (c) 2007 Tobias Nygren 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Serial Presence Detect (SPD) memory identification 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.4 2011/08/19 08:25:07 christos Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/device.h> 42 #include <sys/endian.h> 43 #include <sys/sysctl.h> 44 #include <machine/bswap.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/ic/spdmemreg.h> 48 #include <dev/ic/spdmemvar.h> 49 50 SYSCTL_SETUP_PROTO(sysctl_spdmem_setup); 51 52 /* Routines for decoding spd data */ 53 static void decode_edofpm(const struct sysctlnode *, device_t, struct spdmem *); 54 static void decode_rom(const struct sysctlnode *, device_t, struct spdmem *); 55 static void decode_sdram(const struct sysctlnode *, device_t, struct spdmem *, 56 int); 57 static void decode_ddr(const struct sysctlnode *, device_t, struct spdmem *); 58 static void decode_ddr2(const struct sysctlnode *, device_t, struct spdmem *); 59 static void decode_ddr3(const struct sysctlnode *, device_t, struct spdmem *); 60 static void decode_fbdimm(const struct sysctlnode *, device_t, struct spdmem *); 61 62 static void decode_size_speed(device_t, const struct sysctlnode *, 63 int, int, int, int, bool, const char *, int); 64 static void decode_voltage_refresh(device_t, struct spdmem *); 65 66 #define IS_RAMBUS_TYPE (s->sm_len < 4) 67 68 static const char* spdmem_basic_types[] = { 69 "unknown", 70 "FPM", 71 "EDO", 72 "Pipelined Nibble", 73 "SDRAM", 74 "ROM", 75 "DDR SGRAM", 76 "DDR SDRAM", 77 "DDR2 SDRAM", 78 "DDR2 SDRAM FB", 79 "DDR2 SDRAM FB Probe", 80 "DDR3 SDRAM" 81 }; 82 83 static const char* spdmem_superset_types[] = { 84 "unknown", 85 "ESDRAM", 86 "DDR ESDRAM", 87 "PEM EDO", 88 "PEM SDRAM" 89 }; 90 91 static const char* spdmem_voltage_types[] = { 92 "TTL (5V tolerant)", 93 "LvTTL (not 5V tolerant)", 94 "HSTL 1.5V", 95 "SSTL 3.3V", 96 "SSTL 2.5V", 97 "SSTL 1.8V" 98 }; 99 100 static const char* spdmem_refresh_types[] = { 101 "15.625us", 102 "3.9us", 103 "7.8us", 104 "31.3us", 105 "62.5us", 106 "125us" 107 }; 108 109 static const char* spdmem_parity_types[] = { 110 "no parity or ECC", 111 "data parity", 112 "data ECC", 113 "data parity and ECC", 114 "cmd/addr parity", 115 "cmd/addr/data parity", 116 "cmd/addr parity, data ECC", 117 "cmd/addr/data parity, data ECC" 118 }; 119 120 /* Cycle time fractional values (units of .001 ns) for DDR2 SDRAM */ 121 static const uint16_t spdmem_cycle_frac[] = { 122 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 123 250, 333, 667, 750, 999, 999 124 }; 125 126 /* Format string for timing info */ 127 #define LATENCY "tAA-tRCD-tRP-tRAS: %d-%d-%d-%d\n"; 128 129 /* sysctl stuff */ 130 static int hw_node = CTL_EOL; 131 132 /* CRC functions used for certain memory types */ 133 134 static uint16_t spdcrc16 (struct spdmem_softc *sc, int count) 135 { 136 uint16_t crc; 137 int i, j; 138 uint8_t val; 139 crc = 0; 140 for (j = 0; j <= count; j++) { 141 val = (sc->sc_read)(sc, j); 142 crc = crc ^ val << 8; 143 for (i = 0; i < 8; ++i) 144 if (crc & 0x8000) 145 crc = crc << 1 ^ 0x1021; 146 else 147 crc = crc << 1; 148 } 149 return (crc & 0xFFFF); 150 } 151 152 int 153 spdmem_common_probe(struct spdmem_softc *sc) 154 { 155 int cksum = 0; 156 uint8_t i, val, spd_type; 157 int spd_len, spd_crc_cover; 158 uint16_t crc_calc, crc_spd; 159 160 spd_type = (sc->sc_read)(sc, 2); 161 162 /* For older memory types, validate the checksum over 1st 63 bytes */ 163 if (spd_type <= SPDMEM_MEMTYPE_DDR2SDRAM) { 164 for (i = 0; i < 63; i++) 165 cksum += (sc->sc_read)(sc, i); 166 167 val = (sc->sc_read)(sc, 63); 168 169 if (cksum == 0 || (cksum & 0xff) != val) { 170 aprint_debug("spd checksum failed, calc = 0x%02x, " 171 "spd = 0x%02x\n", cksum, val); 172 return 0; 173 } else 174 return 1; 175 } 176 177 /* For DDR3 and FBDIMM, verify the CRC */ 178 else if (spd_type <= SPDMEM_MEMTYPE_DDR3SDRAM) { 179 spd_len = (sc->sc_read)(sc, 0); 180 if (spd_len & SPDMEM_SPDCRC_116) 181 spd_crc_cover = 116; 182 else 183 spd_crc_cover = 125; 184 switch (spd_len & SPDMEM_SPDLEN_MASK) { 185 case SPDMEM_SPDLEN_128: 186 spd_len = 128; 187 break; 188 case SPDMEM_SPDLEN_176: 189 spd_len = 176; 190 break; 191 case SPDMEM_SPDLEN_256: 192 spd_len = 256; 193 break; 194 default: 195 return 0; 196 } 197 if (spd_crc_cover > spd_len) 198 return 0; 199 crc_calc = spdcrc16(sc, spd_crc_cover); 200 crc_spd = (sc->sc_read)(sc, 127) << 8; 201 crc_spd |= (sc->sc_read)(sc, 126); 202 if (crc_calc != crc_spd) { 203 aprint_debug("crc16 failed, covers %d bytes, " 204 "calc = 0x%04x, spd = 0x%04x\n", 205 spd_crc_cover, crc_calc, crc_spd); 206 return 0; 207 } 208 return 1; 209 } 210 211 /* For unrecognized memory types, don't match at all */ 212 return 0; 213 } 214 215 void 216 spdmem_common_attach(struct spdmem_softc *sc, device_t self) 217 { 218 struct spdmem *s = &(sc->sc_spd_data); 219 const char *type; 220 const char *rambus_rev = "Reserved"; 221 int dimm_size; 222 unsigned int i, spd_len, spd_size; 223 const struct sysctlnode *node = NULL; 224 225 /* 226 * FBDIMM and DDR3 (and probably all newer) have a different 227 * encoding of the SPD EEPROM used/total sizes 228 */ 229 s->sm_len = (sc->sc_read)(sc, 0); 230 s->sm_size = (sc->sc_read)(sc, 1); 231 s->sm_type = (sc->sc_read)(sc, 2); 232 233 if (s->sm_type >= SPDMEM_MEMTYPE_FBDIMM) { 234 spd_size = 64 << (s->sm_len & SPDMEM_SPDSIZE_MASK); 235 switch (s->sm_len & SPDMEM_SPDLEN_MASK) { 236 case SPDMEM_SPDLEN_128: 237 spd_len = 128; 238 break; 239 case SPDMEM_SPDLEN_176: 240 spd_len = 176; 241 break; 242 case SPDMEM_SPDLEN_256: 243 spd_len = 256; 244 break; 245 default: 246 spd_len = 64; 247 break; 248 } 249 } else { 250 spd_size = 1 << s->sm_size; 251 spd_len = s->sm_len; 252 if (spd_len < 64) 253 spd_len = 64; 254 } 255 if (spd_len > spd_size) 256 spd_len = spd_size; 257 if (spd_len > sizeof(struct spdmem)) 258 spd_len = sizeof(struct spdmem); 259 for (i = 3; i < spd_len; i++) 260 ((uint8_t *)s)[i] = (sc->sc_read)(sc, i); 261 262 #ifdef DEBUG 263 for (i = 0; i < spd_len; i += 16) { 264 unsigned int j, k; 265 aprint_debug("\n"); 266 aprint_debug_dev(self, "0x%02x:", i); 267 k = (spd_len > i + 16) ? spd_len : i + 16; 268 for (j = i; j < k; j++) 269 aprint_debug(" %02x", ((uint8_t *)s)[j]); 270 } 271 aprint_debug("\n"); 272 aprint_debug_dev(self, ""); 273 #endif 274 275 /* 276 * Setup our sysctl subtree, hw.spdmemN 277 */ 278 sc->sc_sysctl_log = NULL; 279 #ifdef _MODULE 280 sysctl_spdmem_setup(&sc->sc_sysctl_log); 281 #endif 282 if (hw_node != CTL_EOL) 283 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, 284 0, CTLTYPE_NODE, 285 device_xname(self), NULL, NULL, 0, NULL, 0, 286 CTL_HW, CTL_CREATE, CTL_EOL); 287 if (node != NULL && spd_len != 0) 288 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 289 0, 290 CTLTYPE_STRUCT, "spd_data", 291 SYSCTL_DESCR("raw spd data"), NULL, 292 0, s, spd_len, 293 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 294 295 /* 296 * Decode and print key SPD contents 297 */ 298 if (IS_RAMBUS_TYPE) { 299 if (s->sm_type == SPDMEM_MEMTYPE_RAMBUS) 300 type = "Rambus"; 301 else if (s->sm_type == SPDMEM_MEMTYPE_DIRECTRAMBUS) 302 type = "Direct Rambus"; 303 else 304 type = "Rambus (unknown)"; 305 306 switch (s->sm_len) { 307 case 0: 308 rambus_rev = "Invalid"; 309 break; 310 case 1: 311 rambus_rev = "0.7"; 312 break; 313 case 2: 314 rambus_rev = "1.0"; 315 break; 316 default: 317 rambus_rev = "Reserved"; 318 break; 319 } 320 } else { 321 if (s->sm_type < __arraycount(spdmem_basic_types)) 322 type = spdmem_basic_types[s->sm_type]; 323 else 324 type = "unknown memory type"; 325 326 if (s->sm_type == SPDMEM_MEMTYPE_EDO && 327 s->sm_fpm.fpm_superset == SPDMEM_SUPERSET_EDO_PEM) 328 type = spdmem_superset_types[SPDMEM_SUPERSET_EDO_PEM]; 329 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 330 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_SDRAM_PEM) 331 type = spdmem_superset_types[SPDMEM_SUPERSET_SDRAM_PEM]; 332 if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM && 333 s->sm_ddr.ddr_superset == SPDMEM_SUPERSET_DDR_ESDRAM) 334 type = 335 spdmem_superset_types[SPDMEM_SUPERSET_DDR_ESDRAM]; 336 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 337 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_ESDRAM) { 338 type = spdmem_superset_types[SPDMEM_SUPERSET_ESDRAM]; 339 } 340 } 341 342 aprint_naive("\n"); 343 aprint_normal("\n"); 344 aprint_normal_dev(self, "%s", type); 345 strlcpy(sc->sc_type, type, SPDMEM_TYPE_MAXLEN); 346 if (node != NULL) 347 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 348 0, 349 CTLTYPE_STRING, "mem_type", 350 SYSCTL_DESCR("memory module type"), NULL, 351 0, sc->sc_type, 0, 352 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 353 354 if (IS_RAMBUS_TYPE) { 355 aprint_normal(", SPD Revision %s", rambus_rev); 356 dimm_size = 1 << (s->sm_rdr.rdr_rows + s->sm_rdr.rdr_cols - 13); 357 if (dimm_size >= 1024) 358 aprint_normal(", %dGB\n", dimm_size / 1024); 359 else 360 aprint_normal(", %dMB\n", dimm_size); 361 362 /* No further decode for RAMBUS memory */ 363 return; 364 } 365 switch (s->sm_type) { 366 case SPDMEM_MEMTYPE_EDO: 367 case SPDMEM_MEMTYPE_FPM: 368 decode_edofpm(node, self, s); 369 break; 370 case SPDMEM_MEMTYPE_ROM: 371 decode_rom(node, self, s); 372 break; 373 case SPDMEM_MEMTYPE_SDRAM: 374 decode_sdram(node, self, s, spd_len); 375 break; 376 case SPDMEM_MEMTYPE_DDRSDRAM: 377 decode_ddr(node, self, s); 378 break; 379 case SPDMEM_MEMTYPE_DDR2SDRAM: 380 decode_ddr2(node, self, s); 381 break; 382 case SPDMEM_MEMTYPE_DDR3SDRAM: 383 decode_ddr3(node, self, s); 384 break; 385 case SPDMEM_MEMTYPE_FBDIMM: 386 case SPDMEM_MEMTYPE_FBDIMM_PROBE: 387 decode_fbdimm(node, self, s); 388 break; 389 } 390 } 391 392 int 393 spdmem_common_detach(struct spdmem_softc *sc, device_t self) 394 { 395 sysctl_teardown(&sc->sc_sysctl_log); 396 397 return 0; 398 } 399 400 SYSCTL_SETUP(sysctl_spdmem_setup, "sysctl hw.spdmem subtree setup") 401 { 402 const struct sysctlnode *node; 403 404 if (sysctl_createv(clog, 0, NULL, &node, CTLFLAG_PERMANENT, 405 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 406 CTL_HW, CTL_EOL) != 0) 407 return; 408 409 hw_node = node->sysctl_num; 410 } 411 412 static void 413 decode_size_speed(device_t self, const struct sysctlnode *node, 414 int dimm_size, int cycle_time, int d_clk, int bits, 415 bool round, const char *ddr_type_string, int speed) 416 { 417 int p_clk; 418 struct spdmem_softc *sc = (struct spdmem_softc *)device_private(self); 419 420 if (dimm_size < 1024) 421 aprint_normal("%dMB", dimm_size); 422 else 423 aprint_normal("%dGB", dimm_size / 1024); 424 if (node != NULL) 425 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 426 CTLFLAG_IMMEDIATE, 427 CTLTYPE_INT, "size", 428 SYSCTL_DESCR("module size in MB"), NULL, 429 dimm_size, NULL, 0, 430 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 431 432 if (cycle_time == 0) { 433 aprint_normal("\n"); 434 return; 435 } 436 437 /* 438 * Calculate p_clk first, since for DDR3 we need maximum significance. 439 * DDR3 rating is not rounded to a multiple of 100. This results in 440 * cycle_time of 1.5ns displayed as PC3-10666. 441 * 442 * For SDRAM, the speed is provided by the caller so we use it. 443 */ 444 d_clk *= 1000 * 1000; 445 if (speed) 446 p_clk = speed; 447 else 448 p_clk = (d_clk * bits) / 8 / cycle_time; 449 d_clk = ((d_clk + cycle_time / 2) ) / cycle_time; 450 if (round) { 451 if ((p_clk % 100) >= 50) 452 p_clk += 50; 453 p_clk -= p_clk % 100; 454 } 455 aprint_normal(", %dMHz (%s-%d)\n", 456 d_clk, ddr_type_string, p_clk); 457 if (node != NULL) 458 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 459 CTLFLAG_IMMEDIATE, 460 CTLTYPE_INT, "speed", 461 SYSCTL_DESCR("memory speed in MHz"), 462 NULL, d_clk, NULL, 0, 463 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 464 } 465 466 static void 467 decode_voltage_refresh(device_t self, struct spdmem *s) 468 { 469 const char *voltage, *refresh; 470 471 if (s->sm_voltage < __arraycount(spdmem_voltage_types)) 472 voltage = spdmem_voltage_types[s->sm_voltage]; 473 else 474 voltage = "unknown"; 475 476 if (s->sm_refresh < __arraycount(spdmem_refresh_types)) 477 refresh = spdmem_refresh_types[s->sm_refresh]; 478 else 479 refresh = "unknown"; 480 481 aprint_verbose_dev(self, "voltage %s, refresh time %s%s\n", 482 voltage, refresh, 483 s->sm_selfrefresh?" (self-refreshing)":""); 484 } 485 486 static void 487 decode_edofpm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 488 aprint_normal("\n"); 489 aprint_verbose_dev(self, 490 "%d rows, %d cols, %d banks, %dns tRAC, %dns tCAC\n", 491 s->sm_fpm.fpm_rows, s->sm_fpm.fpm_cols, s->sm_fpm.fpm_banks, 492 s->sm_fpm.fpm_tRAC, s->sm_fpm.fpm_tCAC); 493 } 494 495 static void 496 decode_rom(const struct sysctlnode *node, device_t self, struct spdmem *s) { 497 aprint_normal("\n"); 498 aprint_verbose_dev(self, "%d rows, %d cols, %d banks\n", 499 s->sm_rom.rom_rows, s->sm_rom.rom_cols, s->sm_rom.rom_banks); 500 } 501 502 static void 503 decode_sdram(const struct sysctlnode *node, device_t self, struct spdmem *s, 504 int spd_len) { 505 int dimm_size, cycle_time, bits, tAA, i, speed, freq; 506 507 aprint_normal("%s, %s, ", 508 (s->sm_sdr.sdr_mod_attrs & SPDMEM_SDR_MASK_REG)? 509 " (registered)":"", 510 (s->sm_config < __arraycount(spdmem_parity_types))? 511 spdmem_parity_types[s->sm_config]:"invalid parity"); 512 513 dimm_size = 1 << (s->sm_sdr.sdr_rows + s->sm_sdr.sdr_cols - 17); 514 dimm_size *= s->sm_sdr.sdr_banks * s->sm_sdr.sdr_banks_per_chip; 515 516 cycle_time = s->sm_sdr.sdr_cycle_whole * 1000 + 517 s->sm_sdr.sdr_cycle_tenths * 100; 518 bits = le16toh(s->sm_sdr.sdr_datawidth); 519 if (s->sm_config == 1 || s->sm_config == 2) 520 bits -= 8; 521 522 /* Calculate speed here - from OpenBSD */ 523 if (spd_len >= 128) 524 freq = ((uint8_t *)s)[126]; 525 else 526 freq = 0; 527 switch (freq) { 528 /* 529 * Must check cycle time since some PC-133 DIMMs 530 * actually report PC-100 531 */ 532 case 100: 533 case 133: 534 if (cycle_time < 8000) 535 speed = 133; 536 else 537 speed = 100; 538 break; 539 case 0x66: /* Legacy DIMMs use _hex_ 66! */ 540 default: 541 speed = 66; 542 } 543 decode_size_speed(self, node, dimm_size, cycle_time, 1, bits, FALSE, 544 "PC", speed); 545 546 aprint_verbose_dev(self, 547 "%d rows, %d cols, %d banks, %d banks/chip, %d.%dns cycle time\n", 548 s->sm_sdr.sdr_rows, s->sm_sdr.sdr_cols, s->sm_sdr.sdr_banks, 549 s->sm_sdr.sdr_banks_per_chip, cycle_time/1000, 550 (cycle_time % 1000) / 100); 551 552 tAA = 0; 553 for (i = 0; i < 8; i++) 554 if (s->sm_sdr.sdr_tCAS & (1 << i)) 555 tAA = i; 556 tAA++; 557 aprint_verbose_dev(self, LATENCY, tAA, s->sm_sdr.sdr_tRCD, 558 s->sm_sdr.sdr_tRP, s->sm_sdr.sdr_tRAS); 559 560 decode_voltage_refresh(self, s); 561 } 562 563 static void 564 decode_ddr(const struct sysctlnode *node, device_t self, struct spdmem *s) { 565 int dimm_size, cycle_time, bits, tAA, i; 566 567 aprint_normal("%s, %s, ", 568 (s->sm_ddr.ddr_mod_attrs & SPDMEM_DDR_MASK_REG)? 569 " (registered)":"", 570 (s->sm_config < __arraycount(spdmem_parity_types))? 571 spdmem_parity_types[s->sm_config]:"invalid parity"); 572 573 dimm_size = 1 << (s->sm_ddr.ddr_rows + s->sm_ddr.ddr_cols - 17); 574 dimm_size *= s->sm_ddr.ddr_ranks * s->sm_ddr.ddr_banks_per_chip; 575 576 cycle_time = s->sm_ddr.ddr_cycle_whole * 1000 + 577 spdmem_cycle_frac[s->sm_ddr.ddr_cycle_tenths]; 578 bits = le16toh(s->sm_ddr.ddr_datawidth); 579 if (s->sm_config == 1 || s->sm_config == 2) 580 bits -= 8; 581 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 582 "PC", 0); 583 584 aprint_verbose_dev(self, 585 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%dns cycle time\n", 586 s->sm_ddr.ddr_rows, s->sm_ddr.ddr_cols, s->sm_ddr.ddr_ranks, 587 s->sm_ddr.ddr_banks_per_chip, cycle_time/1000, 588 (cycle_time % 1000 + 50) / 100); 589 590 tAA = 0; 591 for (i = 2; i < 8; i++) 592 if (s->sm_ddr.ddr_tCAS & (1 << i)) 593 tAA = i; 594 tAA /= 2; 595 596 #define __DDR_ROUND(scale, field) \ 597 ((scale * s->sm_ddr.field + cycle_time - 1) / cycle_time) 598 599 aprint_verbose_dev(self, LATENCY, tAA, __DDR_ROUND(250, ddr_tRCD), 600 __DDR_ROUND(250, ddr_tRP), __DDR_ROUND(1000, ddr_tRAS)); 601 602 #undef __DDR_ROUND 603 604 decode_voltage_refresh(self, s); 605 } 606 607 static void 608 decode_ddr2(const struct sysctlnode *node, device_t self, struct spdmem *s) { 609 int dimm_size, cycle_time, bits, tAA, i; 610 611 aprint_normal("%s, %s, ", 612 (s->sm_ddr2.ddr2_mod_attrs & SPDMEM_DDR2_MASK_REG)? 613 " (registered)":"", 614 (s->sm_config < __arraycount(spdmem_parity_types))? 615 spdmem_parity_types[s->sm_config]:"invalid parity"); 616 617 dimm_size = 1 << (s->sm_ddr2.ddr2_rows + s->sm_ddr2.ddr2_cols - 17); 618 dimm_size *= (s->sm_ddr2.ddr2_ranks + 1) * 619 s->sm_ddr2.ddr2_banks_per_chip; 620 621 cycle_time = s->sm_ddr2.ddr2_cycle_whole * 1000 + 622 spdmem_cycle_frac[s->sm_ddr2.ddr2_cycle_frac]; 623 bits = s->sm_ddr2.ddr2_datawidth; 624 if ((s->sm_config & 0x03) != 0) 625 bits -= 8; 626 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 627 "PC2", 0); 628 629 aprint_verbose_dev(self, 630 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%02dns cycle time\n", 631 s->sm_ddr2.ddr2_rows, s->sm_ddr2.ddr2_cols, 632 s->sm_ddr2.ddr2_ranks + 1, s->sm_ddr2.ddr2_banks_per_chip, 633 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 634 635 tAA = 0; 636 for (i = 2; i < 8; i++) 637 if (s->sm_ddr2.ddr2_tCAS & (1 << i)) 638 tAA = i; 639 640 #define __DDR2_ROUND(scale, field) \ 641 ((scale * s->sm_ddr2.field + cycle_time - 1) / cycle_time) 642 643 aprint_verbose_dev(self, LATENCY, tAA, __DDR2_ROUND(250, ddr2_tRCD), 644 __DDR2_ROUND(250, ddr2_tRP), __DDR2_ROUND(1000, ddr2_tRAS)); 645 646 #undef __DDR_ROUND 647 648 decode_voltage_refresh(self, s); 649 } 650 651 static void 652 decode_ddr3(const struct sysctlnode *node, device_t self, struct spdmem *s) { 653 int dimm_size, cycle_time, bits; 654 655 if (s->sm_ddr3.ddr3_mod_type == 656 SPDMEM_DDR3_TYPE_MINI_RDIMM || 657 s->sm_ddr3.ddr3_mod_type == SPDMEM_DDR3_TYPE_RDIMM) 658 aprint_normal(" (registered)"); 659 aprint_normal(", %sECC, %stemp-sensor, ", 660 (s->sm_ddr3.ddr3_hasECC)?"":"no ", 661 (s->sm_ddr3.ddr3_has_therm_sensor)?"":"no "); 662 663 /* 664 * DDR3 size specification is quite different from others 665 * 666 * Module capacity is defined as 667 * Chip_Capacity_in_bits / 8bits-per-byte * 668 * external_bus_width / internal_bus_width 669 * We further divide by 2**20 to get our answer in MB 670 */ 671 dimm_size = (s->sm_ddr3.ddr3_chipsize + 28 - 20) - 3 + 672 (s->sm_ddr3.ddr3_datawidth + 3) - 673 (s->sm_ddr3.ddr3_chipwidth + 2); 674 dimm_size = (1 << dimm_size) * (s->sm_ddr3.ddr3_physbanks + 1); 675 676 cycle_time = (1000 * s->sm_ddr3.ddr3_mtb_dividend + 677 (s->sm_ddr3.ddr3_mtb_divisor / 2)) / 678 s->sm_ddr3.ddr3_mtb_divisor; 679 cycle_time *= s->sm_ddr3.ddr3_tCKmin; 680 bits = 1 << (s->sm_ddr3.ddr3_datawidth + 3); 681 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, FALSE, 682 "PC3", 0); 683 684 aprint_verbose_dev(self, 685 "%d rows, %d cols, %d log. banks, %d phys. banks, " 686 "%d.%03dns cycle time\n", 687 s->sm_ddr3.ddr3_rows + 9, s->sm_ddr3.ddr3_cols + 12, 688 1 << (s->sm_ddr3.ddr3_logbanks + 3), 689 s->sm_ddr3.ddr3_physbanks + 1, 690 cycle_time/1000, cycle_time % 1000); 691 692 #define __DDR3_CYCLES(field) (s->sm_ddr3.field / s->sm_ddr3.ddr3_tCKmin) 693 694 aprint_verbose_dev(self, LATENCY, __DDR3_CYCLES(ddr3_tAAmin), 695 __DDR3_CYCLES(ddr3_tRCDmin), __DDR3_CYCLES(ddr3_tRPmin), 696 (s->sm_ddr3.ddr3_tRAS_msb * 256 + s->sm_ddr3.ddr3_tRAS_lsb) / 697 s->sm_ddr3.ddr3_tCKmin); 698 699 #undef __DDR3_CYCLES 700 } 701 702 static void 703 decode_fbdimm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 704 int dimm_size, cycle_time, bits; 705 706 /* 707 * FB-DIMM module size calculation is very much like DDR3 708 */ 709 dimm_size = s->sm_fbd.fbdimm_rows + 12 + 710 s->sm_fbd.fbdimm_cols + 9 - 20 - 3; 711 dimm_size = (1 << dimm_size) * (1 << (s->sm_fbd.fbdimm_banks + 2)); 712 713 cycle_time = (1000 * s->sm_fbd.fbdimm_mtb_dividend + 714 (s->sm_fbd.fbdimm_mtb_divisor / 2)) / 715 s->sm_fbd.fbdimm_mtb_divisor; 716 bits = 1 << (s->sm_fbd.fbdimm_dev_width + 2); 717 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 718 "PC2", 0); 719 720 aprint_verbose_dev(self, 721 "%d rows, %d cols, %d banks, %d.%02dns cycle time\n", 722 s->sm_fbd.fbdimm_rows, s->sm_fbd.fbdimm_cols, 723 1 << (s->sm_fbd.fbdimm_banks + 2), 724 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 725 726 #define __FBDIMM_CYCLES(field) (s->sm_fbd.field / s->sm_fbd.fbdimm_tCKmin) 727 728 aprint_verbose_dev(self, LATENCY, __FBDIMM_CYCLES(fbdimm_tAAmin), 729 __FBDIMM_CYCLES(fbdimm_tRCDmin), __FBDIMM_CYCLES(fbdimm_tRPmin), 730 (s->sm_fbd.fbdimm_tRAS_msb * 256 + 731 s->sm_fbd.fbdimm_tRAS_lsb) / 732 s->sm_fbd.fbdimm_tCKmin); 733 734 #undef __FBDIMM_CYCLES 735 736 decode_voltage_refresh(self, s); 737 } 738
Indexes created Wed Oct 01 13:09:50 GMT 2025