spdmem.c revision 1.6
1 /* $NetBSD: spdmem.c,v 1.6 2012/05/31 16:09:34 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Nicolas Joly 5 * Copyright (c) 2007 Paul Goyette 6 * Copyright (c) 2007 Tobias Nygren 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Serial Presence Detect (SPD) memory identification 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.6 2012/05/31 16:09:34 pgoyette Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/device.h> 42 #include <sys/endian.h> 43 #include <sys/sysctl.h> 44 #include <machine/bswap.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/ic/spdmemreg.h> 48 #include <dev/ic/spdmemvar.h> 49 50 SYSCTL_SETUP_PROTO(sysctl_spdmem_setup); 51 52 /* Routines for decoding spd data */ 53 static void decode_edofpm(const struct sysctlnode *, device_t, struct spdmem *); 54 static void decode_rom(const struct sysctlnode *, device_t, struct spdmem *); 55 static void decode_sdram(const struct sysctlnode *, device_t, struct spdmem *, 56 int); 57 static void decode_ddr(const struct sysctlnode *, device_t, struct spdmem *); 58 static void decode_ddr2(const struct sysctlnode *, device_t, struct spdmem *); 59 static void decode_ddr3(const struct sysctlnode *, device_t, struct spdmem *); 60 static void decode_fbdimm(const struct sysctlnode *, device_t, struct spdmem *); 61 62 static void decode_size_speed(device_t, const struct sysctlnode *, 63 int, int, int, int, bool, const char *, int); 64 static void decode_voltage_refresh(device_t, struct spdmem *); 65 66 #define IS_RAMBUS_TYPE (s->sm_len < 4) 67 68 static const char* spdmem_basic_types[] = { 69 "unknown", 70 "FPM", 71 "EDO", 72 "Pipelined Nibble", 73 "SDRAM", 74 "ROM", 75 "DDR SGRAM", 76 "DDR SDRAM", 77 "DDR2 SDRAM", 78 "DDR2 SDRAM FB", 79 "DDR2 SDRAM FB Probe", 80 "DDR3 SDRAM" 81 }; 82 83 static const char* spdmem_superset_types[] = { 84 "unknown", 85 "ESDRAM", 86 "DDR ESDRAM", 87 "PEM EDO", 88 "PEM SDRAM" 89 }; 90 91 static const char* spdmem_voltage_types[] = { 92 "TTL (5V tolerant)", 93 "LvTTL (not 5V tolerant)", 94 "HSTL 1.5V", 95 "SSTL 3.3V", 96 "SSTL 2.5V", 97 "SSTL 1.8V" 98 }; 99 100 static const char* spdmem_refresh_types[] = { 101 "15.625us", 102 "3.9us", 103 "7.8us", 104 "31.3us", 105 "62.5us", 106 "125us" 107 }; 108 109 static const char* spdmem_parity_types[] = { 110 "no parity or ECC", 111 "data parity", 112 "data ECC", 113 "data parity and ECC", 114 "cmd/addr parity", 115 "cmd/addr/data parity", 116 "cmd/addr parity, data ECC", 117 "cmd/addr/data parity, data ECC" 118 }; 119 120 /* Cycle time fractional values (units of .001 ns) for DDR2 SDRAM */ 121 static const uint16_t spdmem_cycle_frac[] = { 122 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 123 250, 333, 667, 750, 999, 999 124 }; 125 126 /* Format string for timing info */ 127 #define LATENCY "tAA-tRCD-tRP-tRAS: %d-%d-%d-%d\n" 128 129 /* sysctl stuff */ 130 static int hw_node = CTL_EOL; 131 132 /* CRC functions used for certain memory types */ 133 134 static uint16_t spdcrc16 (struct spdmem_softc *sc, int count) 135 { 136 uint16_t crc; 137 int i, j; 138 uint8_t val; 139 crc = 0; 140 for (j = 0; j <= count; j++) { 141 val = (sc->sc_read)(sc, j); 142 crc = crc ^ val << 8; 143 for (i = 0; i < 8; ++i) 144 if (crc & 0x8000) 145 crc = crc << 1 ^ 0x1021; 146 else 147 crc = crc << 1; 148 } 149 return (crc & 0xFFFF); 150 } 151 152 int 153 spdmem_common_probe(struct spdmem_softc *sc) 154 { 155 int cksum = 0; 156 uint8_t i, val, spd_type; 157 int spd_len, spd_crc_cover; 158 uint16_t crc_calc, crc_spd; 159 160 spd_type = (sc->sc_read)(sc, 2); 161 162 /* For older memory types, validate the checksum over 1st 63 bytes */ 163 if (spd_type <= SPDMEM_MEMTYPE_DDR2SDRAM) { 164 for (i = 0; i < 63; i++) 165 cksum += (sc->sc_read)(sc, i); 166 167 val = (sc->sc_read)(sc, 63); 168 169 if (cksum == 0 || (cksum & 0xff) != val) { 170 aprint_debug("spd checksum failed, calc = 0x%02x, " 171 "spd = 0x%02x\n", cksum, val); 172 return 0; 173 } else 174 return 1; 175 } 176 177 /* For DDR3 and FBDIMM, verify the CRC */ 178 else if (spd_type <= SPDMEM_MEMTYPE_DDR3SDRAM) { 179 spd_len = (sc->sc_read)(sc, 0); 180 if (spd_len & SPDMEM_SPDCRC_116) 181 spd_crc_cover = 116; 182 else 183 spd_crc_cover = 125; 184 switch (spd_len & SPDMEM_SPDLEN_MASK) { 185 case SPDMEM_SPDLEN_128: 186 spd_len = 128; 187 break; 188 case SPDMEM_SPDLEN_176: 189 spd_len = 176; 190 break; 191 case SPDMEM_SPDLEN_256: 192 spd_len = 256; 193 break; 194 default: 195 return 0; 196 } 197 if (spd_crc_cover > spd_len) 198 return 0; 199 crc_calc = spdcrc16(sc, spd_crc_cover); 200 crc_spd = (sc->sc_read)(sc, 127) << 8; 201 crc_spd |= (sc->sc_read)(sc, 126); 202 if (crc_calc != crc_spd) { 203 aprint_debug("crc16 failed, covers %d bytes, " 204 "calc = 0x%04x, spd = 0x%04x\n", 205 spd_crc_cover, crc_calc, crc_spd); 206 return 0; 207 } 208 return 1; 209 } 210 211 /* For unrecognized memory types, don't match at all */ 212 return 0; 213 } 214 215 void 216 spdmem_common_attach(struct spdmem_softc *sc, device_t self) 217 { 218 struct spdmem *s = &(sc->sc_spd_data); 219 const char *type; 220 const char *rambus_rev = "Reserved"; 221 int dimm_size; 222 unsigned int i, spd_len, spd_size; 223 const struct sysctlnode *node = NULL; 224 225 /* 226 * FBDIMM and DDR3 (and probably all newer) have a different 227 * encoding of the SPD EEPROM used/total sizes 228 */ 229 s->sm_len = (sc->sc_read)(sc, 0); 230 s->sm_size = (sc->sc_read)(sc, 1); 231 s->sm_type = (sc->sc_read)(sc, 2); 232 233 if (s->sm_type >= SPDMEM_MEMTYPE_FBDIMM) { 234 spd_size = 64 << (s->sm_len & SPDMEM_SPDSIZE_MASK); 235 switch (s->sm_len & SPDMEM_SPDLEN_MASK) { 236 case SPDMEM_SPDLEN_128: 237 spd_len = 128; 238 break; 239 case SPDMEM_SPDLEN_176: 240 spd_len = 176; 241 break; 242 case SPDMEM_SPDLEN_256: 243 spd_len = 256; 244 break; 245 default: 246 spd_len = 64; 247 break; 248 } 249 } else { 250 spd_size = 1 << s->sm_size; 251 spd_len = s->sm_len; 252 if (spd_len < 64) 253 spd_len = 64; 254 } 255 if (spd_len > spd_size) 256 spd_len = spd_size; 257 if (spd_len > sizeof(struct spdmem)) 258 spd_len = sizeof(struct spdmem); 259 for (i = 3; i < spd_len; i++) 260 ((uint8_t *)s)[i] = (sc->sc_read)(sc, i); 261 262 #ifdef DEBUG 263 for (i = 0; i < spd_len; i += 16) { 264 unsigned int j, k; 265 aprint_debug("\n"); 266 aprint_debug_dev(self, "0x%02x:", i); 267 k = (spd_len > i + 16) ? spd_len : i + 16; 268 for (j = i; j < k; j++) 269 aprint_debug(" %02x", ((uint8_t *)s)[j]); 270 } 271 aprint_debug("\n"); 272 aprint_debug_dev(self, ""); 273 #endif 274 275 /* 276 * Setup our sysctl subtree, hw.spdmemN 277 */ 278 sc->sc_sysctl_log = NULL; 279 if (hw_node != CTL_EOL) 280 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, 281 0, CTLTYPE_NODE, 282 device_xname(self), NULL, NULL, 0, NULL, 0, 283 CTL_HW, CTL_CREATE, CTL_EOL); 284 if (node != NULL && spd_len != 0) 285 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 286 0, 287 CTLTYPE_STRUCT, "spd_data", 288 SYSCTL_DESCR("raw spd data"), NULL, 289 0, s, spd_len, 290 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 291 292 /* 293 * Decode and print key SPD contents 294 */ 295 if (IS_RAMBUS_TYPE) { 296 if (s->sm_type == SPDMEM_MEMTYPE_RAMBUS) 297 type = "Rambus"; 298 else if (s->sm_type == SPDMEM_MEMTYPE_DIRECTRAMBUS) 299 type = "Direct Rambus"; 300 else 301 type = "Rambus (unknown)"; 302 303 switch (s->sm_len) { 304 case 0: 305 rambus_rev = "Invalid"; 306 break; 307 case 1: 308 rambus_rev = "0.7"; 309 break; 310 case 2: 311 rambus_rev = "1.0"; 312 break; 313 default: 314 rambus_rev = "Reserved"; 315 break; 316 } 317 } else { 318 if (s->sm_type < __arraycount(spdmem_basic_types)) 319 type = spdmem_basic_types[s->sm_type]; 320 else 321 type = "unknown memory type"; 322 323 if (s->sm_type == SPDMEM_MEMTYPE_EDO && 324 s->sm_fpm.fpm_superset == SPDMEM_SUPERSET_EDO_PEM) 325 type = spdmem_superset_types[SPDMEM_SUPERSET_EDO_PEM]; 326 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 327 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_SDRAM_PEM) 328 type = spdmem_superset_types[SPDMEM_SUPERSET_SDRAM_PEM]; 329 if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM && 330 s->sm_ddr.ddr_superset == SPDMEM_SUPERSET_DDR_ESDRAM) 331 type = 332 spdmem_superset_types[SPDMEM_SUPERSET_DDR_ESDRAM]; 333 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 334 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_ESDRAM) { 335 type = spdmem_superset_types[SPDMEM_SUPERSET_ESDRAM]; 336 } 337 } 338 339 aprint_naive("\n"); 340 aprint_normal("\n"); 341 aprint_normal_dev(self, "%s", type); 342 strlcpy(sc->sc_type, type, SPDMEM_TYPE_MAXLEN); 343 if (node != NULL) 344 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 345 0, 346 CTLTYPE_STRING, "mem_type", 347 SYSCTL_DESCR("memory module type"), NULL, 348 0, sc->sc_type, 0, 349 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 350 351 if (IS_RAMBUS_TYPE) { 352 aprint_normal(", SPD Revision %s", rambus_rev); 353 dimm_size = 1 << (s->sm_rdr.rdr_rows + s->sm_rdr.rdr_cols - 13); 354 if (dimm_size >= 1024) 355 aprint_normal(", %dGB\n", dimm_size / 1024); 356 else 357 aprint_normal(", %dMB\n", dimm_size); 358 359 /* No further decode for RAMBUS memory */ 360 return; 361 } 362 switch (s->sm_type) { 363 case SPDMEM_MEMTYPE_EDO: 364 case SPDMEM_MEMTYPE_FPM: 365 decode_edofpm(node, self, s); 366 break; 367 case SPDMEM_MEMTYPE_ROM: 368 decode_rom(node, self, s); 369 break; 370 case SPDMEM_MEMTYPE_SDRAM: 371 decode_sdram(node, self, s, spd_len); 372 break; 373 case SPDMEM_MEMTYPE_DDRSDRAM: 374 decode_ddr(node, self, s); 375 break; 376 case SPDMEM_MEMTYPE_DDR2SDRAM: 377 decode_ddr2(node, self, s); 378 break; 379 case SPDMEM_MEMTYPE_DDR3SDRAM: 380 decode_ddr3(node, self, s); 381 break; 382 case SPDMEM_MEMTYPE_FBDIMM: 383 case SPDMEM_MEMTYPE_FBDIMM_PROBE: 384 decode_fbdimm(node, self, s); 385 break; 386 } 387 } 388 389 int 390 spdmem_common_detach(struct spdmem_softc *sc, device_t self) 391 { 392 sysctl_teardown(&sc->sc_sysctl_log); 393 394 return 0; 395 } 396 397 SYSCTL_SETUP(sysctl_spdmem_setup, "sysctl hw.spdmem subtree setup") 398 { 399 const struct sysctlnode *node; 400 401 if (sysctl_createv(clog, 0, NULL, &node, 402 #ifdef _MODULE 403 0, 404 #else 405 CTLFLAG_PERMANENT, 406 #endif 407 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 408 CTL_HW, CTL_EOL) != 0) 409 return; 410 411 hw_node = node->sysctl_num; 412 } 413 414 static void 415 decode_size_speed(device_t self, const struct sysctlnode *node, 416 int dimm_size, int cycle_time, int d_clk, int bits, 417 bool round, const char *ddr_type_string, int speed) 418 { 419 int p_clk; 420 struct spdmem_softc *sc = (struct spdmem_softc *)device_private(self); 421 422 if (dimm_size < 1024) 423 aprint_normal("%dMB", dimm_size); 424 else 425 aprint_normal("%dGB", dimm_size / 1024); 426 if (node != NULL) 427 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 428 CTLFLAG_IMMEDIATE, 429 CTLTYPE_INT, "size", 430 SYSCTL_DESCR("module size in MB"), NULL, 431 dimm_size, NULL, 0, 432 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 433 434 if (cycle_time == 0) { 435 aprint_normal("\n"); 436 return; 437 } 438 439 /* 440 * Calculate p_clk first, since for DDR3 we need maximum significance. 441 * DDR3 rating is not rounded to a multiple of 100. This results in 442 * cycle_time of 1.5ns displayed as PC3-10666. 443 * 444 * For SDRAM, the speed is provided by the caller so we use it. 445 */ 446 d_clk *= 1000 * 1000; 447 if (speed) 448 p_clk = speed; 449 else 450 p_clk = (d_clk * bits) / 8 / cycle_time; 451 d_clk = ((d_clk + cycle_time / 2) ) / cycle_time; 452 if (round) { 453 if ((p_clk % 100) >= 50) 454 p_clk += 50; 455 p_clk -= p_clk % 100; 456 } 457 aprint_normal(", %dMHz (%s-%d)\n", 458 d_clk, ddr_type_string, p_clk); 459 if (node != NULL) 460 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 461 CTLFLAG_IMMEDIATE, 462 CTLTYPE_INT, "speed", 463 SYSCTL_DESCR("memory speed in MHz"), 464 NULL, d_clk, NULL, 0, 465 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 466 } 467 468 static void 469 decode_voltage_refresh(device_t self, struct spdmem *s) 470 { 471 const char *voltage, *refresh; 472 473 if (s->sm_voltage < __arraycount(spdmem_voltage_types)) 474 voltage = spdmem_voltage_types[s->sm_voltage]; 475 else 476 voltage = "unknown"; 477 478 if (s->sm_refresh < __arraycount(spdmem_refresh_types)) 479 refresh = spdmem_refresh_types[s->sm_refresh]; 480 else 481 refresh = "unknown"; 482 483 aprint_verbose_dev(self, "voltage %s, refresh time %s%s\n", 484 voltage, refresh, 485 s->sm_selfrefresh?" (self-refreshing)":""); 486 } 487 488 static void 489 decode_edofpm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 490 aprint_normal("\n"); 491 aprint_verbose_dev(self, 492 "%d rows, %d cols, %d banks, %dns tRAC, %dns tCAC\n", 493 s->sm_fpm.fpm_rows, s->sm_fpm.fpm_cols, s->sm_fpm.fpm_banks, 494 s->sm_fpm.fpm_tRAC, s->sm_fpm.fpm_tCAC); 495 } 496 497 static void 498 decode_rom(const struct sysctlnode *node, device_t self, struct spdmem *s) { 499 aprint_normal("\n"); 500 aprint_verbose_dev(self, "%d rows, %d cols, %d banks\n", 501 s->sm_rom.rom_rows, s->sm_rom.rom_cols, s->sm_rom.rom_banks); 502 } 503 504 static void 505 decode_sdram(const struct sysctlnode *node, device_t self, struct spdmem *s, 506 int spd_len) { 507 int dimm_size, cycle_time, bits, tAA, i, speed, freq; 508 509 aprint_normal("%s, %s, ", 510 (s->sm_sdr.sdr_mod_attrs & SPDMEM_SDR_MASK_REG)? 511 " (registered)":"", 512 (s->sm_config < __arraycount(spdmem_parity_types))? 513 spdmem_parity_types[s->sm_config]:"invalid parity"); 514 515 dimm_size = 1 << (s->sm_sdr.sdr_rows + s->sm_sdr.sdr_cols - 17); 516 dimm_size *= s->sm_sdr.sdr_banks * s->sm_sdr.sdr_banks_per_chip; 517 518 cycle_time = s->sm_sdr.sdr_cycle_whole * 1000 + 519 s->sm_sdr.sdr_cycle_tenths * 100; 520 bits = le16toh(s->sm_sdr.sdr_datawidth); 521 if (s->sm_config == 1 || s->sm_config == 2) 522 bits -= 8; 523 524 /* Calculate speed here - from OpenBSD */ 525 if (spd_len >= 128) 526 freq = ((uint8_t *)s)[126]; 527 else 528 freq = 0; 529 switch (freq) { 530 /* 531 * Must check cycle time since some PC-133 DIMMs 532 * actually report PC-100 533 */ 534 case 100: 535 case 133: 536 if (cycle_time < 8000) 537 speed = 133; 538 else 539 speed = 100; 540 break; 541 case 0x66: /* Legacy DIMMs use _hex_ 66! */ 542 default: 543 speed = 66; 544 } 545 decode_size_speed(self, node, dimm_size, cycle_time, 1, bits, FALSE, 546 "PC", speed); 547 548 aprint_verbose_dev(self, 549 "%d rows, %d cols, %d banks, %d banks/chip, %d.%dns cycle time\n", 550 s->sm_sdr.sdr_rows, s->sm_sdr.sdr_cols, s->sm_sdr.sdr_banks, 551 s->sm_sdr.sdr_banks_per_chip, cycle_time/1000, 552 (cycle_time % 1000) / 100); 553 554 tAA = 0; 555 for (i = 0; i < 8; i++) 556 if (s->sm_sdr.sdr_tCAS & (1 << i)) 557 tAA = i; 558 tAA++; 559 aprint_verbose_dev(self, LATENCY, tAA, s->sm_sdr.sdr_tRCD, 560 s->sm_sdr.sdr_tRP, s->sm_sdr.sdr_tRAS); 561 562 decode_voltage_refresh(self, s); 563 } 564 565 static void 566 decode_ddr(const struct sysctlnode *node, device_t self, struct spdmem *s) { 567 int dimm_size, cycle_time, bits, tAA, i; 568 569 aprint_normal("%s, %s, ", 570 (s->sm_ddr.ddr_mod_attrs & SPDMEM_DDR_MASK_REG)? 571 " (registered)":"", 572 (s->sm_config < __arraycount(spdmem_parity_types))? 573 spdmem_parity_types[s->sm_config]:"invalid parity"); 574 575 dimm_size = 1 << (s->sm_ddr.ddr_rows + s->sm_ddr.ddr_cols - 17); 576 dimm_size *= s->sm_ddr.ddr_ranks * s->sm_ddr.ddr_banks_per_chip; 577 578 cycle_time = s->sm_ddr.ddr_cycle_whole * 1000 + 579 spdmem_cycle_frac[s->sm_ddr.ddr_cycle_tenths]; 580 bits = le16toh(s->sm_ddr.ddr_datawidth); 581 if (s->sm_config == 1 || s->sm_config == 2) 582 bits -= 8; 583 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 584 "PC", 0); 585 586 aprint_verbose_dev(self, 587 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%dns cycle time\n", 588 s->sm_ddr.ddr_rows, s->sm_ddr.ddr_cols, s->sm_ddr.ddr_ranks, 589 s->sm_ddr.ddr_banks_per_chip, cycle_time/1000, 590 (cycle_time % 1000 + 50) / 100); 591 592 tAA = 0; 593 for (i = 2; i < 8; i++) 594 if (s->sm_ddr.ddr_tCAS & (1 << i)) 595 tAA = i; 596 tAA /= 2; 597 598 #define __DDR_ROUND(scale, field) \ 599 ((scale * s->sm_ddr.field + cycle_time - 1) / cycle_time) 600 601 aprint_verbose_dev(self, LATENCY, tAA, __DDR_ROUND(250, ddr_tRCD), 602 __DDR_ROUND(250, ddr_tRP), __DDR_ROUND(1000, ddr_tRAS)); 603 604 #undef __DDR_ROUND 605 606 decode_voltage_refresh(self, s); 607 } 608 609 static void 610 decode_ddr2(const struct sysctlnode *node, device_t self, struct spdmem *s) { 611 int dimm_size, cycle_time, bits, tAA, i; 612 613 aprint_normal("%s, %s, ", 614 (s->sm_ddr2.ddr2_mod_attrs & SPDMEM_DDR2_MASK_REG)? 615 " (registered)":"", 616 (s->sm_config < __arraycount(spdmem_parity_types))? 617 spdmem_parity_types[s->sm_config]:"invalid parity"); 618 619 dimm_size = 1 << (s->sm_ddr2.ddr2_rows + s->sm_ddr2.ddr2_cols - 17); 620 dimm_size *= (s->sm_ddr2.ddr2_ranks + 1) * 621 s->sm_ddr2.ddr2_banks_per_chip; 622 623 cycle_time = s->sm_ddr2.ddr2_cycle_whole * 1000 + 624 spdmem_cycle_frac[s->sm_ddr2.ddr2_cycle_frac]; 625 bits = s->sm_ddr2.ddr2_datawidth; 626 if ((s->sm_config & 0x03) != 0) 627 bits -= 8; 628 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 629 "PC2", 0); 630 631 aprint_verbose_dev(self, 632 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%02dns cycle time\n", 633 s->sm_ddr2.ddr2_rows, s->sm_ddr2.ddr2_cols, 634 s->sm_ddr2.ddr2_ranks + 1, s->sm_ddr2.ddr2_banks_per_chip, 635 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 636 637 tAA = 0; 638 for (i = 2; i < 8; i++) 639 if (s->sm_ddr2.ddr2_tCAS & (1 << i)) 640 tAA = i; 641 642 #define __DDR2_ROUND(scale, field) \ 643 ((scale * s->sm_ddr2.field + cycle_time - 1) / cycle_time) 644 645 aprint_verbose_dev(self, LATENCY, tAA, __DDR2_ROUND(250, ddr2_tRCD), 646 __DDR2_ROUND(250, ddr2_tRP), __DDR2_ROUND(1000, ddr2_tRAS)); 647 648 #undef __DDR_ROUND 649 650 decode_voltage_refresh(self, s); 651 } 652 653 static void 654 decode_ddr3(const struct sysctlnode *node, device_t self, struct spdmem *s) { 655 int dimm_size, cycle_time, bits; 656 657 if (s->sm_ddr3.ddr3_mod_type == 658 SPDMEM_DDR3_TYPE_MINI_RDIMM || 659 s->sm_ddr3.ddr3_mod_type == SPDMEM_DDR3_TYPE_RDIMM) 660 aprint_normal(" (registered)"); 661 aprint_normal(", %sECC, %stemp-sensor, ", 662 (s->sm_ddr3.ddr3_hasECC)?"":"no ", 663 (s->sm_ddr3.ddr3_has_therm_sensor)?"":"no "); 664 665 /* 666 * DDR3 size specification is quite different from others 667 * 668 * Module capacity is defined as 669 * Chip_Capacity_in_bits / 8bits-per-byte * 670 * external_bus_width / internal_bus_width 671 * We further divide by 2**20 to get our answer in MB 672 */ 673 dimm_size = (s->sm_ddr3.ddr3_chipsize + 28 - 20) - 3 + 674 (s->sm_ddr3.ddr3_datawidth + 3) - 675 (s->sm_ddr3.ddr3_chipwidth + 2); 676 dimm_size = (1 << dimm_size) * (s->sm_ddr3.ddr3_physbanks + 1); 677 678 cycle_time = (1000 * s->sm_ddr3.ddr3_mtb_dividend + 679 (s->sm_ddr3.ddr3_mtb_divisor / 2)) / 680 s->sm_ddr3.ddr3_mtb_divisor; 681 cycle_time *= s->sm_ddr3.ddr3_tCKmin; 682 bits = 1 << (s->sm_ddr3.ddr3_datawidth + 3); 683 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, FALSE, 684 "PC3", 0); 685 686 aprint_verbose_dev(self, 687 "%d rows, %d cols, %d log. banks, %d phys. banks, " 688 "%d.%03dns cycle time\n", 689 s->sm_ddr3.ddr3_rows + 9, s->sm_ddr3.ddr3_cols + 12, 690 1 << (s->sm_ddr3.ddr3_logbanks + 3), 691 s->sm_ddr3.ddr3_physbanks + 1, 692 cycle_time/1000, cycle_time % 1000); 693 694 #define __DDR3_CYCLES(field) (s->sm_ddr3.field / s->sm_ddr3.ddr3_tCKmin) 695 696 aprint_verbose_dev(self, LATENCY, __DDR3_CYCLES(ddr3_tAAmin), 697 __DDR3_CYCLES(ddr3_tRCDmin), __DDR3_CYCLES(ddr3_tRPmin), 698 (s->sm_ddr3.ddr3_tRAS_msb * 256 + s->sm_ddr3.ddr3_tRAS_lsb) / 699 s->sm_ddr3.ddr3_tCKmin); 700 701 #undef __DDR3_CYCLES 702 } 703 704 static void 705 decode_fbdimm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 706 int dimm_size, cycle_time, bits; 707 708 /* 709 * FB-DIMM module size calculation is very much like DDR3 710 */ 711 dimm_size = s->sm_fbd.fbdimm_rows + 12 + 712 s->sm_fbd.fbdimm_cols + 9 - 20 - 3; 713 dimm_size = (1 << dimm_size) * (1 << (s->sm_fbd.fbdimm_banks + 2)); 714 715 cycle_time = (1000 * s->sm_fbd.fbdimm_mtb_dividend + 716 (s->sm_fbd.fbdimm_mtb_divisor / 2)) / 717 s->sm_fbd.fbdimm_mtb_divisor; 718 bits = 1 << (s->sm_fbd.fbdimm_dev_width + 2); 719 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 720 "PC2", 0); 721 722 aprint_verbose_dev(self, 723 "%d rows, %d cols, %d banks, %d.%02dns cycle time\n", 724 s->sm_fbd.fbdimm_rows, s->sm_fbd.fbdimm_cols, 725 1 << (s->sm_fbd.fbdimm_banks + 2), 726 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 727 728 #define __FBDIMM_CYCLES(field) (s->sm_fbd.field / s->sm_fbd.fbdimm_tCKmin) 729 730 aprint_verbose_dev(self, LATENCY, __FBDIMM_CYCLES(fbdimm_tAAmin), 731 __FBDIMM_CYCLES(fbdimm_tRCDmin), __FBDIMM_CYCLES(fbdimm_tRPmin), 732 (s->sm_fbd.fbdimm_tRAS_msb * 256 + 733 s->sm_fbd.fbdimm_tRAS_lsb) / 734 s->sm_fbd.fbdimm_tCKmin); 735 736 #undef __FBDIMM_CYCLES 737 738 decode_voltage_refresh(self, s); 739 } 740
Indexes created Wed Oct 01 18:09:54 GMT 2025