spdmem.c revision 1.7.2.1
1 /* $NetBSD: spdmem.c,v 1.7.2.1 2013/08/28 23:59:25 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Nicolas Joly 5 * Copyright (c) 2007 Paul Goyette 6 * Copyright (c) 2007 Tobias Nygren 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Serial Presence Detect (SPD) memory identification 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.7.2.1 2013/08/28 23:59:25 rmind Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/device.h> 42 #include <sys/endian.h> 43 #include <sys/sysctl.h> 44 #include <machine/bswap.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/ic/spdmemreg.h> 48 #include <dev/ic/spdmemvar.h> 49 50 SYSCTL_SETUP_PROTO(sysctl_spdmem_setup); 51 52 /* Routines for decoding spd data */ 53 static void decode_edofpm(const struct sysctlnode *, device_t, struct spdmem *); 54 static void decode_rom(const struct sysctlnode *, device_t, struct spdmem *); 55 static void decode_sdram(const struct sysctlnode *, device_t, struct spdmem *, 56 int); 57 static void decode_ddr(const struct sysctlnode *, device_t, struct spdmem *); 58 static void decode_ddr2(const struct sysctlnode *, device_t, struct spdmem *); 59 static void decode_ddr3(const struct sysctlnode *, device_t, struct spdmem *); 60 static void decode_fbdimm(const struct sysctlnode *, device_t, struct spdmem *); 61 62 static void decode_size_speed(device_t, const struct sysctlnode *, 63 int, int, int, int, bool, const char *, int); 64 static void decode_voltage_refresh(device_t, struct spdmem *); 65 66 #define IS_RAMBUS_TYPE (s->sm_len < 4) 67 68 static const char* spdmem_basic_types[] = { 69 "unknown", 70 "FPM", 71 "EDO", 72 "Pipelined Nibble", 73 "SDRAM", 74 "ROM", 75 "DDR SGRAM", 76 "DDR SDRAM", 77 "DDR2 SDRAM", 78 "DDR2 SDRAM FB", 79 "DDR2 SDRAM FB Probe", 80 "DDR3 SDRAM" 81 }; 82 83 static const char* spdmem_superset_types[] = { 84 "unknown", 85 "ESDRAM", 86 "DDR ESDRAM", 87 "PEM EDO", 88 "PEM SDRAM" 89 }; 90 91 static const char* spdmem_voltage_types[] = { 92 "TTL (5V tolerant)", 93 "LvTTL (not 5V tolerant)", 94 "HSTL 1.5V", 95 "SSTL 3.3V", 96 "SSTL 2.5V", 97 "SSTL 1.8V" 98 }; 99 100 static const char* spdmem_refresh_types[] = { 101 "15.625us", 102 "3.9us", 103 "7.8us", 104 "31.3us", 105 "62.5us", 106 "125us" 107 }; 108 109 static const char* spdmem_parity_types[] = { 110 "no parity or ECC", 111 "data parity", 112 "data ECC", 113 "data parity and ECC", 114 "cmd/addr parity", 115 "cmd/addr/data parity", 116 "cmd/addr parity, data ECC", 117 "cmd/addr/data parity, data ECC" 118 }; 119 120 /* Cycle time fractional values (units of .001 ns) for DDR2 SDRAM */ 121 static const uint16_t spdmem_cycle_frac[] = { 122 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 123 250, 333, 667, 750, 999, 999 124 }; 125 126 /* Format string for timing info */ 127 #define LATENCY "tAA-tRCD-tRP-tRAS: %d-%d-%d-%d\n" 128 129 /* sysctl stuff */ 130 static int hw_node = CTL_EOL; 131 132 /* CRC functions used for certain memory types */ 133 134 static uint16_t spdcrc16 (struct spdmem_softc *sc, int count) 135 { 136 uint16_t crc; 137 int i, j; 138 uint8_t val; 139 crc = 0; 140 for (j = 0; j <= count; j++) { 141 val = (sc->sc_read)(sc, j); 142 crc = crc ^ val << 8; 143 for (i = 0; i < 8; ++i) 144 if (crc & 0x8000) 145 crc = crc << 1 ^ 0x1021; 146 else 147 crc = crc << 1; 148 } 149 return (crc & 0xFFFF); 150 } 151 152 int 153 spdmem_common_probe(struct spdmem_softc *sc) 154 { 155 int cksum = 0; 156 uint8_t i, val, spd_type; 157 int spd_len, spd_crc_cover; 158 uint16_t crc_calc, crc_spd; 159 160 spd_type = (sc->sc_read)(sc, 2); 161 162 /* For older memory types, validate the checksum over 1st 63 bytes */ 163 if (spd_type <= SPDMEM_MEMTYPE_DDR2SDRAM) { 164 for (i = 0; i < 63; i++) 165 cksum += (sc->sc_read)(sc, i); 166 167 val = (sc->sc_read)(sc, 63); 168 169 if (cksum == 0 || (cksum & 0xff) != val) { 170 aprint_debug("spd checksum failed, calc = 0x%02x, " 171 "spd = 0x%02x\n", cksum, val); 172 return 0; 173 } else 174 return 1; 175 } 176 177 /* For DDR3 and FBDIMM, verify the CRC */ 178 else if (spd_type <= SPDMEM_MEMTYPE_DDR3SDRAM) { 179 spd_len = (sc->sc_read)(sc, 0); 180 if (spd_len & SPDMEM_SPDCRC_116) 181 spd_crc_cover = 116; 182 else 183 spd_crc_cover = 125; 184 switch (spd_len & SPDMEM_SPDLEN_MASK) { 185 case SPDMEM_SPDLEN_128: 186 spd_len = 128; 187 break; 188 case SPDMEM_SPDLEN_176: 189 spd_len = 176; 190 break; 191 case SPDMEM_SPDLEN_256: 192 spd_len = 256; 193 break; 194 default: 195 return 0; 196 } 197 if (spd_crc_cover > spd_len) 198 return 0; 199 crc_calc = spdcrc16(sc, spd_crc_cover); 200 crc_spd = (sc->sc_read)(sc, 127) << 8; 201 crc_spd |= (sc->sc_read)(sc, 126); 202 if (crc_calc != crc_spd) { 203 aprint_debug("crc16 failed, covers %d bytes, " 204 "calc = 0x%04x, spd = 0x%04x\n", 205 spd_crc_cover, crc_calc, crc_spd); 206 return 0; 207 } 208 return 1; 209 } 210 211 /* For unrecognized memory types, don't match at all */ 212 return 0; 213 } 214 215 void 216 spdmem_common_attach(struct spdmem_softc *sc, device_t self) 217 { 218 struct spdmem *s = &(sc->sc_spd_data); 219 const char *type; 220 const char *rambus_rev = "Reserved"; 221 int dimm_size; 222 unsigned int i, spd_len, spd_size; 223 const struct sysctlnode *node = NULL; 224 225 /* 226 * FBDIMM and DDR3 (and probably all newer) have a different 227 * encoding of the SPD EEPROM used/total sizes 228 */ 229 s->sm_len = (sc->sc_read)(sc, 0); 230 s->sm_size = (sc->sc_read)(sc, 1); 231 s->sm_type = (sc->sc_read)(sc, 2); 232 233 if (s->sm_type >= SPDMEM_MEMTYPE_FBDIMM) { 234 spd_size = 64 << (s->sm_len & SPDMEM_SPDSIZE_MASK); 235 switch (s->sm_len & SPDMEM_SPDLEN_MASK) { 236 case SPDMEM_SPDLEN_128: 237 spd_len = 128; 238 break; 239 case SPDMEM_SPDLEN_176: 240 spd_len = 176; 241 break; 242 case SPDMEM_SPDLEN_256: 243 spd_len = 256; 244 break; 245 default: 246 spd_len = 64; 247 break; 248 } 249 } else { 250 spd_size = 1 << s->sm_size; 251 spd_len = s->sm_len; 252 if (spd_len < 64) 253 spd_len = 64; 254 } 255 if (spd_len > spd_size) 256 spd_len = spd_size; 257 if (spd_len > sizeof(struct spdmem)) 258 spd_len = sizeof(struct spdmem); 259 for (i = 3; i < spd_len; i++) 260 ((uint8_t *)s)[i] = (sc->sc_read)(sc, i); 261 262 /* 263 * Setup our sysctl subtree, hw.spdmemN 264 */ 265 sc->sc_sysctl_log = NULL; 266 if (hw_node != CTL_EOL) 267 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, 268 0, CTLTYPE_NODE, 269 device_xname(self), NULL, NULL, 0, NULL, 0, 270 CTL_HW, CTL_CREATE, CTL_EOL); 271 if (node != NULL && spd_len != 0) 272 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 273 0, 274 CTLTYPE_STRUCT, "spd_data", 275 SYSCTL_DESCR("raw spd data"), NULL, 276 0, s, spd_len, 277 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 278 279 /* 280 * Decode and print key SPD contents 281 */ 282 if (IS_RAMBUS_TYPE) { 283 if (s->sm_type == SPDMEM_MEMTYPE_RAMBUS) 284 type = "Rambus"; 285 else if (s->sm_type == SPDMEM_MEMTYPE_DIRECTRAMBUS) 286 type = "Direct Rambus"; 287 else 288 type = "Rambus (unknown)"; 289 290 switch (s->sm_len) { 291 case 0: 292 rambus_rev = "Invalid"; 293 break; 294 case 1: 295 rambus_rev = "0.7"; 296 break; 297 case 2: 298 rambus_rev = "1.0"; 299 break; 300 default: 301 rambus_rev = "Reserved"; 302 break; 303 } 304 } else { 305 if (s->sm_type < __arraycount(spdmem_basic_types)) 306 type = spdmem_basic_types[s->sm_type]; 307 else 308 type = "unknown memory type"; 309 310 if (s->sm_type == SPDMEM_MEMTYPE_EDO && 311 s->sm_fpm.fpm_superset == SPDMEM_SUPERSET_EDO_PEM) 312 type = spdmem_superset_types[SPDMEM_SUPERSET_EDO_PEM]; 313 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 314 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_SDRAM_PEM) 315 type = spdmem_superset_types[SPDMEM_SUPERSET_SDRAM_PEM]; 316 if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM && 317 s->sm_ddr.ddr_superset == SPDMEM_SUPERSET_DDR_ESDRAM) 318 type = 319 spdmem_superset_types[SPDMEM_SUPERSET_DDR_ESDRAM]; 320 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 321 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_ESDRAM) { 322 type = spdmem_superset_types[SPDMEM_SUPERSET_ESDRAM]; 323 } 324 } 325 326 strlcpy(sc->sc_type, type, SPDMEM_TYPE_MAXLEN); 327 if (node != NULL) 328 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 329 0, 330 CTLTYPE_STRING, "mem_type", 331 SYSCTL_DESCR("memory module type"), NULL, 332 0, sc->sc_type, 0, 333 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 334 335 if (IS_RAMBUS_TYPE) { 336 aprint_naive("\n"); 337 aprint_normal("\n"); 338 aprint_normal_dev(self, "%s, SPD Revision %s", type, rambus_rev); 339 dimm_size = 1 << (s->sm_rdr.rdr_rows + s->sm_rdr.rdr_cols - 13); 340 if (dimm_size >= 1024) 341 aprint_normal(", %dGB\n", dimm_size / 1024); 342 else 343 aprint_normal(", %dMB\n", dimm_size); 344 345 /* No further decode for RAMBUS memory */ 346 return; 347 } 348 switch (s->sm_type) { 349 case SPDMEM_MEMTYPE_EDO: 350 case SPDMEM_MEMTYPE_FPM: 351 decode_edofpm(node, self, s); 352 break; 353 case SPDMEM_MEMTYPE_ROM: 354 decode_rom(node, self, s); 355 break; 356 case SPDMEM_MEMTYPE_SDRAM: 357 decode_sdram(node, self, s, spd_len); 358 break; 359 case SPDMEM_MEMTYPE_DDRSDRAM: 360 decode_ddr(node, self, s); 361 break; 362 case SPDMEM_MEMTYPE_DDR2SDRAM: 363 decode_ddr2(node, self, s); 364 break; 365 case SPDMEM_MEMTYPE_DDR3SDRAM: 366 decode_ddr3(node, self, s); 367 break; 368 case SPDMEM_MEMTYPE_FBDIMM: 369 case SPDMEM_MEMTYPE_FBDIMM_PROBE: 370 decode_fbdimm(node, self, s); 371 break; 372 } 373 374 /* Dump SPD */ 375 for (i = 0; i < spd_len; i += 16) { 376 unsigned int j, k; 377 aprint_debug_dev(self, "0x%02x:", i); 378 k = (spd_len > (i + 16)) ? i + 16 : spd_len; 379 for (j = i; j < k; j++) 380 aprint_debug(" %02x", ((uint8_t *)s)[j]); 381 aprint_debug("\n"); 382 } 383 } 384 385 int 386 spdmem_common_detach(struct spdmem_softc *sc, device_t self) 387 { 388 sysctl_teardown(&sc->sc_sysctl_log); 389 390 return 0; 391 } 392 393 SYSCTL_SETUP(sysctl_spdmem_setup, "sysctl hw.spdmem subtree setup") 394 { 395 const struct sysctlnode *node; 396 397 if (sysctl_createv(clog, 0, NULL, &node, 398 #ifdef _MODULE 399 0, 400 #else 401 CTLFLAG_PERMANENT, 402 #endif 403 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 404 CTL_HW, CTL_EOL) != 0) 405 return; 406 407 hw_node = node->sysctl_num; 408 } 409 410 static void 411 decode_size_speed(device_t self, const struct sysctlnode *node, 412 int dimm_size, int cycle_time, int d_clk, int bits, 413 bool round, const char *ddr_type_string, int speed) 414 { 415 int p_clk; 416 struct spdmem_softc *sc = device_private(self); 417 418 if (dimm_size < 1024) 419 aprint_normal("%dMB", dimm_size); 420 else 421 aprint_normal("%dGB", dimm_size / 1024); 422 if (node != NULL) 423 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 424 CTLFLAG_IMMEDIATE, 425 CTLTYPE_INT, "size", 426 SYSCTL_DESCR("module size in MB"), NULL, 427 dimm_size, NULL, 0, 428 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 429 430 if (cycle_time == 0) { 431 aprint_normal("\n"); 432 return; 433 } 434 435 /* 436 * Calculate p_clk first, since for DDR3 we need maximum significance. 437 * DDR3 rating is not rounded to a multiple of 100. This results in 438 * cycle_time of 1.5ns displayed as PC3-10666. 439 * 440 * For SDRAM, the speed is provided by the caller so we use it. 441 */ 442 d_clk *= 1000 * 1000; 443 if (speed) 444 p_clk = speed; 445 else 446 p_clk = (d_clk * bits) / 8 / cycle_time; 447 d_clk = ((d_clk + cycle_time / 2) ) / cycle_time; 448 if (round) { 449 if ((p_clk % 100) >= 50) 450 p_clk += 50; 451 p_clk -= p_clk % 100; 452 } 453 aprint_normal(", %dMHz (%s-%d)\n", 454 d_clk, ddr_type_string, p_clk); 455 if (node != NULL) 456 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 457 CTLFLAG_IMMEDIATE, 458 CTLTYPE_INT, "speed", 459 SYSCTL_DESCR("memory speed in MHz"), 460 NULL, d_clk, NULL, 0, 461 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 462 } 463 464 static void 465 decode_voltage_refresh(device_t self, struct spdmem *s) 466 { 467 const char *voltage, *refresh; 468 469 if (s->sm_voltage < __arraycount(spdmem_voltage_types)) 470 voltage = spdmem_voltage_types[s->sm_voltage]; 471 else 472 voltage = "unknown"; 473 474 if (s->sm_refresh < __arraycount(spdmem_refresh_types)) 475 refresh = spdmem_refresh_types[s->sm_refresh]; 476 else 477 refresh = "unknown"; 478 479 aprint_verbose_dev(self, "voltage %s, refresh time %s%s\n", 480 voltage, refresh, 481 s->sm_selfrefresh?" (self-refreshing)":""); 482 } 483 484 static void 485 decode_edofpm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 486 aprint_naive("\n"); 487 aprint_normal("\n"); 488 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 489 490 aprint_normal("\n"); 491 aprint_verbose_dev(self, 492 "%d rows, %d cols, %d banks, %dns tRAC, %dns tCAC\n", 493 s->sm_fpm.fpm_rows, s->sm_fpm.fpm_cols, s->sm_fpm.fpm_banks, 494 s->sm_fpm.fpm_tRAC, s->sm_fpm.fpm_tCAC); 495 } 496 497 static void 498 decode_rom(const struct sysctlnode *node, device_t self, struct spdmem *s) { 499 aprint_naive("\n"); 500 aprint_normal("\n"); 501 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 502 503 aprint_normal("\n"); 504 aprint_verbose_dev(self, "%d rows, %d cols, %d banks\n", 505 s->sm_rom.rom_rows, s->sm_rom.rom_cols, s->sm_rom.rom_banks); 506 } 507 508 static void 509 decode_sdram(const struct sysctlnode *node, device_t self, struct spdmem *s, 510 int spd_len) { 511 int dimm_size, cycle_time, bits, tAA, i, speed, freq; 512 513 aprint_naive("\n"); 514 aprint_normal("\n"); 515 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 516 517 aprint_normal("%s, %s, ", 518 (s->sm_sdr.sdr_mod_attrs & SPDMEM_SDR_MASK_REG)? 519 " (registered)":"", 520 (s->sm_config < __arraycount(spdmem_parity_types))? 521 spdmem_parity_types[s->sm_config]:"invalid parity"); 522 523 dimm_size = 1 << (s->sm_sdr.sdr_rows + s->sm_sdr.sdr_cols - 17); 524 dimm_size *= s->sm_sdr.sdr_banks * s->sm_sdr.sdr_banks_per_chip; 525 526 cycle_time = s->sm_sdr.sdr_cycle_whole * 1000 + 527 s->sm_sdr.sdr_cycle_tenths * 100; 528 bits = le16toh(s->sm_sdr.sdr_datawidth); 529 if (s->sm_config == 1 || s->sm_config == 2) 530 bits -= 8; 531 532 /* Calculate speed here - from OpenBSD */ 533 if (spd_len >= 128) 534 freq = ((uint8_t *)s)[126]; 535 else 536 freq = 0; 537 switch (freq) { 538 /* 539 * Must check cycle time since some PC-133 DIMMs 540 * actually report PC-100 541 */ 542 case 100: 543 case 133: 544 if (cycle_time < 8000) 545 speed = 133; 546 else 547 speed = 100; 548 break; 549 case 0x66: /* Legacy DIMMs use _hex_ 66! */ 550 default: 551 speed = 66; 552 } 553 decode_size_speed(self, node, dimm_size, cycle_time, 1, bits, FALSE, 554 "PC", speed); 555 556 aprint_verbose_dev(self, 557 "%d rows, %d cols, %d banks, %d banks/chip, %d.%dns cycle time\n", 558 s->sm_sdr.sdr_rows, s->sm_sdr.sdr_cols, s->sm_sdr.sdr_banks, 559 s->sm_sdr.sdr_banks_per_chip, cycle_time/1000, 560 (cycle_time % 1000) / 100); 561 562 tAA = 0; 563 for (i = 0; i < 8; i++) 564 if (s->sm_sdr.sdr_tCAS & (1 << i)) 565 tAA = i; 566 tAA++; 567 aprint_verbose_dev(self, LATENCY, tAA, s->sm_sdr.sdr_tRCD, 568 s->sm_sdr.sdr_tRP, s->sm_sdr.sdr_tRAS); 569 570 decode_voltage_refresh(self, s); 571 } 572 573 static void 574 decode_ddr(const struct sysctlnode *node, device_t self, struct spdmem *s) { 575 int dimm_size, cycle_time, bits, tAA, i; 576 577 aprint_naive("\n"); 578 aprint_normal("\n"); 579 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 580 581 aprint_normal("%s, %s, ", 582 (s->sm_ddr.ddr_mod_attrs & SPDMEM_DDR_MASK_REG)? 583 " (registered)":"", 584 (s->sm_config < __arraycount(spdmem_parity_types))? 585 spdmem_parity_types[s->sm_config]:"invalid parity"); 586 587 dimm_size = 1 << (s->sm_ddr.ddr_rows + s->sm_ddr.ddr_cols - 17); 588 dimm_size *= s->sm_ddr.ddr_ranks * s->sm_ddr.ddr_banks_per_chip; 589 590 cycle_time = s->sm_ddr.ddr_cycle_whole * 1000 + 591 spdmem_cycle_frac[s->sm_ddr.ddr_cycle_tenths]; 592 bits = le16toh(s->sm_ddr.ddr_datawidth); 593 if (s->sm_config == 1 || s->sm_config == 2) 594 bits -= 8; 595 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 596 "PC", 0); 597 598 aprint_verbose_dev(self, 599 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%dns cycle time\n", 600 s->sm_ddr.ddr_rows, s->sm_ddr.ddr_cols, s->sm_ddr.ddr_ranks, 601 s->sm_ddr.ddr_banks_per_chip, cycle_time/1000, 602 (cycle_time % 1000 + 50) / 100); 603 604 tAA = 0; 605 for (i = 2; i < 8; i++) 606 if (s->sm_ddr.ddr_tCAS & (1 << i)) 607 tAA = i; 608 tAA /= 2; 609 610 #define __DDR_ROUND(scale, field) \ 611 ((scale * s->sm_ddr.field + cycle_time - 1) / cycle_time) 612 613 aprint_verbose_dev(self, LATENCY, tAA, __DDR_ROUND(250, ddr_tRCD), 614 __DDR_ROUND(250, ddr_tRP), __DDR_ROUND(1000, ddr_tRAS)); 615 616 #undef __DDR_ROUND 617 618 decode_voltage_refresh(self, s); 619 } 620 621 static void 622 decode_ddr2(const struct sysctlnode *node, device_t self, struct spdmem *s) { 623 int dimm_size, cycle_time, bits, tAA, i; 624 625 aprint_naive("\n"); 626 aprint_normal("\n"); 627 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 628 629 aprint_normal("%s, %s, ", 630 (s->sm_ddr2.ddr2_mod_attrs & SPDMEM_DDR2_MASK_REG)? 631 " (registered)":"", 632 (s->sm_config < __arraycount(spdmem_parity_types))? 633 spdmem_parity_types[s->sm_config]:"invalid parity"); 634 635 dimm_size = 1 << (s->sm_ddr2.ddr2_rows + s->sm_ddr2.ddr2_cols - 17); 636 dimm_size *= (s->sm_ddr2.ddr2_ranks + 1) * 637 s->sm_ddr2.ddr2_banks_per_chip; 638 639 cycle_time = s->sm_ddr2.ddr2_cycle_whole * 1000 + 640 spdmem_cycle_frac[s->sm_ddr2.ddr2_cycle_frac]; 641 bits = s->sm_ddr2.ddr2_datawidth; 642 if ((s->sm_config & 0x03) != 0) 643 bits -= 8; 644 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 645 "PC2", 0); 646 647 aprint_verbose_dev(self, 648 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%02dns cycle time\n", 649 s->sm_ddr2.ddr2_rows, s->sm_ddr2.ddr2_cols, 650 s->sm_ddr2.ddr2_ranks + 1, s->sm_ddr2.ddr2_banks_per_chip, 651 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 652 653 tAA = 0; 654 for (i = 2; i < 8; i++) 655 if (s->sm_ddr2.ddr2_tCAS & (1 << i)) 656 tAA = i; 657 658 #define __DDR2_ROUND(scale, field) \ 659 ((scale * s->sm_ddr2.field + cycle_time - 1) / cycle_time) 660 661 aprint_verbose_dev(self, LATENCY, tAA, __DDR2_ROUND(250, ddr2_tRCD), 662 __DDR2_ROUND(250, ddr2_tRP), __DDR2_ROUND(1000, ddr2_tRAS)); 663 664 #undef __DDR_ROUND 665 666 decode_voltage_refresh(self, s); 667 } 668 669 static void 670 decode_ddr3(const struct sysctlnode *node, device_t self, struct spdmem *s) { 671 int dimm_size, cycle_time, bits; 672 673 aprint_naive("\n"); 674 aprint_normal(": %18s\n", s->sm_ddr3.ddr3_part); 675 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 676 677 if (s->sm_ddr3.ddr3_mod_type == 678 SPDMEM_DDR3_TYPE_MINI_RDIMM || 679 s->sm_ddr3.ddr3_mod_type == SPDMEM_DDR3_TYPE_RDIMM) 680 aprint_normal(" (registered)"); 681 aprint_normal(", %sECC, %stemp-sensor, ", 682 (s->sm_ddr3.ddr3_hasECC)?"":"no ", 683 (s->sm_ddr3.ddr3_has_therm_sensor)?"":"no "); 684 685 /* 686 * DDR3 size specification is quite different from others 687 * 688 * Module capacity is defined as 689 * Chip_Capacity_in_bits / 8bits-per-byte * 690 * external_bus_width / internal_bus_width 691 * We further divide by 2**20 to get our answer in MB 692 */ 693 dimm_size = (s->sm_ddr3.ddr3_chipsize + 28 - 20) - 3 + 694 (s->sm_ddr3.ddr3_datawidth + 3) - 695 (s->sm_ddr3.ddr3_chipwidth + 2); 696 dimm_size = (1 << dimm_size) * (s->sm_ddr3.ddr3_physbanks + 1); 697 698 cycle_time = (1000 * s->sm_ddr3.ddr3_mtb_dividend + 699 (s->sm_ddr3.ddr3_mtb_divisor / 2)) / 700 s->sm_ddr3.ddr3_mtb_divisor; 701 cycle_time *= s->sm_ddr3.ddr3_tCKmin; 702 bits = 1 << (s->sm_ddr3.ddr3_datawidth + 3); 703 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, FALSE, 704 "PC3", 0); 705 706 aprint_verbose_dev(self, 707 "%d rows, %d cols, %d log. banks, %d phys. banks, " 708 "%d.%03dns cycle time\n", 709 s->sm_ddr3.ddr3_rows + 9, s->sm_ddr3.ddr3_cols + 12, 710 1 << (s->sm_ddr3.ddr3_logbanks + 3), 711 s->sm_ddr3.ddr3_physbanks + 1, 712 cycle_time/1000, cycle_time % 1000); 713 714 #define __DDR3_CYCLES(field) (s->sm_ddr3.field / s->sm_ddr3.ddr3_tCKmin) 715 716 aprint_verbose_dev(self, LATENCY, __DDR3_CYCLES(ddr3_tAAmin), 717 __DDR3_CYCLES(ddr3_tRCDmin), __DDR3_CYCLES(ddr3_tRPmin), 718 (s->sm_ddr3.ddr3_tRAS_msb * 256 + s->sm_ddr3.ddr3_tRAS_lsb) / 719 s->sm_ddr3.ddr3_tCKmin); 720 721 #undef __DDR3_CYCLES 722 } 723 724 static void 725 decode_fbdimm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 726 int dimm_size, cycle_time, bits; 727 728 aprint_naive("\n"); 729 aprint_normal("\n"); 730 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 731 732 /* 733 * FB-DIMM module size calculation is very much like DDR3 734 */ 735 dimm_size = s->sm_fbd.fbdimm_rows + 12 + 736 s->sm_fbd.fbdimm_cols + 9 - 20 - 3; 737 dimm_size = (1 << dimm_size) * (1 << (s->sm_fbd.fbdimm_banks + 2)); 738 739 cycle_time = (1000 * s->sm_fbd.fbdimm_mtb_dividend + 740 (s->sm_fbd.fbdimm_mtb_divisor / 2)) / 741 s->sm_fbd.fbdimm_mtb_divisor; 742 bits = 1 << (s->sm_fbd.fbdimm_dev_width + 2); 743 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 744 "PC2", 0); 745 746 aprint_verbose_dev(self, 747 "%d rows, %d cols, %d banks, %d.%02dns cycle time\n", 748 s->sm_fbd.fbdimm_rows, s->sm_fbd.fbdimm_cols, 749 1 << (s->sm_fbd.fbdimm_banks + 2), 750 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 751 752 #define __FBDIMM_CYCLES(field) (s->sm_fbd.field / s->sm_fbd.fbdimm_tCKmin) 753 754 aprint_verbose_dev(self, LATENCY, __FBDIMM_CYCLES(fbdimm_tAAmin), 755 __FBDIMM_CYCLES(fbdimm_tRCDmin), __FBDIMM_CYCLES(fbdimm_tRPmin), 756 (s->sm_fbd.fbdimm_tRAS_msb * 256 + 757 s->sm_fbd.fbdimm_tRAS_lsb) / 758 s->sm_fbd.fbdimm_tCKmin); 759 760 #undef __FBDIMM_CYCLES 761 762 decode_voltage_refresh(self, s); 763 } 764
Indexes created Fri Oct 03 02:09:57 GMT 2025