spdmem.c revision 1.7.2.2
1 /* $NetBSD: spdmem.c,v 1.7.2.2 2014/05/18 17:45:38 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Nicolas Joly 5 * Copyright (c) 2007 Paul Goyette 6 * Copyright (c) 2007 Tobias Nygren 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Serial Presence Detect (SPD) memory identification 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.7.2.2 2014/05/18 17:45:38 rmind Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/device.h> 42 #include <sys/endian.h> 43 #include <sys/sysctl.h> 44 #include <machine/bswap.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/ic/spdmemreg.h> 48 #include <dev/ic/spdmemvar.h> 49 50 /* Routines for decoding spd data */ 51 static void decode_edofpm(const struct sysctlnode *, device_t, struct spdmem *); 52 static void decode_rom(const struct sysctlnode *, device_t, struct spdmem *); 53 static void decode_sdram(const struct sysctlnode *, device_t, struct spdmem *, 54 int); 55 static void decode_ddr(const struct sysctlnode *, device_t, struct spdmem *); 56 static void decode_ddr2(const struct sysctlnode *, device_t, struct spdmem *); 57 static void decode_ddr3(const struct sysctlnode *, device_t, struct spdmem *); 58 static void decode_fbdimm(const struct sysctlnode *, device_t, struct spdmem *); 59 60 static void decode_size_speed(device_t, const struct sysctlnode *, 61 int, int, int, int, bool, const char *, int); 62 static void decode_voltage_refresh(device_t, struct spdmem *); 63 64 #define IS_RAMBUS_TYPE (s->sm_len < 4) 65 66 static const char* spdmem_basic_types[] = { 67 "unknown", 68 "FPM", 69 "EDO", 70 "Pipelined Nibble", 71 "SDRAM", 72 "ROM", 73 "DDR SGRAM", 74 "DDR SDRAM", 75 "DDR2 SDRAM", 76 "DDR2 SDRAM FB", 77 "DDR2 SDRAM FB Probe", 78 "DDR3 SDRAM" 79 }; 80 81 static const char* spdmem_superset_types[] = { 82 "unknown", 83 "ESDRAM", 84 "DDR ESDRAM", 85 "PEM EDO", 86 "PEM SDRAM" 87 }; 88 89 static const char* spdmem_voltage_types[] = { 90 "TTL (5V tolerant)", 91 "LvTTL (not 5V tolerant)", 92 "HSTL 1.5V", 93 "SSTL 3.3V", 94 "SSTL 2.5V", 95 "SSTL 1.8V" 96 }; 97 98 static const char* spdmem_refresh_types[] = { 99 "15.625us", 100 "3.9us", 101 "7.8us", 102 "31.3us", 103 "62.5us", 104 "125us" 105 }; 106 107 static const char* spdmem_parity_types[] = { 108 "no parity or ECC", 109 "data parity", 110 "data ECC", 111 "data parity and ECC", 112 "cmd/addr parity", 113 "cmd/addr/data parity", 114 "cmd/addr parity, data ECC", 115 "cmd/addr/data parity, data ECC" 116 }; 117 118 /* Cycle time fractional values (units of .001 ns) for DDR2 SDRAM */ 119 static const uint16_t spdmem_cycle_frac[] = { 120 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 121 250, 333, 667, 750, 999, 999 122 }; 123 124 /* Format string for timing info */ 125 #define LATENCY "tAA-tRCD-tRP-tRAS: %d-%d-%d-%d\n" 126 127 /* CRC functions used for certain memory types */ 128 129 static uint16_t spdcrc16 (struct spdmem_softc *sc, int count) 130 { 131 uint16_t crc; 132 int i, j; 133 uint8_t val; 134 crc = 0; 135 for (j = 0; j <= count; j++) { 136 val = (sc->sc_read)(sc, j); 137 crc = crc ^ val << 8; 138 for (i = 0; i < 8; ++i) 139 if (crc & 0x8000) 140 crc = crc << 1 ^ 0x1021; 141 else 142 crc = crc << 1; 143 } 144 return (crc & 0xFFFF); 145 } 146 147 int 148 spdmem_common_probe(struct spdmem_softc *sc) 149 { 150 int cksum = 0; 151 uint8_t i, val, spd_type; 152 int spd_len, spd_crc_cover; 153 uint16_t crc_calc, crc_spd; 154 155 spd_type = (sc->sc_read)(sc, 2); 156 157 /* For older memory types, validate the checksum over 1st 63 bytes */ 158 if (spd_type <= SPDMEM_MEMTYPE_DDR2SDRAM) { 159 for (i = 0; i < 63; i++) 160 cksum += (sc->sc_read)(sc, i); 161 162 val = (sc->sc_read)(sc, 63); 163 164 if (cksum == 0 || (cksum & 0xff) != val) { 165 aprint_debug("spd checksum failed, calc = 0x%02x, " 166 "spd = 0x%02x\n", cksum, val); 167 return 0; 168 } else 169 return 1; 170 } 171 172 /* For DDR3 and FBDIMM, verify the CRC */ 173 else if (spd_type <= SPDMEM_MEMTYPE_DDR3SDRAM) { 174 spd_len = (sc->sc_read)(sc, 0); 175 if (spd_len & SPDMEM_SPDCRC_116) 176 spd_crc_cover = 116; 177 else 178 spd_crc_cover = 125; 179 switch (spd_len & SPDMEM_SPDLEN_MASK) { 180 case SPDMEM_SPDLEN_128: 181 spd_len = 128; 182 break; 183 case SPDMEM_SPDLEN_176: 184 spd_len = 176; 185 break; 186 case SPDMEM_SPDLEN_256: 187 spd_len = 256; 188 break; 189 default: 190 return 0; 191 } 192 if (spd_crc_cover > spd_len) 193 return 0; 194 crc_calc = spdcrc16(sc, spd_crc_cover); 195 crc_spd = (sc->sc_read)(sc, 127) << 8; 196 crc_spd |= (sc->sc_read)(sc, 126); 197 if (crc_calc != crc_spd) { 198 aprint_debug("crc16 failed, covers %d bytes, " 199 "calc = 0x%04x, spd = 0x%04x\n", 200 spd_crc_cover, crc_calc, crc_spd); 201 return 0; 202 } 203 return 1; 204 } 205 206 /* For unrecognized memory types, don't match at all */ 207 return 0; 208 } 209 210 void 211 spdmem_common_attach(struct spdmem_softc *sc, device_t self) 212 { 213 struct spdmem *s = &(sc->sc_spd_data); 214 const char *type; 215 const char *rambus_rev = "Reserved"; 216 int dimm_size; 217 unsigned int i, spd_len, spd_size; 218 const struct sysctlnode *node = NULL; 219 220 /* 221 * FBDIMM and DDR3 (and probably all newer) have a different 222 * encoding of the SPD EEPROM used/total sizes 223 */ 224 s->sm_len = (sc->sc_read)(sc, 0); 225 s->sm_size = (sc->sc_read)(sc, 1); 226 s->sm_type = (sc->sc_read)(sc, 2); 227 228 if (s->sm_type >= SPDMEM_MEMTYPE_FBDIMM) { 229 spd_size = 64 << (s->sm_len & SPDMEM_SPDSIZE_MASK); 230 switch (s->sm_len & SPDMEM_SPDLEN_MASK) { 231 case SPDMEM_SPDLEN_128: 232 spd_len = 128; 233 break; 234 case SPDMEM_SPDLEN_176: 235 spd_len = 176; 236 break; 237 case SPDMEM_SPDLEN_256: 238 spd_len = 256; 239 break; 240 default: 241 spd_len = 64; 242 break; 243 } 244 } else { 245 spd_size = 1 << s->sm_size; 246 spd_len = s->sm_len; 247 if (spd_len < 64) 248 spd_len = 64; 249 } 250 if (spd_len > spd_size) 251 spd_len = spd_size; 252 if (spd_len > sizeof(struct spdmem)) 253 spd_len = sizeof(struct spdmem); 254 for (i = 3; i < spd_len; i++) 255 ((uint8_t *)s)[i] = (sc->sc_read)(sc, i); 256 257 /* 258 * Setup our sysctl subtree, hw.spdmemN 259 */ 260 sc->sc_sysctl_log = NULL; 261 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, 262 0, CTLTYPE_NODE, 263 device_xname(self), NULL, NULL, 0, NULL, 0, 264 CTL_HW, CTL_CREATE, CTL_EOL); 265 if (node != NULL && spd_len != 0) 266 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 267 0, 268 CTLTYPE_STRUCT, "spd_data", 269 SYSCTL_DESCR("raw spd data"), NULL, 270 0, s, spd_len, 271 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 272 273 /* 274 * Decode and print key SPD contents 275 */ 276 if (IS_RAMBUS_TYPE) { 277 if (s->sm_type == SPDMEM_MEMTYPE_RAMBUS) 278 type = "Rambus"; 279 else if (s->sm_type == SPDMEM_MEMTYPE_DIRECTRAMBUS) 280 type = "Direct Rambus"; 281 else 282 type = "Rambus (unknown)"; 283 284 switch (s->sm_len) { 285 case 0: 286 rambus_rev = "Invalid"; 287 break; 288 case 1: 289 rambus_rev = "0.7"; 290 break; 291 case 2: 292 rambus_rev = "1.0"; 293 break; 294 default: 295 rambus_rev = "Reserved"; 296 break; 297 } 298 } else { 299 if (s->sm_type < __arraycount(spdmem_basic_types)) 300 type = spdmem_basic_types[s->sm_type]; 301 else 302 type = "unknown memory type"; 303 304 if (s->sm_type == SPDMEM_MEMTYPE_EDO && 305 s->sm_fpm.fpm_superset == SPDMEM_SUPERSET_EDO_PEM) 306 type = spdmem_superset_types[SPDMEM_SUPERSET_EDO_PEM]; 307 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 308 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_SDRAM_PEM) 309 type = spdmem_superset_types[SPDMEM_SUPERSET_SDRAM_PEM]; 310 if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM && 311 s->sm_ddr.ddr_superset == SPDMEM_SUPERSET_DDR_ESDRAM) 312 type = 313 spdmem_superset_types[SPDMEM_SUPERSET_DDR_ESDRAM]; 314 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 315 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_ESDRAM) { 316 type = spdmem_superset_types[SPDMEM_SUPERSET_ESDRAM]; 317 } 318 } 319 320 strlcpy(sc->sc_type, type, SPDMEM_TYPE_MAXLEN); 321 if (node != NULL) 322 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 323 0, 324 CTLTYPE_STRING, "mem_type", 325 SYSCTL_DESCR("memory module type"), NULL, 326 0, sc->sc_type, 0, 327 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 328 329 if (IS_RAMBUS_TYPE) { 330 aprint_naive("\n"); 331 aprint_normal("\n"); 332 aprint_normal_dev(self, "%s, SPD Revision %s", type, rambus_rev); 333 dimm_size = 1 << (s->sm_rdr.rdr_rows + s->sm_rdr.rdr_cols - 13); 334 if (dimm_size >= 1024) 335 aprint_normal(", %dGB\n", dimm_size / 1024); 336 else 337 aprint_normal(", %dMB\n", dimm_size); 338 339 /* No further decode for RAMBUS memory */ 340 return; 341 } 342 switch (s->sm_type) { 343 case SPDMEM_MEMTYPE_EDO: 344 case SPDMEM_MEMTYPE_FPM: 345 decode_edofpm(node, self, s); 346 break; 347 case SPDMEM_MEMTYPE_ROM: 348 decode_rom(node, self, s); 349 break; 350 case SPDMEM_MEMTYPE_SDRAM: 351 decode_sdram(node, self, s, spd_len); 352 break; 353 case SPDMEM_MEMTYPE_DDRSDRAM: 354 decode_ddr(node, self, s); 355 break; 356 case SPDMEM_MEMTYPE_DDR2SDRAM: 357 decode_ddr2(node, self, s); 358 break; 359 case SPDMEM_MEMTYPE_DDR3SDRAM: 360 decode_ddr3(node, self, s); 361 break; 362 case SPDMEM_MEMTYPE_FBDIMM: 363 case SPDMEM_MEMTYPE_FBDIMM_PROBE: 364 decode_fbdimm(node, self, s); 365 break; 366 } 367 368 /* Dump SPD */ 369 for (i = 0; i < spd_len; i += 16) { 370 unsigned int j, k; 371 aprint_debug_dev(self, "0x%02x:", i); 372 k = (spd_len > (i + 16)) ? i + 16 : spd_len; 373 for (j = i; j < k; j++) 374 aprint_debug(" %02x", ((uint8_t *)s)[j]); 375 aprint_debug("\n"); 376 } 377 } 378 379 int 380 spdmem_common_detach(struct spdmem_softc *sc, device_t self) 381 { 382 sysctl_teardown(&sc->sc_sysctl_log); 383 384 return 0; 385 } 386 387 static void 388 decode_size_speed(device_t self, const struct sysctlnode *node, 389 int dimm_size, int cycle_time, int d_clk, int bits, 390 bool round, const char *ddr_type_string, int speed) 391 { 392 int p_clk; 393 struct spdmem_softc *sc = device_private(self); 394 395 if (dimm_size < 1024) 396 aprint_normal("%dMB", dimm_size); 397 else 398 aprint_normal("%dGB", dimm_size / 1024); 399 if (node != NULL) 400 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 401 CTLFLAG_IMMEDIATE, 402 CTLTYPE_INT, "size", 403 SYSCTL_DESCR("module size in MB"), NULL, 404 dimm_size, NULL, 0, 405 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 406 407 if (cycle_time == 0) { 408 aprint_normal("\n"); 409 return; 410 } 411 412 /* 413 * Calculate p_clk first, since for DDR3 we need maximum significance. 414 * DDR3 rating is not rounded to a multiple of 100. This results in 415 * cycle_time of 1.5ns displayed as PC3-10666. 416 * 417 * For SDRAM, the speed is provided by the caller so we use it. 418 */ 419 d_clk *= 1000 * 1000; 420 if (speed) 421 p_clk = speed; 422 else 423 p_clk = (d_clk * bits) / 8 / cycle_time; 424 d_clk = ((d_clk + cycle_time / 2) ) / cycle_time; 425 if (round) { 426 if ((p_clk % 100) >= 50) 427 p_clk += 50; 428 p_clk -= p_clk % 100; 429 } 430 aprint_normal(", %dMHz (%s-%d)\n", 431 d_clk, ddr_type_string, p_clk); 432 if (node != NULL) 433 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 434 CTLFLAG_IMMEDIATE, 435 CTLTYPE_INT, "speed", 436 SYSCTL_DESCR("memory speed in MHz"), 437 NULL, d_clk, NULL, 0, 438 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 439 } 440 441 static void 442 decode_voltage_refresh(device_t self, struct spdmem *s) 443 { 444 const char *voltage, *refresh; 445 446 if (s->sm_voltage < __arraycount(spdmem_voltage_types)) 447 voltage = spdmem_voltage_types[s->sm_voltage]; 448 else 449 voltage = "unknown"; 450 451 if (s->sm_refresh < __arraycount(spdmem_refresh_types)) 452 refresh = spdmem_refresh_types[s->sm_refresh]; 453 else 454 refresh = "unknown"; 455 456 aprint_verbose_dev(self, "voltage %s, refresh time %s%s\n", 457 voltage, refresh, 458 s->sm_selfrefresh?" (self-refreshing)":""); 459 } 460 461 static void 462 decode_edofpm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 463 aprint_naive("\n"); 464 aprint_normal("\n"); 465 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 466 467 aprint_normal("\n"); 468 aprint_verbose_dev(self, 469 "%d rows, %d cols, %d banks, %dns tRAC, %dns tCAC\n", 470 s->sm_fpm.fpm_rows, s->sm_fpm.fpm_cols, s->sm_fpm.fpm_banks, 471 s->sm_fpm.fpm_tRAC, s->sm_fpm.fpm_tCAC); 472 } 473 474 static void 475 decode_rom(const struct sysctlnode *node, device_t self, struct spdmem *s) { 476 aprint_naive("\n"); 477 aprint_normal("\n"); 478 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 479 480 aprint_normal("\n"); 481 aprint_verbose_dev(self, "%d rows, %d cols, %d banks\n", 482 s->sm_rom.rom_rows, s->sm_rom.rom_cols, s->sm_rom.rom_banks); 483 } 484 485 static void 486 decode_sdram(const struct sysctlnode *node, device_t self, struct spdmem *s, 487 int spd_len) { 488 int dimm_size, cycle_time, bits, tAA, i, speed, freq; 489 490 aprint_naive("\n"); 491 aprint_normal("\n"); 492 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 493 494 aprint_normal("%s, %s, ", 495 (s->sm_sdr.sdr_mod_attrs & SPDMEM_SDR_MASK_REG)? 496 " (registered)":"", 497 (s->sm_config < __arraycount(spdmem_parity_types))? 498 spdmem_parity_types[s->sm_config]:"invalid parity"); 499 500 dimm_size = 1 << (s->sm_sdr.sdr_rows + s->sm_sdr.sdr_cols - 17); 501 dimm_size *= s->sm_sdr.sdr_banks * s->sm_sdr.sdr_banks_per_chip; 502 503 cycle_time = s->sm_sdr.sdr_cycle_whole * 1000 + 504 s->sm_sdr.sdr_cycle_tenths * 100; 505 bits = le16toh(s->sm_sdr.sdr_datawidth); 506 if (s->sm_config == 1 || s->sm_config == 2) 507 bits -= 8; 508 509 /* Calculate speed here - from OpenBSD */ 510 if (spd_len >= 128) 511 freq = ((uint8_t *)s)[126]; 512 else 513 freq = 0; 514 switch (freq) { 515 /* 516 * Must check cycle time since some PC-133 DIMMs 517 * actually report PC-100 518 */ 519 case 100: 520 case 133: 521 if (cycle_time < 8000) 522 speed = 133; 523 else 524 speed = 100; 525 break; 526 case 0x66: /* Legacy DIMMs use _hex_ 66! */ 527 default: 528 speed = 66; 529 } 530 decode_size_speed(self, node, dimm_size, cycle_time, 1, bits, FALSE, 531 "PC", speed); 532 533 aprint_verbose_dev(self, 534 "%d rows, %d cols, %d banks, %d banks/chip, %d.%dns cycle time\n", 535 s->sm_sdr.sdr_rows, s->sm_sdr.sdr_cols, s->sm_sdr.sdr_banks, 536 s->sm_sdr.sdr_banks_per_chip, cycle_time/1000, 537 (cycle_time % 1000) / 100); 538 539 tAA = 0; 540 for (i = 0; i < 8; i++) 541 if (s->sm_sdr.sdr_tCAS & (1 << i)) 542 tAA = i; 543 tAA++; 544 aprint_verbose_dev(self, LATENCY, tAA, s->sm_sdr.sdr_tRCD, 545 s->sm_sdr.sdr_tRP, s->sm_sdr.sdr_tRAS); 546 547 decode_voltage_refresh(self, s); 548 } 549 550 static void 551 decode_ddr(const struct sysctlnode *node, device_t self, struct spdmem *s) { 552 int dimm_size, cycle_time, bits, tAA, i; 553 554 aprint_naive("\n"); 555 aprint_normal("\n"); 556 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 557 558 aprint_normal("%s, %s, ", 559 (s->sm_ddr.ddr_mod_attrs & SPDMEM_DDR_MASK_REG)? 560 " (registered)":"", 561 (s->sm_config < __arraycount(spdmem_parity_types))? 562 spdmem_parity_types[s->sm_config]:"invalid parity"); 563 564 dimm_size = 1 << (s->sm_ddr.ddr_rows + s->sm_ddr.ddr_cols - 17); 565 dimm_size *= s->sm_ddr.ddr_ranks * s->sm_ddr.ddr_banks_per_chip; 566 567 cycle_time = s->sm_ddr.ddr_cycle_whole * 1000 + 568 spdmem_cycle_frac[s->sm_ddr.ddr_cycle_tenths]; 569 bits = le16toh(s->sm_ddr.ddr_datawidth); 570 if (s->sm_config == 1 || s->sm_config == 2) 571 bits -= 8; 572 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 573 "PC", 0); 574 575 aprint_verbose_dev(self, 576 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%dns cycle time\n", 577 s->sm_ddr.ddr_rows, s->sm_ddr.ddr_cols, s->sm_ddr.ddr_ranks, 578 s->sm_ddr.ddr_banks_per_chip, cycle_time/1000, 579 (cycle_time % 1000 + 50) / 100); 580 581 tAA = 0; 582 for (i = 2; i < 8; i++) 583 if (s->sm_ddr.ddr_tCAS & (1 << i)) 584 tAA = i; 585 tAA /= 2; 586 587 #define __DDR_ROUND(scale, field) \ 588 ((scale * s->sm_ddr.field + cycle_time - 1) / cycle_time) 589 590 aprint_verbose_dev(self, LATENCY, tAA, __DDR_ROUND(250, ddr_tRCD), 591 __DDR_ROUND(250, ddr_tRP), __DDR_ROUND(1000, ddr_tRAS)); 592 593 #undef __DDR_ROUND 594 595 decode_voltage_refresh(self, s); 596 } 597 598 static void 599 decode_ddr2(const struct sysctlnode *node, device_t self, struct spdmem *s) { 600 int dimm_size, cycle_time, bits, tAA, i; 601 602 aprint_naive("\n"); 603 aprint_normal("\n"); 604 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 605 606 aprint_normal("%s, %s, ", 607 (s->sm_ddr2.ddr2_mod_attrs & SPDMEM_DDR2_MASK_REG)? 608 " (registered)":"", 609 (s->sm_config < __arraycount(spdmem_parity_types))? 610 spdmem_parity_types[s->sm_config]:"invalid parity"); 611 612 dimm_size = 1 << (s->sm_ddr2.ddr2_rows + s->sm_ddr2.ddr2_cols - 17); 613 dimm_size *= (s->sm_ddr2.ddr2_ranks + 1) * 614 s->sm_ddr2.ddr2_banks_per_chip; 615 616 cycle_time = s->sm_ddr2.ddr2_cycle_whole * 1000 + 617 spdmem_cycle_frac[s->sm_ddr2.ddr2_cycle_frac]; 618 bits = s->sm_ddr2.ddr2_datawidth; 619 if ((s->sm_config & 0x03) != 0) 620 bits -= 8; 621 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 622 "PC2", 0); 623 624 aprint_verbose_dev(self, 625 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%02dns cycle time\n", 626 s->sm_ddr2.ddr2_rows, s->sm_ddr2.ddr2_cols, 627 s->sm_ddr2.ddr2_ranks + 1, s->sm_ddr2.ddr2_banks_per_chip, 628 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 629 630 tAA = 0; 631 for (i = 2; i < 8; i++) 632 if (s->sm_ddr2.ddr2_tCAS & (1 << i)) 633 tAA = i; 634 635 #define __DDR2_ROUND(scale, field) \ 636 ((scale * s->sm_ddr2.field + cycle_time - 1) / cycle_time) 637 638 aprint_verbose_dev(self, LATENCY, tAA, __DDR2_ROUND(250, ddr2_tRCD), 639 __DDR2_ROUND(250, ddr2_tRP), __DDR2_ROUND(1000, ddr2_tRAS)); 640 641 #undef __DDR_ROUND 642 643 decode_voltage_refresh(self, s); 644 } 645 646 static void 647 decode_ddr3(const struct sysctlnode *node, device_t self, struct spdmem *s) { 648 int dimm_size, cycle_time, bits; 649 650 aprint_naive("\n"); 651 aprint_normal(": %18s\n", s->sm_ddr3.ddr3_part); 652 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 653 654 if (s->sm_ddr3.ddr3_mod_type == 655 SPDMEM_DDR3_TYPE_MINI_RDIMM || 656 s->sm_ddr3.ddr3_mod_type == SPDMEM_DDR3_TYPE_RDIMM) 657 aprint_normal(" (registered)"); 658 aprint_normal(", %sECC, %stemp-sensor, ", 659 (s->sm_ddr3.ddr3_hasECC)?"":"no ", 660 (s->sm_ddr3.ddr3_has_therm_sensor)?"":"no "); 661 662 /* 663 * DDR3 size specification is quite different from others 664 * 665 * Module capacity is defined as 666 * Chip_Capacity_in_bits / 8bits-per-byte * 667 * external_bus_width / internal_bus_width 668 * We further divide by 2**20 to get our answer in MB 669 */ 670 dimm_size = (s->sm_ddr3.ddr3_chipsize + 28 - 20) - 3 + 671 (s->sm_ddr3.ddr3_datawidth + 3) - 672 (s->sm_ddr3.ddr3_chipwidth + 2); 673 dimm_size = (1 << dimm_size) * (s->sm_ddr3.ddr3_physbanks + 1); 674 675 cycle_time = (1000 * s->sm_ddr3.ddr3_mtb_dividend + 676 (s->sm_ddr3.ddr3_mtb_divisor / 2)) / 677 s->sm_ddr3.ddr3_mtb_divisor; 678 cycle_time *= s->sm_ddr3.ddr3_tCKmin; 679 bits = 1 << (s->sm_ddr3.ddr3_datawidth + 3); 680 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, FALSE, 681 "PC3", 0); 682 683 aprint_verbose_dev(self, 684 "%d rows, %d cols, %d log. banks, %d phys. banks, " 685 "%d.%03dns cycle time\n", 686 s->sm_ddr3.ddr3_rows + 9, s->sm_ddr3.ddr3_cols + 12, 687 1 << (s->sm_ddr3.ddr3_logbanks + 3), 688 s->sm_ddr3.ddr3_physbanks + 1, 689 cycle_time/1000, cycle_time % 1000); 690 691 #define __DDR3_CYCLES(field) (s->sm_ddr3.field / s->sm_ddr3.ddr3_tCKmin) 692 693 aprint_verbose_dev(self, LATENCY, __DDR3_CYCLES(ddr3_tAAmin), 694 __DDR3_CYCLES(ddr3_tRCDmin), __DDR3_CYCLES(ddr3_tRPmin), 695 (s->sm_ddr3.ddr3_tRAS_msb * 256 + s->sm_ddr3.ddr3_tRAS_lsb) / 696 s->sm_ddr3.ddr3_tCKmin); 697 698 #undef __DDR3_CYCLES 699 } 700 701 static void 702 decode_fbdimm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 703 int dimm_size, cycle_time, bits; 704 705 aprint_naive("\n"); 706 aprint_normal("\n"); 707 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 708 709 /* 710 * FB-DIMM module size calculation is very much like DDR3 711 */ 712 dimm_size = s->sm_fbd.fbdimm_rows + 12 + 713 s->sm_fbd.fbdimm_cols + 9 - 20 - 3; 714 dimm_size = (1 << dimm_size) * (1 << (s->sm_fbd.fbdimm_banks + 2)); 715 716 cycle_time = (1000 * s->sm_fbd.fbdimm_mtb_dividend + 717 (s->sm_fbd.fbdimm_mtb_divisor / 2)) / 718 s->sm_fbd.fbdimm_mtb_divisor; 719 bits = 1 << (s->sm_fbd.fbdimm_dev_width + 2); 720 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 721 "PC2", 0); 722 723 aprint_verbose_dev(self, 724 "%d rows, %d cols, %d banks, %d.%02dns cycle time\n", 725 s->sm_fbd.fbdimm_rows, s->sm_fbd.fbdimm_cols, 726 1 << (s->sm_fbd.fbdimm_banks + 2), 727 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 728 729 #define __FBDIMM_CYCLES(field) (s->sm_fbd.field / s->sm_fbd.fbdimm_tCKmin) 730 731 aprint_verbose_dev(self, LATENCY, __FBDIMM_CYCLES(fbdimm_tAAmin), 732 __FBDIMM_CYCLES(fbdimm_tRCDmin), __FBDIMM_CYCLES(fbdimm_tRPmin), 733 (s->sm_fbd.fbdimm_tRAS_msb * 256 + 734 s->sm_fbd.fbdimm_tRAS_lsb) / 735 s->sm_fbd.fbdimm_tCKmin); 736 737 #undef __FBDIMM_CYCLES 738 739 decode_voltage_refresh(self, s); 740 } 741
Indexes created Fri Oct 03 02:09:57 GMT 2025