spdmem.c revision 1.9
1 /* $NetBSD: spdmem.c,v 1.9 2014/02/25 18:30:09 pooka Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Nicolas Joly 5 * Copyright (c) 2007 Paul Goyette 6 * Copyright (c) 2007 Tobias Nygren 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Serial Presence Detect (SPD) memory identification 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.9 2014/02/25 18:30:09 pooka Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/device.h> 42 #include <sys/endian.h> 43 #include <sys/sysctl.h> 44 #include <machine/bswap.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/ic/spdmemreg.h> 48 #include <dev/ic/spdmemvar.h> 49 50 SYSCTL_SETUP_PROTO(sysctl_spdmem_setup); 51 52 /* Routines for decoding spd data */ 53 static void decode_edofpm(const struct sysctlnode *, device_t, struct spdmem *); 54 static void decode_rom(const struct sysctlnode *, device_t, struct spdmem *); 55 static void decode_sdram(const struct sysctlnode *, device_t, struct spdmem *, 56 int); 57 static void decode_ddr(const struct sysctlnode *, device_t, struct spdmem *); 58 static void decode_ddr2(const struct sysctlnode *, device_t, struct spdmem *); 59 static void decode_ddr3(const struct sysctlnode *, device_t, struct spdmem *); 60 static void decode_fbdimm(const struct sysctlnode *, device_t, struct spdmem *); 61 62 static void decode_size_speed(device_t, const struct sysctlnode *, 63 int, int, int, int, bool, const char *, int); 64 static void decode_voltage_refresh(device_t, struct spdmem *); 65 66 #define IS_RAMBUS_TYPE (s->sm_len < 4) 67 68 static const char* spdmem_basic_types[] = { 69 "unknown", 70 "FPM", 71 "EDO", 72 "Pipelined Nibble", 73 "SDRAM", 74 "ROM", 75 "DDR SGRAM", 76 "DDR SDRAM", 77 "DDR2 SDRAM", 78 "DDR2 SDRAM FB", 79 "DDR2 SDRAM FB Probe", 80 "DDR3 SDRAM" 81 }; 82 83 static const char* spdmem_superset_types[] = { 84 "unknown", 85 "ESDRAM", 86 "DDR ESDRAM", 87 "PEM EDO", 88 "PEM SDRAM" 89 }; 90 91 static const char* spdmem_voltage_types[] = { 92 "TTL (5V tolerant)", 93 "LvTTL (not 5V tolerant)", 94 "HSTL 1.5V", 95 "SSTL 3.3V", 96 "SSTL 2.5V", 97 "SSTL 1.8V" 98 }; 99 100 static const char* spdmem_refresh_types[] = { 101 "15.625us", 102 "3.9us", 103 "7.8us", 104 "31.3us", 105 "62.5us", 106 "125us" 107 }; 108 109 static const char* spdmem_parity_types[] = { 110 "no parity or ECC", 111 "data parity", 112 "data ECC", 113 "data parity and ECC", 114 "cmd/addr parity", 115 "cmd/addr/data parity", 116 "cmd/addr parity, data ECC", 117 "cmd/addr/data parity, data ECC" 118 }; 119 120 /* Cycle time fractional values (units of .001 ns) for DDR2 SDRAM */ 121 static const uint16_t spdmem_cycle_frac[] = { 122 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 123 250, 333, 667, 750, 999, 999 124 }; 125 126 /* Format string for timing info */ 127 #define LATENCY "tAA-tRCD-tRP-tRAS: %d-%d-%d-%d\n" 128 129 /* CRC functions used for certain memory types */ 130 131 static uint16_t spdcrc16 (struct spdmem_softc *sc, int count) 132 { 133 uint16_t crc; 134 int i, j; 135 uint8_t val; 136 crc = 0; 137 for (j = 0; j <= count; j++) { 138 val = (sc->sc_read)(sc, j); 139 crc = crc ^ val << 8; 140 for (i = 0; i < 8; ++i) 141 if (crc & 0x8000) 142 crc = crc << 1 ^ 0x1021; 143 else 144 crc = crc << 1; 145 } 146 return (crc & 0xFFFF); 147 } 148 149 int 150 spdmem_common_probe(struct spdmem_softc *sc) 151 { 152 int cksum = 0; 153 uint8_t i, val, spd_type; 154 int spd_len, spd_crc_cover; 155 uint16_t crc_calc, crc_spd; 156 157 spd_type = (sc->sc_read)(sc, 2); 158 159 /* For older memory types, validate the checksum over 1st 63 bytes */ 160 if (spd_type <= SPDMEM_MEMTYPE_DDR2SDRAM) { 161 for (i = 0; i < 63; i++) 162 cksum += (sc->sc_read)(sc, i); 163 164 val = (sc->sc_read)(sc, 63); 165 166 if (cksum == 0 || (cksum & 0xff) != val) { 167 aprint_debug("spd checksum failed, calc = 0x%02x, " 168 "spd = 0x%02x\n", cksum, val); 169 return 0; 170 } else 171 return 1; 172 } 173 174 /* For DDR3 and FBDIMM, verify the CRC */ 175 else if (spd_type <= SPDMEM_MEMTYPE_DDR3SDRAM) { 176 spd_len = (sc->sc_read)(sc, 0); 177 if (spd_len & SPDMEM_SPDCRC_116) 178 spd_crc_cover = 116; 179 else 180 spd_crc_cover = 125; 181 switch (spd_len & SPDMEM_SPDLEN_MASK) { 182 case SPDMEM_SPDLEN_128: 183 spd_len = 128; 184 break; 185 case SPDMEM_SPDLEN_176: 186 spd_len = 176; 187 break; 188 case SPDMEM_SPDLEN_256: 189 spd_len = 256; 190 break; 191 default: 192 return 0; 193 } 194 if (spd_crc_cover > spd_len) 195 return 0; 196 crc_calc = spdcrc16(sc, spd_crc_cover); 197 crc_spd = (sc->sc_read)(sc, 127) << 8; 198 crc_spd |= (sc->sc_read)(sc, 126); 199 if (crc_calc != crc_spd) { 200 aprint_debug("crc16 failed, covers %d bytes, " 201 "calc = 0x%04x, spd = 0x%04x\n", 202 spd_crc_cover, crc_calc, crc_spd); 203 return 0; 204 } 205 return 1; 206 } 207 208 /* For unrecognized memory types, don't match at all */ 209 return 0; 210 } 211 212 void 213 spdmem_common_attach(struct spdmem_softc *sc, device_t self) 214 { 215 struct spdmem *s = &(sc->sc_spd_data); 216 const char *type; 217 const char *rambus_rev = "Reserved"; 218 int dimm_size; 219 unsigned int i, spd_len, spd_size; 220 const struct sysctlnode *node = NULL; 221 222 /* 223 * FBDIMM and DDR3 (and probably all newer) have a different 224 * encoding of the SPD EEPROM used/total sizes 225 */ 226 s->sm_len = (sc->sc_read)(sc, 0); 227 s->sm_size = (sc->sc_read)(sc, 1); 228 s->sm_type = (sc->sc_read)(sc, 2); 229 230 if (s->sm_type >= SPDMEM_MEMTYPE_FBDIMM) { 231 spd_size = 64 << (s->sm_len & SPDMEM_SPDSIZE_MASK); 232 switch (s->sm_len & SPDMEM_SPDLEN_MASK) { 233 case SPDMEM_SPDLEN_128: 234 spd_len = 128; 235 break; 236 case SPDMEM_SPDLEN_176: 237 spd_len = 176; 238 break; 239 case SPDMEM_SPDLEN_256: 240 spd_len = 256; 241 break; 242 default: 243 spd_len = 64; 244 break; 245 } 246 } else { 247 spd_size = 1 << s->sm_size; 248 spd_len = s->sm_len; 249 if (spd_len < 64) 250 spd_len = 64; 251 } 252 if (spd_len > spd_size) 253 spd_len = spd_size; 254 if (spd_len > sizeof(struct spdmem)) 255 spd_len = sizeof(struct spdmem); 256 for (i = 3; i < spd_len; i++) 257 ((uint8_t *)s)[i] = (sc->sc_read)(sc, i); 258 259 /* 260 * Setup our sysctl subtree, hw.spdmemN 261 */ 262 sc->sc_sysctl_log = NULL; 263 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, 264 0, CTLTYPE_NODE, 265 device_xname(self), NULL, NULL, 0, NULL, 0, 266 CTL_HW, CTL_CREATE, CTL_EOL); 267 if (node != NULL && spd_len != 0) 268 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 269 0, 270 CTLTYPE_STRUCT, "spd_data", 271 SYSCTL_DESCR("raw spd data"), NULL, 272 0, s, spd_len, 273 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 274 275 /* 276 * Decode and print key SPD contents 277 */ 278 if (IS_RAMBUS_TYPE) { 279 if (s->sm_type == SPDMEM_MEMTYPE_RAMBUS) 280 type = "Rambus"; 281 else if (s->sm_type == SPDMEM_MEMTYPE_DIRECTRAMBUS) 282 type = "Direct Rambus"; 283 else 284 type = "Rambus (unknown)"; 285 286 switch (s->sm_len) { 287 case 0: 288 rambus_rev = "Invalid"; 289 break; 290 case 1: 291 rambus_rev = "0.7"; 292 break; 293 case 2: 294 rambus_rev = "1.0"; 295 break; 296 default: 297 rambus_rev = "Reserved"; 298 break; 299 } 300 } else { 301 if (s->sm_type < __arraycount(spdmem_basic_types)) 302 type = spdmem_basic_types[s->sm_type]; 303 else 304 type = "unknown memory type"; 305 306 if (s->sm_type == SPDMEM_MEMTYPE_EDO && 307 s->sm_fpm.fpm_superset == SPDMEM_SUPERSET_EDO_PEM) 308 type = spdmem_superset_types[SPDMEM_SUPERSET_EDO_PEM]; 309 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 310 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_SDRAM_PEM) 311 type = spdmem_superset_types[SPDMEM_SUPERSET_SDRAM_PEM]; 312 if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM && 313 s->sm_ddr.ddr_superset == SPDMEM_SUPERSET_DDR_ESDRAM) 314 type = 315 spdmem_superset_types[SPDMEM_SUPERSET_DDR_ESDRAM]; 316 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 317 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_ESDRAM) { 318 type = spdmem_superset_types[SPDMEM_SUPERSET_ESDRAM]; 319 } 320 } 321 322 strlcpy(sc->sc_type, type, SPDMEM_TYPE_MAXLEN); 323 if (node != NULL) 324 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 325 0, 326 CTLTYPE_STRING, "mem_type", 327 SYSCTL_DESCR("memory module type"), NULL, 328 0, sc->sc_type, 0, 329 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 330 331 if (IS_RAMBUS_TYPE) { 332 aprint_naive("\n"); 333 aprint_normal("\n"); 334 aprint_normal_dev(self, "%s, SPD Revision %s", type, rambus_rev); 335 dimm_size = 1 << (s->sm_rdr.rdr_rows + s->sm_rdr.rdr_cols - 13); 336 if (dimm_size >= 1024) 337 aprint_normal(", %dGB\n", dimm_size / 1024); 338 else 339 aprint_normal(", %dMB\n", dimm_size); 340 341 /* No further decode for RAMBUS memory */ 342 return; 343 } 344 switch (s->sm_type) { 345 case SPDMEM_MEMTYPE_EDO: 346 case SPDMEM_MEMTYPE_FPM: 347 decode_edofpm(node, self, s); 348 break; 349 case SPDMEM_MEMTYPE_ROM: 350 decode_rom(node, self, s); 351 break; 352 case SPDMEM_MEMTYPE_SDRAM: 353 decode_sdram(node, self, s, spd_len); 354 break; 355 case SPDMEM_MEMTYPE_DDRSDRAM: 356 decode_ddr(node, self, s); 357 break; 358 case SPDMEM_MEMTYPE_DDR2SDRAM: 359 decode_ddr2(node, self, s); 360 break; 361 case SPDMEM_MEMTYPE_DDR3SDRAM: 362 decode_ddr3(node, self, s); 363 break; 364 case SPDMEM_MEMTYPE_FBDIMM: 365 case SPDMEM_MEMTYPE_FBDIMM_PROBE: 366 decode_fbdimm(node, self, s); 367 break; 368 } 369 370 /* Dump SPD */ 371 for (i = 0; i < spd_len; i += 16) { 372 unsigned int j, k; 373 aprint_debug_dev(self, "0x%02x:", i); 374 k = (spd_len > (i + 16)) ? i + 16 : spd_len; 375 for (j = i; j < k; j++) 376 aprint_debug(" %02x", ((uint8_t *)s)[j]); 377 aprint_debug("\n"); 378 } 379 } 380 381 int 382 spdmem_common_detach(struct spdmem_softc *sc, device_t self) 383 { 384 sysctl_teardown(&sc->sc_sysctl_log); 385 386 return 0; 387 } 388 389 static void 390 decode_size_speed(device_t self, const struct sysctlnode *node, 391 int dimm_size, int cycle_time, int d_clk, int bits, 392 bool round, const char *ddr_type_string, int speed) 393 { 394 int p_clk; 395 struct spdmem_softc *sc = device_private(self); 396 397 if (dimm_size < 1024) 398 aprint_normal("%dMB", dimm_size); 399 else 400 aprint_normal("%dGB", dimm_size / 1024); 401 if (node != NULL) 402 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 403 CTLFLAG_IMMEDIATE, 404 CTLTYPE_INT, "size", 405 SYSCTL_DESCR("module size in MB"), NULL, 406 dimm_size, NULL, 0, 407 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 408 409 if (cycle_time == 0) { 410 aprint_normal("\n"); 411 return; 412 } 413 414 /* 415 * Calculate p_clk first, since for DDR3 we need maximum significance. 416 * DDR3 rating is not rounded to a multiple of 100. This results in 417 * cycle_time of 1.5ns displayed as PC3-10666. 418 * 419 * For SDRAM, the speed is provided by the caller so we use it. 420 */ 421 d_clk *= 1000 * 1000; 422 if (speed) 423 p_clk = speed; 424 else 425 p_clk = (d_clk * bits) / 8 / cycle_time; 426 d_clk = ((d_clk + cycle_time / 2) ) / cycle_time; 427 if (round) { 428 if ((p_clk % 100) >= 50) 429 p_clk += 50; 430 p_clk -= p_clk % 100; 431 } 432 aprint_normal(", %dMHz (%s-%d)\n", 433 d_clk, ddr_type_string, p_clk); 434 if (node != NULL) 435 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 436 CTLFLAG_IMMEDIATE, 437 CTLTYPE_INT, "speed", 438 SYSCTL_DESCR("memory speed in MHz"), 439 NULL, d_clk, NULL, 0, 440 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 441 } 442 443 static void 444 decode_voltage_refresh(device_t self, struct spdmem *s) 445 { 446 const char *voltage, *refresh; 447 448 if (s->sm_voltage < __arraycount(spdmem_voltage_types)) 449 voltage = spdmem_voltage_types[s->sm_voltage]; 450 else 451 voltage = "unknown"; 452 453 if (s->sm_refresh < __arraycount(spdmem_refresh_types)) 454 refresh = spdmem_refresh_types[s->sm_refresh]; 455 else 456 refresh = "unknown"; 457 458 aprint_verbose_dev(self, "voltage %s, refresh time %s%s\n", 459 voltage, refresh, 460 s->sm_selfrefresh?" (self-refreshing)":""); 461 } 462 463 static void 464 decode_edofpm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 465 aprint_naive("\n"); 466 aprint_normal("\n"); 467 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 468 469 aprint_normal("\n"); 470 aprint_verbose_dev(self, 471 "%d rows, %d cols, %d banks, %dns tRAC, %dns tCAC\n", 472 s->sm_fpm.fpm_rows, s->sm_fpm.fpm_cols, s->sm_fpm.fpm_banks, 473 s->sm_fpm.fpm_tRAC, s->sm_fpm.fpm_tCAC); 474 } 475 476 static void 477 decode_rom(const struct sysctlnode *node, device_t self, struct spdmem *s) { 478 aprint_naive("\n"); 479 aprint_normal("\n"); 480 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 481 482 aprint_normal("\n"); 483 aprint_verbose_dev(self, "%d rows, %d cols, %d banks\n", 484 s->sm_rom.rom_rows, s->sm_rom.rom_cols, s->sm_rom.rom_banks); 485 } 486 487 static void 488 decode_sdram(const struct sysctlnode *node, device_t self, struct spdmem *s, 489 int spd_len) { 490 int dimm_size, cycle_time, bits, tAA, i, speed, freq; 491 492 aprint_naive("\n"); 493 aprint_normal("\n"); 494 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 495 496 aprint_normal("%s, %s, ", 497 (s->sm_sdr.sdr_mod_attrs & SPDMEM_SDR_MASK_REG)? 498 " (registered)":"", 499 (s->sm_config < __arraycount(spdmem_parity_types))? 500 spdmem_parity_types[s->sm_config]:"invalid parity"); 501 502 dimm_size = 1 << (s->sm_sdr.sdr_rows + s->sm_sdr.sdr_cols - 17); 503 dimm_size *= s->sm_sdr.sdr_banks * s->sm_sdr.sdr_banks_per_chip; 504 505 cycle_time = s->sm_sdr.sdr_cycle_whole * 1000 + 506 s->sm_sdr.sdr_cycle_tenths * 100; 507 bits = le16toh(s->sm_sdr.sdr_datawidth); 508 if (s->sm_config == 1 || s->sm_config == 2) 509 bits -= 8; 510 511 /* Calculate speed here - from OpenBSD */ 512 if (spd_len >= 128) 513 freq = ((uint8_t *)s)[126]; 514 else 515 freq = 0; 516 switch (freq) { 517 /* 518 * Must check cycle time since some PC-133 DIMMs 519 * actually report PC-100 520 */ 521 case 100: 522 case 133: 523 if (cycle_time < 8000) 524 speed = 133; 525 else 526 speed = 100; 527 break; 528 case 0x66: /* Legacy DIMMs use _hex_ 66! */ 529 default: 530 speed = 66; 531 } 532 decode_size_speed(self, node, dimm_size, cycle_time, 1, bits, FALSE, 533 "PC", speed); 534 535 aprint_verbose_dev(self, 536 "%d rows, %d cols, %d banks, %d banks/chip, %d.%dns cycle time\n", 537 s->sm_sdr.sdr_rows, s->sm_sdr.sdr_cols, s->sm_sdr.sdr_banks, 538 s->sm_sdr.sdr_banks_per_chip, cycle_time/1000, 539 (cycle_time % 1000) / 100); 540 541 tAA = 0; 542 for (i = 0; i < 8; i++) 543 if (s->sm_sdr.sdr_tCAS & (1 << i)) 544 tAA = i; 545 tAA++; 546 aprint_verbose_dev(self, LATENCY, tAA, s->sm_sdr.sdr_tRCD, 547 s->sm_sdr.sdr_tRP, s->sm_sdr.sdr_tRAS); 548 549 decode_voltage_refresh(self, s); 550 } 551 552 static void 553 decode_ddr(const struct sysctlnode *node, device_t self, struct spdmem *s) { 554 int dimm_size, cycle_time, bits, tAA, i; 555 556 aprint_naive("\n"); 557 aprint_normal("\n"); 558 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 559 560 aprint_normal("%s, %s, ", 561 (s->sm_ddr.ddr_mod_attrs & SPDMEM_DDR_MASK_REG)? 562 " (registered)":"", 563 (s->sm_config < __arraycount(spdmem_parity_types))? 564 spdmem_parity_types[s->sm_config]:"invalid parity"); 565 566 dimm_size = 1 << (s->sm_ddr.ddr_rows + s->sm_ddr.ddr_cols - 17); 567 dimm_size *= s->sm_ddr.ddr_ranks * s->sm_ddr.ddr_banks_per_chip; 568 569 cycle_time = s->sm_ddr.ddr_cycle_whole * 1000 + 570 spdmem_cycle_frac[s->sm_ddr.ddr_cycle_tenths]; 571 bits = le16toh(s->sm_ddr.ddr_datawidth); 572 if (s->sm_config == 1 || s->sm_config == 2) 573 bits -= 8; 574 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 575 "PC", 0); 576 577 aprint_verbose_dev(self, 578 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%dns cycle time\n", 579 s->sm_ddr.ddr_rows, s->sm_ddr.ddr_cols, s->sm_ddr.ddr_ranks, 580 s->sm_ddr.ddr_banks_per_chip, cycle_time/1000, 581 (cycle_time % 1000 + 50) / 100); 582 583 tAA = 0; 584 for (i = 2; i < 8; i++) 585 if (s->sm_ddr.ddr_tCAS & (1 << i)) 586 tAA = i; 587 tAA /= 2; 588 589 #define __DDR_ROUND(scale, field) \ 590 ((scale * s->sm_ddr.field + cycle_time - 1) / cycle_time) 591 592 aprint_verbose_dev(self, LATENCY, tAA, __DDR_ROUND(250, ddr_tRCD), 593 __DDR_ROUND(250, ddr_tRP), __DDR_ROUND(1000, ddr_tRAS)); 594 595 #undef __DDR_ROUND 596 597 decode_voltage_refresh(self, s); 598 } 599 600 static void 601 decode_ddr2(const struct sysctlnode *node, device_t self, struct spdmem *s) { 602 int dimm_size, cycle_time, bits, tAA, i; 603 604 aprint_naive("\n"); 605 aprint_normal("\n"); 606 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 607 608 aprint_normal("%s, %s, ", 609 (s->sm_ddr2.ddr2_mod_attrs & SPDMEM_DDR2_MASK_REG)? 610 " (registered)":"", 611 (s->sm_config < __arraycount(spdmem_parity_types))? 612 spdmem_parity_types[s->sm_config]:"invalid parity"); 613 614 dimm_size = 1 << (s->sm_ddr2.ddr2_rows + s->sm_ddr2.ddr2_cols - 17); 615 dimm_size *= (s->sm_ddr2.ddr2_ranks + 1) * 616 s->sm_ddr2.ddr2_banks_per_chip; 617 618 cycle_time = s->sm_ddr2.ddr2_cycle_whole * 1000 + 619 spdmem_cycle_frac[s->sm_ddr2.ddr2_cycle_frac]; 620 bits = s->sm_ddr2.ddr2_datawidth; 621 if ((s->sm_config & 0x03) != 0) 622 bits -= 8; 623 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 624 "PC2", 0); 625 626 aprint_verbose_dev(self, 627 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%02dns cycle time\n", 628 s->sm_ddr2.ddr2_rows, s->sm_ddr2.ddr2_cols, 629 s->sm_ddr2.ddr2_ranks + 1, s->sm_ddr2.ddr2_banks_per_chip, 630 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 631 632 tAA = 0; 633 for (i = 2; i < 8; i++) 634 if (s->sm_ddr2.ddr2_tCAS & (1 << i)) 635 tAA = i; 636 637 #define __DDR2_ROUND(scale, field) \ 638 ((scale * s->sm_ddr2.field + cycle_time - 1) / cycle_time) 639 640 aprint_verbose_dev(self, LATENCY, tAA, __DDR2_ROUND(250, ddr2_tRCD), 641 __DDR2_ROUND(250, ddr2_tRP), __DDR2_ROUND(1000, ddr2_tRAS)); 642 643 #undef __DDR_ROUND 644 645 decode_voltage_refresh(self, s); 646 } 647 648 static void 649 decode_ddr3(const struct sysctlnode *node, device_t self, struct spdmem *s) { 650 int dimm_size, cycle_time, bits; 651 652 aprint_naive("\n"); 653 aprint_normal(": %18s\n", s->sm_ddr3.ddr3_part); 654 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 655 656 if (s->sm_ddr3.ddr3_mod_type == 657 SPDMEM_DDR3_TYPE_MINI_RDIMM || 658 s->sm_ddr3.ddr3_mod_type == SPDMEM_DDR3_TYPE_RDIMM) 659 aprint_normal(" (registered)"); 660 aprint_normal(", %sECC, %stemp-sensor, ", 661 (s->sm_ddr3.ddr3_hasECC)?"":"no ", 662 (s->sm_ddr3.ddr3_has_therm_sensor)?"":"no "); 663 664 /* 665 * DDR3 size specification is quite different from others 666 * 667 * Module capacity is defined as 668 * Chip_Capacity_in_bits / 8bits-per-byte * 669 * external_bus_width / internal_bus_width 670 * We further divide by 2**20 to get our answer in MB 671 */ 672 dimm_size = (s->sm_ddr3.ddr3_chipsize + 28 - 20) - 3 + 673 (s->sm_ddr3.ddr3_datawidth + 3) - 674 (s->sm_ddr3.ddr3_chipwidth + 2); 675 dimm_size = (1 << dimm_size) * (s->sm_ddr3.ddr3_physbanks + 1); 676 677 cycle_time = (1000 * s->sm_ddr3.ddr3_mtb_dividend + 678 (s->sm_ddr3.ddr3_mtb_divisor / 2)) / 679 s->sm_ddr3.ddr3_mtb_divisor; 680 cycle_time *= s->sm_ddr3.ddr3_tCKmin; 681 bits = 1 << (s->sm_ddr3.ddr3_datawidth + 3); 682 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, FALSE, 683 "PC3", 0); 684 685 aprint_verbose_dev(self, 686 "%d rows, %d cols, %d log. banks, %d phys. banks, " 687 "%d.%03dns cycle time\n", 688 s->sm_ddr3.ddr3_rows + 9, s->sm_ddr3.ddr3_cols + 12, 689 1 << (s->sm_ddr3.ddr3_logbanks + 3), 690 s->sm_ddr3.ddr3_physbanks + 1, 691 cycle_time/1000, cycle_time % 1000); 692 693 #define __DDR3_CYCLES(field) (s->sm_ddr3.field / s->sm_ddr3.ddr3_tCKmin) 694 695 aprint_verbose_dev(self, LATENCY, __DDR3_CYCLES(ddr3_tAAmin), 696 __DDR3_CYCLES(ddr3_tRCDmin), __DDR3_CYCLES(ddr3_tRPmin), 697 (s->sm_ddr3.ddr3_tRAS_msb * 256 + s->sm_ddr3.ddr3_tRAS_lsb) / 698 s->sm_ddr3.ddr3_tCKmin); 699 700 #undef __DDR3_CYCLES 701 } 702 703 static void 704 decode_fbdimm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 705 int dimm_size, cycle_time, bits; 706 707 aprint_naive("\n"); 708 aprint_normal("\n"); 709 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 710 711 /* 712 * FB-DIMM module size calculation is very much like DDR3 713 */ 714 dimm_size = s->sm_fbd.fbdimm_rows + 12 + 715 s->sm_fbd.fbdimm_cols + 9 - 20 - 3; 716 dimm_size = (1 << dimm_size) * (1 << (s->sm_fbd.fbdimm_banks + 2)); 717 718 cycle_time = (1000 * s->sm_fbd.fbdimm_mtb_dividend + 719 (s->sm_fbd.fbdimm_mtb_divisor / 2)) / 720 s->sm_fbd.fbdimm_mtb_divisor; 721 bits = 1 << (s->sm_fbd.fbdimm_dev_width + 2); 722 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 723 "PC2", 0); 724 725 aprint_verbose_dev(self, 726 "%d rows, %d cols, %d banks, %d.%02dns cycle time\n", 727 s->sm_fbd.fbdimm_rows, s->sm_fbd.fbdimm_cols, 728 1 << (s->sm_fbd.fbdimm_banks + 2), 729 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 730 731 #define __FBDIMM_CYCLES(field) (s->sm_fbd.field / s->sm_fbd.fbdimm_tCKmin) 732 733 aprint_verbose_dev(self, LATENCY, __FBDIMM_CYCLES(fbdimm_tAAmin), 734 __FBDIMM_CYCLES(fbdimm_tRCDmin), __FBDIMM_CYCLES(fbdimm_tRPmin), 735 (s->sm_fbd.fbdimm_tRAS_msb * 256 + 736 s->sm_fbd.fbdimm_tRAS_lsb) / 737 s->sm_fbd.fbdimm_tCKmin); 738 739 #undef __FBDIMM_CYCLES 740 741 decode_voltage_refresh(self, s); 742 } 743
Indexes created Wed Oct 01 13:09:50 GMT 2025