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spdmemreg.h revision 1.1.42.2
      1  1.1.42.2     skrll /* $NetBSD: spdmemreg.h,v 1.1.42.2 2015/06/06 14:40:08 skrll Exp $ */
      2       1.1  pgoyette 
      3       1.1  pgoyette /*
      4       1.1  pgoyette  * Copyright (c) 2007 Paul Goyette
      5       1.1  pgoyette  * All rights reserved.
      6       1.1  pgoyette  *
      7       1.1  pgoyette  * Redistribution and use in source and binary forms, with or without
      8       1.1  pgoyette  * modification, are permitted provided that the following conditions
      9       1.1  pgoyette  * are met:
     10       1.1  pgoyette  * 1. Redistributions of source code must retain the above copyright
     11       1.1  pgoyette  *    notice, this list of conditions and the following disclaimer.
     12       1.1  pgoyette  * 2. Redistributions in binary form must reproduce the above copyright
     13       1.1  pgoyette  *    notice, this list of conditions and the following disclaimer in the
     14       1.1  pgoyette  *    documentation and/or other materials provided with the distribution.
     15       1.1  pgoyette  * 3. The name of the author may not be used to endorse or promote products
     16       1.1  pgoyette  *    derived from this software without specific prior written permission.
     17       1.1  pgoyette  *
     18       1.1  pgoyette  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS
     19       1.1  pgoyette  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20       1.1  pgoyette  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21       1.1  pgoyette  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22       1.1  pgoyette  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23       1.1  pgoyette  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24       1.1  pgoyette  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25       1.1  pgoyette  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26       1.1  pgoyette  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27       1.1  pgoyette  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28       1.1  pgoyette  * POSSIBILITY OF SUCH DAMAGE.
     29       1.1  pgoyette  */
     30       1.1  pgoyette 
     31       1.1  pgoyette /* possible values for the memory type */
     32       1.1  pgoyette #define	SPDMEM_MEMTYPE_FPM		0x01
     33       1.1  pgoyette #define	SPDMEM_MEMTYPE_EDO		0x02
     34       1.1  pgoyette #define	SPDMEM_MEMTYPE_PIPE_NIBBLE	0x03
     35       1.1  pgoyette #define	SPDMEM_MEMTYPE_SDRAM		0x04
     36       1.1  pgoyette #define	SPDMEM_MEMTYPE_ROM		0x05
     37       1.1  pgoyette #define	SPDMEM_MEMTYPE_DDRSGRAM		0x06
     38       1.1  pgoyette #define	SPDMEM_MEMTYPE_DDRSDRAM		0x07
     39       1.1  pgoyette #define	SPDMEM_MEMTYPE_DDR2SDRAM	0x08
     40       1.1  pgoyette #define	SPDMEM_MEMTYPE_FBDIMM		0x09
     41       1.1  pgoyette #define	SPDMEM_MEMTYPE_FBDIMM_PROBE	0x0A
     42       1.1  pgoyette #define	SPDMEM_MEMTYPE_DDR3SDRAM	0x0B
     43  1.1.42.1     skrll #define	SPDMEM_MEMTYPE_DDR4SDRAM	0x0C
     44       1.1  pgoyette 
     45       1.1  pgoyette #define	SPDMEM_MEMTYPE_RAMBUS		0x11
     46       1.1  pgoyette #define	SPDMEM_MEMTYPE_DIRECTRAMBUS	0x01
     47       1.1  pgoyette 
     48       1.1  pgoyette /* Encodings of the size used/total byte for certain memory types    */
     49       1.1  pgoyette #define	SPDMEM_SPDSIZE_MASK		0x0F	/* SPD EEPROM Size   */
     50       1.1  pgoyette 
     51       1.1  pgoyette #define	SPDMEM_SPDLEN_128		0x00	/* SPD EEPROM Sizes  */
     52       1.1  pgoyette #define	SPDMEM_SPDLEN_176		0x10
     53       1.1  pgoyette #define	SPDMEM_SPDLEN_256		0x20
     54       1.1  pgoyette #define	SPDMEM_SPDLEN_MASK		0x70	/* Bits 4 - 6        */
     55       1.1  pgoyette 
     56       1.1  pgoyette #define	SPDMEM_SPDCRC_116		0x80	/* CRC Bytes covered */
     57       1.1  pgoyette #define	SPDMEM_SPDCRC_125		0x00
     58       1.1  pgoyette #define	SPDMEM_SPDCRC_MASK		0x80	/* Bit 7             */
     59       1.1  pgoyette 
     60       1.1  pgoyette /* possible values for the supply voltage */
     61       1.1  pgoyette #define	SPDMEM_VOLTAGE_TTL_5V		0x00
     62       1.1  pgoyette #define	SPDMEM_VOLTAGE_TTL_LV		0x01
     63       1.1  pgoyette #define	SPDMEM_VOLTAGE_HSTTL_1_5V	0x02
     64       1.1  pgoyette #define	SPDMEM_VOLTAGE_SSTL_3_3V	0x03
     65       1.1  pgoyette #define	SPDMEM_VOLTAGE_SSTL_2_5V	0x04
     66       1.1  pgoyette #define	SPDMEM_VOLTAGE_SSTL_1_8V	0x05
     67       1.1  pgoyette 
     68       1.1  pgoyette /* possible values for module configuration */
     69       1.1  pgoyette #define	SPDMEM_MODCONFIG_PARITY		0x01
     70       1.1  pgoyette #define	SPDMEM_MODCONFIG_ECC		0x02
     71       1.1  pgoyette 
     72       1.1  pgoyette /* for DDR2, module configuration is a bit-mask field */
     73       1.1  pgoyette #define	SPDMEM_MODCONFIG_HAS_DATA_PARITY	0x01
     74       1.1  pgoyette #define	SPDMEM_MODCONFIG_HAS_DATA_ECC		0x02
     75       1.1  pgoyette #define	SPDMEM_MODCONFIG_HAS_ADDR_CMD_PARITY	0x04
     76       1.1  pgoyette 
     77       1.1  pgoyette /* possible values for the refresh field */
     78       1.1  pgoyette #define	SPDMEM_REFRESH_STD		0x00
     79       1.1  pgoyette #define	SPDMEM_REFRESH_QUARTER		0x01
     80       1.1  pgoyette #define	SPDMEM_REFRESH_HALF		0x02
     81       1.1  pgoyette #define	SPDMEM_REFRESH_TWOX		0x03
     82       1.1  pgoyette #define	SPDMEM_REFRESH_FOURX		0x04
     83       1.1  pgoyette #define	SPDMEM_REFRESH_EIGHTX		0x05
     84       1.1  pgoyette #define	SPDMEM_REFRESH_SELFREFRESH	0x80
     85       1.1  pgoyette 
     86       1.1  pgoyette /* superset types */
     87       1.1  pgoyette #define	SPDMEM_SUPERSET_ESDRAM		0x01
     88       1.1  pgoyette #define	SPDMEM_SUPERSET_DDR_ESDRAM	0x02
     89       1.1  pgoyette #define	SPDMEM_SUPERSET_EDO_PEM		0x03
     90       1.1  pgoyette #define	SPDMEM_SUPERSET_SDRAM_PEM	0x04
     91       1.1  pgoyette 
     92       1.1  pgoyette /* bit masks for "registered" module attribute */
     93       1.1  pgoyette #define	SPDMEM_SDR_MASK_REG		0x02
     94       1.1  pgoyette #define	SPDMEM_DDR_MASK_REG		0x02
     95       1.1  pgoyette #define	SPDMEM_DDR2_MASK_REG		0x05
     96       1.1  pgoyette 
     97       1.1  pgoyette #define	SPDMEM_DDR3_TYPE_RDIMM		0x01
     98       1.1  pgoyette #define	SPDMEM_DDR3_TYPE_UDIMM		0x02
     99       1.1  pgoyette #define	SPDMEM_DDR3_TYPE_SODIMM		0x03
    100       1.1  pgoyette #define	SPDMEM_DDR3_TYPE_MICRODIMM	0x04
    101       1.1  pgoyette #define	SPDMEM_DDR3_TYPE_MINI_RDIMM	0x05
    102       1.1  pgoyette #define	SPDMEM_DDR3_TYPE_MINI_UDIMM	0x06
    103  1.1.42.2     skrll 
    104  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_EXTENDED	0x00
    105  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_RDIMM		0x01
    106  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_UDIMM		0x02
    107  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_SODIMM		0x03
    108  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_LRDIMM		0x04
    109  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_MINI_RDIMM	0x05
    110  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_MINI_UDIMM	0x06
    111  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_RESERVED1	0x07
    112  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_72B_SO_RDIMM	0x08
    113  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_72B_SO_UDIMM	0x09
    114  1.1.42.2     skrll /* not defined				0x0a */
    115  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_RESERVED2	0x0b
    116  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_16B_SO_DIMM	0x0c
    117  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_32B_SO_DIMM	0x0d
    118  1.1.42.2     skrll #define	SPDMEM_DDR4_TYPE_RESERVED3	0x0e
    119  1.1.42.2     skrll /* not defined				0x0f */
    120