spdmemvar.h revision 1.15
1 /* $NetBSD: spdmemvar.h,v 1.15 2020/03/24 03:45:25 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Paul Goyette 5 * Copyright (c) 2007 Tobias Nygren 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * This information is extracted from JEDEC standard SPD4_01 (www.jedec.org) 34 */ 35 36 #if BYTE_ORDER == BIG_ENDIAN 37 #define SPD_BITFIELD(a, b, c, d) d; c; b; a 38 #else 39 #define SPD_BITFIELD(a, b, c, d) a; b; c; d 40 #endif 41 42 /* 43 * NOTE 44 * 45 * Fields with "offsets" are field widths, measured in bits, 46 * with "offset" additional bits. Thus, a field with value 47 * of 2 with an offset of 14 defines a field with total width 48 * of 16 bits. 49 */ 50 51 struct spdmem_fpm { /* FPM and EDO DIMMS */ 52 uint8_t fpm_len; 53 uint8_t fpm_size; 54 uint8_t fpm_type; 55 uint8_t fpm_rows; 56 uint8_t fpm_cols; 57 uint8_t fpm_banks; 58 uint16_t fpm_datawidth; /* endian-sensitive */ 59 uint8_t fpm_voltage; 60 uint8_t fpm_tRAC; 61 uint8_t fpm_tCAC; 62 uint8_t fpm_config; 63 SPD_BITFIELD( \ 64 uint8_t fpm_refresh:7, \ 65 uint8_t fpm_selfrefresh:1, , \ 66 ); 67 uint8_t fpm_dram_dramwidth; 68 uint8_t fpm_dram_eccwidth; 69 uint8_t fpm_unused2[17]; 70 uint8_t fpm_superset; 71 uint8_t fpm_unused3[30]; 72 uint8_t fpm_cksum; 73 } __packed; 74 75 struct spdmem_sdram { /* PC66/PC100/PC133 SDRAM */ 76 uint8_t sdr_len; 77 uint8_t sdr_size; 78 uint8_t sdr_type; 79 SPD_BITFIELD( \ 80 uint8_t sdr_rows:4, \ 81 uint8_t sdr_rows2:4, , \ 82 ); 83 SPD_BITFIELD( \ 84 uint8_t sdr_cols:4, \ 85 uint8_t sdr_cols2:4, , \ 86 ); 87 uint8_t sdr_banks; 88 uint16_t sdr_datawidth; /* endian-sensitive */ 89 uint8_t sdr_voltage; 90 SPD_BITFIELD( \ 91 uint8_t sdr_cycle_tenths:4, \ 92 uint8_t sdr_cycle_whole:4, , \ 93 ); 94 SPD_BITFIELD( 95 uint8_t sdr_tAC_tenths:4, \ 96 uint8_t sdr_tAC_whole:4, , \ 97 ); 98 uint8_t sdr_config; 99 SPD_BITFIELD( \ 100 uint8_t sdr_refresh:7, \ 101 uint8_t sdr_selfrefresh:1, , \ 102 ); 103 SPD_BITFIELD( \ 104 uint8_t sdr_dramwidth:7, \ 105 uint8_t sdr_dram_asym_bank2:1, ,\ 106 ); 107 SPD_BITFIELD( \ 108 uint8_t sdr_eccwidth:7, \ 109 uint8_t sdr_ecc_asym_bank2:1, , \ 110 ); 111 uint8_t sdr_min_clk_delay; 112 SPD_BITFIELD( \ 113 uint8_t sdr_burstlengths:4, \ 114 uint8_t sdr_unused1:4, , \ 115 ); 116 uint8_t sdr_banks_per_chip; 117 uint8_t sdr_tCAS; 118 uint8_t sdr_tCS; 119 uint8_t sdr_tWE; 120 uint8_t sdr_mod_attrs; 121 uint8_t sdr_dev_attrs; 122 uint8_t sdr_min_cc_1; 123 uint8_t sdr_max_tAC_1; 124 uint8_t sdr_min_cc_2; 125 uint8_t sdr_max_tAC_2; 126 uint8_t sdr_tRP; 127 uint8_t sdr_tRRD; 128 uint8_t sdr_tRCD; 129 uint8_t sdr_tRAS; 130 uint8_t sdr_module_rank_density; 131 uint8_t sdr_tIS; 132 #define sdr_superset sdr_tIS 133 uint8_t sdr_tIH; 134 uint8_t sdr_tDS; 135 uint8_t sdr_tDH; 136 uint8_t sdr_unused2[5]; 137 uint8_t sdr_tRC; 138 uint8_t sdr_unused3[18]; 139 uint8_t sdr_esdram; 140 uint8_t sdr_super_tech; 141 uint8_t sdr_spdrev; 142 uint8_t sdr_cksum; 143 } __packed; 144 145 struct spdmem_rom { 146 uint8_t rom_len; 147 uint8_t rom_size; 148 uint8_t rom_type; 149 uint8_t rom_rows; 150 uint8_t rom_cols; 151 uint8_t rom_banks; 152 uint16_t rom_datawidth; /* endian-sensitive */ 153 uint8_t rom_voltage; 154 uint16_t rom_tAA; /* endian-sensitive */ 155 uint8_t rom_config; 156 uint8_t rom_unused1; 157 uint8_t rom_tPA; 158 uint8_t rom_tOE; 159 uint16_t rom_tCE; /* endian-sensitive */ 160 uint8_t rom_burstlength; 161 uint8_t rom_unused2[14]; 162 uint8_t rom_superset[31]; 163 uint8_t rom_cksum; 164 } __packed; 165 166 167 struct spdmem_ddr { /* Dual Data Rate SDRAM */ 168 uint8_t ddr_len; 169 uint8_t ddr_size; 170 uint8_t ddr_type; 171 SPD_BITFIELD( \ 172 uint8_t ddr_rows:4, \ 173 uint8_t ddr_rows2:4, , \ 174 ); 175 SPD_BITFIELD( \ 176 uint8_t ddr_cols:4, \ 177 uint8_t ddr_cols2:4, , \ 178 ); 179 uint8_t ddr_ranks; 180 uint16_t ddr_datawidth; /* endian-sensitive */ 181 uint8_t ddr_voltage; 182 SPD_BITFIELD( \ 183 uint8_t ddr_cycle_tenths:4, \ 184 uint8_t ddr_cycle_whole:4, , \ 185 ); 186 SPD_BITFIELD( \ 187 uint8_t ddr_tAC_hundredths:4, \ 188 uint8_t ddr_tAC_tenths:4, , \ 189 ); 190 uint8_t ddr_config; 191 SPD_BITFIELD( \ 192 uint8_t ddr_refresh:7, \ 193 uint8_t ddr_selfrefresh:1, , \ 194 ); 195 SPD_BITFIELD( \ 196 uint8_t ddr_dramwidth:7, \ 197 uint8_t ddr_dram_asym_bank2:1, ,\ 198 ); 199 SPD_BITFIELD( \ 200 uint8_t ddr_eccwidth:7, \ 201 uint8_t ddr_ecc_asym_bank2:1, , \ 202 ); 203 uint8_t ddr_min_clk_delay; 204 SPD_BITFIELD( \ 205 uint8_t ddr_burstlengths:4, \ 206 uint8_t ddr_unused1:4, , \ 207 ); 208 uint8_t ddr_banks_per_chip; 209 uint8_t ddr_tCAS; 210 uint8_t ddr_tCS; 211 uint8_t ddr_tWE; 212 uint8_t ddr_mod_attrs; 213 uint8_t ddr_dev_attrs; 214 uint8_t ddr_min_cc_05; 215 uint8_t ddr_max_tAC_05; 216 uint8_t ddr_min_cc_1; 217 uint8_t ddr_max_tAC_1; 218 uint8_t ddr_tRP; 219 uint8_t ddr_tRRD; 220 uint8_t ddr_tRCD; 221 uint8_t ddr_tRAS; 222 uint8_t ddr_module_rank_density; 223 uint8_t ddr_tIS; 224 #define ddr_superset ddr_tIS 225 uint8_t ddr_tIH; 226 uint8_t ddr_tDS; 227 uint8_t ddr_tDH; 228 uint8_t ddr_unused2[5]; 229 uint8_t ddr_tRC; 230 uint8_t ddr_tRFC; 231 uint8_t ddr_tCK; 232 uint8_t ddr_tDQSQ; 233 uint8_t ddr_tQHS; 234 uint8_t ddr_unused3; 235 uint8_t ddr_height; 236 uint8_t ddr_unused4[15]; 237 uint8_t ddr_cksum; 238 } __packed; 239 240 struct spdmem_ddr2 { /* Dual Data Rate 2 SDRAM */ 241 uint8_t ddr2_len; 242 uint8_t ddr2_size; 243 uint8_t ddr2_type; 244 SPD_BITFIELD( \ 245 uint8_t ddr2_rows:5, \ 246 uint8_t ddr2_unused1:3, , \ 247 ); 248 SPD_BITFIELD( \ 249 uint8_t ddr2_cols:4, \ 250 uint8_t ddr2_unused2:4, , \ 251 ); 252 SPD_BITFIELD( \ 253 uint8_t ddr2_ranks:3, 254 uint8_t ddr2_cardoncard:1, \ 255 uint8_t ddr2_package:1, \ 256 uint8_t ddr2_height:3 \ 257 ); 258 uint8_t ddr2_datawidth; 259 uint8_t ddr2_unused3; 260 uint8_t ddr2_voltage; 261 SPD_BITFIELD( \ 262 uint8_t ddr2_cycle_frac:4, \ 263 uint8_t ddr2_cycle_whole:4, , \ 264 ); 265 SPD_BITFIELD( \ 266 uint8_t ddr2_tAC_hundredths:4, \ 267 uint8_t ddr2_tAC_tenths:4, , \ 268 ); 269 uint8_t ddr2_config; 270 SPD_BITFIELD( \ 271 uint8_t ddr2_refresh:7, \ 272 uint8_t ddr2_selfrefresh:1, , \ 273 ); 274 uint8_t ddr2_dramwidth; 275 uint8_t ddr2_eccwidth; 276 uint8_t ddr2_unused4; 277 SPD_BITFIELD( \ 278 uint8_t ddr2_burstlengths:4, \ 279 uint8_t ddr2_unused5:4, , \ 280 ); 281 uint8_t ddr2_banks_per_chip; 282 uint8_t ddr2_tCAS; 283 uint8_t ddr2_mechanical; 284 uint8_t ddr2_dimm_type; 285 uint8_t ddr2_mod_attrs; 286 uint8_t ddr2_dev_attrs; 287 uint8_t ddr2_min_cc_1; 288 uint8_t ddr2_max_tAC_1; 289 uint8_t ddr2_min_cc_2; 290 uint8_t ddr2_max_tAC_2; 291 uint8_t ddr2_tRP; 292 uint8_t ddr2_tRRD; 293 uint8_t ddr2_tRCD; 294 uint8_t ddr2_tRAS; 295 uint8_t ddr2_module_rank_density; 296 uint8_t ddr2_tIS; 297 uint8_t ddr2_tIH; 298 uint8_t ddr2_tDS; 299 uint8_t ddr2_tDH; 300 uint8_t ddr2_tWR; 301 uint8_t ddr2_tWTR; 302 uint8_t ddr2_tRTP; 303 uint8_t ddr2_probe; 304 uint8_t ddr2_extensions; 305 uint8_t ddr2_tRC; 306 uint8_t ddr2_tRFC; 307 uint8_t ddr2_tCK; 308 uint8_t ddr2_tDQSQ; 309 uint8_t ddr2_tQHS; 310 uint8_t ddr2_pll_relock; 311 uint8_t ddr2_Tcasemax; 312 uint8_t ddr2_Psi_TA_DRAM; 313 uint8_t ddr2_dt0; 314 uint8_t ddr2_dt2NQ; 315 uint8_t ddr2_dr2P; 316 uint8_t ddr2_dt3N; 317 uint8_t ddr2_dt3Pfast; 318 uint8_t ddr2_dt3Pslow; 319 uint8_t ddr2_dt4R_4R4W_mode; 320 uint8_t ddr2_dt5B; 321 uint8_t ddr2_dt7; 322 uint8_t ddr2_Psi_TA_PLL; 323 uint8_t ddr2_Psi_TA_Reg; 324 uint8_t ddr2_dt_PLL_Active; 325 uint8_t ddr2_dt_Reg_Active; 326 uint8_t ddr2_spdrev; 327 uint8_t ddr2_cksum; 328 } __packed; 329 330 struct spdmem_fbdimm { /* Fully-buffered DIMM */ 331 uint8_t fbdimm_len; 332 uint8_t fbdimm_size; 333 uint8_t fbdimm_type; 334 SPD_BITFIELD( \ 335 uint8_t fbdimm_ps1_voltage:4, \ 336 uint8_t fbdimm_ps2_voltage:4, , \ 337 ); 338 SPD_BITFIELD( \ 339 uint8_t fbdimm_banks:2, \ 340 uint8_t fbdimm_cols:3, \ 341 uint8_t fbdimm_rows:3, \ 342 ); 343 SPD_BITFIELD( \ 344 uint8_t fbdimm_thick:3, \ 345 uint8_t fbdimm_height:3, \ 346 uint8_t fbdimm_unused1:2, \ 347 ); 348 uint8_t fbdimm_mod_type; 349 SPD_BITFIELD( \ 350 uint8_t fbdimm_dev_width:3, \ 351 uint8_t fbdimm_ranks:3, \ 352 uint8_t fbdimm_unused2:2, \ 353 ); 354 SPD_BITFIELD( \ 355 uint8_t fbdimm_ftb_divisor:4, \ 356 uint8_t fbdimm_ftb_dividend:4, ,\ 357 ); 358 uint8_t fbdimm_mtb_dividend; 359 uint8_t fbdimm_mtb_divisor; 360 uint8_t fbdimm_tCKmin; 361 uint8_t fbdimm_tCKmax; 362 uint8_t fbdimm_tCAS; 363 uint8_t fbdimm_tAAmin; 364 SPD_BITFIELD( \ 365 uint8_t fbdimm_tWR_min:4, \ 366 uint8_t fbdimm_WR_range:4, , \ 367 ); 368 uint8_t fbdimm_tWR; 369 SPD_BITFIELD( \ 370 uint8_t fbdimm_tWL_min:4, \ 371 uint8_t fbdimm_tWL_range:4, , \ 372 ); 373 SPD_BITFIELD( \ 374 uint8_t fbdimm_tAL_min:4, \ 375 uint8_t fbdimm_tAL_range:4, , \ 376 ); 377 uint8_t fbdimm_tRCDmin; 378 uint8_t fbdimm_tRRDmin; 379 uint8_t fbdimm_tRPmin; 380 SPD_BITFIELD( \ 381 uint8_t fbdimm_tRAS_msb:4, \ 382 uint8_t fbdimm_tRC_msb:4, , \ 383 ); 384 uint8_t fbdimm_tRAS_lsb; 385 uint8_t fbdimm_tRC_lsb; 386 uint16_t fbdimm_tRFC; /* endian-sensitive */ 387 uint8_t fbdimm_tWTR; 388 uint8_t fbdimm_tRTP; 389 SPD_BITFIELD( \ 390 uint8_t fbdimm_burst_4:1, \ 391 uint8_t fbdimm_burst_8:1, \ 392 uint8_t fbdimm_unused3:6, \ 393 ); 394 uint8_t fbdimm_terms; 395 uint8_t fbdimm_drivers; 396 uint8_t fbdimm_tREFI; 397 uint8_t fbdimm_Tcasemax; 398 uint8_t fbdimm_Psi_TA_SDRAM; 399 uint8_t fbdimm_DT0; 400 uint8_t fbdimm_DT2N_DT2Q; 401 uint8_t fbdimm_DT2P; 402 uint8_t fbdimm_DT3N; 403 uint8_t fbdimm_DT4R_DT4R4W; 404 uint8_t fbdimm_DT5B; 405 uint8_t fbdimm_DT7; 406 uint8_t fbdimm_unused4[84]; 407 uint16_t fbdimm_crc; 408 } __packed; 409 410 struct spdmem_rambus { /* Direct Rambus DRAM */ 411 uint8_t rdr_len; 412 uint8_t rdr_size; 413 uint8_t rdr_type; 414 SPD_BITFIELD( \ 415 uint8_t rdr_rows:4, \ 416 uint8_t rdr_cols:4, , \ 417 ); 418 } __packed; 419 420 struct spdmem_ddr3 { /* Dual Data Rate 3 SDRAM */ 421 SPD_BITFIELD( \ 422 uint8_t ddr3_ROM_used:4, \ 423 uint8_t ddr3_ROM_size:3, \ 424 uint8_t ddr3_crccover:1, \ 425 ); 426 uint8_t ddr3_romrev; 427 uint8_t ddr3_type; 428 uint8_t ddr3_mod_type; 429 SPD_BITFIELD( \ 430 /* chipsize is offset by 28: 0 = 256M, 1 = 512M, ... */ \ 431 uint8_t ddr3_chipsize:4, \ 432 /* logbanks is offset by 3 */ \ 433 uint8_t ddr3_logbanks:3, \ 434 uint8_t ddr3_unused1:1, \ 435 ); 436 /* cols is offset by 9, rows offset by 12 */ 437 SPD_BITFIELD( \ 438 uint8_t ddr3_cols:3, \ 439 uint8_t ddr3_rows:5, , \ 440 ); 441 SPD_BITFIELD( \ 442 uint8_t ddr3_NOT15V:1, \ 443 uint8_t ddr3_135V:1, \ 444 uint8_t ddr3_125V:1, \ 445 uint8_t ddr3_unused2:5 \ 446 ); 447 /* chipwidth in bits offset by 2: 0 = X4, 1 = X8, 2 = X16 */ 448 /* physbanks is offset by 1 */ 449 SPD_BITFIELD( \ 450 uint8_t ddr3_chipwidth:3, \ 451 uint8_t ddr3_physbanks:5, , \ 452 ); 453 /* datawidth in bits offset by 3: 1 = 16b, 2 = 32b, 3 = 64b */ 454 SPD_BITFIELD( \ 455 uint8_t ddr3_datawidth:3, \ 456 uint8_t ddr3_hasECC:2, \ 457 uint8_t ddr3_unused2a:3 , \ 458 ); 459 /* Fine time base, in pico-seconds */ 460 SPD_BITFIELD( \ 461 uint8_t ddr3_ftb_divisor:4, \ 462 uint8_t ddr3_ftb_dividend:4, , \ 463 ); 464 uint8_t ddr3_mtb_dividend; /* 0x0108 = 0.1250ns */ 465 uint8_t ddr3_mtb_divisor; /* 0x010f = 0.0625ns */ 466 uint8_t ddr3_tCKmin_mtb; 467 uint8_t ddr3_unused3; 468 uint16_t ddr3_CAS_sup; /* Bit 0 ==> CAS 4 cycles */ 469 uint8_t ddr3_tAAmin_mtb; 470 uint8_t ddr3_tWRmin; 471 uint8_t ddr3_tRCDmin_mtb; 472 uint8_t ddr3_tRRDmin; 473 uint8_t ddr3_tRPmin_mtb; 474 SPD_BITFIELD( \ 475 uint8_t ddr3_tRAS_msb:4, \ 476 uint8_t ddr3_tRCmin_mtb_msb:4, , \ 477 ); 478 uint8_t ddr3_tRAS_lsb; 479 uint8_t ddr3_tRCmin_mtb_lsb; 480 uint8_t ddr3_tRFCmin_lsb; 481 uint8_t ddr3_tRFCmin_msb; 482 uint8_t ddr3_tWTRmin; 483 uint8_t ddr3_tRTPmin; 484 SPD_BITFIELD( \ 485 uint8_t ddr3_tFAW_msb:4, , , \ 486 ); 487 uint8_t ddr3_tFAW_lsb; 488 uint8_t ddr3_output_drvrs; 489 SPD_BITFIELD( \ 490 uint8_t ddr3_ext_temp_range:1, \ 491 uint8_t ddr3_ext_temp_2x_refresh:1, \ 492 uint8_t ddr3_asr_refresh:1, \ 493 /* Bit 4 indicates on-die thermal sensor */ 494 /* Bit 7 indicates Partial-Array Self-Refresh (PASR) */ 495 uint8_t ddr3_unused7:5 \ 496 ); 497 SPD_BITFIELD( \ 498 uint8_t ddr3_therm_sensor_acc:7,\ 499 uint8_t ddr3_has_therm_sensor:1, , \ 500 ); 501 SPD_BITFIELD( \ 502 uint8_t ddr3_non_std_devtype:7, \ 503 uint8_t ddr3_std_device:1, , \ 504 ); 505 uint8_t ddr3_tCKmin_ftb; 506 uint8_t ddr3_tAAmin_ftb; 507 uint8_t ddr3_tRCDmin_ftb; 508 uint8_t ddr3_tRPmin_ftb; 509 uint8_t ddr3_tRCmin_ftb; 510 uint8_t ddr3_unused4[2]; 511 uint8_t ddr3_MAC; 512 uint8_t ddr3_unused4a[17]; 513 uint8_t ddr3_mod_height; 514 uint8_t ddr3_mod_thickness; 515 uint8_t ddr3_ref_card; 516 uint8_t ddr3_mapping; 517 uint8_t ddr3_unused5[53]; 518 uint8_t ddr3_mfgID_lsb; 519 uint8_t ddr3_mfgID_msb; 520 uint8_t ddr3_mfgloc; 521 uint8_t ddr3_mfg_year; 522 uint8_t ddr3_mfg_week; 523 uint8_t ddr3_serial[4]; 524 uint16_t ddr3_crc; 525 uint8_t ddr3_part[18]; 526 uint8_t ddr3_rev[2]; 527 uint8_t ddr3_dram_mfgID_lsb; 528 uint8_t ddr3_dram_mfgID_msb; 529 uint8_t ddr3_vendor[26]; 530 } __packed; 531 532 /* DDR4 info from JEDEC Standard No. 21-C, Annex L - 4.1.2.12 */ 533 534 /* Module-type specific bytes - bytes 0x080 thru 0x0ff */ 535 536 struct spdmem_ddr4_mod_unbuffered { 537 SPD_BITFIELD( \ 538 uint8_t ddr4_unbuf_mod_height:4, \ 539 uint8_t ddr4_unbuf_card_ext:4, , \ 540 ); 541 SPD_BITFIELD( \ 542 uint8_t ddr4_unbuf_max_thick_front:4, \ 543 uint8_t ddr4_unbuf_max_thick_back:4, , \ 544 ); 545 SPD_BITFIELD( \ 546 uint8_t ddr4_unbuf_refcard:5, \ 547 uint8_t ddr4_unbuf_refcard_rev:2, \ 548 uint8_t ddr4_unbuf_refcard_ext:1, \ 549 ); 550 SPD_BITFIELD( \ 551 uint8_t ddr4_unbuf_mirror_mapping:1, \ 552 uint8_t ddr4_unbuf_unused1:7, , \ 553 ); 554 uint8_t ddr4_unbuf_unused2[122]; 555 uint8_t ddr4_unbuf_crc[2]; 556 } __packed; 557 558 struct spdmem_ddr4_mod_registered { 559 SPD_BITFIELD( \ 560 uint8_t ddr4_reg_mod_height:4, \ 561 uint8_t ddr4_reg_card_ext:4, , \ 562 ); 563 SPD_BITFIELD( \ 564 uint8_t ddr4_reg_max_thick_front:4, \ 565 uint8_t ddr4_reg_max_thick_back:4, , \ 566 ); 567 SPD_BITFIELD( \ 568 uint8_t ddr4_reg_refcard:5, \ 569 uint8_t ddr4_reg_refcard_rev:2, \ 570 uint8_t ddr4_reg_refcard_ext:1, \ 571 ); 572 SPD_BITFIELD( \ 573 uint8_t ddr4_reg_regcnt:2, \ 574 uint8_t ddr4_reg_dram_rows:2, \ 575 uint8_t ddr4_reg_unused1:4, \ 576 ); 577 SPD_BITFIELD( \ 578 uint8_t ddr4_reg_heat_spread_char:7, \ 579 uint8_t ddr4_reg_heat_spread_exist:1, , \ 580 ); 581 uint8_t ddr4_reg_mfg_id_lsb; 582 uint8_t ddr4_reg_mfg_id_msb; 583 uint8_t ddr4_reg_revision; 584 SPD_BITFIELD( \ 585 uint8_t ddr4_reg_mirror_mapping:1, \ 586 uint8_t ddr4_reg_unused2:7, , \ 587 ); 588 SPD_BITFIELD( \ 589 uint8_t ddr4_reg_output_drive_CKE:2, \ 590 uint8_t ddr4_reg_output_drive_ODT:2, \ 591 uint8_t ddr4_reg_output_drive_CmdAddr:2,\ 592 uint8_t ddr4_reg_output_drive_chipsel:2 \ 593 ); 594 SPD_BITFIELD( \ 595 uint8_t ddr4_reg_output_drive_CK_Y0Y2:2,\ 596 uint8_t ddr4_reg_output_drive_CK_Y1Y3:2,\ 597 uint8_t ddr4_reg_unused3:4, \ 598 ); 599 uint8_t ddr4_reg_unused4[115]; 600 uint8_t ddr4_reg_crc[2]; 601 } __packed; 602 603 struct spdmem_ddr4_mod_reduced_load { 604 SPD_BITFIELD( \ 605 uint8_t ddr4_rload_mod_height:4, \ 606 uint8_t ddr4_rload_card_ext:4, , \ 607 ); 608 SPD_BITFIELD( \ 609 uint8_t ddr4_rload_max_thick_front:4, \ 610 uint8_t ddr4_rload_max_thick_back:4, , \ 611 ); 612 SPD_BITFIELD( \ 613 uint8_t ddr4_rload_refcard:5, \ 614 uint8_t ddr4_rload_refcard_rev:2, \ 615 uint8_t ddr4_rload_refcard_ext:1, \ 616 ); 617 SPD_BITFIELD( \ 618 uint8_t ddr4_rload_regcnt:2, \ 619 uint8_t ddr4_rload_dram_rows:2, \ 620 uint8_t ddr4_rload_unused1:4, \ 621 ); 622 SPD_BITFIELD( \ 623 uint8_t ddr4_rload_unused2:7, \ 624 uint8_t ddr4_rload_heat_spread_exist:1, , \ 625 ); 626 uint8_t ddr4_rload_reg_mfg_id_lsb; 627 uint8_t ddr4_rload_reg_mfg_id_msb; 628 uint8_t ddr4_rload_reg_revision; 629 SPD_BITFIELD( \ 630 uint8_t ddr4_rload_reg_mirror_mapping:1,\ 631 uint8_t ddr4_rload_unused3:7, , \ 632 ); 633 SPD_BITFIELD( \ 634 uint8_t ddr4_rload_output_drive_CKE:2, \ 635 uint8_t ddr4_rload_output_drive_ODT:2, \ 636 uint8_t ddr4_rload_output_drive_CmdAddr:2, \ 637 uint8_t ddr4_rload_output_drive_chipsel:2 \ 638 ); 639 SPD_BITFIELD( \ 640 uint8_t ddr4_rload_output_drive_CK_Y0Y2:2, \ 641 uint8_t ddr4_rload_output_drive_CK_Y1Y3:2, \ 642 uint8_t ddr4_rload_unused4:4, \ 643 ); 644 uint8_t ddr4_rload_dbuff_revision; 645 SPD_BITFIELD( \ 646 uint8_t ddr4_rload_VrefDQ_0:6, \ 647 uint8_t ddr4_rload_unused5:2, , \ 648 ); 649 SPD_BITFIELD( \ 650 uint8_t ddr4_rload_VrefDQ_1:6, \ 651 uint8_t ddr4_rload_unused6:2, , \ 652 ); 653 SPD_BITFIELD( \ 654 uint8_t ddr4_rload_VrefDQ_2:6, \ 655 uint8_t ddr4_rload_unused7:2, , \ 656 ); 657 SPD_BITFIELD( \ 658 uint8_t ddr4_rload_VrefDQ_3:6, \ 659 uint8_t ddr4_rload_unused8:2, , \ 660 ); 661 SPD_BITFIELD( \ 662 uint8_t ddr4_rload_VrefDQ_buffer:6, \ 663 uint8_t ddr4_rload_unused9:2, , \ 664 ); 665 SPD_BITFIELD( \ 666 uint8_t ddr4_rload_MDQ_Read_Term_Str_1866:3, \ 667 uint8_t ddr4_rload_unused10:1, \ 668 uint8_t ddr4_rload_MDQ_Drive_Str_1866:3, \ 669 uint8_t ddr4_rload_unused11:1 \ 670 ); 671 SPD_BITFIELD( \ 672 uint8_t ddr4_rload_MDQ_Read_Term_Str_2400:3, \ 673 uint8_t ddr4_rload_unused12:1, \ 674 uint8_t ddr4_rload_MDQ_Drive_Str_2400:3, \ 675 uint8_t ddr4_rload_unused13:1 \ 676 ); 677 SPD_BITFIELD( \ 678 uint8_t ddr4_rload_MDQ_Read_Term_Str_3200:3, \ 679 uint8_t ddr4_rload_unused14:1, \ 680 uint8_t ddr4_rload_MDQ_Drive_Str_3200:3, \ 681 uint8_t ddr4_rload_unused15:1 \ 682 ); 683 SPD_BITFIELD( \ 684 uint8_t ddr4_rload_DRAM_Drive_Str_1866:2, \ 685 uint8_t ddr4_rload_DRAM_Drive_Str_2400:2, \ 686 uint8_t ddr4_rload_DRAM_Drive_Str_3200:2, \ 687 uint8_t ddr4_rload_unused16:2 \ 688 ); 689 SPD_BITFIELD( \ 690 uint8_t ddr4_rload_DRAM_ODT_RTT_NOM_1866:3, \ 691 uint8_t ddr4_rload_DRAM_ODT_RTT_WR_1866:3, \ 692 uint8_t ddr4_rload_unused17:2, \ 693 ); 694 SPD_BITFIELD( \ 695 uint8_t ddr4_rload_DRAM_ODT_RTT_NOM_2400:3, \ 696 uint8_t ddr4_rload_DRAM_ODT_RTT_WR_2400:3, \ 697 uint8_t ddr4_rload_unused18:2, \ 698 ); 699 SPD_BITFIELD( \ 700 uint8_t ddr4_rload_DRAM_ODT_RTT_NOM_3200:3, \ 701 uint8_t ddr4_rload_DRAM_ODT_RTT_WR_3200:3, \ 702 uint8_t ddr4_rload_unused19:2, \ 703 ); 704 SPD_BITFIELD( \ 705 uint8_t ddr4_rload_DRAM_ODT_RTT_PARK_01_1866:3, \ 706 uint8_t ddr4_rload_DRAM_ODT_RTT_PARK_23_1866:3, \ 707 uint8_t ddr4_rload_unused20:2, \ 708 ); 709 SPD_BITFIELD( \ 710 uint8_t ddr4_rload_DRAM_ODT_RTT_PARK_01_2400:3, \ 711 uint8_t ddr4_rload_DRAM_ODT_RTT_PARK_23_2400:3, \ 712 uint8_t ddr4_rload_unused21:2, \ 713 ); 714 SPD_BITFIELD( \ 715 uint8_t ddr4_rload_DRAM_ODT_RTT_PARK_01_3200:3, \ 716 uint8_t ddr4_rload_DRAM_ODT_RTT_PARK_23_3200:3, \ 717 uint8_t ddr4_rload_unused22:2, \ 718 ); 719 uint8_t ddr4_rload_unused23[99]; 720 uint8_t ddr4_rload_crc[2]; 721 } __packed; 722 723 struct spdmem_ddr4 { /* Dual Data Rate 4 SDRAM */ 724 SPD_BITFIELD( \ 725 uint8_t ddr4_ROM_used:4, \ 726 uint8_t ddr4_ROM_size:3, \ 727 uint8_t ddr4_unused0:1, \ 728 ); 729 uint8_t ddr4_romrev; 730 uint8_t ddr4_type; 731 SPD_BITFIELD( \ 732 uint8_t ddr4_mod_type:4, \ 733 uint8_t ddr4_hybrid_media:3, \ 734 uint8_t ddr4_hybrid:1, \ 735 ); 736 SPD_BITFIELD( \ 737 /* capacity is offset by 28: 0 = 256M, 1 = 512M, ... */ \ 738 uint8_t ddr4_capacity:4, \ 739 /* logbanks is offset by 2 */ \ 740 uint8_t ddr4_logbanks:2, \ 741 /* bankgroups is offset by 0 */ 742 uint8_t ddr4_bankgroups:2, \ 743 ); 744 /* cols is offset by 9, rows offset by 12 */ 745 SPD_BITFIELD( \ 746 uint8_t ddr4_cols:3, \ 747 uint8_t ddr4_rows:3, \ 748 uint8_t ddr4_unused2:2, \ 749 ); 750 SPD_BITFIELD( \ 751 uint8_t ddr4_signal_loading:2, \ 752 uint8_t ddr4_unused3:2, \ 753 uint8_t ddr4_diecount:3, \ 754 uint8_t ddr4_non_monolithic:1 \ 755 ); 756 SPD_BITFIELD( \ 757 uint8_t ddr4_max_activate_count:4, \ 758 uint8_t ddr4_max_activate_window:2, \ 759 uint8_t ddr4_unused4:2, \ 760 ); 761 uint8_t ddr4_unused5; /* SDRAM Thermal & Refresh Options */ 762 SPD_BITFIELD( \ 763 uint8_t ddr4_unused6:6, \ 764 uint8_t ddr4_ppr_support:2, , /* post package repair */ \ 765 ); 766 uint8_t ddr4_unused7; 767 SPD_BITFIELD( \ 768 uint8_t ddr4_dram_vdd_12:2, \ 769 uint8_t ddr4_dram_vdd_tbd1:2, \ 770 uint8_t ddr4_dram_vdd_tbd2:2, \ 771 uint8_t ddr4_unused8:2 \ 772 ); 773 SPD_BITFIELD( \ 774 /* device width is 0=4, 1=8, 2=16, or 4=32 bits */ \ 775 uint8_t ddr4_device_width:3, \ 776 /* number of package ranks is field value plus 1 */ \ 777 uint8_t ddr4_package_ranks:3, \ 778 uint8_t ddr4_rank_mix:1, \ 779 uint8_t ddr4_unused9:1 \ 780 ); 781 SPD_BITFIELD( \ 782 /* primary width is offset by 3, extension is offset by 2 */ \ 783 uint8_t ddr4_primary_bus_width:3, \ 784 uint8_t ddr4_bus_width_extension:2, \ 785 uint8_t ddr4_unused10:3, \ 786 ); 787 SPD_BITFIELD( \ 788 uint8_t ddr4_unused11:7, \ 789 uint8_t ddr4_has_therm_sensor:1, , \ 790 ); 791 SPD_BITFIELD( \ 792 uint8_t ddr4_ext_mod_type:4, \ 793 uint8_t ddr4_unused12:4, , \ 794 ); 795 uint8_t ddr4_unused13; 796 SPD_BITFIELD( \ 797 /* units = 1ps (10**-12sec) */ \ 798 uint8_t ddr4_fine_timebase:2, \ 799 /* units = 125ps */ \ 800 uint8_t ddr4_medium_timebase:2, , \ 801 ); 802 uint8_t ddr4_tCKAVGmin_mtb; 803 uint8_t ddr4_tCKAVGmax_mtb; 804 /* Bit 0 of CAS_supported[0 corresponds to CL=7 */ 805 uint8_t ddr4_CAS_supported[4]; 806 uint8_t ddr4_tAAmin_mtb; 807 uint8_t ddr4_tRCDmin_mtb; 808 uint8_t ddr4_tRPmin_mtb; 809 SPD_BITFIELD( \ 810 uint8_t ddr4_tRASmin_msb:4, \ 811 uint8_t ddr4_tRCmin_mtb_msb:4, , \ 812 ); 813 uint8_t ddr4_tRASmin_lsb; 814 uint8_t ddr4_tRCmin_mtb_lsb; 815 uint8_t ddr4_tRFC1min_lsb; 816 uint8_t ddr4_tRFC1min_msb; 817 uint8_t ddr4_tRFC2min_lsb; 818 uint8_t ddr4_tRFC2min_msb; 819 uint8_t ddr4_tRFC4min_lsb; 820 uint8_t ddr4_tRFC4min_msb; 821 SPD_BITFIELD( \ 822 uint8_t ddr4_tFAW_mtb_msb:4, \ 823 uint8_t ddr4_unused14:4, , \ 824 ); 825 uint8_t ddr4_tFAWmin_mtb_lsb; 826 uint8_t ddr4_tRRD_Smin_mtb; 827 uint8_t ddr4_tRRD_Lmin_mtb; 828 uint8_t ddr4_tCCD_Lmin_mtb; 829 uint8_t ddr4_tWR_min_msb; 830 uint8_t ddr4_tWR_min_mtb; 831 uint8_t ddr4_tWTR_min; 832 uint8_t ddr4_tWTR_Smin_mtb; 833 uint8_t ddr4_tWTR_Lmin_mtb; 834 uint8_t ddr4_unused15[14]; 835 uint8_t ddr4_connector_map[18]; 836 uint8_t ddr4_unused16[39]; 837 uint8_t ddr4_tCCD_Lmin_ftb; 838 uint8_t ddr4_tRRD_Lmin_ftb; 839 uint8_t ddr4_tRRD_Smin_ftb; 840 uint8_t ddr4_tRCmin_ftb; 841 uint8_t ddr4_tRPmin_ftb; 842 uint8_t ddr4_tRCDmin_ftb; 843 uint8_t ddr4_tAAmin_ftb; 844 uint8_t ddr4_tCKAVGmax_ftb; 845 uint8_t ddr4_tCKAVGmin_ftb; 846 uint16_t ddr4_crc; 847 union { 848 struct spdmem_ddr4_mod_unbuffered u2_unbuf; 849 struct spdmem_ddr4_mod_registered u2_reg; 850 struct spdmem_ddr4_mod_reduced_load u2_red_load; 851 } ddr4_u2; 852 uint8_t ddr4_unused17[64]; 853 uint8_t ddr4_module_mfg_lsb; 854 uint8_t ddr4_module_mfg_msb; 855 uint8_t ddr4_module_mfg_loc; 856 uint8_t ddr4_module_mfg_year; 857 uint8_t ddr4_module_mfg_week; 858 uint8_t ddr4_serial_number[4]; 859 uint8_t ddr4_part_number[20]; 860 uint8_t ddr4_revision_code; 861 uint8_t ddr4_dram_mfgID_lsb; 862 uint8_t ddr4_dram_mfgID_msb; 863 uint8_t ddr4_dram_stepping; 864 uint8_t ddr4_mfg_specific_data[29]; 865 uint8_t ddr4_unused18[2]; 866 uint8_t ddr4_user_data[128]; 867 } __packed; 868 869 struct spdmem { 870 union { 871 struct spdmem_fbdimm u1_fbd; 872 struct spdmem_fpm u1_fpm; 873 struct spdmem_ddr u1_ddr; 874 struct spdmem_ddr2 u1_ddr2; 875 struct spdmem_sdram u1_sdr; 876 struct spdmem_rambus u1_rdr; 877 struct spdmem_rom u1_rom; 878 struct spdmem_ddr3 u1_ddr3; 879 struct spdmem_ddr4 u1_ddr4; 880 } sm_u1; 881 } __packed; 882 #define sm_fbd sm_u1.u1_fbd 883 #define sm_fpm sm_u1.u1_fpm 884 #define sm_ddr sm_u1.u1_ddr 885 #define sm_ddr2 sm_u1.u1_ddr2 886 #define sm_rdr sm_u1.u1_rdr 887 #define sm_rom sm_u1.u1_rom 888 #define sm_ddr3 sm_u1.u1_ddr3 889 #define sm_sdr sm_u1.u1_sdr 890 #define sm_ddr4 sm_u1.u1_ddr4 891 892 /* some fields are in the same place for all memory types */ 893 894 #define sm_len sm_fpm.fpm_len 895 #define sm_size sm_fpm.fpm_size 896 #define sm_type sm_fpm.fpm_type 897 #define sm_cksum sm_fpm.fpm_cksum 898 #define sm_config sm_fpm.fpm_config 899 #define sm_voltage sm_fpm.fpm_voltage 900 #define sm_refresh sm_fpm.fpm_refresh 901 #define sm_selfrefresh sm_fpm.fpm_selfrefresh 902 903 #define SPDMEM_TYPE_MAXLEN 40 904 905 struct spdmem_softc { 906 int (*sc_read)(struct spdmem_softc *, uint16_t, uint8_t *); 907 struct spdmem sc_spd_data; 908 struct sysctllog *sc_sysctl_log; 909 char sc_type[SPDMEM_TYPE_MAXLEN]; 910 }; 911 912 int spdmem_common_probe(struct spdmem_softc *); 913 void spdmem_common_attach(struct spdmem_softc *, device_t); 914 int spdmem_common_detach(struct spdmem_softc *, device_t); 915
Indexes created Wed Oct 01 19:09:53 GMT 2025