summitreg.h revision 1.12
1 /* $NetBSD: summitreg.h,v 1.12 2024/12/26 10:40:46 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2024 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* HP Visualize FX 4 and related hardware, aka Summit */ 30 31 /* 32 * register values, found by disassembling the ROM 33 * some found by Sven Schnelle 34 * ( see https://patchwork.kernel.org/project/linux-parisc/patch/20211031204952.25678-2-svens@stackframe.org/ ) 35 * some by me 36 */ 37 38 #ifndef SUMMITREG_H 39 #define SUMMITREG_H 40 41 #define VISFX_CONTROL 0x641000 42 #define CONTROL_WFC 0x00000200 // FIFO when 0, direct when 1 43 #define VISFX_FC 0x641040 // Fault Control 44 #define VISFX_STATUS 0x641400 // zero when idle 45 #define VISFX_FIFO 0x641440 46 #define VISFX_FOE 0x920404 // Fragment Operation Enable 47 #define FOE_TEXTURE 0x00000001 48 #define FOE_SPECULAR 0x00000002 49 #define FOE_DEPTHCUE 0x00000004 50 #define FOE_ALPHATEST 0x00000008 51 #define FOE_STENCIL 0x00000010 52 #define FOE_Z_TEST 0x00000020 53 #define FOE_BLEND_ROP 0x00000040 // IBO is used 54 #define FOE_DITHER 0x00000080 55 #define VISFX_IBO 0x921110 // ROP in lowest nibble 56 #define VISFX_IAA0 0x921200 // XLUT, 16 entries 57 #define VISFX_IAA(n) (0x921200 + ((n) << 2)) 58 #define VISFX_OTR 0x921148 // overlay transparency 59 60 #define VISFX_VRAM_WRITE_MODE 0xa00808 61 #define VISFX_VRAM_READ_MODE 0xa0080c 62 #define VISFX_PIXEL_MASK 0xa0082c 63 #define VISFX_FG_COLOUR 0xa0083c 64 #define VISFX_BG_COLOUR 0xa00844 65 #define VISFX_PLANE_MASK 0xa0084c 66 /* this controls what we see in the FB aperture */ 67 #define VISFX_APERTURE_ACCESS 0xa00858 68 #define VISFX_DEPTH_8 0x30 69 #define VISFX_DEPTH_32 0x50 70 71 #define VISFX_VRAM_WRITE_DATA_INCRX 0xa60000 72 #define VISFX_VRAM_WRITE_DATA_INCRY 0xa68000 73 #define VISFX_VRAM_WRITE_DEST 0xac1000 74 #define VISFX_TCR 0xac1024 /* throttle control */ 75 #define VISFX_CLIP_TL 0xac1050 /* clipping rect, top/left */ 76 #define VISFX_CLIP_WH 0xac1054 /* clipping rect, w/h */ 77 78 #define VISFX_WRITE_MODE_PLAIN 0x02000000 79 #define VISFX_WRITE_MODE_EXPAND 0x050004c0 80 #define VISFX_WRITE_MODE_FILL 0x050008c0 81 #define VISFX_WRITE_MODE_TRANSPARENT 0x00000800 /* bg is tansparent */ 82 #define VISFX_WRITE_MODE_MASK 0x00000400 /* apply pixel mask */ 83 /* 0x00000200 - some pattern */ 84 /* looks like 0x000000c0 enables fb/bg colours to be applied */ 85 86 #define VISFX_READ_MODE_COPY 0x02000400 87 88 #define OTC01 0x00000000 /* one pixel per 32bit write */ 89 #define OTC04 0x02000000 /* 4 pixels per 32bit write */ 90 #define OTC32 0x05000000 /* 32 pixels per 32bit write */ 91 #define BIN8I 0x00000000 /* 8bit indexed */ 92 #define BIN12I 0x00010000 /* 12bit indexed */ 93 #define BIN332F 0x00040000 /* R3G3B2 */ 94 #define BIN8F 0x00070000 /* ARGB8 */ 95 #define BINapln 0x00110000 /* attribute plane */ 96 #define BINhost 0x00300000 /* DMA to host */ 97 #define BUFovl 0x00000000 /* 8bit overlay */ 98 #define BUFBL 0x00008000 /* back/left */ 99 #define BUFFL 0x00004000 /* front/left */ 100 #define BUFBR 0x00002000 /* back/right */ 101 #define BUFFR 0x00001000 /* front/right */ 102 103 /* attribute table */ 104 #define IAA_8I 0x00000000 /* 8bit CI */ 105 #define IAA_8F 0x00000070 /* RGB8 */ 106 #define IAA_CFS0 0x00000000 /* CFS select */ 107 #define IAA_CFS1 0x00000100 /* CFS 1 etc. */ 108 109 #define OTR_T 0x00010000 /* when set 0 is transparent, otherwise 0xff */ 110 #define OTR_A 0x00000100 /* always transparent */ 111 #define OTR_L1 0x00000002 /* transparency controlled by CFS17 */ 112 #define OTR_L0 0x00000001 /* transparency controlled by CFS16 */ 113 114 /* 115 * for STI colour change mode: 116 * set VISFX_FG_COLOUR, VISFX_BG_COLOUR 117 * set VISFX_VRAM_READ_MODE 0x05000400 118 * set VISFX_VRAM_WRITE_MODE 0x050000c0 119 */ 120 121 /* fill */ 122 #define VISFX_START 0xb3c000 123 #define VISFX_SIZE 0xb3c808 /* start, FX4 uses 0xb3c908 */ 124 125 /* copy */ 126 #define VISFX_COPY_SRC 0xb3c010 127 #define VISFX_COPY_WH 0xb3c008 128 #define VISFX_COPY_DST 0xb3cc00 129 /* 130 * looks like ORing 0x800 to the register address starts a command 131 * - 0x800 - fill 132 * - 0xc00 - copy 133 * 0x100 and 0x200 seem to have functions as well, not sure what though 134 * for example, the FX4 ROM uses 0xb3c908 to start a rectangle fill, but 135 * it also works with 0xb3c808 and 0xb3ca08 136 * same with copy, 0xc00 seems to be what matters, setting 0x100 or 0x200 137 * doesn't seem to make a difference 138 * 0x400 or 0x100 by themselves don't start a command either 139 */ 140 141 /* 142 * Turns out 0x40xxxx and 0x80xxxx access the same registers, one difference 143 * is that through 0x80xxxx we can read back at least some values, so use 144 * that one 145 * The _POS, _INDEX and _DATA registers work exactly like on HCRX 146 */ 147 148 #define VISFX_CURSOR_POS 0x800000 149 #define VISFX_CURSOR_ENABLE 0x80000000 150 #define VISFX_CURSOR_INDEX 0x800004 151 #define VISFX_CURSOR_DATA 0x800008 152 #define VISFX_CURSOR_FG 0x80000c 153 #define VISFX_CURSOR_BG 0x800010 154 #define VISFX_COLOR_MASK 0x800018 155 #define VISFX_COLOR_INDEX 0x800020 156 #define VISFX_COLOR_VALUE 0x800024 157 #define VISFX_FATTR 0x80003c /* force attribute */ 158 #define VISFX_MPC 0x80004c 159 #define MPC_VIDEO_ON 0x0c 160 #define MPC_VSYNC_OFF 0x02 161 #define MPC_HSYNC_OFF 0x01 162 #define VISFX_CFS0 0x800100 /* colour function select */ 163 #define VISFX_CFS(n) (VISFX_CFS0 + ((n) << 2)) 164 /* 0 ... 6 for image planes, 7 or bypass, 16 and 17 for overlay */ 165 #define CFS_CR 0x80 // enable color recovery 166 #define CFS_332 0x00 // R3G3B2 167 #define CFS_8I 0x40 // 8bit indexed 168 #define CFS_8F 0x70 // ARGB8 169 #define CFS_LUT0 0x00 // use LUT 0 170 #define CFS_LUT1 0x01 // LUT 1 etc. 171 #define CFS_BYPASS 0x07 // bypass LUT 172 173 #endif /* SUMMITREG_H */ 174
Indexes created Tue Sep 30 11:09:46 GMT 2025