tms9914reg.h revision 1.2
1/* $NetBSD: tms9914reg.h,v 1.2 2008/04/28 20:23:51 martin Exp $ */ 2 3/*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gregory McGarry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#define TMS9914_IOSIZE 8 33 34/* 35 * Direct-access Registers (write only) 36 */ 37 38#define TMS9914_IMR0 0 /* (W) interrupt mask 0 */ 39#define IMR0_MAC 0x01 /* my address change */ 40#define IMR0_RLC 0x02 /* remote/local address change */ 41#define IMR0_SPAS 0x04 /* serial poll active state */ 42#define IMR0_END 0x08 /* EOI or EOS */ 43#define IMR0_BO 0x10 /* byte out */ 44#define IMR0_BI 0x20 /* byte in */ 45#define TMS9914_IMR1 1 /* (W) interrupt mask 1 */ 46#define IMR1_IFC 0x01 /* IFC asserted */ 47#define IMR1_SRQ 0x02 /* SRQ asserted */ 48#define IMR1_MA 0x04 /* my address */ 49#define IMR1_DCAS 0x08 /* device clear active state */ 50#define IMR1_APT 0x10 /* address pass-through */ 51#define IMR1_UCG 0x20 /* unrecognised command */ 52#define IMR1_ERR 0x40 /* data transmission error */ 53#define IMR1_GET 0x80 /* group execute trigger */ 54#define TMS9914_AUXCR 3 /* (W) auxiliary command */ 55#define TMS9914_ADDR 4 /* (W) address register */ 56#define ADDR_DAT 0x20 57#define ADDR_DAL 0x40 58#define ADDR_EDPA 0x80 59#define TMS9914_SPMR 5 /* (W) serial poll register */ 60#define TMS9914_PPR 6 /* (W) parallel poll */ 61#define TMS9914_CDOR 7 /* (W) data-out register */ 62 63/* 64 * Direct-access Registers (read only) 65 */ 66 67#define TMS9914_ISR0 0 /* (R) interrupt status 0 */ 68#define ISR0_MAC 0x01 /* my address change */ 69#define ISR0_RLC 0x02 /* remote/local address change */ 70#define ISR0_SPAS 0x04 /* serial poll active state */ 71#define ISR0_END 0x08 /* EOI or EOS */ 72#define ISR0_BO 0x10 /* byte out */ 73#define ISR0_BI 0x20 /* byte in */ 74#define TMS9914_ISR1 1 /* (R) interrupt status 1 */ 75#define ISR1_IFC 0x01 /* IFC asserted */ 76#define ISR1_SRQ 0x02 /* SRQ asserted */ 77#define ISR1_MA 0x04 /* my address */ 78#define ISR1_DCAS 0x08 /* device clear active state */ 79#define ISR1_APT 0x10 /* address pass-through */ 80#define ISR1_UCG 0x20 /* unrecognised command */ 81#define ISR1_ERR 0x40 /* data transmission error */ 82#define ISR1_GET 0x80 /* group execute trigger */ 83#define TMS9914_ADSR 2 /* (R) address status */ 84#define ADSR_ULPA 0x01 /* store last address LSB */ 85#define ADSR_TADS 0x02 /* talker addressed */ 86#define ADSR_LADS 0x04 /* listener addressed */ 87#define ADSR_TPAS 0x08 /* talker primary address state */ 88#define ADSR_LPAS 0x10 /* listener primary address state */ 89#define ADSR_ATN 0x20 /* ATN active */ 90#define ADSR_LLO 0x40 /* LLO active */ 91#define ADSR_REM 0x80 /* REM active */ 92#define TMS9914_CPTR 6 /* (R) command pass-through */ 93#define TMS9914_DIR 7 /* (R) data-in register */ 94 95/* 96 * Auxiliary Commands 97 * 98 * Two basic type of commands are implemented: pulsed and static. 99 * Static commands enable (set) or disable (clear) chip features. 100 * Pulsed commands stay active for one clock pulse. 101 * 102 */ 103 104/* pulsed commands */ 105#define AUXCMD_RHDF 0x02 /* release RFD holdoff */ 106#define AUXCMD_NBAF 0x05 /* new byte available false */ 107#define AUXCMD_SEOI 0x08 /* send EOI with next byte */ 108#define AUXCMD_GTS 0x0b /* go to standby (clear ATN line) */ 109#define AUXCMD_TCA 0x0c /* take control (async) */ 110#define AUXCMD_TCS 0x0d /* take control (sync) */ 111 112/* static commands */ 113#define AUXCMD_SET 0x80 114#define AUXCMD_CLEAR 0x00 115#define AUXCMD_SWRST 0x00 /* Software reset */ 116#define AUXCMD_HDFA 0x03 /* holdoff on all data */ 117#define AUXCMD_HDFE 0x04 /* holdoff on EOI data only */ 118#define AUXCMD_RTL 0x07 /* return to local */ 119#define AUXCMD_LON 0x09 /* listen only */ 120#define AUXCMD_TON 0x0a /* talk only */ 121#define AUXCMD_RPP 0x0e /* request parallel poll */ 122#define AUXCMD_SIC 0x0f /* IFC (interface clear) line */ 123#define AUXCMD_SRE 0x10 /* REN (remote enable) line */ 124#define AUXCMD_DAI 0x13 /* interrupt disable */ 125#define AUXCMD_STD1 0x15 /* 1200ns T1 delay */ 126#define AUXCMD_SHDW 0x16 /* shadow handshake */ 127#define AUXCMD_VSTD1 0x17 /* 600ns T1 delay */ 128