1 1.11 riastrad /* $NetBSD: tpmreg.h,v 1.11 2022/01/29 12:27:30 riastradh Exp $ */ 2 1.1 christos 3 1.1 christos /* 4 1.4 maxv * Copyright (c) 2019 The NetBSD Foundation, Inc. 5 1.1 christos * All rights reserved. 6 1.1 christos * 7 1.4 maxv * This code is derived from software contributed to The NetBSD Foundation 8 1.4 maxv * by Maxime Villard. 9 1.1 christos * 10 1.4 maxv * Redistribution and use in source and binary forms, with or without 11 1.4 maxv * modification, are permitted provided that the following conditions 12 1.4 maxv * are met: 13 1.4 maxv * 1. Redistributions of source code must retain the above copyright 14 1.4 maxv * notice, this list of conditions and the following disclaimer. 15 1.4 maxv * 2. Redistributions in binary form must reproduce the above copyright 16 1.4 maxv * notice, this list of conditions and the following disclaimer in the 17 1.4 maxv * documentation and/or other materials provided with the distribution. 18 1.4 maxv * 19 1.4 maxv * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.4 maxv * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.4 maxv * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.4 maxv * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.4 maxv * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.4 maxv * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.4 maxv * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.4 maxv * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.4 maxv * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.4 maxv * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.4 maxv * POSSIBILITY OF SUCH DAMAGE. 30 1.1 christos */ 31 1.1 christos 32 1.7 riastrad #ifndef DEV_IC_TPMREG_H 33 1.7 riastrad #define DEV_IC_TPMREG_H 34 1.7 riastrad 35 1.7 riastrad #include <sys/types.h> 36 1.7 riastrad 37 1.7 riastrad #include <sys/cdefs.h> 38 1.7 riastrad #include <sys/endian.h> 39 1.7 riastrad 40 1.6 maxv struct tpm_header { 41 1.6 maxv uint16_t tag; 42 1.6 maxv uint32_t length; 43 1.6 maxv uint32_t code; 44 1.6 maxv } __packed; 45 1.6 maxv 46 1.6 maxv /* -------------------------------------------------------------------------- */ 47 1.6 maxv 48 1.4 maxv /* 49 1.4 maxv * TPM Interface Specification 1.2 (TIS12). 50 1.4 maxv */ 51 1.1 christos 52 1.4 maxv #define TPM_ACCESS 0x0000 /* 8bit register */ 53 1.4 maxv #define TPM_ACCESS_VALID __BIT(7) 54 1.4 maxv #define TPM_ACCESS_ACTIVE_LOCALITY __BIT(5) 55 1.4 maxv #define TPM_ACCESS_BEEN_SEIZED __BIT(4) 56 1.4 maxv #define TPM_ACCESS_SEIZE __BIT(3) 57 1.4 maxv #define TPM_ACCESS_PENDING_REQUEST __BIT(2) 58 1.4 maxv #define TPM_ACCESS_REQUEST_USE __BIT(1) 59 1.4 maxv #define TPM_ACCESS_ESTABLISHMENT __BIT(0) 60 1.4 maxv 61 1.4 maxv #define TPM_INT_ENABLE 0x0008 /* 32bit register */ 62 1.4 maxv #define TPM_GLOBAL_INT_ENABLE __BIT(31) 63 1.4 maxv #define TPM_CMD_READY_INT __BIT(7) 64 1.4 maxv #define TPM_TYPE_POLARITY __BITS(4,3) 65 1.4 maxv #define TPM_INT_LEVEL_HIGH __SHIFTIN(0, TPM_TYPE_POLARITY) 66 1.4 maxv #define TPM_INT_LEVEL_LOW __SHIFTIN(1, TPM_TYPE_POLARITY) 67 1.4 maxv #define TPM_INT_EDGE_RISING __SHIFTIN(2, TPM_TYPE_POLARITY) 68 1.4 maxv #define TPM_INT_EDGE_FALLING __SHIFTIN(3, TPM_TYPE_POLARITY) 69 1.4 maxv #define TPM_LOCALITY_CHANGE_INT __BIT(2) 70 1.4 maxv #define TPM_STS_VALID_INT __BIT(1) 71 1.4 maxv #define TPM_DATA_AVAIL_INT __BIT(0) 72 1.4 maxv 73 1.4 maxv #define TPM_INT_VECTOR 0x000c /* 8bit register */ 74 1.4 maxv #define TPM_INT_STATUS 0x0010 /* 32bit register */ 75 1.4 maxv 76 1.4 maxv #define TPM_INTF_CAPABILITY 0x0014 /* 32bit register */ 77 1.4 maxv #define TPM_INTF_BURST_COUNT_STATIC __BIT(8) 78 1.4 maxv #define TPM_INTF_CMD_READY_INT __BIT(7) 79 1.4 maxv #define TPM_INTF_INT_EDGE_FALLING __BIT(6) 80 1.4 maxv #define TPM_INTF_INT_EDGE_RISING __BIT(5) 81 1.4 maxv #define TPM_INTF_INT_LEVEL_LOW __BIT(4) 82 1.4 maxv #define TPM_INTF_INT_LEVEL_HIGH __BIT(3) 83 1.4 maxv #define TPM_INTF_LOCALITY_CHANGE_INT __BIT(2) 84 1.4 maxv #define TPM_INTF_STS_VALID_INT __BIT(1) 85 1.4 maxv #define TPM_INTF_DATA_AVAIL_INT __BIT(0) 86 1.4 maxv #define TPM_INTF_CAPABILITY_BITS \ 87 1.4 maxv "\020\01IDRDY\02ISTSV\03ILOCH\04IHIGH\05ILOW\06IRISE\07IFALL\010IRDY\011BCST" 88 1.4 maxv 89 1.4 maxv #define TPM_STS 0x0018 /* 24bit register */ 90 1.4 maxv #define TPM_STS_BURST_COUNT __BITS(23,8) 91 1.4 maxv #define TPM_STS_STATUS_BITS __BITS(7,0) 92 1.4 maxv #define TPM_STS_VALID __BIT(7) 93 1.4 maxv #define TPM_STS_CMD_READY __BIT(6) 94 1.4 maxv #define TPM_STS_GO __BIT(5) 95 1.4 maxv #define TPM_STS_DATA_AVAIL __BIT(4) 96 1.4 maxv #define TPM_STS_DATA_EXPECT __BIT(3) 97 1.5 maxv #define TPM_STS_SELFTEST_DONE __BIT(2) 98 1.4 maxv #define TPM_STS_RESP_RETRY __BIT(1) 99 1.4 maxv 100 1.4 maxv #define TPM_DATA 0x0024 /* 32bit register */ 101 1.4 maxv #define TPM_ID 0x0f00 /* 32bit register */ 102 1.4 maxv #define TPM_REV 0x0f04 /* 8bit register */ 103 1.1 christos 104 1.4 maxv /* 105 1.10 riastrad * Five localities, 4K per locality. But we only use the registers for 106 1.10 riastrad * the first locality, so this is 0x1000 rather than 0x5000. 107 1.4 maxv */ 108 1.10 riastrad #define TPM_SPACE_SIZE 0x1000 109 1.7 riastrad 110 1.8 riastrad #define TPM_TAG_RQU_COMMAND 0x00c1 111 1.8 riastrad #define TPM_TAG_RSP_COMMAND 0x00c4 112 1.8 riastrad 113 1.8 riastrad #define TPM_ORD_GetRandom 0x00000046 114 1.8 riastrad 115 1.8 riastrad /* TPM_RESULT return codes */ 116 1.8 riastrad #define TPM_AUTHFAIL 1 117 1.8 riastrad #define TPM_BADINDEX 2 118 1.8 riastrad #define TPM_BAD_PARAMETER 3 119 1.8 riastrad #define TPM_AUDITFAILURE 4 120 1.8 riastrad #define TPM_CLEAR_DISABLED 5 121 1.8 riastrad #define TPM_DEACTIVATED 6 122 1.8 riastrad #define TPM_DISABLED 7 123 1.8 riastrad #define TPM_DISABLED_CMD 8 124 1.8 riastrad #define TPM_FAIL 9 125 1.8 riastrad #define TPM_BAD_ORDINAL 10 126 1.8 riastrad /* ... */ 127 1.8 riastrad 128 1.8 riastrad #define TPM_NON_FATAL 0x800 129 1.8 riastrad 130 1.9 riastrad /* -------------------------------------------------------------------------- */ 131 1.9 riastrad 132 1.9 riastrad /* 133 1.9 riastrad * Trusted Platform Module Library Specification, Family "2.0", 134 1.9 riastrad * Level 00, Revision 01.59 -- November 2019 135 1.9 riastrad * 136 1.9 riastrad * https://trustedcomputinggroup.org/resource/tpm-library-specification/ 137 1.9 riastrad * 138 1.9 riastrad * Where this spec names things TPM_* that don't obviously coincide 139 1.9 riastrad * with the 1.2 things, we name them TPM2_*. 140 1.9 riastrad */ 141 1.9 riastrad 142 1.9 riastrad /* https://trustedcomputinggroup.org/wp-content/uploads/TPM-Rev-2.0-Part-4-Supporting-Routines-01.38-code.pdf#page=172 */ 143 1.9 riastrad #define TPM2_ST_RSP_COMMAND 0x00c4 144 1.9 riastrad #define TPM2_ST_NULL 0x8000 145 1.9 riastrad #define TPM2_ST_NO_SESSIONS 0x8001 146 1.9 riastrad #define TPM2_ST_SESSIONS 0x8002 147 1.9 riastrad /* ... */ 148 1.9 riastrad 149 1.9 riastrad /* https://trustedcomputinggroup.org/wp-content/uploads/TPM-Rev-2.0-Part-2-Structures-01.38.pdf#page=45 */ 150 1.9 riastrad #define TPM2_CC_GetRandom 0x0000017b 151 1.9 riastrad 152 1.9 riastrad /* https://trustedcomputinggroup.org/wp-content/uploads/TPM-Rev-2.0-Part-2-Structures-01.38.pdf#page=53 */ 153 1.9 riastrad #define TPM2_RC_SUCCESS 0x000 154 1.9 riastrad #define TPM2_RC_BAD_TAG 0x01e 155 1.9 riastrad 156 1.9 riastrad #define TPM2_RC_VER1 0x100 157 1.9 riastrad 158 1.9 riastrad #define TPM2_RC_FMT1 0x080 159 1.9 riastrad 160 1.9 riastrad #define TPM2_RC_WARN 0x900 161 1.9 riastrad #define TPM2_RC_TESTING (TPM2_RC_WARN + 0x00a) 162 1.9 riastrad #define TPM2_RC_RETRY (TPM2_RC_WARN + 0x022) 163 1.9 riastrad 164 1.7 riastrad #endif /* DEV_IC_TPMREG_H */ 165