tpmreg.h revision 1.4 1 1.4 maxv /* $NetBSD: tpmreg.h,v 1.4 2019/06/22 12:57:41 maxv Exp $ */
2 1.1 christos
3 1.1 christos /*
4 1.4 maxv * Copyright (c) 2019 The NetBSD Foundation, Inc.
5 1.1 christos * All rights reserved.
6 1.1 christos *
7 1.4 maxv * This code is derived from software contributed to The NetBSD Foundation
8 1.4 maxv * by Maxime Villard.
9 1.1 christos *
10 1.4 maxv * Redistribution and use in source and binary forms, with or without
11 1.4 maxv * modification, are permitted provided that the following conditions
12 1.4 maxv * are met:
13 1.4 maxv * 1. Redistributions of source code must retain the above copyright
14 1.4 maxv * notice, this list of conditions and the following disclaimer.
15 1.4 maxv * 2. Redistributions in binary form must reproduce the above copyright
16 1.4 maxv * notice, this list of conditions and the following disclaimer in the
17 1.4 maxv * documentation and/or other materials provided with the distribution.
18 1.4 maxv *
19 1.4 maxv * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.4 maxv * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.4 maxv * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.4 maxv * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.4 maxv * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.4 maxv * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.4 maxv * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.4 maxv * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.4 maxv * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.4 maxv * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.4 maxv * POSSIBILITY OF SUCH DAMAGE.
30 1.1 christos */
31 1.1 christos
32 1.4 maxv /*
33 1.4 maxv * TPM Interface Specification 1.2 (TIS12).
34 1.4 maxv */
35 1.1 christos
36 1.4 maxv #define TPM_ACCESS 0x0000 /* 8bit register */
37 1.4 maxv #define TPM_ACCESS_VALID __BIT(7)
38 1.4 maxv #define TPM_ACCESS_ACTIVE_LOCALITY __BIT(5)
39 1.4 maxv #define TPM_ACCESS_BEEN_SEIZED __BIT(4)
40 1.4 maxv #define TPM_ACCESS_SEIZE __BIT(3)
41 1.4 maxv #define TPM_ACCESS_PENDING_REQUEST __BIT(2)
42 1.4 maxv #define TPM_ACCESS_REQUEST_USE __BIT(1)
43 1.4 maxv #define TPM_ACCESS_ESTABLISHMENT __BIT(0)
44 1.4 maxv
45 1.4 maxv #define TPM_INT_ENABLE 0x0008 /* 32bit register */
46 1.4 maxv #define TPM_GLOBAL_INT_ENABLE __BIT(31)
47 1.4 maxv #define TPM_CMD_READY_INT __BIT(7)
48 1.4 maxv #define TPM_TYPE_POLARITY __BITS(4,3)
49 1.4 maxv #define TPM_INT_LEVEL_HIGH __SHIFTIN(0, TPM_TYPE_POLARITY)
50 1.4 maxv #define TPM_INT_LEVEL_LOW __SHIFTIN(1, TPM_TYPE_POLARITY)
51 1.4 maxv #define TPM_INT_EDGE_RISING __SHIFTIN(2, TPM_TYPE_POLARITY)
52 1.4 maxv #define TPM_INT_EDGE_FALLING __SHIFTIN(3, TPM_TYPE_POLARITY)
53 1.4 maxv #define TPM_LOCALITY_CHANGE_INT __BIT(2)
54 1.4 maxv #define TPM_STS_VALID_INT __BIT(1)
55 1.4 maxv #define TPM_DATA_AVAIL_INT __BIT(0)
56 1.4 maxv
57 1.4 maxv #define TPM_INT_VECTOR 0x000c /* 8bit register */
58 1.4 maxv #define TPM_INT_STATUS 0x0010 /* 32bit register */
59 1.4 maxv
60 1.4 maxv #define TPM_INTF_CAPABILITY 0x0014 /* 32bit register */
61 1.4 maxv #define TPM_INTF_BURST_COUNT_STATIC __BIT(8)
62 1.4 maxv #define TPM_INTF_CMD_READY_INT __BIT(7)
63 1.4 maxv #define TPM_INTF_INT_EDGE_FALLING __BIT(6)
64 1.4 maxv #define TPM_INTF_INT_EDGE_RISING __BIT(5)
65 1.4 maxv #define TPM_INTF_INT_LEVEL_LOW __BIT(4)
66 1.4 maxv #define TPM_INTF_INT_LEVEL_HIGH __BIT(3)
67 1.4 maxv #define TPM_INTF_LOCALITY_CHANGE_INT __BIT(2)
68 1.4 maxv #define TPM_INTF_STS_VALID_INT __BIT(1)
69 1.4 maxv #define TPM_INTF_DATA_AVAIL_INT __BIT(0)
70 1.4 maxv #define TPM_INTF_CAPABILITY_BITS \
71 1.4 maxv "\020\01IDRDY\02ISTSV\03ILOCH\04IHIGH\05ILOW\06IRISE\07IFALL\010IRDY\011BCST"
72 1.4 maxv
73 1.4 maxv #define TPM_STS 0x0018 /* 24bit register */
74 1.4 maxv #define TPM_STS_BURST_COUNT __BITS(23,8)
75 1.4 maxv #define TPM_STS_STATUS_BITS __BITS(7,0)
76 1.4 maxv #define TPM_STS_VALID __BIT(7)
77 1.4 maxv #define TPM_STS_CMD_READY __BIT(6)
78 1.4 maxv #define TPM_STS_GO __BIT(5)
79 1.4 maxv #define TPM_STS_DATA_AVAIL __BIT(4)
80 1.4 maxv #define TPM_STS_DATA_EXPECT __BIT(3)
81 1.4 maxv #define TPM_STS_RESP_RETRY __BIT(1)
82 1.4 maxv
83 1.4 maxv #define TPM_DATA 0x0024 /* 32bit register */
84 1.4 maxv #define TPM_ID 0x0f00 /* 32bit register */
85 1.4 maxv #define TPM_REV 0x0f04 /* 8bit register */
86 1.1 christos
87 1.4 maxv /*
88 1.4 maxv * Five localities, 4K per locality.
89 1.4 maxv */
90 1.4 maxv #define TPM_SPACE_SIZE 0x5000
91