tulipreg.h revision 1.1
1 /* $NetBSD: tulipreg.h,v 1.1 1999/09/01 00:32:41 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_IC_TULIPREG_H_ 41 #define _DEV_IC_TULIPREG_H_ 42 43 /* 44 * Register description for the Digital Semiconductor ``Tulip'' (21x4x) 45 * Ethernet controller family, and a variety of clone chips, including: 46 * 47 * - Macronix 98713, 98713A, 98715, 98715A, 98725 (PMAC): 48 * 49 * These chips are fairly straight-forward Tulip clones. 50 * The 98713 and 98713A have an MII. All have an internal 51 * transciever capable of NWAY. The 98713A, 98715A, and 52 * 98725 support power management. 53 * 54 * - Lite-On 82C168, 82C169 (PNIC): 55 * 56 * These are Tulip clones with a few small differences; the 57 * EEPROM is accessed totally differently, as is the MII. 58 * The PNIC also has a built-in NWAY transciever. 59 * 60 * - Winbond 89C840F 61 * 62 * Fairly straight-forward Tulip clone, with the exception 63 * that registers don't have a pad longword between them, 64 * and the receive filter is set up differently: instead of 65 * a setup packet, we have 2 32-bit multicast hash table 66 * registers, and 2 station address registers. 67 * 68 * Some of the clone chips have different registers, and some have 69 * different bits in the same registers. These will be denoted by 70 * PMAC, PNIC, and WINB in the register/bit names. 71 */ 72 73 /* 74 * Tulip buffer descriptor. Must be 4-byte aligned. 75 * 76 * Note for receive descriptors, the byte count fields must 77 * be a multiple of 4. 78 */ 79 struct tulip_desc { 80 __volatile u_int32_t td_status; /* Status */ 81 __volatile u_int32_t td_ctl; /* Control and Byte Counts */ 82 __volatile u_int32_t td_bufaddr1; /* Buffer Address 1 */ 83 __volatile u_int32_t td_bufaddr2; /* Buffer Address 2 */ 84 }; 85 86 /* 87 * Descriptor Status bits common to transmit and receive. 88 */ 89 #define TDSTAT_OWN 0x80000000 /* Tulip owns descriptor */ 90 #define TDSTAT_ES 0x00008000 /* Error Summary */ 91 92 /* 93 * Descriptor Status bits for Receive Descriptor. 94 */ 95 #define TDSTAT_Rx_FF 0x40000000 /* Filtering Fail */ 96 #define TDSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */ 97 #define TDSTAT_Rx_DE 0x00004000 /* Descriptor Error */ 98 #define TDSTAT_Rx_DT 0x00003000 /* Data Type */ 99 #define TDSTAT_Rx_RF 0x00000800 /* Runt Frame */ 100 #define TDSTAT_Rx_MF 0x00000400 /* Multicast Frame */ 101 #define TDSTAT_Rx_FS 0x00000200 /* First Descriptor */ 102 #define TDSTAT_Rx_LS 0x00000100 /* Last Descriptor */ 103 #define TDSTAT_Rx_TL 0x00000080 /* Frame Too Long */ 104 #define TDSTAT_Rx_CS 0x00000040 /* Collision Seen */ 105 #define TDSTAT_Rx_RT 0x00000020 /* Frame Type */ 106 #define TDSTAT_Rx_RW 0x00000010 /* Receive Watchdog */ 107 #define TDSTAT_Rx_RE 0x00000008 /* Report on MII Error */ 108 #define TDSTAT_Rx_DB 0x00000004 /* Dribbling Bit */ 109 #define TDSTAT_Rx_CE 0x00000002 /* CRC Error */ 110 #define TDSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */ 111 112 #define TDSTAT_Rx_LENGTH(x) (((x) & TDSTAT_Rx_FL) >> 16) 113 114 #define TDSTAT_Rx_DT_SR 0x00000000 /* Serial Received Frame */ 115 #define TDSTAT_Rx_DT_IL 0x00001000 /* Internal Loopback Frame */ 116 #define TDSTAT_Rx_DT_EL 0x00002000 /* External Loopback Frame */ 117 #define TDSTAT_Rx_DT_r 0x00003000 /* Reserved */ 118 119 /* 120 * Descriptor Status bits for Transmit Descriptor. 121 */ 122 #define TDSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */ 123 #define TDSTAT_Tx_LO 0x00000800 /* Loss of Carrier */ 124 #define TDSTAT_Tx_NC 0x00000400 /* No Carrier */ 125 #define TDSTAT_Tx_LC 0x00000200 /* Late Collision */ 126 #define TDSTAT_Tx_EC 0x00000100 /* Excessive Collisions */ 127 #define TDSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */ 128 #define TDSTAT_Tx_CC 0x00000078 /* Collision Count */ 129 #define TDSTAT_Tx_LF 0x00000004 /* Link Fail */ 130 #define TDSTAT_Tx_UF 0x00000002 /* Underflow Error */ 131 #define TDSTAT_Tx_DE 0x00000001 /* Deferred */ 132 133 #define TDSTAT_Tx_COLLISIONS(x) (((x) & TDSTAT_Tx_CC) >> 3) 134 135 /* 136 * Descriptor Control bits common to transmit and receive. 137 */ 138 #define TDCTL_SIZE1 0x000007ff /* Size of buffer 1 */ 139 #define TDCTL_SIZE1_SHIFT 0 140 141 #define TDCTL_SIZE2 0x003ff800 /* Size of buffer 2 */ 142 #define TDCTL_SIZE2_SHIFT 11 143 144 #define TDCTL_ER 0x02000000 /* End of Ring */ 145 #define TDCTL_CH 0x01000000 /* Second Address Chained */ 146 147 /* 148 * Descriptor Control bits for Transmit Descriptor. 149 */ 150 #define TDCTL_Tx_IC 0x80000000 /* Interrupt on Completion */ 151 #define TDCTL_Tx_LS 0x40000000 /* Last Segment */ 152 #define TDCTL_Tx_FS 0x20000000 /* First Segment */ 153 #define TDCTL_Tx_FT1 0x10000000 /* Filtering Type 1 */ 154 #define TDCTL_Tx_SET 0x08000000 /* Setup Packet */ 155 #define TDCTL_Tx_AC 0x04000000 /* Add CRC Disable */ 156 #define TDCTL_Tx_DPD 0x00800000 /* Disabled Padding */ 157 #define TDCTL_Tx_FT0 0x00400000 /* Filtering Type 0 */ 158 159 /* 160 * The Tulip filter is programmed by "transmitting" a Setup Packet 161 * (indicated by TDCTL_Tx_SET). The filtering type is indicated 162 * as follows: 163 * 164 * FT1 FT0 Description 165 * --- --- ----------- 166 * 0 0 Perfect Filtering: The Tulip interprets the 167 * descriptor buffer as a table of 16 MAC addresses 168 * that the Tulip should receive. 169 * 170 * 0 1 Hash Filtering: The Tulip interprets the 171 * descriptor buffer as a 512-bit hash table 172 * plus one perfect address. If the incoming 173 * address is Multicast, the hash table filters 174 * the address, else the address is filtered by 175 * the perfect address. 176 * 177 * 1 0 Inverse Filtering: Like Perfect Filtering, except 178 * the table is addresses that the Tulip does NOT 179 * receive. 180 * 181 * 1 1 Hash-only Filtering: Like Hash Filtering, but 182 * physical addresses are matched by the hash table 183 * as well, and not by matching a single perfect 184 * address. 185 * 186 * A Setup Packet must always be 192 bytes long. The Tulip can store 187 * 16 MAC addresses. If not all 16 are specified in Perfect Filtering 188 * or Inverse Filtering mode, then unused entries should duplicate 189 * one of the valid entries. 190 */ 191 #define TDCTL_Tx_FT_PERFECT 0 192 #define TDCTL_Tx_FT_HASH TDCTL_Tx_FT0 193 #define TDCTL_Tx_FT_INVERSE TDCTL_Tx_FT1 194 #define TDCTL_Tx_FT_HASHONLY (TDCTL_Tx_FT1|TDCTL_Tx_FT0) 195 196 #define TULIP_SETUP_PACKET_LEN 192 197 #define TULIP_MAXADDRS 16 198 #define TULIP_MCHASHSIZE 512 199 200 /* 201 * Maximum size of a Tulip Ethernet Address ROM or SROM. 202 */ 203 #define TULIP_MAX_ROM_SIZE 128 204 205 /* 206 * Tulip control registers. 207 */ 208 209 #define TULIP_CSR0 0x00 210 #define TULIP_CSR1 0x08 211 #define TULIP_CSR2 0x10 212 #define TULIP_CSR3 0x18 213 #define TULIP_CSR4 0x20 214 #define TULIP_CSR5 0x28 215 #define TULIP_CSR6 0x30 216 #define TULIP_CSR7 0x38 217 #define TULIP_CSR8 0x40 218 #define TULIP_CSR9 0x48 219 #define TULIP_CSR10 0x50 220 #define TULIP_CSR11 0x58 221 #define TULIP_CSR12 0x60 222 #define TULIP_CSR13 0x68 223 #define TULIP_CSR14 0x70 224 #define TULIP_CSR15 0x78 225 #define TULIP_CSR16 0x80 226 #define TULIP_CSR17 0x88 227 #define TULIP_CSR18 0x90 228 #define TULIP_CSR19 0x98 229 #define TULIP_CSR20 0xa0 230 231 /* CSR0 - Bus Mode */ 232 #define CSR_BUSMODE TULIP_CSR0 233 #define BUSMODE_SWR 0x00000001 /* software reset */ 234 #define BUSMODE_BAR 0x00000002 /* bus arbitration */ 235 #define BUSMODE_DSL 0x0000007c /* descriptor skip length */ 236 #define BUSMODE_BLE 0x00000080 /* big endian */ 237 /* programmable burst length */ 238 #define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */ 239 #define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */ 240 #define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */ 241 #define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */ 242 #define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */ 243 #define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */ 244 #define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */ 245 /* cache alignment */ 246 #define BUSMODE_CAL_NONE 0x00000000 /* no alignment */ 247 #define BUSMODE_CAL_8LW 0x00004000 /* 8 longwords */ 248 #define BUSMODE_CAL_16LW 0x00008000 /* 16 longwords */ 249 #define BUSMODE_CAL_32LW 0x0000c000 /* 32 longwords */ 250 #define BUSMODE_DAS 0x00010000 /* diagnostic address space */ 251 /* must be zero on most */ 252 /* transmit auto-poll */ 253 #define BUSMODE_TAP_NONE 0x00000000 /* no auto-polling */ 254 #define BUSMODE_TAP_200us 0x00020000 /* 200 uS */ 255 #define BUSMODE_TAP_800us 0x00040000 /* 400 uS */ 256 #define BUSMODE_TAP_1_6ms 0x00060000 /* 1.6 mS */ 257 #define BUSMODE_TAP_12_8us 0x00080000 /* 12.8 uS (21041+) */ 258 #define BUSMODE_TAP_25_6us 0x000a0000 /* 25.6 uS (21041+) */ 259 #define BUSMODE_TAP_51_2us 0x000c0000 /* 51.2 uS (21041+) */ 260 #define BUSMODE_TAP_102_4us 0x000e0000 /* 102.4 uS (21041+) */ 261 #define BUSMODE_DBO 0x00100000 /* desc-only b/e (21041+) */ 262 #define BUSMODE_RME 0x00200000 /* rd/mult enab (21140+) */ 263 #define BUSMODE_RLE 0x00800000 /* rd/line enab (21140+) */ 264 #define BUSMODE_WLE 0x01000000 /* wt/line enab (21140+) */ 265 #define BUSMODE_PNIC_MBO 0x04000000 /* magic `must be one' bit */ 266 /* on Lite-On PNIC */ 267 268 269 /* CSR1 - Transmit Poll Demand */ 270 #define CSR_TXPOLL TULIP_CSR1 271 #define TXPOLL_TPD 0x00000001 /* transmit poll demand */ 272 273 274 /* CSR2 - Receive Poll Demand */ 275 #define CSR_RXPOLL TULIP_CSR2 276 #define RXPOLL_RPD 0x00000001 /* receive poll demand */ 277 278 279 /* CSR3 - Receive List Base Address */ 280 #define CSR_RXLIST TULIP_CSR3 281 282 /* CSR4 - Transmit List Base Address */ 283 #define CSR_TXLIST TULIP_CSR4 284 285 /* CSR5 - Status */ 286 #define CSR_STATUS TULIP_CSR5 287 #define STATUS_TI 0x00000001 /* transmit interrupt */ 288 #define STATUS_TPS 0x00000002 /* transmit process stopped */ 289 #define STATUS_TU 0x00000004 /* transmit buffer unavail */ 290 #define STATUS_TJT 0x00000008 /* transmit jabber timeout */ 291 #define STATUS_LNPANC 0x00000010 /* link pass (21041) */ 292 #define STATUS_UNF 0x00000020 /* transmit underflow */ 293 #define STATUS_RI 0x00000040 /* receive interrupt */ 294 #define STATUS_RU 0x00000080 /* receive buffer unavail */ 295 #define STATUS_RPS 0x00000100 /* receive process stopped */ 296 #define STATUS_RWT 0x00000200 /* receive watchdog timeout */ 297 #define STATUS_AT 0x00000400 /* SIA AUI/TP pin changed 298 (21040) */ 299 #define STATUS_FD 0x00000800 /* full duplex short frame 300 received (21040) */ 301 #define STATUS_TM 0x00000800 /* timer expired (21041) */ 302 #define STATUS_LNF 0x00001000 /* link fail (21040) */ 303 #define STATUS_SE 0x00002000 /* system error */ 304 #define STATUS_ER 0x00004000 /* early receive (21041) */ 305 #define STATUS_AIS 0x00008000 /* abnormal interrupt summary */ 306 #define STATUS_NIS 0x00010000 /* normal interrupt summary */ 307 #define STATUS_RS 0x000e0000 /* receive process state */ 308 #define STATUS_RS_STOPPED 0x00000000 /* Stopped */ 309 #define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive 310 descriptor */ 311 #define STATUS_RS_CHECK 0x00040000 /* Running - check for end 312 of receive */ 313 #define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */ 314 #define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */ 315 #define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive 316 descriptor */ 317 #define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current 318 frame from FIFO */ 319 #define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current 320 frame from FIFO into 321 buffer */ 322 #define STATUS_TS 0x00700000 /* transmit process state */ 323 #define STATUS_TS_STOPPED 0x00000000 /* Stopped */ 324 #define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit 325 descriptor */ 326 #define STATUS_TS_WAIT 0x00200000 /* Running - wait for end 327 of transmission */ 328 #define STATUS_TS_READING 0x00300000 /* Running - read buffer from 329 memory and queue into 330 FIFO */ 331 #define STATUS_TS_RESERVED 0x00400000 /* RESERVED */ 332 #define STATUS_TS_SETUP 0x00500000 /* Running - Setup packet */ 333 #define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */ 334 #define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit 335 descriptor */ 336 #define STATUS_EB 0x03800000 /* error bits */ 337 #define STATUS_EB_PARITY 0x00000000 /* parity errror */ 338 #define STATUS_EB_MABT 0x00800000 /* master abort */ 339 #define STATUS_EB_TABT 0x01000000 /* target abort */ 340 341 342 /* CSR6 - Operation Mode */ 343 #define CSR_OPMODE TULIP_CSR6 344 #define OPMODE_HP 0x00000001 /* hash/perfect mode (ro) */ 345 #define OPMODE_SR 0x00000002 /* start receive */ 346 #define OPMODE_HO 0x00000004 /* hash only mode (ro) */ 347 #define OPMODE_PB 0x00000008 /* pass bad frames */ 348 #define OPMODE_IF 0x00000010 /* inverse filter mode (ro) */ 349 #define OPMODE_SB 0x00000020 /* start backoff counter */ 350 #define OPMODE_PR 0x00000040 /* promiscuous mode */ 351 #define OPMODE_PM 0x00000080 /* pass all multicast */ 352 #define OPMODE_FKD 0x00000100 /* flaky oscillator disable */ 353 #define OPMODE_FD 0x00000200 /* full-duplex mode */ 354 #define OPMODE_OM 0x00000c00 /* operating mode */ 355 #define OPMODE_OM_NORMAL 0x00000000 /* normal mode */ 356 #define OPMODE_OM_INTLOOP 0x00000400 /* internal loopback */ 357 #define OPMODE_OM_EXTLOOP 0x00000800 /* external loopback */ 358 #define OPMODE_FC 0x00001000 /* force collision */ 359 #define OPMODE_ST 0x00002000 /* start transmitter */ 360 #define OPMODE_TR 0x0000c000 /* threshold control */ 361 #define OPMODE_TR_72 0x00000000 /* 72 bytes */ 362 #define OPMODE_TR_96 0x00004000 /* 96 bytes */ 363 #define OPMODE_TR_128 0x00008000 /* 128 bytes */ 364 #define OPMODE_TR_160 0x0000c000 /* 160 bytes */ 365 #define OPMODE_BP 0x00010000 /* backpressure enable */ 366 #define OPMODE_CA 0x00020000 /* capture effect enable */ 367 #define OPMODE_PMAC_COE 0x00020000 /* collision offset enable */ 368 #define OPMODE_PS 0x00040000 /* port select: 369 1 = MII/SYM, 0 = SRL 370 (21140) */ 371 #define OPMODE_HBD 0x00080000 /* heartbeat disable: 372 set in MII/SYM 100mbps, 373 set according to PHY 374 in MII 10mbps mode 375 (21140) */ 376 #define OPMODE_SF 0x00200000 /* store and forward mode 377 (21140) */ 378 #define OPMODE_TTM 0x00400000 /* Transmit Threshold Mode: 379 1 = 10mbps, 0 = 100mbps 380 (21140) */ 381 #define OPMODE_PCS 0x00800000 /* PCS function (21140) */ 382 #define OPMODE_SCR 0x01000000 /* scrambler mode (21140) */ 383 #define OPMODE_MBO 0x02000000 /* must be one (21140) */ 384 #define OPMODE_PNIC_RXCRCDIS 0x20000000 /* don't include CRC in Rx 385 frames (PNIC) */ 386 #define OPMODE_RA 0x40000000 /* receive all (21140) */ 387 #define OPMODE_PNIC_EXT_ENDEC 0x40000000 /* 1 == ext, 0 == int PHY 388 (PNIC) */ 389 #define OPMODE_SC 0x80000000 /* special capture effect 390 enable (21041+) */ 391 392 /* CSR7 - Interrupt Enable */ 393 #define CSR_INTEN TULIP_CSR7 394 /* See bits for CSR5 -- Status */ 395 396 397 /* CSR8 - Missed Frames */ 398 #define CSR_MISSED TULIP_CSR8 399 #define MISSED_MFC 0x0000ffff /* missed packet count */ 400 #define MISSED_MFO 0x00010000 /* missed packet count 401 overflowed */ 402 #define MISSED_FOC 0x0ffe0000 /* fifo overflow counter 403 (21140) */ 404 #define MISSED_OCO 0x10000000 /* overflow counter overflowed 405 (21140) */ 406 407 #define MISSED_GETMFC(x) ((x) & MISSED_MFC) 408 #define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 17) 409 410 411 /* CSR9 - MII, SROM, Boot ROM, Ethernet Address ROM register. */ 412 #define CSR_MIIROM TULIP_CSR9 413 #define MIIROM_DATA 0x000000ff /* byte of data from 414 Ethernet Address ROM 415 (21040), byte of data 416 to/from Boot ROM (21041+) */ 417 #define MIIROM_SROMCS 0x00000001 /* SROM chip select */ 418 #define MIIROM_SROMSK 0x00000002 /* SROM clock */ 419 #define MIIROM_SROMDI 0x00000004 /* SROM data in (to) */ 420 #define MIIROM_SROMDO 0x00000008 /* SROM data out (from) */ 421 #define MIIROM_REG 0x00000400 /* external register select */ 422 #define MIIROM_SR 0x00000800 /* SROM select */ 423 #define MIIROM_BR 0x00001000 /* boot ROM select */ 424 #define MIIROM_WR 0x00002000 /* write to boot ROM */ 425 #define MIIROM_RD 0x00004000 /* read from boot ROM */ 426 #define MIIROM_MOD 0x00008000 /* mode select (ro) (21041) */ 427 #define MIIROM_MDC 0x00010000 /* MII clock */ 428 #define MIIROM_MDO 0x00020000 /* MII data out */ 429 #define MIIROM_MIIDIR 0x00040000 /* MII direction mode 430 1 = PHY in read, 431 0 = PHY in write */ 432 #define MIIROM_MDI 0x00080000 /* MII data in */ 433 #define MIIROM_DN 0x80000000 /* data not valid (21040) */ 434 435 /* SROM opcodes */ 436 #define TULIP_SROM_OPC_ERASE 0x04 437 #define TULIP_SROM_OPC_WRITE 0x05 438 #define TULIP_SROM_OPC_READ 0x06 439 440 /* The Lite-On PNIC does this completely differently */ 441 #define PNIC_MIIROM_DATA 0x0000ffff /* mask of data bits ??? */ 442 #define PNIC_MIIROM_BUSY 0x80000000 /* EEPROM is busy */ 443 444 445 /* CSR10 - Boot ROM address register (21041+). */ 446 #define CSR_ROMADDR TULIP_CSR10 447 #define ROMADDR_MASK 0x000003ff /* boot rom address */ 448 449 450 /* CSR11 - General Purpose Timer (21041+). */ 451 #define CSR_GPT TULIP_CSR11 452 #define GPT_VALUE 0x0000ffff /* timer value */ 453 #define GPT_CON 0x00010000 /* continuous mode */ 454 455 456 /* CSR12 - SIA Status Register (21040, 21041). */ 457 #define CSR_SIASTAT TULIP_CSR12 458 #define SIASTAT_PAUI 0x00000001 /* pin AUI/TP indication 459 (21040) */ 460 #define SIASTAT_NCR 0x00000002 /* network connection error */ 461 #define SIASTAT_LKF 0x00000004 /* link fail status */ 462 #define SIASTAT_APS 0x00000008 /* auto polarity status */ 463 #define SIASTAT_DSD 0x00000010 /* PLL self test done */ 464 #define SIASTAT_DSP 0x00000020 /* PLL self test pass */ 465 #define SIASTAT_DAZ 0x00000040 /* PLL all zero */ 466 #define SIASTAT_DAO 0x00000080 /* PLL all one */ 467 #define SIASTAT_SRA 0x00000100 /* selected port receive 468 activity (21041) */ 469 #define SIASTAT_NRA 0x00000200 /* non-selected port 470 receive activity (21041) */ 471 #define SIASTAT_NSN 0x00000400 /* non-stable NLPs detected 472 (21041) */ 473 #define SIASTAT_TRF 0x00000800 /* transmit remote fault 474 (21041) */ 475 #define SIASTAT_ANS 0x00007000 /* autonegotiation state 476 (21041) */ 477 #define SIASTAT_ANS_DIS 0x00000000 /* disabled */ 478 #define SIASTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 479 #define SIASTAT_ANS_ABD 0x00002000 /* ability detect */ 480 #define SIASTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 481 #define SIASTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 482 #define SIASTAT_ANS_FPLGOOD 0x00005000 /* FLP link good */ 483 #define SIASTAT_ANS_LINKCHECK 0x00006000 /* link check */ 484 #define SIASTAT_LPN 0x00008000 /* link partner negotiable 485 (21041) */ 486 #define SIASTAT_LPC 0xffff0000 /* link partner code word */ 487 488 #define SIASTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 489 490 491 /* CSR13 - SIA Connectivity Register (21040, 21041). */ 492 #define CSR_SIACONN TULIP_CSR13 493 #define SIACONN_SRL 0x00000001 /* SIA reset */ 494 #define SIACONN_PS 0x00000002 /* pin AUI/TP selection 495 (21040) */ 496 #define SIACONN_CAC 0x00000004 /* CSR autoconfiguration */ 497 #define SIACONN_AUI 0x00000008 /* select AUI (0 = TP) */ 498 #define SIACONN_EDP 0x00000010 /* SIA PLL external input 499 enable (21040) */ 500 #define SIACONN_ENI 0x00000020 /* encoder input multiplexer 501 (21040) */ 502 #define SIACONN_SIM 0x00000040 /* serial interface input 503 multiplexer (21040) */ 504 #define SIACONN_ASE 0x00000080 /* APLL start enable 505 (21040) */ 506 #define SIACONN_SEL 0x00000f00 /* external port output 507 multiplexer select 508 (21040) */ 509 #define SIACONN_IE 0x00001000 /* input enable (21040) */ 510 #define SIACONN_OE1_3 0x00002000 /* output enable 1, 3 511 (21040) */ 512 #define SIACONN_OE2_4 0x00004000 /* output enable 2, 4 513 (21040) */ 514 #define SIACONN_OE5_6_7 0x00008000 /* output enable 5, 6, 7 515 (21040) */ 516 #define SIACONN_SDM 0x0000ef00 /* SIA diagnostic mode; 517 always set to this value 518 for normal operation 519 (21041) */ 520 521 522 /* CSR14 - SIA Transmit Receive Register (21040, 21041). */ 523 #define CSR_SIATXRX TULIP_CSR14 524 #define SIATXRX_ECEN 0x00000001 /* encoder enable */ 525 #define SIATXRX_LBK 0x00000002 /* loopback enable */ 526 #define SIATXRX_DREN 0x00000004 /* driver enable */ 527 #define SIATXRX_LSE 0x00000008 /* link pulse send enable */ 528 #define SIATXRX_CPEN 0x00000030 /* compensation enable */ 529 #define SIATXRX_CPEN_DIS0 0x00000000 /* disabled */ 530 #define SIATXRX_CPEN_DIS1 0x00000010 /* disabled */ 531 #define SIATXRX_CPEN_HIGHPWR 0x00000020 /* high power */ 532 #define SIATXRX_CPEN_NORMAL 0x00000030 /* normal */ 533 #define SIATXRX_MBO 0x00000040 /* must be one (21041 pass 2) */ 534 #define SIATXRX_ANE 0x00000080 /* autonegotiation enable 535 (21041) */ 536 #define SIATXRX_RSQ 0x00000100 /* receive squelch enable */ 537 #define SIATXRX_CSQ 0x00000200 /* collision squelch enable */ 538 #define SIATXRX_CLD 0x00000400 /* collision detect enable */ 539 #define SIATXRX_SQE 0x00000800 /* signal quality generation 540 enable */ 541 #define SIATXRX_LTE 0x00001000 /* link test enable */ 542 #define SIATXRX_APE 0x00002000 /* auto-polarity enable */ 543 #define SIATXRX_SPP 0x00004000 /* set plarity plus */ 544 #define SIATXRX_TAS 0x00008000 /* 10base-T/AUI autosensing 545 enable (21041) */ 546 547 548 /* CSR15 - SIA General Register (21040, 21041). */ 549 #define CSR_SIAGEN TULIP_CSR15 550 #define SIAGEN_JBD 0x00000001 /* jabber disable */ 551 #define SIAGEN_HUJ 0x00000002 /* host unjab */ 552 #define SIAGEN_JCK 0x00000004 /* jabber clock */ 553 #define SIAGEN_ABM 0x00000008 /* BNC select (21041) */ 554 #define SIAGEN_RWD 0x00000010 /* receive watchdog disable */ 555 #define SIAGEN_RWR 0x00000020 /* receive watchdog release */ 556 #define SIAGEN_LE1 0x00000040 /* LED 1 enable (21041) */ 557 #define SIAGEN_LV1 0x00000080 /* LED 1 value (21041) */ 558 #define SIAGEN_TSCK 0x00000100 /* test clock */ 559 #define SIAGEN_FUSQ 0x00000200 /* force unsquelch */ 560 #define SIAGEN_FLF 0x00000400 /* force link fail */ 561 #define SIAGEN_LSD 0x00000800 /* LED stretch disable 562 (21041) */ 563 #define SIAGEN_DPST 0x00001000 /* PLL self-test start */ 564 #define SIAGEN_FRL 0x00002000 /* force receiver low */ 565 #define SIAGEN_LE2 0x00004000 /* LED 2 enable (21041) */ 566 #define SIAGEN_LV2 0x00008000 /* LED 2 value (21041) */ 567 568 569 /* CSR12 - General Purpose Port (21140+). */ 570 #define CSR_GPP TULIP_CSR12 571 #define GPP_MD 0x000000ff /* general purpose mode/data */ 572 #define GPP_GPC 0x00000100 /* general purpose control */ 573 #define GPP_PNIC_SPEEDSEL 0x00000001 /* 1 == 100mbps, 0 == 10mbps 574 (PNIC) */ 575 #define GPP_PNIC_100TX_LOOP 0x00000002 /* 1 == normal, 0 == loop 576 (PNIC) */ 577 #define GPP_PNIC_BNC_ENB 0x00000004 /* BNC enable (PNIC) */ 578 #define GPP_PNIC_100TX_LINK 0x00000008 /* 100base-TX link (PNIC) */ 579 #define GPP_PNIC_MBO 0x00000030 /* must be one (PNIC) */ 580 581 582 /* CSR15 - Watchdog timer (21140+). */ 583 #define CSR_WATCHDOG TULIP_CSR15 584 #define WATCHDOG_JBD 0x00000001 /* jabber disable */ 585 #define WATCHDOG_HUJ 0x00000002 /* host unjab */ 586 #define WATCHDOG_JCK 0x00000004 /* jabber clock */ 587 #define WATCHDOG_RWD 0x00000010 /* receive watchdog disable */ 588 #define WATCHDOG_RWR 0x00000020 /* receive watchdog release */ 589 590 591 /* 592 * Digital Semiconductor 21040 registers. 593 */ 594 595 /* CSR11 - Full Duplex Register */ 596 #define CSR_21040_FDX TULIP_CSR11 597 #define FDX21040_FDXACV 0x0000ffff /* full duplex 598 autoconfiguration value */ 599 600 601 /* SIA configuration for 10base-T (from the 21040 manual) */ 602 #define SIACONN_21040_10BASET 0x0000ef01 603 #define SIATXRX_21040_10BASET 0x0000ffff 604 #define SIAGEN_21040_10BASET 0x00000000 605 606 607 /* SIA configuration for 10base-T full-duplex (from the 21040 manual) */ 608 #define SIACONN_21040_10BASET_FDX 0x0000ef01 609 #define SIATXRX_21040_10BASET_FDX 0x0000fffd 610 #define SIAGEN_21040_10BASET_FDX 0x00000000 611 612 613 /* SIA configuration for 10base-5 (from the 21040 manual) */ 614 #define SIACONN_21040_AUI 0x0000ef09 615 #define SIATXRX_21040_AUI 0x00000705 616 #define SIAGEN_21040_AUI 0x00000006 617 618 619 /* SIA configuration for External SIA (from the 21040 manual) */ 620 #define SIACONN_21040_EXTSIA 0x00003041 621 #define SIATXRX_21040_EXTSIA 0x00000000 622 #define SIAGEN_21040_EXTSIA 0x00000006 623 624 625 /* 626 * Digital Semiconductor 21041 registers. 627 */ 628 629 /* SIA configuration for 10base-T (from the 21041 manual) */ 630 #define SIACONN_21041_10BASET 0x0000ef01 631 #define SIATXRX_21041_10BASET 0x0000ff3f 632 #define SIAGEN_21041_10BASET 0x00000000 633 634 #define SIACONN_21041P2_10BASET SIACONN_21041_10BASET 635 #define SIATXRX_21041P2_10BASET 0x0000ffff 636 #define SIAGEN_21041P2_10BASET SIAGEN_21041_10BASET 637 638 639 /* SIA configuration for 10base-T full-duplex (from the 21041 manual) */ 640 #define SIACONN_21041_10BASET_FDX 0x0000ef01 641 #define SIATXRX_21041_10BASET_FDX 0x0000ff3d 642 #define SIAGEN_21041_10BASET_FDX 0x00000000 643 644 #define SIACONN_21041P2_10BASET_FDX SIACONN_21041_10BASET_FDX 645 #define SIATXRX_21041P2_10BASET_FDX 0x0000ffff 646 #define SIAGEN_21041P2_10BASET_FDX SIAGEN_21041_10BASET_FDX 647 648 649 /* SIA configuration for 10base-5 (from the 21041 manual) */ 650 #define SIACONN_21041_AUI 0x0000ef09 651 #define SIATXRX_21041_AUI 0x0000f73d 652 #define SIAGEN_21041_AUI 0x0000000e 653 654 #define SIACONN_21041P2_AUI SIACONN_21041_AUI 655 #define SIATXRX_21041P2_AUI 0x0000f7fd 656 #define SIAGEN_21041P2_AUI SIAGEN_21041_AUI 657 658 659 /* SIA configuration for 10base-2 (from the 21041 manual) */ 660 #define SIACONN_21041_BNC 0x0000ef09 661 #define SIATXRX_21041_BNC 0x0000f73d 662 #define SIAGEN_21041_BNC 0x00000006 663 664 #define SIACONN_21041P2_BNC SIACONN_21041_BNC 665 #define SIATXRX_21041P2_BNC 0x0000f7fd 666 #define SIAGEN_21041P2_BNC SIAGEN_21041_BNC 667 668 669 /* 670 * Digital Semiconductor 21142/21143 registers. 671 */ 672 673 /* XXX */ 674 675 /* 676 * Lite-On 82C168/82C169 registers. 677 */ 678 679 /* ENDEC General Register */ 680 #define CSR_PNIC_ENDEC 0x78 681 #define PNIC_ENDEC_JABBERDIS 0x00000001 /* jabber disable */ 682 683 /* SROM Power Register */ 684 #define CSR_PNIC_SROMPWR 0x90 685 686 /* SROM Control Register */ 687 #define CSR_PNIC_SROMCTL 0x98 688 #define PNIC_SROMCTL_addr 0x000000ff /* mask of address bits */ 689 #define PNIC_SROMCTL_READ 0x00000600 /* read command */ 690 691 /* MII Access Register */ 692 #define CSR_PNIC_MII 0xa0 693 #define PNIC_MII_DATA 0x0000ffff /* mask of data bits */ 694 #define PNIC_MII_REG 0x007c0000 /* register mask */ 695 #define PNIC_MII_REGSHIFT 18 696 #define PNIC_MII_PHY 0x0f800000 /* phy mask */ 697 #define PNIC_MII_PHYSHIFT 23 698 #define PNIC_MII_OPCODE 0x30000000 /* opcode mask */ 699 #define PNIC_MII_RESERVED 0x00020000 700 #define PNIC_MII_BUSY 0x80000000 /* MII is busy */ 701 702 /* !@##!@^ PNIC doesn't behave as it should */ 703 #define PNIC_MII_READ 0x60020000 /* read PHY command */ 704 #define PNIC_MII_WRITE 0x50020000 /* write PHY command */ 705 706 /* NWAY Register */ 707 #define CSR_PNIC_NWAY 0xb8 708 #define PNIC_NWAY_RESET 0x00000001 /* reset NWay logic */ 709 #define PNIC_NWAY_PDOWN 0x00000002 /* power down */ 710 #define PNIC_NWAY_BYPASS 0x00000004 /* bypass */ 711 #define PNIC_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 712 #define PNIC_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 713 #define PNIC_NWAY_POLARITY 0x00000020 /* 0 == normal, 1 == reverse */ 714 #define PNIC_NWAY_TP 0x00000040 /* 1 == TP, 0 == AUI */ 715 #define PNIC_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 716 #define PNIC_NWAY_DUPLEX 0x00000100 /* 1 == full, 0 == half */ 717 #define PNIC_NWAY_LINKTEST 0x00000200 /* 1 == on, 0 == off */ 718 #define PNIC_NWAY_AUTODETECT 0x00000400 /* 1 == on, 0 == off */ 719 #define PNIC_NWAY_SPEEDSEL 0x00000800 /* 0 == 10mbps, 1 == 100mbps */ 720 #define PNIC_NWAY_ENB 0x00001000 /* 1 == on, 0 == off */ 721 #define PNIC_NWAY_CAP10T 0x00002000 /* adv. 10baseT */ 722 #define PNIC_NWAY_CAP10TFDX 0x00004000 /* adv. 10baseT-FDX */ 723 #define PNIC_NWAY_CAP100TXFDX 0x00008000 /* adv. 100baseTX-FDX */ 724 #define PNIC_NWAY_CAP100TX 0x00010000 /* adv. 100baseTX */ 725 #define PNIC_NWAY_CAP100T4 0x00020000 /* adv. 100base-T4 */ 726 #define PNIC_NWAY_AUTONEGRSTR 0x02000000 727 #define PNIC_NWAY_REMFAULT 0x04000000 /* remote fault detected */ 728 #define PNIC_NWAY_LPAR10T 0x08000000 /* link part. 10baseT */ 729 #define PNIC_NWAY_LPAR10TFDX 0x10000000 /* link part. 10baseT-FDX */ 730 #define PNIC_NWAY_LPAR100TXFDX 0x20000000 /* link part. 100baseTX-FDX */ 731 #define PNIC_NWAY_LPAR100TX 0x40000000 /* link part. 100baseTX */ 732 #define PNIC_NWAY_LPAR100T4 0x80000000 /* link part. 100base-T4 */ 733 734 735 /* 736 * Macronix 98713, 98713A, 98715, 98715A, 98725 registers. 737 */ 738 739 /* CSR12 - 10base-T Status Port (similar to SIASTAT) */ 740 #define CSR_PMAC_10TSTAT TULIP_CSR12 741 #define PMAC_10TSTAT_LS100 0x00000002 /* link status 100TX 742 0 = link up */ 743 #define PMAC_10TSTAT_LS10 0x00000004 /* link status 10T 744 0 = link up */ 745 #define PMAC_10TSTAT_APS 0x00000008 /* auto polarity status */ 746 #define PMAC_10TSTAT_TRF 0x00000800 /* transmit remote fault 747 (21041) */ 748 #define PMAC_10TSTAT_ANS 0x00007000 /* autonegotiation state 749 (21041) */ 750 #define PMAC_10TSTAT_ANS_DIS 0x00000000 /* disabled */ 751 #define PMAC_10TSTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 752 #define PMAC_10TSTAT_ANS_ABD 0x00002000 /* ability detect */ 753 #define PMAC_10TSTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 754 #define PMAC_10TSTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 755 #define PMAC_10TSTAT_ANS_FPLGOOD 0x00005000 /* FLP link good */ 756 #define PMAC_10TSTAT_ANS_LINKCHECK 0x00006000 /* link check */ 757 #define PMAC_10TSTAT_LPN 0x00008000 /* link partner negotiable 758 (21041) */ 759 #define PMAC_10TSTAT_LPC 0xffff0000 /* link partner code word */ 760 761 #define PMAC_10TSTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 762 763 764 /* CSR13 - NWAY Reset Register */ 765 #define CSR_PMAC_NWAYRESET TULIP_CSR13 766 #define PMAC_NWAYRESET_RESET 0x00000000 /* NWAY reset */ 767 768 769 /* CSR14 - 10base-T Control Port */ 770 #define CSR_PMAC_10TCTL TULIP_CSR14 771 #define PMAC_10TCTL_LBK 0x00000002 /* loopback */ 772 #define PMAC_10TCTL_PWD10 0x00000004 /* power down 10base-T */ 773 #define PMAC_10TCTL_HDE 0x00000040 /* half-duplex enable */ 774 #define PMAC_10TCTL_ANE 0x00000080 /* autonegotiation enable */ 775 #define PMAC_10TCTL_RSQ 0x00000100 /* receive squelch enable */ 776 #define PMAC_10TCTL_LTE 0x00001000 /* link test enable */ 777 #define PMAC_10TCTL_TXH 0x00010000 /* adv. 100tx */ 778 #define PMAC_10TCTL_TXF 0x00020000 /* adv. 100tx-fdx */ 779 #define PMAC_10TCTL_T4 0x00040000 /* adv. 100t4 */ 780 781 782 /* CSR16 - Test Operation Register (a.k.a. Magic Packet Register) */ 783 #define CSR_PMAC_TOR TULIP_CSR16 784 #define PMAC_TOR_98713 0x0F370000 785 #define PMAC_TOR_98715 0x0B3C0000 786 787 788 /* CSR20 - NWAY Status */ 789 #define CSR_PMAC_NWAYSTAT TULIP_CSR20 790 #define PMAC_NWAYSTAT_10TXH 0x08000000 /* 10t accepted */ 791 #define PMAC_NWAYSTAT_10TXF 0x10000000 /* 10t-fdx accepted */ 792 #define PMAC_NWAYSTAT_100TXH 0x20000000 /* 100tx accepted */ 793 #define PMAC_NWAYSTAT_100TXF 0x40000000 /* 100tx-fdx accepted */ 794 #define PMAC_NWAYSTAT_T4 0x80000000 /* 100t4 accepted */ 795 796 797 /* 798 * Winbond 89C840F registers. 799 */ 800 801 /* CSR12 - Current Receive Descriptor Register */ 802 #define CSR_WINB_CURRXDESC TULIP_CSR12 803 804 805 /* CSR13 - Current Receive Buffer Register */ 806 #define CSR_WINB_CURRXBUF TULIP_CSR13 807 808 809 /* CSR14 - Multicast Address Register 0 */ 810 #define CSR_WINB_MAR0 TULIP_CSR14 811 812 813 /* CSR15 - Multicast Address Register 1 */ 814 #define CSR_WINB_MAR1 TULIP_CSR15 815 816 817 /* CSR16 - Node Address Register 0 */ 818 #define CSR_WINB_NODE0 TULIP_CSR16 819 820 821 /* CSR17 - Node Address Register 1 */ 822 #define CSR_WINB_NODE1 TULIP_CSR17 823 824 825 /* CSR18 - Boot ROM Size Register */ 826 #define CSR_WINB_BOOTROMSIZE TULIP_CSR18 827 828 829 /* CSR19 - Current Transmit Descriptor Register */ 830 #define CSR_WINB_CURTXDESC TULIP_CSR19 831 832 833 /* CSR20 - Current Transmit Buffer Register */ 834 #define CSR_WINB_CURTXBUF TULIP_CSR20 835 836 #endif /* _DEV_IC_TULIPREG_H_ */ 837
Indexes created Mon Sep 29 21:09:56 GMT 2025