tulipreg.h revision 1.10
1 /* $NetBSD: tulipreg.h,v 1.10 1999/09/29 18:50:39 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_IC_TULIPREG_H_ 41 #define _DEV_IC_TULIPREG_H_ 42 43 /* 44 * Register description for the Digital Semiconductor ``Tulip'' (21x4x) 45 * Ethernet controller family, and a variety of clone chips, including: 46 * 47 * - Macronix 98713, 98713A, 98715, 98715A, 98725 (PMAC): 48 * 49 * These chips are fairly straight-forward Tulip clones. 50 * The 98713 and 98713A have an MII. All have an internal 51 * transciever capable of NWAY. The 98713A, 98715A, and 52 * 98725 support power management. 53 * 54 * - Lite-On 82C168, 82C169 (PNIC): 55 * 56 * These are Tulip clones with a few small differences; the 57 * EEPROM is accessed totally differently, as is the MII. 58 * The PNIC also has a built-in NWAY transciever. 59 * 60 * - Winbond 89C840F 61 * 62 * Fairly straight-forward Tulip clone, with the exception 63 * that registers don't have a pad longword between them, 64 * and the receive filter is set up differently: instead of 65 * a setup packet, we have 2 32-bit multicast hash table 66 * registers, and 2 station address registers. 67 * 68 * - ADMtek AL981 69 * 70 * These clones have power management, Wake-On-Lan, and don't 71 * use a setup frame to program the receive filter. Instead, 72 * we have station address and multicast hash registers. We 73 * talk to the network over a built-in PHY which we communicate 74 * with over special PHY access registers. Note that starting 75 * at CSR16, the AL981 registers no longer have the pad word! 76 * That is to say, CSR16 is in the normal place, and CSR17 is 77 * CSR16 + 4. 78 * 79 * Some of the clone chips have different registers, and some have 80 * different bits in the same registers. These will be denoted by 81 * PMAC, PNIC, WINB, and ADM in the register/bit names. 82 */ 83 84 /* 85 * Tulip buffer descriptor. Must be 4-byte aligned. 86 * 87 * Note for receive descriptors, the byte count fields must 88 * be a multiple of 4. 89 */ 90 struct tulip_desc { 91 __volatile u_int32_t td_status; /* Status */ 92 __volatile u_int32_t td_ctl; /* Control and Byte Counts */ 93 __volatile u_int32_t td_bufaddr1; /* Buffer Address 1 */ 94 __volatile u_int32_t td_bufaddr2; /* Buffer Address 2 */ 95 }; 96 97 /* 98 * Descriptor Status bits common to transmit and receive. 99 */ 100 #define TDSTAT_OWN 0x80000000 /* Tulip owns descriptor */ 101 #define TDSTAT_ES 0x00008000 /* Error Summary */ 102 103 /* 104 * Descriptor Status bits for Receive Descriptor. 105 */ 106 #define TDSTAT_Rx_FF 0x40000000 /* Filtering Fail */ 107 #define TDSTAT_WINB_Rx_RCMP 0x40000000 /* Receive Complete */ 108 #define TDSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */ 109 #define TDSTAT_Rx_DE 0x00004000 /* Descriptor Error */ 110 #define TDSTAT_Rx_DT 0x00003000 /* Data Type */ 111 #define TDSTAT_Rx_RF 0x00000800 /* Runt Frame */ 112 #define TDSTAT_Rx_MF 0x00000400 /* Multicast Frame */ 113 #define TDSTAT_Rx_FS 0x00000200 /* First Descriptor */ 114 #define TDSTAT_Rx_LS 0x00000100 /* Last Descriptor */ 115 #define TDSTAT_Rx_TL 0x00000080 /* Frame Too Long */ 116 #define TDSTAT_Rx_CS 0x00000040 /* Collision Seen */ 117 #define TDSTAT_Rx_RT 0x00000020 /* Frame Type */ 118 #define TDSTAT_Rx_RW 0x00000010 /* Receive Watchdog */ 119 #define TDSTAT_Rx_RE 0x00000008 /* Report on MII Error */ 120 #define TDSTAT_Rx_DB 0x00000004 /* Dribbling Bit */ 121 #define TDSTAT_Rx_CE 0x00000002 /* CRC Error */ 122 #define TDSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */ 123 124 #define TDSTAT_Rx_LENGTH(x) (((x) & TDSTAT_Rx_FL) >> 16) 125 126 #define TDSTAT_Rx_DT_SR 0x00000000 /* Serial Received Frame */ 127 #define TDSTAT_Rx_DT_IL 0x00001000 /* Internal Loopback Frame */ 128 #define TDSTAT_Rx_DT_EL 0x00002000 /* External Loopback Frame */ 129 #define TDSTAT_Rx_DT_r 0x00003000 /* Reserved */ 130 131 /* 132 * Descriptor Status bits for Transmit Descriptor. 133 */ 134 #define TDSTAT_WINB_Tx_TE 0x00008000 /* Transmit Error */ 135 #define TDSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */ 136 #define TDSTAT_Tx_LO 0x00000800 /* Loss of Carrier */ 137 #define TDSTAT_Tx_NC 0x00000400 /* No Carrier */ 138 #define TDSTAT_Tx_LC 0x00000200 /* Late Collision */ 139 #define TDSTAT_Tx_EC 0x00000100 /* Excessive Collisions */ 140 #define TDSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */ 141 #define TDSTAT_Tx_CC 0x00000078 /* Collision Count */ 142 #define TDSTAT_Tx_LF 0x00000004 /* Link Fail */ 143 #define TDSTAT_Tx_UF 0x00000002 /* Underflow Error */ 144 #define TDSTAT_Tx_DE 0x00000001 /* Deferred */ 145 146 #define TDSTAT_Tx_COLLISIONS(x) (((x) & TDSTAT_Tx_CC) >> 3) 147 148 /* 149 * Descriptor Control bits common to transmit and receive. 150 */ 151 #define TDCTL_SIZE1 0x000007ff /* Size of buffer 1 */ 152 #define TDCTL_SIZE1_SHIFT 0 153 154 #define TDCTL_SIZE2 0x003ff800 /* Size of buffer 2 */ 155 #define TDCTL_SIZE2_SHIFT 11 156 157 #define TDCTL_ER 0x02000000 /* End of Ring */ 158 #define TDCTL_CH 0x01000000 /* Second Address Chained */ 159 160 /* 161 * Descriptor Control bits for Transmit Descriptor. 162 */ 163 #define TDCTL_Tx_IC 0x80000000 /* Interrupt on Completion */ 164 #define TDCTL_Tx_LS 0x40000000 /* Last Segment */ 165 #define TDCTL_Tx_FS 0x20000000 /* First Segment */ 166 #define TDCTL_Tx_FT1 0x10000000 /* Filtering Type 1 */ 167 #define TDCTL_Tx_SET 0x08000000 /* Setup Packet */ 168 #define TDCTL_Tx_AC 0x04000000 /* Add CRC Disable */ 169 #define TDCTL_Tx_DPD 0x00800000 /* Disabled Padding */ 170 #define TDCTL_Tx_FT0 0x00400000 /* Filtering Type 0 */ 171 172 /* 173 * The Tulip filter is programmed by "transmitting" a Setup Packet 174 * (indicated by TDCTL_Tx_SET). The filtering type is indicated 175 * as follows: 176 * 177 * FT1 FT0 Description 178 * --- --- ----------- 179 * 0 0 Perfect Filtering: The Tulip interprets the 180 * descriptor buffer as a table of 16 MAC addresses 181 * that the Tulip should receive. 182 * 183 * 0 1 Hash Filtering: The Tulip interprets the 184 * descriptor buffer as a 512-bit hash table 185 * plus one perfect address. If the incoming 186 * address is Multicast, the hash table filters 187 * the address, else the address is filtered by 188 * the perfect address. 189 * 190 * 1 0 Inverse Filtering: Like Perfect Filtering, except 191 * the table is addresses that the Tulip does NOT 192 * receive. 193 * 194 * 1 1 Hash-only Filtering: Like Hash Filtering, but 195 * physical addresses are matched by the hash table 196 * as well, and not by matching a single perfect 197 * address. 198 * 199 * A Setup Packet must always be 192 bytes long. The Tulip can store 200 * 16 MAC addresses. If not all 16 are specified in Perfect Filtering 201 * or Inverse Filtering mode, then unused entries should duplicate 202 * one of the valid entries. 203 */ 204 #define TDCTL_Tx_FT_PERFECT 0 205 #define TDCTL_Tx_FT_HASH TDCTL_Tx_FT0 206 #define TDCTL_Tx_FT_INVERSE TDCTL_Tx_FT1 207 #define TDCTL_Tx_FT_HASHONLY (TDCTL_Tx_FT1|TDCTL_Tx_FT0) 208 209 #define TULIP_SETUP_PACKET_LEN 192 210 #define TULIP_MAXADDRS 16 211 #define TULIP_MCHASHSIZE 512 212 213 /* 214 * Maximum size of a Tulip Ethernet Address ROM or SROM. 215 */ 216 #define TULIP_MAX_ROM_SIZE 128 217 218 /* 219 * Format of the standard Tulip SROM information: 220 * 221 * Byte offset Size Usage 222 * 0 18 reserved 223 * 18 1 SROM Format Version 224 * 19 1 Chip Count 225 * 20 6 IEEE Network Address 226 * 26 1 Chip 0 Device Number 227 * 27 2 Chip 0 Info Leaf Offset 228 * 29 1 Chip 1 Device Number 229 * 30 2 Chip 1 Info Leaf Offset 230 * 32 1 Chip 2 Device Number 231 * 33 2 Chip 2 Info Leaf Offset 232 * ... 1 Chip n Device Number 233 * ... 2 Chip n Info Leaf Offset 234 * ... ... ... 235 * Chip Info Leaf Information 236 * ... 237 * ... 238 * ... 239 * 126 2 CRC32 checksum 240 */ 241 #define TULIP_ROM_SROM_FORMAT_VERION 18 /* B */ 242 #define TULIP_ROM_CHIP_COUNT 19 /* B */ 243 #define TULIP_ROM_IEEE_NETWORK_ADDRESS 20 244 #define TULIP_ROM_CHIPn_DEVICE_NUMBER(n) (26 + ((n) * 3))/* B */ 245 #define TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(n) (27 + ((n) * 3))/* W */ 246 #define TULIP_ROM_CRC32_CHECKSUM 126 /* W */ 247 248 #define TULIP_ROM_IL_SELECT_CONN_TYPE 0 /* W */ 249 #define TULIP_ROM_IL_MEDIA_COUNT 2 /* B */ 250 #define TULIP_ROM_IL_MEDIAn_BLOCK_BASE 3 251 252 #define SELECT_CONN_TYPE_TP 0x0000 253 #define SELECT_CONN_TYPE_BNC 0x0001 254 #define SELECT_CONN_TYPE_AUI 0x0002 255 #define SELECT_CONN_TYPE_100TX 0x0003 256 #define SELECT_CONN_TYPE_100T4 0x0006 257 #define SELECT_CONN_TYPE_100FX 0x0007 258 #define SELECT_CONN_TYPE MII_10T 0x0009 259 #define SELECT_CONN_TYPE_MII_100TX 0x000d 260 #define SELECT_CONN_TYPE_MII_100T4 0x000f 261 #define SELECT_CONN_TYPE_MII_100FX 0x0010 262 #define SELECT_CONN_TYPE_TP_AUTONEG 0x0100 263 #define SELECT_CONN_TYPE_TP_FDX 0x0204 264 #define SELECT_CONN_TYPE_MII_10T_FDX 0x020a 265 #define SELECT_CONN_TYPE_100TX_FDX 0x020e 266 #define SELECT_CONN_TYPE_MII_100TX_FDX 0x0211 267 #define SELECT_CONN_TYPE_TP_NOLINKPASS 0x0400 268 #define SELECT_CONN_TYPE_ASENSE 0x0800 269 #define SELECT_CONN_TYPE_ASENSE_POWERUP 0x8800 270 #define SELECT_CONN_TYPE_ASENSE_AUTONEG 0x0900 271 272 #define TULIP_ROM_MB_MEDIA_CODE 0x3f 273 #define TULIP_ROM_MB_MEDIA_TP 0x00 274 #define TULIP_ROM_MB_MEDIA_BNC 0x01 275 #define TULIP_ROM_MB_MEDIA_AUI 0x02 276 #define TULIP_ROM_MB_MEDIA_100TX 0x03 277 #define TULIP_ROM_MB_MEDIA_TP_FDX 0x04 278 #define TULIP_ROM_MB_MEDIA_100TX_FDX 0x05 279 #define TULIP_ROM_MB_MEDIA_100T4 0x06 280 #define TULIP_ROM_MB_MEDIA_100FX 0x07 281 #define TULIP_ROM_MB_MEDIA_100FX_FDX 0x08 282 283 #define TULIP_ROM_MB_EXT 0x40 284 285 #define TULIP_ROM_MB_CSR13 1 /* W */ 286 #define TULIP_ROM_MB_CSR14 3 /* W */ 287 #define TULIP_ROM_MB_CSR15 5 /* W */ 288 289 #define TULIP_ROM_MB_SIZE(mc) (((mc) & TULIP_ROM_MB_EXT) ? 7 : 1) 290 291 #define TULIP_ROM_MB_NOINDICATOR 0x8000 292 #define TULIP_ROM_MB_DEFAULT 0x4000 293 #define TULIP_ROM_MB_POLARITY 0x0080 294 #define TULIP_ROM_MB_OPMODE(x) (((x) & 0x71) << 18) 295 #define TULIP_ROM_MB_BITPOS(x) (1 << (((x) & 0x0e) >> 1)) 296 297 #define TULIP_ROM_MB_21140_GPR 0 /* 21140[A] GPR block */ 298 #define TULIP_ROM_MB_21140_MII 1 /* 21140[A] MII block */ 299 #define TULIP_ROM_MB_21142_SIA 2 /* 2114[23] SIA block */ 300 #define TULIP_ROM_MB_21142_MII 3 /* 2114[23] MII block */ 301 #define TULIP_ROM_MB_21143_SYM 4 /* 21143 SYM block */ 302 #define TULIP_ROM_MB_21143_RESET 5 /* 21143 reset block */ 303 304 #define TULIP_ROM_GETW(data, off) ((data)[(off)] | ((data)[(off) + 1]) << 8) 305 306 /* 307 * Tulip control registers. 308 */ 309 310 #define TULIP_CSR0 0x00 311 #define TULIP_CSR1 0x08 312 #define TULIP_CSR2 0x10 313 #define TULIP_CSR3 0x18 314 #define TULIP_CSR4 0x20 315 #define TULIP_CSR5 0x28 316 #define TULIP_CSR6 0x30 317 #define TULIP_CSR7 0x38 318 #define TULIP_CSR8 0x40 319 #define TULIP_CSR9 0x48 320 #define TULIP_CSR10 0x50 321 #define TULIP_CSR11 0x58 322 #define TULIP_CSR12 0x60 323 #define TULIP_CSR13 0x68 324 #define TULIP_CSR14 0x70 325 #define TULIP_CSR15 0x78 326 #define TULIP_CSR16 0x80 327 #define TULIP_CSR17 0x88 328 #define TULIP_CSR18 0x90 329 #define TULIP_CSR19 0x98 330 #define TULIP_CSR20 0xa0 331 332 #define TULIP_CSR_INDEX(csr) ((csr) >> 3) 333 334 /* CSR0 - Bus Mode */ 335 #define CSR_BUSMODE TULIP_CSR0 336 #define BUSMODE_SWR 0x00000001 /* software reset */ 337 #define BUSMODE_BAR 0x00000002 /* bus arbitration */ 338 #define BUSMODE_DSL 0x0000007c /* descriptor skip length */ 339 #define BUSMODE_BLE 0x00000080 /* big endian */ 340 /* programmable burst length */ 341 #define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */ 342 #define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */ 343 #define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */ 344 #define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */ 345 #define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */ 346 #define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */ 347 #define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */ 348 /* cache alignment */ 349 #define BUSMODE_CAL_NONE 0x00000000 /* no alignment */ 350 #define BUSMODE_CAL_8LW 0x00004000 /* 8 longwords */ 351 #define BUSMODE_CAL_16LW 0x00008000 /* 16 longwords */ 352 #define BUSMODE_CAL_32LW 0x0000c000 /* 32 longwords */ 353 #define BUSMODE_DAS 0x00010000 /* diagnostic address space */ 354 /* must be zero on most */ 355 /* transmit auto-poll */ 356 /* 357 * Transmit auto-polling not supported on: 358 * Winbond 89C040F 359 */ 360 #define BUSMODE_TAP_NONE 0x00000000 /* no auto-polling */ 361 #define BUSMODE_TAP_200us 0x00020000 /* 200 uS */ 362 #define BUSMODE_TAP_800us 0x00040000 /* 400 uS */ 363 #define BUSMODE_TAP_1_6ms 0x00060000 /* 1.6 mS */ 364 #define BUSMODE_TAP_12_8us 0x00080000 /* 12.8 uS (21041+) */ 365 #define BUSMODE_TAP_25_6us 0x000a0000 /* 25.6 uS (21041+) */ 366 #define BUSMODE_TAP_51_2us 0x000c0000 /* 51.2 uS (21041+) */ 367 #define BUSMODE_TAP_102_4us 0x000e0000 /* 102.4 uS (21041+) */ 368 #define BUSMODE_DBO 0x00100000 /* desc-only b/e (21041+) */ 369 #define BUSMODE_RME 0x00200000 /* rd/mult enab (21140+) */ 370 #define BUSMODE_WINB_WAIT 0x00200000 /* wait state insertion */ 371 #define BUSMODE_RLE 0x00800000 /* rd/line enab (21140+) */ 372 #define BUSMODE_WLE 0x01000000 /* wt/line enab (21140+) */ 373 #define BUSMODE_PNIC_MBO 0x04000000 /* magic `must be one' bit */ 374 /* on Lite-On PNIC */ 375 376 377 /* CSR1 - Transmit Poll Demand */ 378 #define CSR_TXPOLL TULIP_CSR1 379 #define TXPOLL_TPD 0x00000001 /* transmit poll demand */ 380 381 382 /* CSR2 - Receive Poll Demand */ 383 #define CSR_RXPOLL TULIP_CSR2 384 #define RXPOLL_RPD 0x00000001 /* receive poll demand */ 385 386 387 /* CSR3 - Receive List Base Address */ 388 #define CSR_RXLIST TULIP_CSR3 389 390 /* CSR4 - Transmit List Base Address */ 391 #define CSR_TXLIST TULIP_CSR4 392 393 /* CSR5 - Status */ 394 #define CSR_STATUS TULIP_CSR5 395 #define STATUS_TI 0x00000001 /* transmit interrupt */ 396 #define STATUS_TPS 0x00000002 /* transmit process stopped */ 397 #define STATUS_TU 0x00000004 /* transmit buffer unavail */ 398 #define STATUS_TJT 0x00000008 /* transmit jabber timeout */ 399 #define STATUS_WINB_REI 0x00000008 /* receive early interrupt */ 400 #define STATUS_LNPANC 0x00000010 /* link pass (21041) */ 401 #define STATUS_WINB_RERR 0x00000010 /* receive error */ 402 #define STATUS_UNF 0x00000020 /* transmit underflow */ 403 #define STATUS_RI 0x00000040 /* receive interrupt */ 404 #define STATUS_RU 0x00000080 /* receive buffer unavail */ 405 #define STATUS_RPS 0x00000100 /* receive process stopped */ 406 #define STATUS_RWT 0x00000200 /* receive watchdog timeout */ 407 #define STATUS_AT 0x00000400 /* SIA AUI/TP pin changed 408 (21040) */ 409 #define STATUS_WINB_TEI 0x00000400 /* transmit early interrupt */ 410 #define STATUS_FD 0x00000800 /* full duplex short frame 411 received (21040) */ 412 #define STATUS_TM 0x00000800 /* timer expired (21041) */ 413 #define STATUS_LNF 0x00001000 /* link fail (21040) */ 414 #define STATUS_SE 0x00002000 /* system error */ 415 #define STATUS_ER 0x00004000 /* early receive (21041) */ 416 #define STATUS_AIS 0x00008000 /* abnormal interrupt summary */ 417 #define STATUS_NIS 0x00010000 /* normal interrupt summary */ 418 #define STATUS_RS 0x000e0000 /* receive process state */ 419 #define STATUS_RS_STOPPED 0x00000000 /* Stopped */ 420 #define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive 421 descriptor */ 422 #define STATUS_RS_CHECK 0x00040000 /* Running - check for end 423 of receive */ 424 #define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */ 425 #define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */ 426 #define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive 427 descriptor */ 428 #define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current 429 frame from FIFO */ 430 #define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current 431 frame from FIFO into 432 buffer */ 433 #define STATUS_TS 0x00700000 /* transmit process state */ 434 #define STATUS_TS_STOPPED 0x00000000 /* Stopped */ 435 #define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit 436 descriptor */ 437 #define STATUS_TS_WAIT 0x00200000 /* Running - wait for end 438 of transmission */ 439 #define STATUS_TS_READING 0x00300000 /* Running - read buffer from 440 memory and queue into 441 FIFO */ 442 #define STATUS_TS_RESERVED 0x00400000 /* RESERVED */ 443 #define STATUS_TS_SETUP 0x00500000 /* Running - Setup packet */ 444 #define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */ 445 #define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit 446 descriptor */ 447 #define STATUS_EB 0x03800000 /* error bits */ 448 #define STATUS_EB_PARITY 0x00000000 /* parity errror */ 449 #define STATUS_EB_MABT 0x00800000 /* master abort */ 450 #define STATUS_EB_TABT 0x01000000 /* target abort */ 451 #define STATUS_PNIC_TXABORT 0x04000000 /* transmit aborted */ 452 453 454 /* CSR6 - Operation Mode */ 455 #define CSR_OPMODE TULIP_CSR6 456 #define OPMODE_HP 0x00000001 /* hash/perfect mode (ro) */ 457 #define OPMODE_SR 0x00000002 /* start receive */ 458 #define OPMODE_HO 0x00000004 /* hash only mode (ro) */ 459 #define OPMODE_PB 0x00000008 /* pass bad frames */ 460 #define OPMODE_WINB_APP 0x00000008 /* accept all physcal packet */ 461 #define OPMODE_IF 0x00000010 /* inverse filter mode (ro) */ 462 #define OPMODE_WINB_AMP 0x00000010 /* accept multicast packet */ 463 #define OPMODE_SB 0x00000020 /* start backoff counter */ 464 #define OPMODE_WINB_ABP 0x00000020 /* accept broadcast packet */ 465 #define OPMODE_PR 0x00000040 /* promiscuous mode */ 466 #define OPMODE_WINB_ARP 0x00000040 /* accept runt packet */ 467 #define OPMODE_PM 0x00000080 /* pass all multicast */ 468 #define OPMODE_WINB_AEP 0x00000080 /* accept error packet */ 469 #define OPMODE_FKD 0x00000100 /* flaky oscillator disable */ 470 #define OPMODE_FD 0x00000200 /* full-duplex mode */ 471 #define OPMODE_OM 0x00000c00 /* operating mode */ 472 #define OPMODE_OM_NORMAL 0x00000000 /* normal mode */ 473 #define OPMODE_OM_INTLOOP 0x00000400 /* internal loopback */ 474 #define OPMODE_OM_EXTLOOP 0x00000800 /* external loopback */ 475 #define OPMODE_FC 0x00001000 /* force collision */ 476 #define OPMODE_ST 0x00002000 /* start transmitter */ 477 #define OPMODE_TR 0x0000c000 /* threshold control */ 478 #define OPMODE_TR_72 0x00000000 /* 72 bytes */ 479 #define OPMODE_TR_96 0x00004000 /* 96 bytes */ 480 #define OPMODE_TR_128 0x00008000 /* 128 bytes */ 481 #define OPMODE_TR_160 0x0000c000 /* 160 bytes */ 482 #define OPMODE_WINB_TTH 0x001fc000 /* transmit threshold */ 483 #define OPMODE_WINB_TTH_SHIFT 14 484 #define OPMODE_BP 0x00010000 /* backpressure enable */ 485 #define OPMODE_CA 0x00020000 /* capture effect enable */ 486 #define OPMODE_PNIC_TBEN 0x00020000 /* Tx backoff offset enable */ 487 #define OPMODE_PS 0x00040000 /* port select: 488 1 = MII/SYM, 0 = SRL 489 (21140) */ 490 #define OPMODE_HBD 0x00080000 /* heartbeat disable: 491 set in MII/SYM 100mbps, 492 set according to PHY 493 in MII 10mbps mode 494 (21140) */ 495 #define OPMODE_PNIC_IT 0x00100000 /* immediate transmit */ 496 #define OPMODE_SF 0x00200000 /* store and forward mode 497 (21140) */ 498 #define OPMODE_WINB_REIT 0x1fe00000 /* receive eartly intr thresh */ 499 #define OPMODE_WINB_REIT_SHIFT 21 500 #define OPMODE_TTM 0x00400000 /* Transmit Threshold Mode: 501 1 = 10mbps, 0 = 100mbps 502 (21140) */ 503 #define OPMODE_PCS 0x00800000 /* PCS function (21140) */ 504 #define OPMODE_SCR 0x01000000 /* scrambler mode (21140) */ 505 #define OPMODE_MBO 0x02000000 /* must be one (21140) */ 506 #define OPMODE_PNIC_DRC 0x20000000 /* don't include CRC in Rx 507 frames (PNIC) */ 508 #define OPMODE_WINB_FES 0x20000000 /* fast ethernet select */ 509 #define OPMODE_RA 0x40000000 /* receive all (21140) */ 510 #define OPMODE_PNIC_EED 0x40000000 /* 1 == ext, 0 == int ENDEC 511 (PNIC) */ 512 #define OPMODE_WINB_TEIO 0x40000000 /* transmit early intr on */ 513 #define OPMODE_SC 0x80000000 /* special capture effect 514 enable (21041+) */ 515 #define OPMODE_WINB_REIO 0x80000000 /* receive early intr on */ 516 517 /* Shorthand for media-related OPMODE bits */ 518 #define OPMODE_MEDIA_BITS (OPMODE_PS|OPMODE_PCS|OPMODE_SCR) 519 520 /* CSR7 - Interrupt Enable */ 521 #define CSR_INTEN TULIP_CSR7 522 /* See bits for CSR5 -- Status */ 523 524 525 /* CSR8 - Missed Frames */ 526 #define CSR_MISSED TULIP_CSR8 527 #define MISSED_MFC 0x0000ffff /* missed packet count */ 528 #define MISSED_MFO 0x00010000 /* missed packet count 529 overflowed */ 530 #define MISSED_FOC 0x0ffe0000 /* fifo overflow counter 531 (21140) */ 532 #define MISSED_OCO 0x10000000 /* overflow counter overflowed 533 (21140) */ 534 535 #define MISSED_GETMFC(x) ((x) & MISSED_MFC) 536 #define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 17) 537 538 539 /* CSR9 - MII, SROM, Boot ROM, Ethernet Address ROM register. */ 540 #define CSR_MIIROM TULIP_CSR9 541 #define MIIROM_DATA 0x000000ff /* byte of data from 542 Ethernet Address ROM 543 (21040), byte of data 544 to/from Boot ROM (21041+) */ 545 #define MIIROM_SROMCS 0x00000001 /* SROM chip select */ 546 #define MIIROM_SROMSK 0x00000002 /* SROM clock */ 547 #define MIIROM_SROMDI 0x00000004 /* SROM data in (to) */ 548 #define MIIROM_SROMDO 0x00000008 /* SROM data out (from) */ 549 #define MIIROM_REG 0x00000400 /* external register select */ 550 #define MIIROM_SR 0x00000800 /* SROM select */ 551 #define MIIROM_BR 0x00001000 /* boot ROM select */ 552 #define MIIROM_WR 0x00002000 /* write to boot ROM */ 553 #define MIIROM_RD 0x00004000 /* read from boot ROM */ 554 #define MIIROM_MOD 0x00008000 /* mode select (ro) (21041) */ 555 #define MIIROM_MDC 0x00010000 /* MII clock */ 556 #define MIIROM_MDO 0x00020000 /* MII data out */ 557 #define MIIROM_MIIDIR 0x00040000 /* MII direction mode 558 1 = PHY in read, 559 0 = PHY in write */ 560 #define MIIROM_MDI 0x00080000 /* MII data in */ 561 #define MIIROM_DN 0x80000000 /* data not valid (21040) */ 562 563 /* SROM opcodes */ 564 #define TULIP_SROM_OPC_ERASE 0x04 565 #define TULIP_SROM_OPC_WRITE 0x05 566 #define TULIP_SROM_OPC_READ 0x06 567 568 /* The Lite-On PNIC does this completely differently */ 569 #define PNIC_MIIROM_DATA 0x0000ffff /* mask of data bits ??? */ 570 #define PNIC_MIIROM_BUSY 0x80000000 /* EEPROM is busy */ 571 572 573 /* CSR10 - Boot ROM address register (21041+). */ 574 #define CSR_ROMADDR TULIP_CSR10 575 #define ROMADDR_MASK 0x000003ff /* boot rom address */ 576 577 578 /* CSR11 - General Purpose Timer (21041+). */ 579 #define CSR_GPT TULIP_CSR11 580 #define GPT_VALUE 0x0000ffff /* timer value */ 581 #define GPT_CON 0x00010000 /* continuous mode */ 582 583 584 /* CSR12 - SIA Status Register (21040, 21041). */ 585 #define CSR_SIASTAT TULIP_CSR12 586 #define SIASTAT_PAUI 0x00000001 /* pin AUI/TP indication 587 (21040) */ 588 #define SIASTAT_NCR 0x00000002 /* network connection error */ 589 #define SIASTAT_LKF 0x00000004 /* link fail status */ 590 #define SIASTAT_APS 0x00000008 /* auto polarity status */ 591 #define SIASTAT_DSD 0x00000010 /* PLL self test done */ 592 #define SIASTAT_DSP 0x00000020 /* PLL self test pass */ 593 #define SIASTAT_DAZ 0x00000040 /* PLL all zero */ 594 #define SIASTAT_DAO 0x00000080 /* PLL all one */ 595 #define SIASTAT_SRA 0x00000100 /* selected port receive 596 activity (21041) */ 597 #define SIASTAT_NRA 0x00000200 /* non-selected port 598 receive activity (21041) */ 599 #define SIASTAT_NSN 0x00000400 /* non-stable NLPs detected 600 (21041) */ 601 #define SIASTAT_TRF 0x00000800 /* transmit remote fault 602 (21041) */ 603 #define SIASTAT_ANS 0x00007000 /* autonegotiation state 604 (21041) */ 605 #define SIASTAT_ANS_DIS 0x00000000 /* disabled */ 606 #define SIASTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 607 #define SIASTAT_ANS_ABD 0x00002000 /* ability detect */ 608 #define SIASTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 609 #define SIASTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 610 #define SIASTAT_ANS_FPLGOOD 0x00005000 /* FLP link good */ 611 #define SIASTAT_ANS_LINKCHECK 0x00006000 /* link check */ 612 #define SIASTAT_LPN 0x00008000 /* link partner negotiable 613 (21041) */ 614 #define SIASTAT_LPC 0xffff0000 /* link partner code word */ 615 616 #define SIASTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 617 618 619 /* CSR13 - SIA Connectivity Register (21040, 21041). */ 620 #define CSR_SIACONN TULIP_CSR13 621 #define SIACONN_SRL 0x00000001 /* SIA reset */ 622 #define SIACONN_PS 0x00000002 /* pin AUI/TP selection 623 (21040) */ 624 #define SIACONN_CAC 0x00000004 /* CSR autoconfiguration */ 625 #define SIACONN_AUI 0x00000008 /* select AUI (0 = TP) */ 626 #define SIACONN_EDP 0x00000010 /* SIA PLL external input 627 enable (21040) */ 628 #define SIACONN_ENI 0x00000020 /* encoder input multiplexer 629 (21040) */ 630 #define SIACONN_SIM 0x00000040 /* serial interface input 631 multiplexer (21040) */ 632 #define SIACONN_ASE 0x00000080 /* APLL start enable 633 (21040) */ 634 #define SIACONN_SEL 0x00000f00 /* external port output 635 multiplexer select 636 (21040) */ 637 #define SIACONN_IE 0x00001000 /* input enable (21040) */ 638 #define SIACONN_OE1_3 0x00002000 /* output enable 1, 3 639 (21040) */ 640 #define SIACONN_OE2_4 0x00004000 /* output enable 2, 4 641 (21040) */ 642 #define SIACONN_OE5_6_7 0x00008000 /* output enable 5, 6, 7 643 (21040) */ 644 #define SIACONN_SDM 0x0000ef00 /* SIA diagnostic mode; 645 always set to this value 646 for normal operation 647 (21041) */ 648 649 650 /* CSR14 - SIA Transmit Receive Register (21040, 21041). */ 651 #define CSR_SIATXRX TULIP_CSR14 652 #define SIATXRX_ECEN 0x00000001 /* encoder enable */ 653 #define SIATXRX_LBK 0x00000002 /* loopback enable */ 654 #define SIATXRX_DREN 0x00000004 /* driver enable */ 655 #define SIATXRX_LSE 0x00000008 /* link pulse send enable */ 656 #define SIATXRX_CPEN 0x00000030 /* compensation enable */ 657 #define SIATXRX_CPEN_DIS0 0x00000000 /* disabled */ 658 #define SIATXRX_CPEN_DIS1 0x00000010 /* disabled */ 659 #define SIATXRX_CPEN_HIGHPWR 0x00000020 /* high power */ 660 #define SIATXRX_CPEN_NORMAL 0x00000030 /* normal */ 661 #define SIATXRX_MBO 0x00000040 /* must be one (21041 pass 2) */ 662 #define SIATXRX_ANE 0x00000080 /* autonegotiation enable 663 (21041) */ 664 #define SIATXRX_RSQ 0x00000100 /* receive squelch enable */ 665 #define SIATXRX_CSQ 0x00000200 /* collision squelch enable */ 666 #define SIATXRX_CLD 0x00000400 /* collision detect enable */ 667 #define SIATXRX_SQE 0x00000800 /* signal quality generation 668 enable */ 669 #define SIATXRX_LTE 0x00001000 /* link test enable */ 670 #define SIATXRX_APE 0x00002000 /* auto-polarity enable */ 671 #define SIATXRX_SPP 0x00004000 /* set plarity plus */ 672 #define SIATXRX_TAS 0x00008000 /* 10base-T/AUI autosensing 673 enable (21041) */ 674 675 676 /* CSR15 - SIA General Register (21040, 21041). */ 677 #define CSR_SIAGEN TULIP_CSR15 678 #define SIAGEN_JBD 0x00000001 /* jabber disable */ 679 #define SIAGEN_HUJ 0x00000002 /* host unjab */ 680 #define SIAGEN_JCK 0x00000004 /* jabber clock */ 681 #define SIAGEN_ABM 0x00000008 /* BNC select (21041) */ 682 #define SIAGEN_RWD 0x00000010 /* receive watchdog disable */ 683 #define SIAGEN_RWR 0x00000020 /* receive watchdog release */ 684 #define SIAGEN_LE1 0x00000040 /* LED 1 enable (21041) */ 685 #define SIAGEN_LV1 0x00000080 /* LED 1 value (21041) */ 686 #define SIAGEN_TSCK 0x00000100 /* test clock */ 687 #define SIAGEN_FUSQ 0x00000200 /* force unsquelch */ 688 #define SIAGEN_FLF 0x00000400 /* force link fail */ 689 #define SIAGEN_LSD 0x00000800 /* LED stretch disable 690 (21041) */ 691 #define SIAGEN_DPST 0x00001000 /* PLL self-test start */ 692 #define SIAGEN_FRL 0x00002000 /* force receiver low */ 693 #define SIAGEN_LE2 0x00004000 /* LED 2 enable (21041) */ 694 #define SIAGEN_LV2 0x00008000 /* LED 2 value (21041) */ 695 696 697 /* CSR12 - General Purpose Port (21140+). */ 698 #define CSR_GPP TULIP_CSR12 699 #define GPP_MD 0x000000ff /* general purpose mode/data */ 700 #define GPP_GPC 0x00000100 /* general purpose control */ 701 #define GPP_PNIC_GPD 0x0000000f /* general purpose data */ 702 #define GPP_PNIC_GPC 0x000000f0 /* general purpose control */ 703 704 #define GPP_PNIC_IN(x) (1 << (x)) 705 #define GPP_PNIC_OUT(x, on) (((on) << (x)) | (1 << ((x) + 4))) 706 707 /* 708 * The Lite-On PNIC manual recommends the following for the General Purpose 709 * I/O pins: 710 * 711 * 0 Speed Relay 1 == 100mbps 712 * 1 100mbps loopback 1 == loopback 713 * 2 BNC DC-DC converter 1 == select BNC 714 * 3 Link 100 1 == 100baseTX link status 715 */ 716 #define GPP_PNIC_PIN_SPEED_RLY 0 717 #define GPP_PNIC_PIN_100M_LPKB 1 718 #define GPP_PNIC_PIN_BNC_XMER 2 719 #define GPP_PNIC_PIN_LNK100X 3 720 721 722 /* CSR15 - Watchdog timer (21140+). */ 723 #define CSR_WATCHDOG TULIP_CSR15 724 #define WATCHDOG_JBD 0x00000001 /* jabber disable */ 725 #define WATCHDOG_HUJ 0x00000002 /* host unjab */ 726 #define WATCHDOG_JCK 0x00000004 /* jabber clock */ 727 #define WATCHDOG_RWD 0x00000010 /* receive watchdog disable */ 728 #define WATCHDOG_RWR 0x00000020 /* receive watchdog release */ 729 730 731 /* 732 * Digital Semiconductor 21040 registers. 733 */ 734 735 /* CSR11 - Full Duplex Register */ 736 #define CSR_21040_FDX TULIP_CSR11 737 #define FDX21040_FDXACV 0x0000ffff /* full duplex 738 autoconfiguration value */ 739 740 741 /* SIA configuration for 10base-T (from the 21040 manual) */ 742 #define SIACONN_21040_10BASET 0x0000ef01 743 #define SIATXRX_21040_10BASET 0x0000ffff 744 #define SIAGEN_21040_10BASET 0x00000000 745 746 747 /* SIA configuration for 10base-T full-duplex (from the 21040 manual) */ 748 #define SIACONN_21040_10BASET_FDX 0x0000ef01 749 #define SIATXRX_21040_10BASET_FDX 0x0000fffd 750 #define SIAGEN_21040_10BASET_FDX 0x00000000 751 752 753 /* SIA configuration for 10base-5 (from the 21040 manual) */ 754 #define SIACONN_21040_AUI 0x0000ef09 755 #define SIATXRX_21040_AUI 0x00000705 756 #define SIAGEN_21040_AUI 0x00000006 757 758 759 /* SIA configuration for External SIA (from the 21040 manual) */ 760 #define SIACONN_21040_EXTSIA 0x00003041 761 #define SIATXRX_21040_EXTSIA 0x00000000 762 #define SIAGEN_21040_EXTSIA 0x00000006 763 764 765 /* 766 * Digital Semiconductor 21041 registers. 767 */ 768 769 /* SIA configuration for 10base-T (from the 21041 manual) */ 770 #define SIACONN_21041_10BASET 0x0000ef01 771 #define SIATXRX_21041_10BASET 0x0000ff3f 772 #define SIAGEN_21041_10BASET 0x00000000 773 774 #define SIACONN_21041P2_10BASET SIACONN_21041_10BASET 775 #define SIATXRX_21041P2_10BASET 0x0000ffff 776 #define SIAGEN_21041P2_10BASET SIAGEN_21041_10BASET 777 778 779 /* SIA configuration for 10base-T full-duplex (from the 21041 manual) */ 780 #define SIACONN_21041_10BASET_FDX 0x0000ef01 781 #define SIATXRX_21041_10BASET_FDX 0x0000ff3d 782 #define SIAGEN_21041_10BASET_FDX 0x00000000 783 784 #define SIACONN_21041P2_10BASET_FDX SIACONN_21041_10BASET_FDX 785 #define SIATXRX_21041P2_10BASET_FDX 0x0000ffff 786 #define SIAGEN_21041P2_10BASET_FDX SIAGEN_21041_10BASET_FDX 787 788 789 /* SIA configuration for 10base-5 (from the 21041 manual) */ 790 #define SIACONN_21041_AUI 0x0000ef09 791 #define SIATXRX_21041_AUI 0x0000f73d 792 #define SIAGEN_21041_AUI 0x0000000e 793 794 #define SIACONN_21041P2_AUI SIACONN_21041_AUI 795 #define SIATXRX_21041P2_AUI 0x0000f7fd 796 #define SIAGEN_21041P2_AUI SIAGEN_21041_AUI 797 798 799 /* SIA configuration for 10base-2 (from the 21041 manual) */ 800 #define SIACONN_21041_BNC 0x0000ef09 801 #define SIATXRX_21041_BNC 0x0000f73d 802 #define SIAGEN_21041_BNC 0x00000006 803 804 #define SIACONN_21041P2_BNC SIACONN_21041_BNC 805 #define SIATXRX_21041P2_BNC 0x0000f7fd 806 #define SIAGEN_21041P2_BNC SIAGEN_21041_BNC 807 808 809 /* 810 * Digital Semiconductor 21142/21143 registers. 811 */ 812 813 /* XXX */ 814 815 /* 816 * Lite-On 82C168/82C169 registers. 817 */ 818 819 /* ENDEC General Register */ 820 #define CSR_PNIC_ENDEC 0x78 821 #define PNIC_ENDEC_JDIS 0x00000001 /* jabber disable */ 822 823 /* SROM Power Register */ 824 #define CSR_PNIC_SROMPWR 0x90 825 #define PNIC_SROMPWR_MRLE 0x00000001 /* Memory-Read-Line enable */ 826 #define PNIC_SROMPWR_CB 0x00000002 /* cache boundary alignment 827 burst type; 1 == burst to 828 boundary, 0 == single-cycle 829 to boundary */ 830 831 /* SROM Control Register */ 832 #define CSR_PNIC_SROMCTL 0x98 833 #define PNIC_SROMCTL_addr 0x0000003f /* mask of address bits */ 834 /* XXX THESE ARE WRONG ACCORDING TO THE MANUAL! */ 835 #define PNIC_SROMCTL_READ 0x00000600 /* read command */ 836 837 /* MII Access Register */ 838 #define CSR_PNIC_MII 0xa0 839 #define PNIC_MII_DATA 0x0000ffff /* mask of data bits */ 840 #define PNIC_MII_REG 0x007c0000 /* register mask */ 841 #define PNIC_MII_REGSHIFT 18 842 #define PNIC_MII_PHY 0x0f800000 /* phy mask */ 843 #define PNIC_MII_PHYSHIFT 23 844 #define PNIC_MII_OPCODE 0x30000000 /* opcode mask */ 845 #define PNIC_MII_RESERVED 0x00020000 /* must be one/must be zero; 846 2 bits are described here */ 847 #define PNIC_MII_MBO 0x40000000 /* must be one */ 848 #define PNIC_MII_BUSY 0x80000000 /* MII is busy */ 849 850 #define PNIC_MII_WRITE 0x10000000 /* write PHY command */ 851 #define PNIC_MII_READ 0x20000000 /* read PHY command */ 852 853 /* NWAY Register */ 854 #define CSR_PNIC_NWAY 0xb8 855 #define PNIC_NWAY_RS 0x00000001 /* reset NWay block */ 856 #define PNIC_NWAY_PD 0x00000002 /* power down NWay block */ 857 #define PNIC_NWAY_BX 0x00000004 /* bypass transciever */ 858 #define PNIC_NWAY_LC 0x00000008 /* AUI low current mode */ 859 #define PNIC_NWAY_UV 0x00000010 /* low squelch voltage */ 860 #define PNIC_NWAY_DX 0x00000020 /* disable TP pol. correction */ 861 #define PNIC_NWAY_TW 0x00000040 /* select TP (0 == AUI) */ 862 #define PNIC_NWAY_AF 0x00000080 /* AUI full/half step input 863 voltage */ 864 #define PNIC_NWAY_FD 0x00000100 /* full duplex mode */ 865 #define PNIC_NWAY_DL 0x00000200 /* disable link integrity 866 test */ 867 #define PNIC_NWAY_DM 0x00000400 /* disable AUI/TP autodetect */ 868 #define PNIC_NWAY_100 0x00000800 /* 1 == 100mbps, 0 == 10mbps */ 869 #define PNIC_NWAY_NW 0x00001000 /* enable NWay block */ 870 #define PNIC_NWAY_CAP10T 0x00002000 /* adv. 10baseT */ 871 #define PNIC_NWAY_CAP10TFDX 0x00004000 /* adv. 10baseT-FDX */ 872 #define PNIC_NWAY_CAP100TXFDX 0x00008000 /* adv. 100baseTX-FDX */ 873 #define PNIC_NWAY_CAP100TX 0x00010000 /* adv. 100baseTX */ 874 #define PNIC_NWAY_CAP100T4 0x00020000 /* adv. 100base-T4 */ 875 #define PNIC_NWAY_RN 0x02000000 /* re-negotiate enable */ 876 #define PNIC_NWAY_RF 0x04000000 /* remote fault detected */ 877 #define PNIC_NWAY_LPAR10T 0x08000000 /* link part. 10baseT */ 878 #define PNIC_NWAY_LPAR10TFDX 0x10000000 /* link part. 10baseT-FDX */ 879 #define PNIC_NWAY_LPAR100TXFDX 0x20000000 /* link part. 100baseTX-FDX */ 880 #define PNIC_NWAY_LPAR100TX 0x40000000 /* link part. 100baseTX */ 881 #define PNIC_NWAY_LPAR100T4 0x80000000 /* link part. 100base-T4 */ 882 #define PNIC_NWAY_LPAR_MASK 0xf8000000 883 884 885 /* 886 * Macronix 98713, 98713A, 98715, 98715A, 98725 registers. 887 */ 888 889 /* 890 * Note, the MX98713 is very Tulip-like: 891 * 892 * CSR12 General Purpose Port (like 21140) 893 * CSR13 reserved 894 * CSR14 reserved 895 * CSR15 Watchdog Timer (like 21140) 896 * 897 * The Macronix CSR12, CSR13, CSR14, and CSR15 exist only 898 * on the MX98713A and higher. 899 */ 900 901 /* CSR12 - 10base-T Status Port (similar to SIASTAT) */ 902 #define CSR_PMAC_10TSTAT TULIP_CSR12 903 #define PMAC_10TSTAT_LS100 0x00000002 /* link status 100TX 904 0 = link up */ 905 #define PMAC_10TSTAT_LS10 0x00000004 /* link status 10T 906 0 = link up */ 907 #define PMAC_10TSTAT_APS 0x00000008 /* auto polarity status */ 908 #define PMAC_10TSTAT_TRF 0x00000800 /* transmit remote fault 909 (21041) */ 910 #define PMAC_10TSTAT_ANS 0x00007000 /* autonegotiation state 911 (21041) */ 912 #define PMAC_10TSTAT_ANS_DIS 0x00000000 /* disabled */ 913 #define PMAC_10TSTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 914 #define PMAC_10TSTAT_ANS_ABD 0x00002000 /* ability detect */ 915 #define PMAC_10TSTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 916 #define PMAC_10TSTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 917 #define PMAC_10TSTAT_ANS_FPLGOOD 0x00005000 /* FLP link good */ 918 #define PMAC_10TSTAT_ANS_LINKCHECK 0x00006000 /* link check */ 919 #define PMAC_10TSTAT_LPN 0x00008000 /* link partner negotiable 920 (21041) */ 921 #define PMAC_10TSTAT_LPC 0xffff0000 /* link partner code word */ 922 923 #define PMAC_10TSTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 924 925 926 /* CSR13 - NWAY Reset Register */ 927 #define CSR_PMAC_NWAYRESET TULIP_CSR13 928 #define PMAC_NWAYRESET_RESET 0x00000000 /* NWAY reset */ 929 930 931 /* CSR14 - 10base-T Control Port */ 932 #define CSR_PMAC_10TCTL TULIP_CSR14 933 #define PMAC_10TCTL_LBK 0x00000002 /* loopback */ 934 #define PMAC_10TCTL_PWD10 0x00000004 /* power down 10base-T */ 935 #define PMAC_10TCTL_HDE 0x00000040 /* half-duplex enable */ 936 #define PMAC_10TCTL_ANE 0x00000080 /* autonegotiation enable */ 937 #define PMAC_10TCTL_RSQ 0x00000100 /* receive squelch enable */ 938 #define PMAC_10TCTL_LTE 0x00001000 /* link test enable */ 939 #define PMAC_10TCTL_TXH 0x00010000 /* adv. 100tx */ 940 #define PMAC_10TCTL_TXF 0x00020000 /* adv. 100tx-fdx */ 941 #define PMAC_10TCTL_T4 0x00040000 /* adv. 100t4 */ 942 943 944 /* CSR16 - Test Operation Register (a.k.a. Magic Packet Register) */ 945 #define CSR_PMAC_TOR TULIP_CSR16 946 #define PMAC_TOR_98713 0x0F370000 947 #define PMAC_TOR_98715 0x0B3C0000 948 949 950 /* CSR20 - NWAY Status */ 951 #define CSR_PMAC_NWAYSTAT TULIP_CSR20 952 #define PMAC_NWAYSTAT_10TXH 0x08000000 /* 10t accepted */ 953 #define PMAC_NWAYSTAT_10TXF 0x10000000 /* 10t-fdx accepted */ 954 #define PMAC_NWAYSTAT_100TXH 0x20000000 /* 100tx accepted */ 955 #define PMAC_NWAYSTAT_100TXF 0x40000000 /* 100tx-fdx accepted */ 956 #define PMAC_NWAYSTAT_T4 0x80000000 /* 100t4 accepted */ 957 958 959 /* 960 * Winbond 89C840F registers. 961 */ 962 963 /* CSR12 - Current Receive Descriptor Register */ 964 #define CSR_WINB_CRDAR TULIP_CSR12 965 966 967 /* CSR13 - Current Receive Buffer Register */ 968 #define CSR_WINB_CCRBAR TULIP_CSR13 969 970 971 /* CSR14 - Multicast Address Register 0 */ 972 #define CSR_WINB_CMA0 TULIP_CSR14 973 974 975 /* CSR15 - Multicast Address Register 1 */ 976 #define CSR_WINB_CMA1 TULIP_CSR15 977 978 979 /* CSR16 - Physical Address Register 0 */ 980 #define CSR_WINB_CPA0 TULIP_CSR16 981 982 983 /* CSR17 - Physical Address Register 1 */ 984 #define CSR_WINB_CPA1 TULIP_CSR17 985 986 987 /* CSR18 - Boot ROM Size Register */ 988 #define CSR_WINB_CBRCR TULIP_CSR18 989 #define WINB_CBRCR_NONE 0x00000000 /* no boot rom */ 990 /* 0x00000001 also no boot rom */ 991 #define WINB_CBRCR_8K 0x00000002 /* 8k */ 992 #define WINB_CBRCR_16K 0x00000003 /* 16k */ 993 #define WINB_CBRCR_32K 0x00000004 /* 32k */ 994 #define WINB_CBRCR_64K 0x00000005 /* 64k */ 995 #define WINB_CBRCR_128K 0x00000006 /* 128k */ 996 #define WINB_CBRCR_256K 0x00000007 997 998 999 /* CSR19 - Current Transmit Descriptor Register */ 1000 #define CSR_WINB_CTDAR TULIP_CSR19 1001 1002 1003 /* CSR20 - Current Transmit Buffer Register */ 1004 #define CSR_WINB_CTBAR TULIP_CSR20 1005 1006 1007 /* 1008 * ADMtek AL981 registers 1009 * 1010 * We define these as strict byte offsets into PCI space, since 1011 * not all of them have consistent access rules. 1012 */ 1013 1014 /* CSR13 - Wake-up Control/Status Register */ 1015 #define CSR_ADM_WCSR 0x68 1016 #define ADM_WCSR_LSC 0x00000001 /* link status changed */ 1017 #define ADM_WCSR_MPR 0x00000002 /* magic packet received */ 1018 #define ADM_WCSR_WFR 0x00000004 /* wake up frame received */ 1019 #define ADM_WCSR_LSCE 0x00000100 /* link status changed en. */ 1020 #define ADM_WCSR_MPRE 0x00000200 /* magic packet receive en. */ 1021 #define ADM_WCSR_WFRE 0x00000400 /* wake up frame receive en. */ 1022 #define ADM_WCSR_LINKON 0x00010000 /* link-on detect en. */ 1023 #define ADM_WCSR_LINKOFF 0x00020000 /* link-off detect en. */ 1024 #define ADM_WCSR_WP5E 0x02000000 /* wake up pat. 5 en. */ 1025 #define ADM_WCSR_WP4E 0x04000000 /* wake up pat. 4 en. */ 1026 #define ADM_WCSR_WP3E 0x08000000 /* wake up pat. 3 en. */ 1027 #define ADM_WCSR_WP2E 0x10000000 /* wake up pat. 2 en. */ 1028 #define ADM_WCSR_WP1E 0x20000000 /* wake up pat. 1 en. */ 1029 #define ADM_WCSR_CRCT 0x40000000 /* CRC-16 type: 1030 0 == 0000 initial 1031 1 == ffff initial */ 1032 1033 1034 /* CSR14 - Wake-up Pattern Data Register */ 1035 #define CSR_ADM_WPDR 0x70 1036 1037 /* 1038 * 25 consecutive longword writes are issued to WPDR to 1039 * program the wake-up pattern filter. The data written 1040 * is as follows: 1041 * 1042 * XXX 1043 */ 1044 1045 1046 /* CSR15 - see 21140 CSR15 (Watchdog Timer) */ 1047 1048 1049 /* CSR16 - Assistant CSR5 (Status Register 2) */ 1050 #define CSR_ADM_ASR 0x80 1051 /* 0 - 14: same as CSR5 */ 1052 #define ADM_ASR_AAISS 0x00080000 /* added abnormal int. sum. */ 1053 #define ADM_ASR_ANISS 0x00010000 /* added normal int. sum. */ 1054 /* XXX Receive state */ 1055 /* XXX Transmit state */ 1056 #define ADM_ASR_BET 0x03800000 /* bus error type */ 1057 #define ADM_ASR_BET_PERR 0x00000000 /* parity error */ 1058 #define ADM_ASR_BET_MABT 0x00800000 /* master abort */ 1059 #define ADM_ASR_BET_TABT 0x01000000 /* target abort */ 1060 #define ADM_ASR_PFR 0x04000000 /* PAUSE frame received */ 1061 #define ADM_ASR_TDIS 0x10000000 /* transmit def. int. status */ 1062 #define ADM_ASR_XIS 0x20000000 /* xcvr int. status */ 1063 #define ADM_ASR_REIS 0x40000000 /* receive early int. status */ 1064 #define ADM_ASR_TEIS 0x80000000 /* transmit early int. status */ 1065 1066 1067 /* CSR17 - Assistant CSR7 (Interrupt Enable Register 2) */ 1068 #define CSR_ADM_AIE 0x84 1069 /* See CSR16 for valid bits */ 1070 1071 1072 /* CSR18 - Command Register */ 1073 #define CSR_ADM_CR 0x88 1074 #define ADM_CR_ATUR 0x00000001 /* auto. tx underrun recover */ 1075 #define ADM_CR_SINT 0x00000002 /* software interrupt */ 1076 #define ADM_CR_DRT 0x0000000c /* drain recieve threshold */ 1077 #define ADM_CR_DRT_8LW 0x00000000 /* 8 longwords */ 1078 #define ADM_CR_DRT_16LW 0x00000004 /* 16 longwords */ 1079 #define ADM_CR_DRT_SF 0x00000008 /* store-and-forward */ 1080 #define ADM_CR_RTE 0x00000010 /* receive threshold enable */ 1081 #define ADM_CR_PAUSE 0x00000020 /* enable PAUSE function */ 1082 #define ADM_CR_RWP 0x00000040 /* reset wake-up pattern 1083 data register pointer */ 1084 /* 16 - 31 are automatically recalled from the EEPROM */ 1085 #define ADM_CR_WOL 0x00040000 /* wake-on-lan enable */ 1086 #define ADM_CR_PM 0x00080000 /* power management enable */ 1087 #define ADM_CR_RFS 0x00600000 /* Receive FIFO size */ 1088 #define ADM_CR_RFS_1K 0x00600000 /* 1K FIFO */ 1089 #define ADM_CR_RFS_2K 0x00400000 /* 2K FIFO */ 1090 #define ADM_CR_LEDMODE 0x00800000 /* LED mode */ 1091 #define ADM_CR_AUXCL 0x30000000 /* aux current load */ 1092 #define ADM_CR_D3CS 0x80000000 /* D3 cold wake up enable */ 1093 1094 1095 /* CSR19 - PCI bus performance counter */ 1096 #define CSR_ADM_PCIC 0x8c 1097 #define ADM_PCIC_DWCNT 0x000000ff /* double-word count of 1098 last bus-master 1099 transaction */ 1100 #define ADM_PCIC_CLKCNT 0xffff0000 /* number of PCI clocks 1101 between read request 1102 and access completed */ 1103 1104 /* CSR20 - Power Management Control/Status Register */ 1105 #define CSR_ADM_PMCSR 0x90 1106 /* 1107 * This register is also mapped into the PCI configuration 1108 * space as the PMCSR. 1109 */ 1110 1111 1112 /* CSR23 - Transmit Burst Count/Time Out Register */ 1113 #define CSR_ADM_TXBR 0x9c 1114 /* XXX */ 1115 1116 1117 /* CSR24 - Flash ROM Port Register */ 1118 #define CSR_ADM_FROM 0xa0 1119 /* XXX */ 1120 1121 1122 /* CSR25 - Physical Address Register 0 */ 1123 #define CSR_ADM_PAR0 0xa4 1124 1125 1126 /* CSR26 - Physical Address Register 1 */ 1127 #define CSR_ADM_PAR1 0xa8 1128 1129 1130 /* CSR27 - Multicast Address Register 0 */ 1131 #define CSR_ADM_MAR0 0xac 1132 1133 1134 /* CSR28 - Multicast Address Register 1 */ 1135 #define CSR_ADM_MAR1 0xb0 1136 1137 1138 /* Internal PHY registers are mapped here (lower 16 bits valid) */ 1139 1140 #define CSR_ADM_BMCR 0xb4 1141 #define CSR_ADM_BMSR 0xb8 1142 #define CSR_ADM_PHYIDR1 0xbc 1143 #define CSR_ADM_PHYIDR2 0xc0 1144 #define CSR_ADM_ANAR 0xc4 1145 #define CSR_ADM_ANLPAR 0xc8 1146 #define CSR_ADM_ANER 0xcc 1147 1148 /* XCVR Mode Control Register */ 1149 #define CSR_ADM_XMC 0xd0 1150 1151 /* XCVR Configuration Information and Interrupt Status Register */ 1152 #define CSR_ADM_XCIIS 0xd4 1153 1154 /* XCVR Interrupt Enable Register */ 1155 #define CSR_ADM_XIE 0xd8 1156 1157 /* XCVR 100baseTX PHY Control/Status Register */ 1158 #define CSR_ADM_100CTR 0xdc 1159 1160 #endif /* _DEV_IC_TULIPREG_H_ */ 1161
Indexes created Mon Sep 29 21:09:56 GMT 2025