tulipreg.h revision 1.11
1 /* $NetBSD: tulipreg.h,v 1.11 1999/09/30 17:41:39 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_IC_TULIPREG_H_ 41 #define _DEV_IC_TULIPREG_H_ 42 43 /* 44 * Register description for the Digital Semiconductor ``Tulip'' (21x4x) 45 * Ethernet controller family, and a variety of clone chips, including: 46 * 47 * - Macronix 98713, 98713A, 98715, 98715A, 98725 (PMAC): 48 * 49 * These chips are fairly straight-forward Tulip clones. 50 * The 98713 is a very close 21140A clone. It has GPR 51 * and MII media, and a GPIO facility, and uses the ISV 52 * SROM format (or, at least, should, because of the GPIO 53 * facility). The 98713A has MII, no GPIO facility, and 54 * an internal NWay block. The 98715, 98715A, and 98725 55 * have only GPR media and the NWay block. The 98715, 56 * 98715A, and 98725 support power management. 57 * 58 * - Lite-On 82C115 (PNIC II): 59 * 60 * A clone of the Macronix MX98725, with the following differences: 61 * 62 * - Wake-On-LAN support 63 * - 128-bit multicast hash table rather than the 64 * standard 512-bit hash table 65 * - 802.3x flow control 66 * 67 * - Lite-On 82C168, 82C169 (PNIC): 68 * 69 * Pretty close, with only a few minor differences: 70 * 71 * - EEPROM is accessed completely differently. 72 * - MII is accessed completely differently. 73 * - No SIO facility (due to the above two differences). 74 * - GPIO interface is different than the 21140's. 75 * - Boards that lack PHYs use the internal NWay block 76 * and transciever. 77 * 78 * - Winbond 89C840F 79 * 80 * Less similar, but still roughly compatible (enough so 81 * that the driver can be adapted, at least): 82 * 83 * - Registers lack the pad word between them. 84 * - Instead of a setup frame, there are two station 85 * address registers and two multicast hash table 86 * registers (64-bit multicast hash table). 87 * - Only supported media interface is MII-over-SIO. 88 * - Different OPMODE register bits for various things 89 * (mostly media related). 90 * 91 * - ADMtek AL981 92 * 93 * Another pretty-close clone: 94 * 95 * - Wake-On-LAN support 96 * - Instead of a setup frame, there are two station 97 * address registers and two multicast hash table 98 * registers (64-bit multicast hash table). 99 * - 802.3x flow control 100 * - Only supported media interface is built-in PHY 101 * which is accessed through a set of special registers. 102 * - Not all registers have the pad word between them, 103 * but luckily, there are all AL981-specific registers, 104 * so this is easy to deal with. 105 * 106 * Some of the clone chips have different registers, and some have 107 * different bits in the same registers. These will be denoted by 108 * PMAC, PNICII, PNIC, WINB, and ADM in the register/bit names. 109 */ 110 111 /* 112 * Tulip buffer descriptor. Must be 4-byte aligned. 113 * 114 * Note for receive descriptors, the byte count fields must 115 * be a multiple of 4. 116 */ 117 struct tulip_desc { 118 __volatile u_int32_t td_status; /* Status */ 119 __volatile u_int32_t td_ctl; /* Control and Byte Counts */ 120 __volatile u_int32_t td_bufaddr1; /* Buffer Address 1 */ 121 __volatile u_int32_t td_bufaddr2; /* Buffer Address 2 */ 122 }; 123 124 /* 125 * Descriptor Status bits common to transmit and receive. 126 */ 127 #define TDSTAT_OWN 0x80000000 /* Tulip owns descriptor */ 128 #define TDSTAT_ES 0x00008000 /* Error Summary */ 129 130 /* 131 * Descriptor Status bits for Receive Descriptor. 132 */ 133 #define TDSTAT_Rx_FF 0x40000000 /* Filtering Fail */ 134 #define TDSTAT_WINB_Rx_RCMP 0x40000000 /* Receive Complete */ 135 #define TDSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */ 136 #define TDSTAT_Rx_DE 0x00004000 /* Descriptor Error */ 137 #define TDSTAT_Rx_DT 0x00003000 /* Data Type */ 138 #define TDSTAT_Rx_RF 0x00000800 /* Runt Frame */ 139 #define TDSTAT_Rx_MF 0x00000400 /* Multicast Frame */ 140 #define TDSTAT_Rx_FS 0x00000200 /* First Descriptor */ 141 #define TDSTAT_Rx_LS 0x00000100 /* Last Descriptor */ 142 #define TDSTAT_Rx_TL 0x00000080 /* Frame Too Long */ 143 #define TDSTAT_Rx_CS 0x00000040 /* Collision Seen */ 144 #define TDSTAT_Rx_RT 0x00000020 /* Frame Type */ 145 #define TDSTAT_Rx_RW 0x00000010 /* Receive Watchdog */ 146 #define TDSTAT_Rx_RE 0x00000008 /* Report on MII Error */ 147 #define TDSTAT_Rx_DB 0x00000004 /* Dribbling Bit */ 148 #define TDSTAT_Rx_CE 0x00000002 /* CRC Error */ 149 #define TDSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */ 150 151 #define TDSTAT_Rx_LENGTH(x) (((x) & TDSTAT_Rx_FL) >> 16) 152 153 #define TDSTAT_Rx_DT_SR 0x00000000 /* Serial Received Frame */ 154 #define TDSTAT_Rx_DT_IL 0x00001000 /* Internal Loopback Frame */ 155 #define TDSTAT_Rx_DT_EL 0x00002000 /* External Loopback Frame */ 156 #define TDSTAT_Rx_DT_r 0x00003000 /* Reserved */ 157 158 /* 159 * Descriptor Status bits for Transmit Descriptor. 160 */ 161 #define TDSTAT_WINB_Tx_TE 0x00008000 /* Transmit Error */ 162 #define TDSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */ 163 #define TDSTAT_Tx_LO 0x00000800 /* Loss of Carrier */ 164 #define TDSTAT_Tx_NC 0x00000400 /* No Carrier */ 165 #define TDSTAT_Tx_LC 0x00000200 /* Late Collision */ 166 #define TDSTAT_Tx_EC 0x00000100 /* Excessive Collisions */ 167 #define TDSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */ 168 #define TDSTAT_Tx_CC 0x00000078 /* Collision Count */ 169 #define TDSTAT_Tx_LF 0x00000004 /* Link Fail */ 170 #define TDSTAT_Tx_UF 0x00000002 /* Underflow Error */ 171 #define TDSTAT_Tx_DE 0x00000001 /* Deferred */ 172 173 #define TDSTAT_Tx_COLLISIONS(x) (((x) & TDSTAT_Tx_CC) >> 3) 174 175 /* 176 * Descriptor Control bits common to transmit and receive. 177 */ 178 #define TDCTL_SIZE1 0x000007ff /* Size of buffer 1 */ 179 #define TDCTL_SIZE1_SHIFT 0 180 181 #define TDCTL_SIZE2 0x003ff800 /* Size of buffer 2 */ 182 #define TDCTL_SIZE2_SHIFT 11 183 184 #define TDCTL_ER 0x02000000 /* End of Ring */ 185 #define TDCTL_CH 0x01000000 /* Second Address Chained */ 186 187 /* 188 * Descriptor Control bits for Transmit Descriptor. 189 */ 190 #define TDCTL_Tx_IC 0x80000000 /* Interrupt on Completion */ 191 #define TDCTL_Tx_LS 0x40000000 /* Last Segment */ 192 #define TDCTL_Tx_FS 0x20000000 /* First Segment */ 193 #define TDCTL_Tx_FT1 0x10000000 /* Filtering Type 1 */ 194 #define TDCTL_Tx_SET 0x08000000 /* Setup Packet */ 195 #define TDCTL_Tx_AC 0x04000000 /* Add CRC Disable */ 196 #define TDCTL_Tx_DPD 0x00800000 /* Disabled Padding */ 197 #define TDCTL_Tx_FT0 0x00400000 /* Filtering Type 0 */ 198 199 /* 200 * The Tulip filter is programmed by "transmitting" a Setup Packet 201 * (indicated by TDCTL_Tx_SET). The filtering type is indicated 202 * as follows: 203 * 204 * FT1 FT0 Description 205 * --- --- ----------- 206 * 0 0 Perfect Filtering: The Tulip interprets the 207 * descriptor buffer as a table of 16 MAC addresses 208 * that the Tulip should receive. 209 * 210 * 0 1 Hash Filtering: The Tulip interprets the 211 * descriptor buffer as a 512-bit hash table 212 * plus one perfect address. If the incoming 213 * address is Multicast, the hash table filters 214 * the address, else the address is filtered by 215 * the perfect address. 216 * 217 * 1 0 Inverse Filtering: Like Perfect Filtering, except 218 * the table is addresses that the Tulip does NOT 219 * receive. 220 * 221 * 1 1 Hash-only Filtering: Like Hash Filtering, but 222 * physical addresses are matched by the hash table 223 * as well, and not by matching a single perfect 224 * address. 225 * 226 * A Setup Packet must always be 192 bytes long. The Tulip can store 227 * 16 MAC addresses. If not all 16 are specified in Perfect Filtering 228 * or Inverse Filtering mode, then unused entries should duplicate 229 * one of the valid entries. 230 */ 231 #define TDCTL_Tx_FT_PERFECT 0 232 #define TDCTL_Tx_FT_HASH TDCTL_Tx_FT0 233 #define TDCTL_Tx_FT_INVERSE TDCTL_Tx_FT1 234 #define TDCTL_Tx_FT_HASHONLY (TDCTL_Tx_FT1|TDCTL_Tx_FT0) 235 236 #define TULIP_SETUP_PACKET_LEN 192 237 #define TULIP_MAXADDRS 16 238 #define TULIP_MCHASHSIZE 512 239 #define TULIP_PNICII_HASHSIZE 128 240 241 /* 242 * Maximum size of a Tulip Ethernet Address ROM or SROM. 243 */ 244 #define TULIP_MAX_ROM_SIZE 128 245 246 /* 247 * Format of the standard Tulip SROM information: 248 * 249 * Byte offset Size Usage 250 * 0 18 reserved 251 * 18 1 SROM Format Version 252 * 19 1 Chip Count 253 * 20 6 IEEE Network Address 254 * 26 1 Chip 0 Device Number 255 * 27 2 Chip 0 Info Leaf Offset 256 * 29 1 Chip 1 Device Number 257 * 30 2 Chip 1 Info Leaf Offset 258 * 32 1 Chip 2 Device Number 259 * 33 2 Chip 2 Info Leaf Offset 260 * ... 1 Chip n Device Number 261 * ... 2 Chip n Info Leaf Offset 262 * ... ... ... 263 * Chip Info Leaf Information 264 * ... 265 * ... 266 * ... 267 * 126 2 CRC32 checksum 268 */ 269 #define TULIP_ROM_SROM_FORMAT_VERION 18 /* B */ 270 #define TULIP_ROM_CHIP_COUNT 19 /* B */ 271 #define TULIP_ROM_IEEE_NETWORK_ADDRESS 20 272 #define TULIP_ROM_CHIPn_DEVICE_NUMBER(n) (26 + ((n) * 3))/* B */ 273 #define TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(n) (27 + ((n) * 3))/* W */ 274 #define TULIP_ROM_CRC32_CHECKSUM 126 /* W */ 275 276 #define TULIP_ROM_IL_SELECT_CONN_TYPE 0 /* W */ 277 #define TULIP_ROM_IL_MEDIA_COUNT 2 /* B */ 278 #define TULIP_ROM_IL_MEDIAn_BLOCK_BASE 3 279 280 #define SELECT_CONN_TYPE_TP 0x0000 281 #define SELECT_CONN_TYPE_BNC 0x0001 282 #define SELECT_CONN_TYPE_AUI 0x0002 283 #define SELECT_CONN_TYPE_100TX 0x0003 284 #define SELECT_CONN_TYPE_100T4 0x0006 285 #define SELECT_CONN_TYPE_100FX 0x0007 286 #define SELECT_CONN_TYPE MII_10T 0x0009 287 #define SELECT_CONN_TYPE_MII_100TX 0x000d 288 #define SELECT_CONN_TYPE_MII_100T4 0x000f 289 #define SELECT_CONN_TYPE_MII_100FX 0x0010 290 #define SELECT_CONN_TYPE_TP_AUTONEG 0x0100 291 #define SELECT_CONN_TYPE_TP_FDX 0x0204 292 #define SELECT_CONN_TYPE_MII_10T_FDX 0x020a 293 #define SELECT_CONN_TYPE_100TX_FDX 0x020e 294 #define SELECT_CONN_TYPE_MII_100TX_FDX 0x0211 295 #define SELECT_CONN_TYPE_TP_NOLINKPASS 0x0400 296 #define SELECT_CONN_TYPE_ASENSE 0x0800 297 #define SELECT_CONN_TYPE_ASENSE_POWERUP 0x8800 298 #define SELECT_CONN_TYPE_ASENSE_AUTONEG 0x0900 299 300 #define TULIP_ROM_MB_MEDIA_CODE 0x3f 301 #define TULIP_ROM_MB_MEDIA_TP 0x00 302 #define TULIP_ROM_MB_MEDIA_BNC 0x01 303 #define TULIP_ROM_MB_MEDIA_AUI 0x02 304 #define TULIP_ROM_MB_MEDIA_100TX 0x03 305 #define TULIP_ROM_MB_MEDIA_TP_FDX 0x04 306 #define TULIP_ROM_MB_MEDIA_100TX_FDX 0x05 307 #define TULIP_ROM_MB_MEDIA_100T4 0x06 308 #define TULIP_ROM_MB_MEDIA_100FX 0x07 309 #define TULIP_ROM_MB_MEDIA_100FX_FDX 0x08 310 311 #define TULIP_ROM_MB_EXT 0x40 312 313 #define TULIP_ROM_MB_CSR13 1 /* W */ 314 #define TULIP_ROM_MB_CSR14 3 /* W */ 315 #define TULIP_ROM_MB_CSR15 5 /* W */ 316 317 #define TULIP_ROM_MB_SIZE(mc) (((mc) & TULIP_ROM_MB_EXT) ? 7 : 1) 318 319 #define TULIP_ROM_MB_NOINDICATOR 0x8000 320 #define TULIP_ROM_MB_DEFAULT 0x4000 321 #define TULIP_ROM_MB_POLARITY 0x0080 322 #define TULIP_ROM_MB_OPMODE(x) (((x) & 0x71) << 18) 323 #define TULIP_ROM_MB_BITPOS(x) (1 << (((x) & 0x0e) >> 1)) 324 325 #define TULIP_ROM_MB_21140_GPR 0 /* 21140[A] GPR block */ 326 #define TULIP_ROM_MB_21140_MII 1 /* 21140[A] MII block */ 327 #define TULIP_ROM_MB_21142_SIA 2 /* 2114[23] SIA block */ 328 #define TULIP_ROM_MB_21142_MII 3 /* 2114[23] MII block */ 329 #define TULIP_ROM_MB_21143_SYM 4 /* 21143 SYM block */ 330 #define TULIP_ROM_MB_21143_RESET 5 /* 21143 reset block */ 331 332 #define TULIP_ROM_GETW(data, off) ((data)[(off)] | ((data)[(off) + 1]) << 8) 333 334 /* 335 * Tulip control registers. 336 */ 337 338 #define TULIP_CSR0 0x00 339 #define TULIP_CSR1 0x08 340 #define TULIP_CSR2 0x10 341 #define TULIP_CSR3 0x18 342 #define TULIP_CSR4 0x20 343 #define TULIP_CSR5 0x28 344 #define TULIP_CSR6 0x30 345 #define TULIP_CSR7 0x38 346 #define TULIP_CSR8 0x40 347 #define TULIP_CSR9 0x48 348 #define TULIP_CSR10 0x50 349 #define TULIP_CSR11 0x58 350 #define TULIP_CSR12 0x60 351 #define TULIP_CSR13 0x68 352 #define TULIP_CSR14 0x70 353 #define TULIP_CSR15 0x78 354 #define TULIP_CSR16 0x80 355 #define TULIP_CSR17 0x88 356 #define TULIP_CSR18 0x90 357 #define TULIP_CSR19 0x98 358 #define TULIP_CSR20 0xa0 359 #define TULIP_CSR21 0xa8 360 #define TULIP_CSR22 0xb0 361 #define TULIP_CSR23 0xb8 362 #define TULIP_CSR24 0xc0 363 #define TULIP_CSR25 0xc8 364 #define TULIP_CSR26 0xd0 365 #define TULIP_CSR27 0xd8 366 #define TULIP_CSR28 0xe0 367 #define TULIP_CSR29 0xe8 368 #define TULIP_CSR30 0xf0 369 #define TULIP_CSR31 0xf8 370 371 #define TULIP_CSR_INDEX(csr) ((csr) >> 3) 372 373 /* CSR0 - Bus Mode */ 374 #define CSR_BUSMODE TULIP_CSR0 375 #define BUSMODE_SWR 0x00000001 /* software reset */ 376 #define BUSMODE_BAR 0x00000002 /* bus arbitration */ 377 #define BUSMODE_DSL 0x0000007c /* descriptor skip length */ 378 #define BUSMODE_BLE 0x00000080 /* big endian */ 379 /* programmable burst length */ 380 #define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */ 381 #define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */ 382 #define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */ 383 #define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */ 384 #define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */ 385 #define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */ 386 #define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */ 387 /* cache alignment */ 388 #define BUSMODE_CAL_NONE 0x00000000 /* no alignment */ 389 #define BUSMODE_CAL_8LW 0x00004000 /* 8 longwords */ 390 #define BUSMODE_CAL_16LW 0x00008000 /* 16 longwords */ 391 #define BUSMODE_CAL_32LW 0x0000c000 /* 32 longwords */ 392 #define BUSMODE_DAS 0x00010000 /* diagnostic address space */ 393 /* must be zero on most */ 394 /* transmit auto-poll */ 395 /* 396 * Transmit auto-polling not supported on: 397 * Winbond 89C040F 398 */ 399 #define BUSMODE_TAP_NONE 0x00000000 /* no auto-polling */ 400 #define BUSMODE_TAP_200us 0x00020000 /* 200 uS */ 401 #define BUSMODE_TAP_800us 0x00040000 /* 400 uS */ 402 #define BUSMODE_TAP_1_6ms 0x00060000 /* 1.6 mS */ 403 #define BUSMODE_TAP_12_8us 0x00080000 /* 12.8 uS (21041+) */ 404 #define BUSMODE_TAP_25_6us 0x000a0000 /* 25.6 uS (21041+) */ 405 #define BUSMODE_TAP_51_2us 0x000c0000 /* 51.2 uS (21041+) */ 406 #define BUSMODE_TAP_102_4us 0x000e0000 /* 102.4 uS (21041+) */ 407 #define BUSMODE_DBO 0x00100000 /* desc-only b/e (21041+) */ 408 #define BUSMODE_RME 0x00200000 /* rd/mult enab (21140+) */ 409 #define BUSMODE_WINB_WAIT 0x00200000 /* wait state insertion */ 410 #define BUSMODE_RLE 0x00800000 /* rd/line enab (21140+) */ 411 #define BUSMODE_WLE 0x01000000 /* wt/line enab (21140+) */ 412 #define BUSMODE_PNIC_MBO 0x04000000 /* magic `must be one' bit */ 413 /* on Lite-On PNIC */ 414 415 416 /* CSR1 - Transmit Poll Demand */ 417 #define CSR_TXPOLL TULIP_CSR1 418 #define TXPOLL_TPD 0x00000001 /* transmit poll demand */ 419 420 421 /* CSR2 - Receive Poll Demand */ 422 #define CSR_RXPOLL TULIP_CSR2 423 #define RXPOLL_RPD 0x00000001 /* receive poll demand */ 424 425 426 /* CSR3 - Receive List Base Address */ 427 #define CSR_RXLIST TULIP_CSR3 428 429 /* CSR4 - Transmit List Base Address */ 430 #define CSR_TXLIST TULIP_CSR4 431 432 /* CSR5 - Status */ 433 #define CSR_STATUS TULIP_CSR5 434 #define STATUS_TI 0x00000001 /* transmit interrupt */ 435 #define STATUS_TPS 0x00000002 /* transmit process stopped */ 436 #define STATUS_TU 0x00000004 /* transmit buffer unavail */ 437 #define STATUS_TJT 0x00000008 /* transmit jabber timeout */ 438 #define STATUS_WINB_REI 0x00000008 /* receive early interrupt */ 439 #define STATUS_LNPANC 0x00000010 /* link pass (21041) */ 440 #define STATUS_WINB_RERR 0x00000010 /* receive error */ 441 #define STATUS_UNF 0x00000020 /* transmit underflow */ 442 #define STATUS_RI 0x00000040 /* receive interrupt */ 443 #define STATUS_RU 0x00000080 /* receive buffer unavail */ 444 #define STATUS_RPS 0x00000100 /* receive process stopped */ 445 #define STATUS_RWT 0x00000200 /* receive watchdog timeout */ 446 #define STATUS_AT 0x00000400 /* SIA AUI/TP pin changed 447 (21040) */ 448 #define STATUS_PMAC_ETI 0x00000400 /* early transmit interrupt */ 449 #define STATUS_WINB_TEI 0x00000400 /* transmit early interrupt */ 450 #define STATUS_FD 0x00000800 /* full duplex short frame 451 received (21040) */ 452 #define STATUS_TM 0x00000800 /* timer expired (21041) */ 453 #define STATUS_LNF 0x00001000 /* link fail (21040) */ 454 #define STATUS_SE 0x00002000 /* system error */ 455 #define STATUS_ER 0x00004000 /* early receive (21041) */ 456 #define STATUS_AIS 0x00008000 /* abnormal interrupt summary */ 457 #define STATUS_NIS 0x00010000 /* normal interrupt summary */ 458 #define STATUS_RS 0x000e0000 /* receive process state */ 459 #define STATUS_RS_STOPPED 0x00000000 /* Stopped */ 460 #define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive 461 descriptor */ 462 #define STATUS_RS_CHECK 0x00040000 /* Running - check for end 463 of receive */ 464 #define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */ 465 #define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */ 466 #define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive 467 descriptor */ 468 #define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current 469 frame from FIFO */ 470 #define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current 471 frame from FIFO into 472 buffer */ 473 #define STATUS_TS 0x00700000 /* transmit process state */ 474 #define STATUS_TS_STOPPED 0x00000000 /* Stopped */ 475 #define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit 476 descriptor */ 477 #define STATUS_TS_WAIT 0x00200000 /* Running - wait for end 478 of transmission */ 479 #define STATUS_TS_READING 0x00300000 /* Running - read buffer from 480 memory and queue into 481 FIFO */ 482 #define STATUS_TS_RESERVED 0x00400000 /* RESERVED */ 483 #define STATUS_TS_SETUP 0x00500000 /* Running - Setup packet */ 484 #define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */ 485 #define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit 486 descriptor */ 487 #define STATUS_EB 0x03800000 /* error bits */ 488 #define STATUS_EB_PARITY 0x00000000 /* parity errror */ 489 #define STATUS_EB_MABT 0x00800000 /* master abort */ 490 #define STATUS_EB_TABT 0x01000000 /* target abort */ 491 #define STATUS_PNIC_TXABORT 0x04000000 /* transmit aborted */ 492 #define STATUS_PMAC_LC 0x08000000 /* 100baseTX link change */ 493 #define STATUS_PMAC_WKUPI 0x10000000 /* wake up event */ 494 495 496 /* CSR6 - Operation Mode */ 497 #define CSR_OPMODE TULIP_CSR6 498 #define OPMODE_HP 0x00000001 /* hash/perfect mode (ro) */ 499 #define OPMODE_SR 0x00000002 /* start receive */ 500 #define OPMODE_HO 0x00000004 /* hash only mode (ro) */ 501 #define OPMODE_PB 0x00000008 /* pass bad frames */ 502 #define OPMODE_WINB_APP 0x00000008 /* accept all physcal packet */ 503 #define OPMODE_IF 0x00000010 /* inverse filter mode (ro) */ 504 #define OPMODE_WINB_AMP 0x00000010 /* accept multicast packet */ 505 #define OPMODE_SB 0x00000020 /* start backoff counter */ 506 #define OPMODE_WINB_ABP 0x00000020 /* accept broadcast packet */ 507 #define OPMODE_PR 0x00000040 /* promiscuous mode */ 508 #define OPMODE_WINB_ARP 0x00000040 /* accept runt packet */ 509 #define OPMODE_PM 0x00000080 /* pass all multicast */ 510 #define OPMODE_WINB_AEP 0x00000080 /* accept error packet */ 511 #define OPMODE_FKD 0x00000100 /* flaky oscillator disable */ 512 #define OPMODE_FD 0x00000200 /* full-duplex mode */ 513 #define OPMODE_OM 0x00000c00 /* operating mode */ 514 #define OPMODE_OM_NORMAL 0x00000000 /* normal mode */ 515 #define OPMODE_OM_INTLOOP 0x00000400 /* internal loopback */ 516 #define OPMODE_OM_EXTLOOP 0x00000800 /* external loopback */ 517 #define OPMODE_FC 0x00001000 /* force collision */ 518 #define OPMODE_ST 0x00002000 /* start transmitter */ 519 #define OPMODE_TR 0x0000c000 /* threshold control */ 520 #define OPMODE_TR_72 0x00000000 /* 72 bytes */ 521 #define OPMODE_TR_96 0x00004000 /* 96 bytes */ 522 #define OPMODE_TR_128 0x00008000 /* 128 bytes */ 523 #define OPMODE_TR_160 0x0000c000 /* 160 bytes */ 524 #define OPMODE_WINB_TTH 0x001fc000 /* transmit threshold */ 525 #define OPMODE_WINB_TTH_SHIFT 14 526 #define OPMODE_BP 0x00010000 /* backpressure enable */ 527 #define OPMODE_CA 0x00020000 /* capture effect enable */ 528 #define OPMODE_PNIC_TBEN 0x00020000 /* Tx backoff offset enable */ 529 #define OPMODE_PS 0x00040000 /* port select: 530 1 = MII/SYM, 0 = SRL 531 (21140) */ 532 #define OPMODE_HBD 0x00080000 /* heartbeat disable: 533 set in MII/SYM 100mbps, 534 set according to PHY 535 in MII 10mbps mode 536 (21140) */ 537 #define OPMODE_PNIC_IT 0x00100000 /* immediate transmit */ 538 #define OPMODE_SF 0x00200000 /* store and forward mode 539 (21140) */ 540 #define OPMODE_WINB_REIT 0x1fe00000 /* receive eartly intr thresh */ 541 #define OPMODE_WINB_REIT_SHIFT 21 542 #define OPMODE_TTM 0x00400000 /* Transmit Threshold Mode: 543 1 = 10mbps, 0 = 100mbps 544 (21140) */ 545 #define OPMODE_PCS 0x00800000 /* PCS function (21140) */ 546 #define OPMODE_SCR 0x01000000 /* scrambler mode (21140) */ 547 #define OPMODE_MBO 0x02000000 /* must be one (21140) */ 548 #define OPMODE_PNIC_DRC 0x20000000 /* don't include CRC in Rx 549 frames (PNIC) */ 550 #define OPMODE_WINB_FES 0x20000000 /* fast ethernet select */ 551 #define OPMODE_RA 0x40000000 /* receive all (21140) */ 552 #define OPMODE_PNIC_EED 0x40000000 /* 1 == ext, 0 == int ENDEC 553 (PNIC) */ 554 #define OPMODE_WINB_TEIO 0x40000000 /* transmit early intr on */ 555 #define OPMODE_SC 0x80000000 /* special capture effect 556 enable (21041+) */ 557 #define OPMODE_WINB_REIO 0x80000000 /* receive early intr on */ 558 559 /* Shorthand for media-related OPMODE bits */ 560 #define OPMODE_MEDIA_BITS (OPMODE_PS|OPMODE_PCS|OPMODE_SCR) 561 562 /* CSR7 - Interrupt Enable */ 563 #define CSR_INTEN TULIP_CSR7 564 /* See bits for CSR5 -- Status */ 565 566 567 /* CSR8 - Missed Frames */ 568 #define CSR_MISSED TULIP_CSR8 569 #define MISSED_MFC 0x0000ffff /* missed packet count */ 570 #define MISSED_MFO 0x00010000 /* missed packet count 571 overflowed */ 572 #define MISSED_FOC 0x0ffe0000 /* fifo overflow counter 573 (21140) */ 574 #define MISSED_OCO 0x10000000 /* overflow counter overflowed 575 (21140) */ 576 577 #define MISSED_GETMFC(x) ((x) & MISSED_MFC) 578 #define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 17) 579 580 581 /* CSR9 - MII, SROM, Boot ROM, Ethernet Address ROM register. */ 582 #define CSR_MIIROM TULIP_CSR9 583 #define MIIROM_DATA 0x000000ff /* byte of data from 584 Ethernet Address ROM 585 (21040), byte of data 586 to/from Boot ROM (21041+) */ 587 #define MIIROM_SROMCS 0x00000001 /* SROM chip select */ 588 #define MIIROM_SROMSK 0x00000002 /* SROM clock */ 589 #define MIIROM_SROMDI 0x00000004 /* SROM data in (to) */ 590 #define MIIROM_SROMDO 0x00000008 /* SROM data out (from) */ 591 #define MIIROM_REG 0x00000400 /* external register select */ 592 #define MIIROM_SR 0x00000800 /* SROM select */ 593 #define MIIROM_BR 0x00001000 /* boot ROM select */ 594 #define MIIROM_WR 0x00002000 /* write to boot ROM */ 595 #define MIIROM_RD 0x00004000 /* read from boot ROM */ 596 #define MIIROM_MOD 0x00008000 /* mode select (ro) (21041) */ 597 #define MIIROM_MDC 0x00010000 /* MII clock */ 598 #define MIIROM_MDO 0x00020000 /* MII data out */ 599 #define MIIROM_MIIDIR 0x00040000 /* MII direction mode 600 1 = PHY in read, 601 0 = PHY in write */ 602 #define MIIROM_MDI 0x00080000 /* MII data in */ 603 #define MIIROM_DN 0x80000000 /* data not valid (21040) */ 604 605 #define MIIROM_PMAC_LED0SEL 0x10000000 /* 0 == LED0 activity (def) 606 1 == LED0 speed */ 607 #define MIIROM_PMAC_LED1SEL 0x20000000 /* 0 == LED1 link (def) 608 1 == LED1 link/act */ 609 #define MIIROM_PMAC_LED2SEL 0x40000000 /* 0 == LED2 speed (def) 610 1 == LED2 collision */ 611 #define MIIROM_PMAC_LED3SEL 0x80000000 /* 0 == LED3 receive (def) 612 1 == LED3 full duplex */ 613 614 /* SROM opcodes */ 615 #define TULIP_SROM_OPC_ERASE 0x04 616 #define TULIP_SROM_OPC_WRITE 0x05 617 #define TULIP_SROM_OPC_READ 0x06 618 619 /* The Lite-On PNIC does this completely differently */ 620 #define PNIC_MIIROM_DATA 0x0000ffff /* mask of data bits ??? */ 621 #define PNIC_MIIROM_BUSY 0x80000000 /* EEPROM is busy */ 622 623 624 /* CSR10 - Boot ROM address register (21041+). */ 625 #define CSR_ROMADDR TULIP_CSR10 626 #define ROMADDR_MASK 0x000003ff /* boot rom address */ 627 628 629 /* CSR11 - General Purpose Timer (21041+). */ 630 #define CSR_GPT TULIP_CSR11 631 #define GPT_VALUE 0x0000ffff /* timer value */ 632 #define GPT_CON 0x00010000 /* continuous mode */ 633 634 635 /* CSR12 - SIA Status Register (21040, 21041). */ 636 #define CSR_SIASTAT TULIP_CSR12 637 #define SIASTAT_PAUI 0x00000001 /* pin AUI/TP indication 638 (21040) */ 639 #define SIASTAT_NCR 0x00000002 /* network connection error */ 640 #define SIASTAT_LKF 0x00000004 /* link fail status */ 641 #define SIASTAT_APS 0x00000008 /* auto polarity status */ 642 #define SIASTAT_DSD 0x00000010 /* PLL self test done */ 643 #define SIASTAT_DSP 0x00000020 /* PLL self test pass */ 644 #define SIASTAT_DAZ 0x00000040 /* PLL all zero */ 645 #define SIASTAT_DAO 0x00000080 /* PLL all one */ 646 #define SIASTAT_SRA 0x00000100 /* selected port receive 647 activity (21041) */ 648 #define SIASTAT_NRA 0x00000200 /* non-selected port 649 receive activity (21041) */ 650 #define SIASTAT_NSN 0x00000400 /* non-stable NLPs detected 651 (21041) */ 652 #define SIASTAT_TRF 0x00000800 /* transmit remote fault 653 (21041) */ 654 #define SIASTAT_ANS 0x00007000 /* autonegotiation state 655 (21041) */ 656 #define SIASTAT_ANS_DIS 0x00000000 /* disabled */ 657 #define SIASTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 658 #define SIASTAT_ANS_ABD 0x00002000 /* ability detect */ 659 #define SIASTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 660 #define SIASTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 661 #define SIASTAT_ANS_FPLGOOD 0x00005000 /* FLP link good */ 662 #define SIASTAT_ANS_LINKCHECK 0x00006000 /* link check */ 663 #define SIASTAT_LPN 0x00008000 /* link partner negotiable 664 (21041) */ 665 #define SIASTAT_LPC 0xffff0000 /* link partner code word */ 666 667 #define SIASTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 668 669 670 /* CSR13 - SIA Connectivity Register (21040, 21041). */ 671 #define CSR_SIACONN TULIP_CSR13 672 #define SIACONN_SRL 0x00000001 /* SIA reset */ 673 #define SIACONN_PS 0x00000002 /* pin AUI/TP selection 674 (21040) */ 675 #define SIACONN_CAC 0x00000004 /* CSR autoconfiguration */ 676 #define SIACONN_AUI 0x00000008 /* select AUI (0 = TP) */ 677 #define SIACONN_EDP 0x00000010 /* SIA PLL external input 678 enable (21040) */ 679 #define SIACONN_ENI 0x00000020 /* encoder input multiplexer 680 (21040) */ 681 #define SIACONN_SIM 0x00000040 /* serial interface input 682 multiplexer (21040) */ 683 #define SIACONN_ASE 0x00000080 /* APLL start enable 684 (21040) */ 685 #define SIACONN_SEL 0x00000f00 /* external port output 686 multiplexer select 687 (21040) */ 688 #define SIACONN_IE 0x00001000 /* input enable (21040) */ 689 #define SIACONN_OE1_3 0x00002000 /* output enable 1, 3 690 (21040) */ 691 #define SIACONN_OE2_4 0x00004000 /* output enable 2, 4 692 (21040) */ 693 #define SIACONN_OE5_6_7 0x00008000 /* output enable 5, 6, 7 694 (21040) */ 695 #define SIACONN_SDM 0x0000ef00 /* SIA diagnostic mode; 696 always set to this value 697 for normal operation 698 (21041) */ 699 700 701 /* CSR14 - SIA Transmit Receive Register (21040, 21041). */ 702 #define CSR_SIATXRX TULIP_CSR14 703 #define SIATXRX_ECEN 0x00000001 /* encoder enable */ 704 #define SIATXRX_LBK 0x00000002 /* loopback enable */ 705 #define SIATXRX_DREN 0x00000004 /* driver enable */ 706 #define SIATXRX_LSE 0x00000008 /* link pulse send enable */ 707 #define SIATXRX_CPEN 0x00000030 /* compensation enable */ 708 #define SIATXRX_CPEN_DIS0 0x00000000 /* disabled */ 709 #define SIATXRX_CPEN_DIS1 0x00000010 /* disabled */ 710 #define SIATXRX_CPEN_HIGHPWR 0x00000020 /* high power */ 711 #define SIATXRX_CPEN_NORMAL 0x00000030 /* normal */ 712 #define SIATXRX_MBO 0x00000040 /* must be one (21041 pass 2) */ 713 #define SIATXRX_ANE 0x00000080 /* autonegotiation enable 714 (21041) */ 715 #define SIATXRX_RSQ 0x00000100 /* receive squelch enable */ 716 #define SIATXRX_CSQ 0x00000200 /* collision squelch enable */ 717 #define SIATXRX_CLD 0x00000400 /* collision detect enable */ 718 #define SIATXRX_SQE 0x00000800 /* signal quality generation 719 enable */ 720 #define SIATXRX_LTE 0x00001000 /* link test enable */ 721 #define SIATXRX_APE 0x00002000 /* auto-polarity enable */ 722 #define SIATXRX_SPP 0x00004000 /* set plarity plus */ 723 #define SIATXRX_TAS 0x00008000 /* 10base-T/AUI autosensing 724 enable (21041) */ 725 726 727 /* CSR15 - SIA General Register (21040, 21041). */ 728 #define CSR_SIAGEN TULIP_CSR15 729 #define SIAGEN_JBD 0x00000001 /* jabber disable */ 730 #define SIAGEN_HUJ 0x00000002 /* host unjab */ 731 #define SIAGEN_JCK 0x00000004 /* jabber clock */ 732 #define SIAGEN_ABM 0x00000008 /* BNC select (21041) */ 733 #define SIAGEN_RWD 0x00000010 /* receive watchdog disable */ 734 #define SIAGEN_RWR 0x00000020 /* receive watchdog release */ 735 #define SIAGEN_LE1 0x00000040 /* LED 1 enable (21041) */ 736 #define SIAGEN_LV1 0x00000080 /* LED 1 value (21041) */ 737 #define SIAGEN_TSCK 0x00000100 /* test clock */ 738 #define SIAGEN_FUSQ 0x00000200 /* force unsquelch */ 739 #define SIAGEN_FLF 0x00000400 /* force link fail */ 740 #define SIAGEN_LSD 0x00000800 /* LED stretch disable 741 (21041) */ 742 #define SIAGEN_DPST 0x00001000 /* PLL self-test start */ 743 #define SIAGEN_FRL 0x00002000 /* force receiver low */ 744 #define SIAGEN_LE2 0x00004000 /* LED 2 enable (21041) */ 745 #define SIAGEN_LV2 0x00008000 /* LED 2 value (21041) */ 746 747 748 /* CSR12 - General Purpose Port (21140+). */ 749 #define CSR_GPP TULIP_CSR12 750 #define GPP_MD 0x000000ff /* general purpose mode/data */ 751 #define GPP_GPC 0x00000100 /* general purpose control */ 752 #define GPP_PNIC_GPD 0x0000000f /* general purpose data */ 753 #define GPP_PNIC_GPC 0x000000f0 /* general purpose control */ 754 755 #define GPP_PNIC_IN(x) (1 << (x)) 756 #define GPP_PNIC_OUT(x, on) (((on) << (x)) | (1 << ((x) + 4))) 757 758 /* 759 * The Lite-On PNIC manual recommends the following for the General Purpose 760 * I/O pins: 761 * 762 * 0 Speed Relay 1 == 100mbps 763 * 1 100mbps loopback 1 == loopback 764 * 2 BNC DC-DC converter 1 == select BNC 765 * 3 Link 100 1 == 100baseTX link status 766 */ 767 #define GPP_PNIC_PIN_SPEED_RLY 0 768 #define GPP_PNIC_PIN_100M_LPKB 1 769 #define GPP_PNIC_PIN_BNC_XMER 2 770 #define GPP_PNIC_PIN_LNK100X 3 771 772 773 /* CSR15 - Watchdog timer (21140+). */ 774 #define CSR_WATCHDOG TULIP_CSR15 775 #define WATCHDOG_JBD 0x00000001 /* jabber disable */ 776 #define WATCHDOG_HUJ 0x00000002 /* host unjab */ 777 #define WATCHDOG_JCK 0x00000004 /* jabber clock */ 778 #define WATCHDOG_RWD 0x00000010 /* receive watchdog disable */ 779 #define WATCHDOG_RWR 0x00000020 /* receive watchdog release */ 780 781 782 /* 783 * Digital Semiconductor 21040 registers. 784 */ 785 786 /* CSR11 - Full Duplex Register */ 787 #define CSR_21040_FDX TULIP_CSR11 788 #define FDX21040_FDXACV 0x0000ffff /* full duplex 789 autoconfiguration value */ 790 791 792 /* SIA configuration for 10base-T (from the 21040 manual) */ 793 #define SIACONN_21040_10BASET 0x0000ef01 794 #define SIATXRX_21040_10BASET 0x0000ffff 795 #define SIAGEN_21040_10BASET 0x00000000 796 797 798 /* SIA configuration for 10base-T full-duplex (from the 21040 manual) */ 799 #define SIACONN_21040_10BASET_FDX 0x0000ef01 800 #define SIATXRX_21040_10BASET_FDX 0x0000fffd 801 #define SIAGEN_21040_10BASET_FDX 0x00000000 802 803 804 /* SIA configuration for 10base-5 (from the 21040 manual) */ 805 #define SIACONN_21040_AUI 0x0000ef09 806 #define SIATXRX_21040_AUI 0x00000705 807 #define SIAGEN_21040_AUI 0x00000006 808 809 810 /* SIA configuration for External SIA (from the 21040 manual) */ 811 #define SIACONN_21040_EXTSIA 0x00003041 812 #define SIATXRX_21040_EXTSIA 0x00000000 813 #define SIAGEN_21040_EXTSIA 0x00000006 814 815 816 /* 817 * Digital Semiconductor 21041 registers. 818 */ 819 820 /* SIA configuration for 10base-T (from the 21041 manual) */ 821 #define SIACONN_21041_10BASET 0x0000ef01 822 #define SIATXRX_21041_10BASET 0x0000ff3f 823 #define SIAGEN_21041_10BASET 0x00000000 824 825 #define SIACONN_21041P2_10BASET SIACONN_21041_10BASET 826 #define SIATXRX_21041P2_10BASET 0x0000ffff 827 #define SIAGEN_21041P2_10BASET SIAGEN_21041_10BASET 828 829 830 /* SIA configuration for 10base-T full-duplex (from the 21041 manual) */ 831 #define SIACONN_21041_10BASET_FDX 0x0000ef01 832 #define SIATXRX_21041_10BASET_FDX 0x0000ff3d 833 #define SIAGEN_21041_10BASET_FDX 0x00000000 834 835 #define SIACONN_21041P2_10BASET_FDX SIACONN_21041_10BASET_FDX 836 #define SIATXRX_21041P2_10BASET_FDX 0x0000ffff 837 #define SIAGEN_21041P2_10BASET_FDX SIAGEN_21041_10BASET_FDX 838 839 840 /* SIA configuration for 10base-5 (from the 21041 manual) */ 841 #define SIACONN_21041_AUI 0x0000ef09 842 #define SIATXRX_21041_AUI 0x0000f73d 843 #define SIAGEN_21041_AUI 0x0000000e 844 845 #define SIACONN_21041P2_AUI SIACONN_21041_AUI 846 #define SIATXRX_21041P2_AUI 0x0000f7fd 847 #define SIAGEN_21041P2_AUI SIAGEN_21041_AUI 848 849 850 /* SIA configuration for 10base-2 (from the 21041 manual) */ 851 #define SIACONN_21041_BNC 0x0000ef09 852 #define SIATXRX_21041_BNC 0x0000f73d 853 #define SIAGEN_21041_BNC 0x00000006 854 855 #define SIACONN_21041P2_BNC SIACONN_21041_BNC 856 #define SIATXRX_21041P2_BNC 0x0000f7fd 857 #define SIAGEN_21041P2_BNC SIAGEN_21041_BNC 858 859 860 /* 861 * Digital Semiconductor 21142/21143 registers. 862 */ 863 864 /* XXX */ 865 866 /* 867 * Lite-On 82C168/82C169 registers. 868 */ 869 870 /* ENDEC General Register */ 871 #define CSR_PNIC_ENDEC 0x78 872 #define PNIC_ENDEC_JDIS 0x00000001 /* jabber disable */ 873 874 /* SROM Power Register */ 875 #define CSR_PNIC_SROMPWR 0x90 876 #define PNIC_SROMPWR_MRLE 0x00000001 /* Memory-Read-Line enable */ 877 #define PNIC_SROMPWR_CB 0x00000002 /* cache boundary alignment 878 burst type; 1 == burst to 879 boundary, 0 == single-cycle 880 to boundary */ 881 882 /* SROM Control Register */ 883 #define CSR_PNIC_SROMCTL 0x98 884 #define PNIC_SROMCTL_addr 0x0000003f /* mask of address bits */ 885 /* XXX THESE ARE WRONG ACCORDING TO THE MANUAL! */ 886 #define PNIC_SROMCTL_READ 0x00000600 /* read command */ 887 888 /* MII Access Register */ 889 #define CSR_PNIC_MII 0xa0 890 #define PNIC_MII_DATA 0x0000ffff /* mask of data bits */ 891 #define PNIC_MII_REG 0x007c0000 /* register mask */ 892 #define PNIC_MII_REGSHIFT 18 893 #define PNIC_MII_PHY 0x0f800000 /* phy mask */ 894 #define PNIC_MII_PHYSHIFT 23 895 #define PNIC_MII_OPCODE 0x30000000 /* opcode mask */ 896 #define PNIC_MII_RESERVED 0x00020000 /* must be one/must be zero; 897 2 bits are described here */ 898 #define PNIC_MII_MBO 0x40000000 /* must be one */ 899 #define PNIC_MII_BUSY 0x80000000 /* MII is busy */ 900 901 #define PNIC_MII_WRITE 0x10000000 /* write PHY command */ 902 #define PNIC_MII_READ 0x20000000 /* read PHY command */ 903 904 /* NWAY Register */ 905 #define CSR_PNIC_NWAY 0xb8 906 #define PNIC_NWAY_RS 0x00000001 /* reset NWay block */ 907 #define PNIC_NWAY_PD 0x00000002 /* power down NWay block */ 908 #define PNIC_NWAY_BX 0x00000004 /* bypass transciever */ 909 #define PNIC_NWAY_LC 0x00000008 /* AUI low current mode */ 910 #define PNIC_NWAY_UV 0x00000010 /* low squelch voltage */ 911 #define PNIC_NWAY_DX 0x00000020 /* disable TP pol. correction */ 912 #define PNIC_NWAY_TW 0x00000040 /* select TP (0 == AUI) */ 913 #define PNIC_NWAY_AF 0x00000080 /* AUI full/half step input 914 voltage */ 915 #define PNIC_NWAY_FD 0x00000100 /* full duplex mode */ 916 #define PNIC_NWAY_DL 0x00000200 /* disable link integrity 917 test */ 918 #define PNIC_NWAY_DM 0x00000400 /* disable AUI/TP autodetect */ 919 #define PNIC_NWAY_100 0x00000800 /* 1 == 100mbps, 0 == 10mbps */ 920 #define PNIC_NWAY_NW 0x00001000 /* enable NWay block */ 921 #define PNIC_NWAY_CAP10T 0x00002000 /* adv. 10baseT */ 922 #define PNIC_NWAY_CAP10TFDX 0x00004000 /* adv. 10baseT-FDX */ 923 #define PNIC_NWAY_CAP100TXFDX 0x00008000 /* adv. 100baseTX-FDX */ 924 #define PNIC_NWAY_CAP100TX 0x00010000 /* adv. 100baseTX */ 925 #define PNIC_NWAY_CAP100T4 0x00020000 /* adv. 100base-T4 */ 926 #define PNIC_NWAY_RN 0x02000000 /* re-negotiate enable */ 927 #define PNIC_NWAY_RF 0x04000000 /* remote fault detected */ 928 #define PNIC_NWAY_LPAR10T 0x08000000 /* link part. 10baseT */ 929 #define PNIC_NWAY_LPAR10TFDX 0x10000000 /* link part. 10baseT-FDX */ 930 #define PNIC_NWAY_LPAR100TXFDX 0x20000000 /* link part. 100baseTX-FDX */ 931 #define PNIC_NWAY_LPAR100TX 0x40000000 /* link part. 100baseTX */ 932 #define PNIC_NWAY_LPAR100T4 0x80000000 /* link part. 100base-T4 */ 933 #define PNIC_NWAY_LPAR_MASK 0xf8000000 934 935 936 /* 937 * Macronix 98713, 98713A, 98715, 98715A, 98725 and 938 * Lite-On 82C115 registers. 939 */ 940 941 /* 942 * Note, the MX98713 is very Tulip-like: 943 * 944 * CSR12 General Purpose Port (like 21140) 945 * CSR13 reserved 946 * CSR14 reserved 947 * CSR15 Watchdog Timer (like 21140) 948 * 949 * The Macronix CSR12, CSR13, CSR14, and CSR15 exist only 950 * on the MX98713A and higher. 951 */ 952 953 /* CSR12 - 10base-T Status Port (similar to SIASTAT) */ 954 #define CSR_PMAC_10TSTAT TULIP_CSR12 955 #define PMAC_10TSTAT_LS100 0x00000002 /* link status 100TX 956 0 = link up */ 957 #define PMAC_10TSTAT_LS10 0x00000004 /* link status 10T 958 0 = link up */ 959 #define PMAC_10TSTAT_APS 0x00000008 /* auto polarity status */ 960 #define PMAC_10TSTAT_TRF 0x00000800 /* transmit remote fault 961 (21041) */ 962 #define PMAC_10TSTAT_ANS 0x00007000 /* autonegotiation state 963 (21041) */ 964 #define PMAC_10TSTAT_ANS_DIS 0x00000000 /* disabled */ 965 #define PMAC_10TSTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 966 #define PMAC_10TSTAT_ANS_ABD 0x00002000 /* ability detect */ 967 #define PMAC_10TSTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 968 #define PMAC_10TSTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 969 #define PMAC_10TSTAT_ANS_FLPGOOD 0x00005000 /* FLP link good */ 970 #define PMAC_10TSTAT_ANS_LINKCHECK 0x00006000 /* link check */ 971 #define PMAC_10TSTAT_LPN 0x00008000 /* link partner negotiable 972 (21041) */ 973 #define PMAC_10TSTAT_LPC 0xffff0000 /* link partner code word */ 974 975 #define PMAC_10TSTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 976 977 978 /* CSR13 - NWAY Reset Register */ 979 #define CSR_PMAC_NWAYRESET TULIP_CSR13 980 #define PMAC_NWAYRESET_RESET 0x00000000 /* NWay reset */ 981 #define PMAC_NWAYRESET_100TXRESET 0x00000002 /* 100base PMD reset */ 982 983 984 /* CSR14 - 10base-T Control Port */ 985 #define CSR_PMAC_10TCTL TULIP_CSR14 986 #define PMAC_10TCTL_LBK 0x00000002 /* loopback */ 987 #define PMAC_10TCTL_PWD10 0x00000004 /* power down 10base-T: 988 0 == power down 989 1 == normal operation */ 990 #define PMAC_10TCTL_HDE 0x00000040 /* half-duplex enable */ 991 #define PMAC_10TCTL_ANE 0x00000080 /* autonegotiation enable */ 992 #define PMAC_10TCTL_RSQ 0x00000100 /* receive squelch enable */ 993 #define PMAC_10TCTL_LTE 0x00001000 /* link test enable */ 994 #define PMAC_10TCTL_TXH 0x00010000 /* adv. 100tx */ 995 #define PMAC_10TCTL_TXF 0x00020000 /* adv. 100tx-fdx */ 996 #define PMAC_10TCTL_T4 0x00040000 /* adv. 100t4 */ 997 998 999 /* CSR15 - Watchdog Timer Register */ 1000 /* See 21140 CSR15 */ 1001 1002 1003 /* CSR16 - Test Operation Register (a.k.a. Magic Packet Register) */ 1004 #define CSR_PMAC_TOR TULIP_CSR16 1005 #define PMAC_TOR_98713 0x0F370000 1006 #define PMAC_TOR_98715 0x0B3C0000 1007 1008 1009 /* CSR20 - NWAY Status */ 1010 #define CSR_PMAC_NWAYSTAT TULIP_CSR20 1011 /* 1012 * Note: the MX98715A manual claims that EQTEST and PCITEST 1013 * must be set to 1 by software for normal operation, but 1014 * this does not appear to be necessary. This is probably 1015 * one of the things that frobbing the Test Operation Register 1016 * does. 1017 */ 1018 #define PMAC_NWAYSTAT_EQTEST 0x00001000 /* EQ test */ 1019 #define PMAC_NWAYSTAT_PCITEST 0x00010000 /* PCI test */ 1020 #define PMAC_NWAYSTAT_10TXH 0x08000000 /* 10t accepted */ 1021 #define PMAC_NWAYSTAT_10TXF 0x10000000 /* 10t-fdx accepted */ 1022 #define PMAC_NWAYSTAT_100TXH 0x20000000 /* 100tx accepted */ 1023 #define PMAC_NWAYSTAT_100TXF 0x40000000 /* 100tx-fdx accepted */ 1024 #define PMAC_NWAYSTAT_T4 0x80000000 /* 100t4 accepted */ 1025 1026 1027 /* CSR21 - Flow Control Register */ 1028 #define CSR_PNICII_FLOWCTL TULIP_CSR21 1029 #define PNICII_FLOWCTL_WKFCATEN 0x00000010 /* enable wake-up frame 1030 catenation feature */ 1031 #define PNICII_FLOWCTL_NFCE 0x00000020 /* accept flow control result 1032 from NWay */ 1033 #define PNICII_FLOWCTL_FCTH0 0x00000040 /* rx flow control thresh 0 */ 1034 #define PNICII_FLOWCTL_FCTH1 0x00000080 /* rx flow control thresh 1 */ 1035 #define PNICII_FLOWCTL_REJECTFC 0x00000100 /* abort rx flow control */ 1036 #define PNICII_FLOWCTL_STOPTX 0x00000200 /* tx flow stopped */ 1037 #define PNICII_FLOWCTL_RUFCEN 0x00000400 /* send flow control when 1038 RU interrupt occurs */ 1039 #define PNICII_FLOWCTL_RXFCEN 0x00000800 /* rx flow control enable */ 1040 #define PNICII_FLOWCTL_TXFCEN 0x00001000 /* tx flow control enable */ 1041 #define PNICII_FLOWCTL_RESTOP 0x00002000 /* restop mode */ 1042 #define PNICII_FLOWCTL_RESTART 0x00004000 /* restart mode */ 1043 #define PNICII_FLOWCTL_TEST 0x00008000 /* test flow control timer */ 1044 #define PNICII_FLOWCTL_TMVAL 0xffff0000 /* timer value in flow 1045 control frame */ 1046 1047 #define PNICII_FLOWCTL_TH_512 (PNICII_FLOWCTL_FCTH0|PNICII_FLOWCTL_FCTH1) 1048 #define PNICII_FLOWCTL_TH_256 (PNICII_FLOWCTL_FCTH1) 1049 #define PNICII_FLOWCTL_TH_128 (PNICII_FLOWCTL_FCTH0) 1050 #define PNICII_FLOWCTL_TH_OVFLW (0) 1051 1052 1053 /* CSR22 - MAC ID Byte 3-0 Register */ 1054 #define CSR_PNICII_MACID0 TULIP_CSR22 1055 #define PNICII_MACID_1 0 /* shift */ 1056 #define PNICII_MACID_0 8 /* shift */ 1057 #define PNICII_MACID_3 16 /* shift */ 1058 #define PNICII_MACID_2 24 /* shift */ 1059 1060 1061 /* CSR23 - Magic ID Byte 5,4/MACID Byte 5,4 Register */ 1062 #define PNICII_MACID_5 0 /* shift */ 1063 #define PNICII_MACID_4 8 /* shift */ 1064 #define PNICII_MAGID_5 16 /* shift */ 1065 #define PNICII_MAGIC_4 24 /* shift */ 1066 1067 1068 /* CSR24 - Magic ID Byte 3-0 Register */ 1069 #define PNICII_MAGID_1 0 /* shift */ 1070 #define PNICII_MAGID_0 8 /* shift */ 1071 #define PNICII_MAGID_3 16 /* shift */ 1072 #define PNICII_MAGID_2 24 /* shift */ 1073 1074 1075 /* CSR25 - CSR28 - Filter Byte Mask Registers */ 1076 #define CSR_PNICII_MASK0 TULIP_CSR25 1077 1078 #define CSR_PNICII_MASK1 TULIP_CSR26 1079 1080 #define CSR_PNICII_MASK2 TULIP_CSR27 1081 1082 #define CSR_PNICII_MASK3 TULIP_CSR28 1083 1084 1085 /* CSR29 - Filter Offset Register */ 1086 #define CSR_PNICII_FILOFF TULIP_CSR29 1087 #define PNICII_FILOFF_PAT0 0x0000007f /* pattern 0 offset */ 1088 #define PNICII_FILOFF_EN0 0x00000080 /* enable pattern 0 */ 1089 #define PNICII_FILOFF_PAT1 0x00007f00 /* pattern 1 offset */ 1090 #define PNICII_FILOFF_EN1 0x00008000 /* enable pattern 1 */ 1091 #define PNICII_FILOFF_PAT2 0x007f0000 /* pattern 2 offset */ 1092 #define PNICII_FILOFF_EN2 0x00800000 /* enable pattern 2 */ 1093 #define PNICII_FILOFF_PAT3 0x7f000000 /* pattern 3 offset */ 1094 #define PNICII_FILOFF_EN3 0x80000000 /* enable pattern 3 */ 1095 1096 1097 /* CSR30 - Filter 1 and 0 CRC-16 Register */ 1098 #define CSR_PNICII_FIL01 TULIP_CSR30 1099 #define PNICII_FIL01_CRC0 0x0000ffff /* CRC-16 of pattern 0 */ 1100 #define PNICII_FIL01_CRC1 0xffff0000 /* CRC-16 of pattern 1 */ 1101 1102 1103 /* CSR31 = Filter 3 and 2 CRC-16 Register */ 1104 #define CSR_PNICII_FIL23 TULIP_CSR31 1105 #define PNICII_FIL23_CRC2 0x0000ffff /* CRC-16 of pattern 2 */ 1106 #define PNICII_FIL23_CRC3 0xffff0000 /* CRC-16 of pattern 3 */ 1107 1108 1109 /* 1110 * Winbond 89C840F registers. 1111 */ 1112 1113 /* CSR12 - Current Receive Descriptor Register */ 1114 #define CSR_WINB_CRDAR TULIP_CSR12 1115 1116 1117 /* CSR13 - Current Receive Buffer Register */ 1118 #define CSR_WINB_CCRBAR TULIP_CSR13 1119 1120 1121 /* CSR14 - Multicast Address Register 0 */ 1122 #define CSR_WINB_CMA0 TULIP_CSR14 1123 1124 1125 /* CSR15 - Multicast Address Register 1 */ 1126 #define CSR_WINB_CMA1 TULIP_CSR15 1127 1128 1129 /* CSR16 - Physical Address Register 0 */ 1130 #define CSR_WINB_CPA0 TULIP_CSR16 1131 1132 1133 /* CSR17 - Physical Address Register 1 */ 1134 #define CSR_WINB_CPA1 TULIP_CSR17 1135 1136 1137 /* CSR18 - Boot ROM Size Register */ 1138 #define CSR_WINB_CBRCR TULIP_CSR18 1139 #define WINB_CBRCR_NONE 0x00000000 /* no boot rom */ 1140 /* 0x00000001 also no boot rom */ 1141 #define WINB_CBRCR_8K 0x00000002 /* 8k */ 1142 #define WINB_CBRCR_16K 0x00000003 /* 16k */ 1143 #define WINB_CBRCR_32K 0x00000004 /* 32k */ 1144 #define WINB_CBRCR_64K 0x00000005 /* 64k */ 1145 #define WINB_CBRCR_128K 0x00000006 /* 128k */ 1146 #define WINB_CBRCR_256K 0x00000007 1147 1148 1149 /* CSR19 - Current Transmit Descriptor Register */ 1150 #define CSR_WINB_CTDAR TULIP_CSR19 1151 1152 1153 /* CSR20 - Current Transmit Buffer Register */ 1154 #define CSR_WINB_CTBAR TULIP_CSR20 1155 1156 1157 /* 1158 * ADMtek AL981 registers 1159 * 1160 * We define these as strict byte offsets into PCI space, since 1161 * not all of them have consistent access rules. 1162 */ 1163 1164 /* CSR13 - Wake-up Control/Status Register */ 1165 #define CSR_ADM_WCSR 0x68 1166 #define ADM_WCSR_LSC 0x00000001 /* link status changed */ 1167 #define ADM_WCSR_MPR 0x00000002 /* magic packet received */ 1168 #define ADM_WCSR_WFR 0x00000004 /* wake up frame received */ 1169 #define ADM_WCSR_LSCE 0x00000100 /* link status changed en. */ 1170 #define ADM_WCSR_MPRE 0x00000200 /* magic packet receive en. */ 1171 #define ADM_WCSR_WFRE 0x00000400 /* wake up frame receive en. */ 1172 #define ADM_WCSR_LINKON 0x00010000 /* link-on detect en. */ 1173 #define ADM_WCSR_LINKOFF 0x00020000 /* link-off detect en. */ 1174 #define ADM_WCSR_WP5E 0x02000000 /* wake up pat. 5 en. */ 1175 #define ADM_WCSR_WP4E 0x04000000 /* wake up pat. 4 en. */ 1176 #define ADM_WCSR_WP3E 0x08000000 /* wake up pat. 3 en. */ 1177 #define ADM_WCSR_WP2E 0x10000000 /* wake up pat. 2 en. */ 1178 #define ADM_WCSR_WP1E 0x20000000 /* wake up pat. 1 en. */ 1179 #define ADM_WCSR_CRCT 0x40000000 /* CRC-16 type: 1180 0 == 0000 initial 1181 1 == ffff initial */ 1182 1183 1184 /* CSR14 - Wake-up Pattern Data Register */ 1185 #define CSR_ADM_WPDR 0x70 1186 1187 /* 1188 * 25 consecutive longword writes are issued to WPDR to 1189 * program the wake-up pattern filter. The data written 1190 * is as follows: 1191 * 1192 * XXX 1193 */ 1194 1195 1196 /* CSR15 - see 21140 CSR15 (Watchdog Timer) */ 1197 1198 1199 /* CSR16 - Assistant CSR5 (Status Register 2) */ 1200 #define CSR_ADM_ASR 0x80 1201 /* 0 - 14: same as CSR5 */ 1202 #define ADM_ASR_AAISS 0x00080000 /* added abnormal int. sum. */ 1203 #define ADM_ASR_ANISS 0x00010000 /* added normal int. sum. */ 1204 /* XXX Receive state */ 1205 /* XXX Transmit state */ 1206 #define ADM_ASR_BET 0x03800000 /* bus error type */ 1207 #define ADM_ASR_BET_PERR 0x00000000 /* parity error */ 1208 #define ADM_ASR_BET_MABT 0x00800000 /* master abort */ 1209 #define ADM_ASR_BET_TABT 0x01000000 /* target abort */ 1210 #define ADM_ASR_PFR 0x04000000 /* PAUSE frame received */ 1211 #define ADM_ASR_TDIS 0x10000000 /* transmit def. int. status */ 1212 #define ADM_ASR_XIS 0x20000000 /* xcvr int. status */ 1213 #define ADM_ASR_REIS 0x40000000 /* receive early int. status */ 1214 #define ADM_ASR_TEIS 0x80000000 /* transmit early int. status */ 1215 1216 1217 /* CSR17 - Assistant CSR7 (Interrupt Enable Register 2) */ 1218 #define CSR_ADM_AIE 0x84 1219 /* See CSR16 for valid bits */ 1220 1221 1222 /* CSR18 - Command Register */ 1223 #define CSR_ADM_CR 0x88 1224 #define ADM_CR_ATUR 0x00000001 /* auto. tx underrun recover */ 1225 #define ADM_CR_SINT 0x00000002 /* software interrupt */ 1226 #define ADM_CR_DRT 0x0000000c /* drain recieve threshold */ 1227 #define ADM_CR_DRT_8LW 0x00000000 /* 8 longwords */ 1228 #define ADM_CR_DRT_16LW 0x00000004 /* 16 longwords */ 1229 #define ADM_CR_DRT_SF 0x00000008 /* store-and-forward */ 1230 #define ADM_CR_RTE 0x00000010 /* receive threshold enable */ 1231 #define ADM_CR_PAUSE 0x00000020 /* enable PAUSE function */ 1232 #define ADM_CR_RWP 0x00000040 /* reset wake-up pattern 1233 data register pointer */ 1234 /* 16 - 31 are automatically recalled from the EEPROM */ 1235 #define ADM_CR_WOL 0x00040000 /* wake-on-lan enable */ 1236 #define ADM_CR_PM 0x00080000 /* power management enable */ 1237 #define ADM_CR_RFS 0x00600000 /* Receive FIFO size */ 1238 #define ADM_CR_RFS_1K 0x00600000 /* 1K FIFO */ 1239 #define ADM_CR_RFS_2K 0x00400000 /* 2K FIFO */ 1240 #define ADM_CR_LEDMODE 0x00800000 /* LED mode */ 1241 #define ADM_CR_AUXCL 0x30000000 /* aux current load */ 1242 #define ADM_CR_D3CS 0x80000000 /* D3 cold wake up enable */ 1243 1244 1245 /* CSR19 - PCI bus performance counter */ 1246 #define CSR_ADM_PCIC 0x8c 1247 #define ADM_PCIC_DWCNT 0x000000ff /* double-word count of 1248 last bus-master 1249 transaction */ 1250 #define ADM_PCIC_CLKCNT 0xffff0000 /* number of PCI clocks 1251 between read request 1252 and access completed */ 1253 1254 /* CSR20 - Power Management Control/Status Register */ 1255 #define CSR_ADM_PMCSR 0x90 1256 /* 1257 * This register is also mapped into the PCI configuration 1258 * space as the PMCSR. 1259 */ 1260 1261 1262 /* CSR23 - Transmit Burst Count/Time Out Register */ 1263 #define CSR_ADM_TXBR 0x9c 1264 #define ADM_TXBR_TTO 0x00000fff /* transmit timeout */ 1265 #define ADM_TXBR_TBCNT 0x001f0000 /* transmit burst count */ 1266 1267 1268 /* CSR24 - Flash ROM Port Register */ 1269 #define CSR_ADM_FROM 0xa0 1270 #define ADM_FROM_DATA 0x000000ff /* data to/from Flash */ 1271 #define ADM_FROM_ADDR 0x01ffff00 /* Flash address */ 1272 #define ADM_FROM_ADDR_SHIFT 8 1273 #define ADM_FROM_WEN 0x04000000 /* write enable */ 1274 #define ADM_FROM_REN 0x08000000 /* read enable */ 1275 #define ADM_FROM_bra16on 0x80000000 /* pin 87 is brA16, else 1276 pin 87 is fd/col LED pin */ 1277 1278 1279 /* CSR25 - Physical Address Register 0 */ 1280 #define CSR_ADM_PAR0 0xa4 1281 1282 1283 /* CSR26 - Physical Address Register 1 */ 1284 #define CSR_ADM_PAR1 0xa8 1285 1286 1287 /* CSR27 - Multicast Address Register 0 */ 1288 #define CSR_ADM_MAR0 0xac 1289 1290 1291 /* CSR28 - Multicast Address Register 1 */ 1292 #define CSR_ADM_MAR1 0xb0 1293 1294 1295 /* Internal PHY registers are mapped here (lower 16 bits valid) */ 1296 1297 #define CSR_ADM_BMCR 0xb4 1298 #define CSR_ADM_BMSR 0xb8 1299 #define CSR_ADM_PHYIDR1 0xbc 1300 #define CSR_ADM_PHYIDR2 0xc0 1301 #define CSR_ADM_ANAR 0xc4 1302 #define CSR_ADM_ANLPAR 0xc8 1303 #define CSR_ADM_ANER 0xcc 1304 1305 /* XCVR Mode Control Register */ 1306 #define CSR_ADM_XMC 0xd0 1307 #define ADM_XMC_LD 0x00000800 /* long distance mode 1308 (low squelch enable) */ 1309 1310 1311 /* XCVR Configuration Information and Interrupt Status Register */ 1312 #define CSR_ADM_XCIIS 0xd4 1313 #define ADM_XCIIS_REF 0x0001 /* 64 error packets received */ 1314 #define ADM_XCIIS_ANPR 0x0002 /* autoneg page received */ 1315 #define ADM_XCIIS_PDF 0x0004 /* parallel detection fault */ 1316 #define ADM_XCIIS_ANAR 0x0008 /* autoneg ACK */ 1317 #define ADM_XCIIS_LS 0x0010 /* link status (1 == fail) */ 1318 #define ADM_XCIIS_RFD 0x0020 /* remote fault */ 1319 #define ADM_XCIIS_ANC 0x0040 /* autoneg completed */ 1320 #define ADM_XCIIS_PAUSE 0x0080 /* PAUSE enabled */ 1321 #define ADM_XCIIS_DUPLEX 0x0100 /* full duplex */ 1322 #define ADM_XCIIS_SPEED 0x0200 /* 100Mb/s */ 1323 1324 1325 /* XCVR Interrupt Enable Register */ 1326 #define CSR_ADM_XIE 0xd8 1327 /* Bits are as for XCIIS */ 1328 1329 1330 /* XCVR 100baseTX PHY Control/Status Register */ 1331 #define CSR_ADM_100CTR 0xdc 1332 #define ADM_100CTR_DISCRM 0x0001 /* disable scrambler */ 1333 #define ADM_100CTR_DISMLT 0x0002 /* disable MLT3 ENDEC */ 1334 #define ADM_100CTR_CMODE 0x001c /* current operating mode */ 1335 #define ADM_100CTR_CMODE_AUTO 0x0000 /* in autoneg */ 1336 #define ADM_100CTR_CMODE_10 0x0004 /* 10baseT */ 1337 #define ADM_100CTR_CMODE_100 0x0008 /* 100baseTX */ 1338 /* 0x000c reserved */ 1339 /* 0x0010 reserved */ 1340 #define ADM_100CTR_CMODE_10FD 0x0014 /* 10baseT-FDX */ 1341 #define ADM_100CTR_CMODE_100FD 0x0018 /* 100baseTX-FDX */ 1342 #define ADM_100CTR_CMODE_ISO 0x001c /* isolated */ 1343 #define ADM_100CTR_ISOTX 0x0020 /* transmit isolation */ 1344 #define ADM_100CTR_ENRZI 0x0080 /* enable NRZ <> NRZI conv. */ 1345 #define ADM_100CTR_ENDCR 0x0100 /* enable DC restoration */ 1346 #define ADM_100CTR_ENRLB 0x0200 /* enable remote loopback */ 1347 #define ADM_100CTR_RXVPP 0x0800 /* peak Rx voltage: 1348 0 == 1.0 VPP 1349 1 == 1.4 VPP */ 1350 #define ADM_100CTR_ANC 0x1000 /* autoneg completed */ 1351 #define ADM_100CTR_DISRER 0x2000 /* disable Rx error counter */ 1352 1353 #endif /* _DEV_IC_TULIPREG_H_ */ 1354
Indexes created Tue Sep 30 11:09:46 GMT 2025