tulipreg.h revision 1.12
1 /* $NetBSD: tulipreg.h,v 1.12 1999/11/03 22:22:49 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_IC_TULIPREG_H_ 41 #define _DEV_IC_TULIPREG_H_ 42 43 /* 44 * Register description for the Digital Semiconductor ``Tulip'' (21x4x) 45 * Ethernet controller family, and a variety of clone chips, including: 46 * 47 * - Macronix 98713, 98713A, 98715, 98715A, 98725 (PMAC): 48 * 49 * These chips are fairly straight-forward Tulip clones. 50 * The 98713 is a very close 21140A clone. It has GPR 51 * and MII media, and a GPIO facility, and uses the ISV 52 * SROM format (or, at least, should, because of the GPIO 53 * facility). The 98713A has MII, no GPIO facility, and 54 * an internal NWay block. The 98715, 98715A, and 98725 55 * have only GPR media and the NWay block. The 98715, 56 * 98715A, and 98725 support power management. 57 * 58 * - Lite-On 82C115 (PNIC II): 59 * 60 * A clone of the Macronix MX98725, with the following differences: 61 * 62 * - Wake-On-LAN support 63 * - 128-bit multicast hash table rather than the 64 * standard 512-bit hash table 65 * - 802.3x flow control 66 * 67 * - Lite-On 82C168, 82C169 (PNIC): 68 * 69 * Pretty close, with only a few minor differences: 70 * 71 * - EEPROM is accessed completely differently. 72 * - MII is accessed completely differently. 73 * - No SIO facility (due to the above two differences). 74 * - GPIO interface is different than the 21140's. 75 * - Boards that lack PHYs use the internal NWay block 76 * and transciever. 77 * 78 * - Winbond 89C840F 79 * 80 * Less similar, but still roughly compatible (enough so 81 * that the driver can be adapted, at least): 82 * 83 * - Registers lack the pad word between them. 84 * - Instead of a setup frame, there are two station 85 * address registers and two multicast hash table 86 * registers (64-bit multicast hash table). 87 * - Only supported media interface is MII-over-SIO. 88 * - Different OPMODE register bits for various things 89 * (mostly media related). 90 * 91 * - ADMtek AL981 92 * 93 * Another pretty-close clone: 94 * 95 * - Wake-On-LAN support 96 * - Instead of a setup frame, there are two station 97 * address registers and two multicast hash table 98 * registers (64-bit multicast hash table). 99 * - 802.3x flow control 100 * - Only supported media interface is built-in PHY 101 * which is accessed through a set of special registers. 102 * - Not all registers have the pad word between them, 103 * but luckily, there are all AL981-specific registers, 104 * so this is easy to deal with. 105 * 106 * Some of the clone chips have different registers, and some have 107 * different bits in the same registers. These will be denoted by 108 * PMAC, PNICII, PNIC, WINB, and ADM in the register/bit names. 109 */ 110 111 /* 112 * Tulip buffer descriptor. Must be 4-byte aligned. 113 * 114 * Note for receive descriptors, the byte count fields must 115 * be a multiple of 4. 116 */ 117 struct tulip_desc { 118 __volatile u_int32_t td_status; /* Status */ 119 __volatile u_int32_t td_ctl; /* Control and Byte Counts */ 120 __volatile u_int32_t td_bufaddr1; /* Buffer Address 1 */ 121 __volatile u_int32_t td_bufaddr2; /* Buffer Address 2 */ 122 }; 123 124 /* 125 * Descriptor Status bits common to transmit and receive. 126 */ 127 #define TDSTAT_OWN 0x80000000 /* Tulip owns descriptor */ 128 #define TDSTAT_ES 0x00008000 /* Error Summary */ 129 130 /* 131 * Descriptor Status bits for Receive Descriptor. 132 */ 133 #define TDSTAT_Rx_FF 0x40000000 /* Filtering Fail */ 134 #define TDSTAT_WINB_Rx_RCMP 0x40000000 /* Receive Complete */ 135 #define TDSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */ 136 #define TDSTAT_Rx_DE 0x00004000 /* Descriptor Error */ 137 #define TDSTAT_Rx_DT 0x00003000 /* Data Type */ 138 #define TDSTAT_Rx_RF 0x00000800 /* Runt Frame */ 139 #define TDSTAT_Rx_MF 0x00000400 /* Multicast Frame */ 140 #define TDSTAT_Rx_FS 0x00000200 /* First Descriptor */ 141 #define TDSTAT_Rx_LS 0x00000100 /* Last Descriptor */ 142 #define TDSTAT_Rx_TL 0x00000080 /* Frame Too Long */ 143 #define TDSTAT_Rx_CS 0x00000040 /* Collision Seen */ 144 #define TDSTAT_Rx_RT 0x00000020 /* Frame Type */ 145 #define TDSTAT_Rx_RW 0x00000010 /* Receive Watchdog */ 146 #define TDSTAT_Rx_RE 0x00000008 /* Report on MII Error */ 147 #define TDSTAT_Rx_DB 0x00000004 /* Dribbling Bit */ 148 #define TDSTAT_Rx_CE 0x00000002 /* CRC Error */ 149 #define TDSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */ 150 151 #define TDSTAT_Rx_LENGTH(x) (((x) & TDSTAT_Rx_FL) >> 16) 152 153 #define TDSTAT_Rx_DT_SR 0x00000000 /* Serial Received Frame */ 154 #define TDSTAT_Rx_DT_IL 0x00001000 /* Internal Loopback Frame */ 155 #define TDSTAT_Rx_DT_EL 0x00002000 /* External Loopback Frame */ 156 #define TDSTAT_Rx_DT_r 0x00003000 /* Reserved */ 157 158 /* 159 * Descriptor Status bits for Transmit Descriptor. 160 */ 161 #define TDSTAT_WINB_Tx_TE 0x00008000 /* Transmit Error */ 162 #define TDSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */ 163 #define TDSTAT_Tx_LO 0x00000800 /* Loss of Carrier */ 164 #define TDSTAT_Tx_NC 0x00000400 /* No Carrier */ 165 #define TDSTAT_Tx_LC 0x00000200 /* Late Collision */ 166 #define TDSTAT_Tx_EC 0x00000100 /* Excessive Collisions */ 167 #define TDSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */ 168 #define TDSTAT_Tx_CC 0x00000078 /* Collision Count */ 169 #define TDSTAT_Tx_LF 0x00000004 /* Link Fail */ 170 #define TDSTAT_Tx_UF 0x00000002 /* Underflow Error */ 171 #define TDSTAT_Tx_DE 0x00000001 /* Deferred */ 172 173 #define TDSTAT_Tx_COLLISIONS(x) (((x) & TDSTAT_Tx_CC) >> 3) 174 175 /* 176 * Descriptor Control bits common to transmit and receive. 177 */ 178 #define TDCTL_SIZE1 0x000007ff /* Size of buffer 1 */ 179 #define TDCTL_SIZE1_SHIFT 0 180 181 #define TDCTL_SIZE2 0x003ff800 /* Size of buffer 2 */ 182 #define TDCTL_SIZE2_SHIFT 11 183 184 #define TDCTL_ER 0x02000000 /* End of Ring */ 185 #define TDCTL_CH 0x01000000 /* Second Address Chained */ 186 187 /* 188 * Descriptor Control bits for Transmit Descriptor. 189 */ 190 #define TDCTL_Tx_IC 0x80000000 /* Interrupt on Completion */ 191 #define TDCTL_Tx_LS 0x40000000 /* Last Segment */ 192 #define TDCTL_Tx_FS 0x20000000 /* First Segment */ 193 #define TDCTL_Tx_FT1 0x10000000 /* Filtering Type 1 */ 194 #define TDCTL_Tx_SET 0x08000000 /* Setup Packet */ 195 #define TDCTL_Tx_AC 0x04000000 /* Add CRC Disable */ 196 #define TDCTL_Tx_DPD 0x00800000 /* Disabled Padding */ 197 #define TDCTL_Tx_FT0 0x00400000 /* Filtering Type 0 */ 198 199 /* 200 * The Tulip filter is programmed by "transmitting" a Setup Packet 201 * (indicated by TDCTL_Tx_SET). The filtering type is indicated 202 * as follows: 203 * 204 * FT1 FT0 Description 205 * --- --- ----------- 206 * 0 0 Perfect Filtering: The Tulip interprets the 207 * descriptor buffer as a table of 16 MAC addresses 208 * that the Tulip should receive. 209 * 210 * 0 1 Hash Filtering: The Tulip interprets the 211 * descriptor buffer as a 512-bit hash table 212 * plus one perfect address. If the incoming 213 * address is Multicast, the hash table filters 214 * the address, else the address is filtered by 215 * the perfect address. 216 * 217 * 1 0 Inverse Filtering: Like Perfect Filtering, except 218 * the table is addresses that the Tulip does NOT 219 * receive. 220 * 221 * 1 1 Hash-only Filtering: Like Hash Filtering, but 222 * physical addresses are matched by the hash table 223 * as well, and not by matching a single perfect 224 * address. 225 * 226 * A Setup Packet must always be 192 bytes long. The Tulip can store 227 * 16 MAC addresses. If not all 16 are specified in Perfect Filtering 228 * or Inverse Filtering mode, then unused entries should duplicate 229 * one of the valid entries. 230 */ 231 #define TDCTL_Tx_FT_PERFECT 0 232 #define TDCTL_Tx_FT_HASH TDCTL_Tx_FT0 233 #define TDCTL_Tx_FT_INVERSE TDCTL_Tx_FT1 234 #define TDCTL_Tx_FT_HASHONLY (TDCTL_Tx_FT1|TDCTL_Tx_FT0) 235 236 #define TULIP_SETUP_PACKET_LEN 192 237 #define TULIP_MAXADDRS 16 238 #define TULIP_MCHASHSIZE 512 239 #define TULIP_PNICII_HASHSIZE 128 240 241 /* 242 * Maximum size of a Tulip Ethernet Address ROM or SROM. 243 */ 244 #define TULIP_MAX_ROM_SIZE 128 245 246 /* 247 * Format of the standard Tulip SROM information: 248 * 249 * Byte offset Size Usage 250 * 0 18 reserved 251 * 18 1 SROM Format Version 252 * 19 1 Chip Count 253 * 20 6 IEEE Network Address 254 * 26 1 Chip 0 Device Number 255 * 27 2 Chip 0 Info Leaf Offset 256 * 29 1 Chip 1 Device Number 257 * 30 2 Chip 1 Info Leaf Offset 258 * 32 1 Chip 2 Device Number 259 * 33 2 Chip 2 Info Leaf Offset 260 * ... 1 Chip n Device Number 261 * ... 2 Chip n Info Leaf Offset 262 * ... ... ... 263 * Chip Info Leaf Information 264 * ... 265 * ... 266 * ... 267 * 126 2 CRC32 checksum 268 */ 269 #define TULIP_ROM_SROM_FORMAT_VERION 18 /* B */ 270 #define TULIP_ROM_CHIP_COUNT 19 /* B */ 271 #define TULIP_ROM_IEEE_NETWORK_ADDRESS 20 272 #define TULIP_ROM_CHIPn_DEVICE_NUMBER(n) (26 + ((n) * 3))/* B */ 273 #define TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(n) (27 + ((n) * 3))/* W */ 274 #define TULIP_ROM_CRC32_CHECKSUM 126 /* W */ 275 276 #define TULIP_ROM_IL_SELECT_CONN_TYPE 0 /* W */ 277 #define TULIP_ROM_IL_MEDIA_COUNT 2 /* B */ 278 #define TULIP_ROM_IL_MEDIAn_BLOCK_BASE 3 279 280 #define SELECT_CONN_TYPE_TP 0x0000 281 #define SELECT_CONN_TYPE_BNC 0x0001 282 #define SELECT_CONN_TYPE_AUI 0x0002 283 #define SELECT_CONN_TYPE_100TX 0x0003 284 #define SELECT_CONN_TYPE_100T4 0x0006 285 #define SELECT_CONN_TYPE_100FX 0x0007 286 #define SELECT_CONN_TYPE MII_10T 0x0009 287 #define SELECT_CONN_TYPE_MII_100TX 0x000d 288 #define SELECT_CONN_TYPE_MII_100T4 0x000f 289 #define SELECT_CONN_TYPE_MII_100FX 0x0010 290 #define SELECT_CONN_TYPE_TP_AUTONEG 0x0100 291 #define SELECT_CONN_TYPE_TP_FDX 0x0204 292 #define SELECT_CONN_TYPE_MII_10T_FDX 0x020a 293 #define SELECT_CONN_TYPE_100TX_FDX 0x020e 294 #define SELECT_CONN_TYPE_MII_100TX_FDX 0x0211 295 #define SELECT_CONN_TYPE_TP_NOLINKPASS 0x0400 296 #define SELECT_CONN_TYPE_ASENSE 0x0800 297 #define SELECT_CONN_TYPE_ASENSE_POWERUP 0x8800 298 #define SELECT_CONN_TYPE_ASENSE_AUTONEG 0x0900 299 300 #define TULIP_ROM_MB_MEDIA_CODE 0x3f 301 #define TULIP_ROM_MB_MEDIA_TP 0x00 302 #define TULIP_ROM_MB_MEDIA_BNC 0x01 303 #define TULIP_ROM_MB_MEDIA_AUI 0x02 304 #define TULIP_ROM_MB_MEDIA_100TX 0x03 305 #define TULIP_ROM_MB_MEDIA_TP_FDX 0x04 306 #define TULIP_ROM_MB_MEDIA_100TX_FDX 0x05 307 #define TULIP_ROM_MB_MEDIA_100T4 0x06 308 #define TULIP_ROM_MB_MEDIA_100FX 0x07 309 #define TULIP_ROM_MB_MEDIA_100FX_FDX 0x08 310 311 #define TULIP_ROM_MB_EXT 0x40 312 313 #define TULIP_ROM_MB_CSR13 1 /* W */ 314 #define TULIP_ROM_MB_CSR14 3 /* W */ 315 #define TULIP_ROM_MB_CSR15 5 /* W */ 316 317 #define TULIP_ROM_MB_SIZE(mc) (((mc) & TULIP_ROM_MB_EXT) ? 7 : 1) 318 319 #define TULIP_ROM_MB_NOINDICATOR 0x8000 320 #define TULIP_ROM_MB_DEFAULT 0x4000 321 #define TULIP_ROM_MB_POLARITY 0x0080 322 #define TULIP_ROM_MB_OPMODE(x) (((x) & 0x71) << 18) 323 #define TULIP_ROM_MB_BITPOS(x) (1 << (((x) & 0x0e) >> 1)) 324 325 #define TULIP_ROM_MB_21140_GPR 0 /* 21140[A] GPR block */ 326 #define TULIP_ROM_MB_21140_MII 1 /* 21140[A] MII block */ 327 #define TULIP_ROM_MB_21142_SIA 2 /* 2114[23] SIA block */ 328 #define TULIP_ROM_MB_21142_MII 3 /* 2114[23] MII block */ 329 #define TULIP_ROM_MB_21143_SYM 4 /* 21143 SYM block */ 330 #define TULIP_ROM_MB_21143_RESET 5 /* 21143 reset block */ 331 332 #define TULIP_ROM_GETW(data, off) ((data)[(off)] | ((data)[(off) + 1]) << 8) 333 334 /* 335 * Tulip control registers. 336 */ 337 338 #define TULIP_CSR0 0x00 339 #define TULIP_CSR1 0x08 340 #define TULIP_CSR2 0x10 341 #define TULIP_CSR3 0x18 342 #define TULIP_CSR4 0x20 343 #define TULIP_CSR5 0x28 344 #define TULIP_CSR6 0x30 345 #define TULIP_CSR7 0x38 346 #define TULIP_CSR8 0x40 347 #define TULIP_CSR9 0x48 348 #define TULIP_CSR10 0x50 349 #define TULIP_CSR11 0x58 350 #define TULIP_CSR12 0x60 351 #define TULIP_CSR13 0x68 352 #define TULIP_CSR14 0x70 353 #define TULIP_CSR15 0x78 354 #define TULIP_CSR16 0x80 355 #define TULIP_CSR17 0x88 356 #define TULIP_CSR18 0x90 357 #define TULIP_CSR19 0x98 358 #define TULIP_CSR20 0xa0 359 #define TULIP_CSR21 0xa8 360 #define TULIP_CSR22 0xb0 361 #define TULIP_CSR23 0xb8 362 #define TULIP_CSR24 0xc0 363 #define TULIP_CSR25 0xc8 364 #define TULIP_CSR26 0xd0 365 #define TULIP_CSR27 0xd8 366 #define TULIP_CSR28 0xe0 367 #define TULIP_CSR29 0xe8 368 #define TULIP_CSR30 0xf0 369 #define TULIP_CSR31 0xf8 370 371 #define TULIP_CSR_INDEX(csr) ((csr) >> 3) 372 373 /* CSR0 - Bus Mode */ 374 #define CSR_BUSMODE TULIP_CSR0 375 #define BUSMODE_SWR 0x00000001 /* software reset */ 376 #define BUSMODE_BAR 0x00000002 /* bus arbitration */ 377 #define BUSMODE_DSL 0x0000007c /* descriptor skip length */ 378 #define BUSMODE_BLE 0x00000080 /* big endian */ 379 /* programmable burst length */ 380 #define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */ 381 #define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */ 382 #define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */ 383 #define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */ 384 #define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */ 385 #define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */ 386 #define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */ 387 /* cache alignment */ 388 #define BUSMODE_CAL_NONE 0x00000000 /* no alignment */ 389 #define BUSMODE_CAL_8LW 0x00004000 /* 8 longwords */ 390 #define BUSMODE_CAL_16LW 0x00008000 /* 16 longwords */ 391 #define BUSMODE_CAL_32LW 0x0000c000 /* 32 longwords */ 392 #define BUSMODE_DAS 0x00010000 /* diagnostic address space */ 393 /* must be zero on most */ 394 /* transmit auto-poll */ 395 /* 396 * Transmit auto-polling not supported on: 397 * Winbond 89C040F 398 */ 399 #define BUSMODE_TAP_NONE 0x00000000 /* no auto-polling */ 400 #define BUSMODE_TAP_200us 0x00020000 /* 200 uS */ 401 #define BUSMODE_TAP_800us 0x00040000 /* 400 uS */ 402 #define BUSMODE_TAP_1_6ms 0x00060000 /* 1.6 mS */ 403 #define BUSMODE_TAP_12_8us 0x00080000 /* 12.8 uS (21041+) */ 404 #define BUSMODE_TAP_25_6us 0x000a0000 /* 25.6 uS (21041+) */ 405 #define BUSMODE_TAP_51_2us 0x000c0000 /* 51.2 uS (21041+) */ 406 #define BUSMODE_TAP_102_4us 0x000e0000 /* 102.4 uS (21041+) */ 407 #define BUSMODE_DBO 0x00100000 /* desc-only b/e (21041+) */ 408 #define BUSMODE_RME 0x00200000 /* rd/mult enab (21140+) */ 409 #define BUSMODE_WINB_WAIT 0x00200000 /* wait state insertion */ 410 #define BUSMODE_RLE 0x00800000 /* rd/line enab (21140+) */ 411 #define BUSMODE_WLE 0x01000000 /* wt/line enab (21140+) */ 412 #define BUSMODE_PNIC_MBO 0x04000000 /* magic `must be one' bit */ 413 /* on Lite-On PNIC */ 414 415 416 /* CSR1 - Transmit Poll Demand */ 417 #define CSR_TXPOLL TULIP_CSR1 418 #define TXPOLL_TPD 0x00000001 /* transmit poll demand */ 419 420 421 /* CSR2 - Receive Poll Demand */ 422 #define CSR_RXPOLL TULIP_CSR2 423 #define RXPOLL_RPD 0x00000001 /* receive poll demand */ 424 425 426 /* CSR3 - Receive List Base Address */ 427 #define CSR_RXLIST TULIP_CSR3 428 429 /* CSR4 - Transmit List Base Address */ 430 #define CSR_TXLIST TULIP_CSR4 431 432 /* CSR5 - Status */ 433 #define CSR_STATUS TULIP_CSR5 434 #define STATUS_TI 0x00000001 /* transmit interrupt */ 435 #define STATUS_TPS 0x00000002 /* transmit process stopped */ 436 #define STATUS_TU 0x00000004 /* transmit buffer unavail */ 437 #define STATUS_TJT 0x00000008 /* transmit jabber timeout */ 438 #define STATUS_WINB_REI 0x00000008 /* receive early interrupt */ 439 #define STATUS_LNPANC 0x00000010 /* link pass (21041) */ 440 #define STATUS_WINB_RERR 0x00000010 /* receive error */ 441 #define STATUS_UNF 0x00000020 /* transmit underflow */ 442 #define STATUS_RI 0x00000040 /* receive interrupt */ 443 #define STATUS_RU 0x00000080 /* receive buffer unavail */ 444 #define STATUS_RPS 0x00000100 /* receive process stopped */ 445 #define STATUS_RWT 0x00000200 /* receive watchdog timeout */ 446 #define STATUS_AT 0x00000400 /* SIA AUI/TP pin changed 447 (21040) */ 448 #define STATUS_ETI 0x00000400 /* early transmit interrupt 449 (21142/PMAC/Winbond) */ 450 #define STATUS_FD 0x00000800 /* full duplex short frame 451 received (21040) */ 452 #define STATUS_TM 0x00000800 /* timer expired (21041) */ 453 #define STATUS_LNF 0x00001000 /* link fail (21040) */ 454 #define STATUS_SE 0x00002000 /* system error */ 455 #define STATUS_ER 0x00004000 /* early receive (21041) */ 456 #define STATUS_AIS 0x00008000 /* abnormal interrupt summary */ 457 #define STATUS_NIS 0x00010000 /* normal interrupt summary */ 458 #define STATUS_RS 0x000e0000 /* receive process state */ 459 #define STATUS_RS_STOPPED 0x00000000 /* Stopped */ 460 #define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive 461 descriptor */ 462 #define STATUS_RS_CHECK 0x00040000 /* Running - check for end 463 of receive */ 464 #define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */ 465 #define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */ 466 #define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive 467 descriptor */ 468 #define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current 469 frame from FIFO */ 470 #define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current 471 frame from FIFO into 472 buffer */ 473 #define STATUS_TS 0x00700000 /* transmit process state */ 474 #define STATUS_TS_STOPPED 0x00000000 /* Stopped */ 475 #define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit 476 descriptor */ 477 #define STATUS_TS_WAIT 0x00200000 /* Running - wait for end 478 of transmission */ 479 #define STATUS_TS_READING 0x00300000 /* Running - read buffer from 480 memory and queue into 481 FIFO */ 482 #define STATUS_TS_RESERVED 0x00400000 /* RESERVED */ 483 #define STATUS_TS_SETUP 0x00500000 /* Running - Setup packet */ 484 #define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */ 485 #define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit 486 descriptor */ 487 #define STATUS_EB 0x03800000 /* error bits */ 488 #define STATUS_EB_PARITY 0x00000000 /* parity errror */ 489 #define STATUS_EB_MABT 0x00800000 /* master abort */ 490 #define STATUS_EB_TABT 0x01000000 /* target abort */ 491 #define STATUS_GPPI 0x04000000 /* GPIO interrupt (21142) */ 492 #define STATUS_PNIC_TXABORT 0x04000000 /* transmit aborted */ 493 #define STATUS_LC 0x08000000 /* 100baseTX link change 494 (21142/PMAC) */ 495 #define STATUS_PMAC_WKUPI 0x10000000 /* wake up event */ 496 497 498 /* CSR6 - Operation Mode */ 499 #define CSR_OPMODE TULIP_CSR6 500 #define OPMODE_HP 0x00000001 /* hash/perfect mode (ro) */ 501 #define OPMODE_SR 0x00000002 /* start receive */ 502 #define OPMODE_HO 0x00000004 /* hash only mode (ro) */ 503 #define OPMODE_PB 0x00000008 /* pass bad frames */ 504 #define OPMODE_WINB_APP 0x00000008 /* accept all physcal packet */ 505 #define OPMODE_IF 0x00000010 /* inverse filter mode (ro) */ 506 #define OPMODE_WINB_AMP 0x00000010 /* accept multicast packet */ 507 #define OPMODE_SB 0x00000020 /* start backoff counter */ 508 #define OPMODE_WINB_ABP 0x00000020 /* accept broadcast packet */ 509 #define OPMODE_PR 0x00000040 /* promiscuous mode */ 510 #define OPMODE_WINB_ARP 0x00000040 /* accept runt packet */ 511 #define OPMODE_PM 0x00000080 /* pass all multicast */ 512 #define OPMODE_WINB_AEP 0x00000080 /* accept error packet */ 513 #define OPMODE_FKD 0x00000100 /* flaky oscillator disable */ 514 #define OPMODE_FD 0x00000200 /* full-duplex mode */ 515 #define OPMODE_OM 0x00000c00 /* operating mode */ 516 #define OPMODE_OM_NORMAL 0x00000000 /* normal mode */ 517 #define OPMODE_OM_INTLOOP 0x00000400 /* internal loopback */ 518 #define OPMODE_OM_EXTLOOP 0x00000800 /* external loopback */ 519 #define OPMODE_FC 0x00001000 /* force collision */ 520 #define OPMODE_ST 0x00002000 /* start transmitter */ 521 #define OPMODE_TR 0x0000c000 /* threshold control */ 522 #define OPMODE_TR_72 0x00000000 /* 72 bytes */ 523 #define OPMODE_TR_96 0x00004000 /* 96 bytes */ 524 #define OPMODE_TR_128 0x00008000 /* 128 bytes */ 525 #define OPMODE_TR_160 0x0000c000 /* 160 bytes */ 526 #define OPMODE_WINB_TTH 0x001fc000 /* transmit threshold */ 527 #define OPMODE_WINB_TTH_SHIFT 14 528 #define OPMODE_BP 0x00010000 /* backpressure enable */ 529 #define OPMODE_CA 0x00020000 /* capture effect enable */ 530 #define OPMODE_PNIC_TBEN 0x00020000 /* Tx backoff offset enable */ 531 #define OPMODE_PS 0x00040000 /* port select: 532 1 = MII/SYM, 0 = SRL 533 (21140) */ 534 #define OPMODE_HBD 0x00080000 /* heartbeat disable: 535 set in MII/SYM 100mbps, 536 set according to PHY 537 in MII 10mbps mode 538 (21140) */ 539 #define OPMODE_PNIC_IT 0x00100000 /* immediate transmit */ 540 #define OPMODE_SF 0x00200000 /* store and forward mode 541 (21140) */ 542 #define OPMODE_WINB_REIT 0x1fe00000 /* receive eartly intr thresh */ 543 #define OPMODE_WINB_REIT_SHIFT 21 544 #define OPMODE_TTM 0x00400000 /* Transmit Threshold Mode: 545 1 = 10mbps, 0 = 100mbps 546 (21140) */ 547 #define OPMODE_PCS 0x00800000 /* PCS function (21140) */ 548 #define OPMODE_SCR 0x01000000 /* scrambler mode (21140) */ 549 #define OPMODE_MBO 0x02000000 /* must be one (21140) */ 550 #define OPMODE_IDAMSB 0x04000000 /* ignore dest addr MSB 551 (21142) */ 552 #define OPMODE_PNIC_DRC 0x20000000 /* don't include CRC in Rx 553 frames (PNIC) */ 554 #define OPMODE_WINB_FES 0x20000000 /* fast ethernet select */ 555 #define OPMODE_RA 0x40000000 /* receive all (21140) */ 556 #define OPMODE_PNIC_EED 0x40000000 /* 1 == ext, 0 == int ENDEC 557 (PNIC) */ 558 #define OPMODE_WINB_TEIO 0x40000000 /* transmit early intr on */ 559 #define OPMODE_SC 0x80000000 /* special capture effect 560 enable (21041+) */ 561 #define OPMODE_WINB_REIO 0x80000000 /* receive early intr on */ 562 563 /* Shorthand for media-related OPMODE bits */ 564 #define OPMODE_MEDIA_BITS (OPMODE_PS|OPMODE_PCS|OPMODE_SCR) 565 566 /* CSR7 - Interrupt Enable */ 567 #define CSR_INTEN TULIP_CSR7 568 /* See bits for CSR5 -- Status */ 569 570 571 /* CSR8 - Missed Frames */ 572 #define CSR_MISSED TULIP_CSR8 573 #define MISSED_MFC 0x0000ffff /* missed packet count */ 574 #define MISSED_MFO 0x00010000 /* missed packet count 575 overflowed */ 576 #define MISSED_FOC 0x0ffe0000 /* fifo overflow counter 577 (21140) */ 578 #define MISSED_OCO 0x10000000 /* overflow counter overflowed 579 (21140) */ 580 581 #define MISSED_GETMFC(x) ((x) & MISSED_MFC) 582 #define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 17) 583 584 585 /* CSR9 - MII, SROM, Boot ROM, Ethernet Address ROM register. */ 586 #define CSR_MIIROM TULIP_CSR9 587 #define MIIROM_DATA 0x000000ff /* byte of data from 588 Ethernet Address ROM 589 (21040), byte of data 590 to/from Boot ROM (21041+) */ 591 #define MIIROM_SROMCS 0x00000001 /* SROM chip select */ 592 #define MIIROM_SROMSK 0x00000002 /* SROM clock */ 593 #define MIIROM_SROMDI 0x00000004 /* SROM data in (to) */ 594 #define MIIROM_SROMDO 0x00000008 /* SROM data out (from) */ 595 #define MIIROM_REG 0x00000400 /* external register select */ 596 #define MIIROM_SR 0x00000800 /* SROM select */ 597 #define MIIROM_BR 0x00001000 /* boot ROM select */ 598 #define MIIROM_WR 0x00002000 /* write to boot ROM */ 599 #define MIIROM_RD 0x00004000 /* read from boot ROM */ 600 #define MIIROM_MOD 0x00008000 /* mode select (ro) (21041) */ 601 #define MIIROM_MDC 0x00010000 /* MII clock */ 602 #define MIIROM_MDO 0x00020000 /* MII data out */ 603 #define MIIROM_MIIDIR 0x00040000 /* MII direction mode 604 1 = PHY in read, 605 0 = PHY in write */ 606 #define MIIROM_MDI 0x00080000 /* MII data in */ 607 #define MIIROM_DN 0x80000000 /* data not valid (21040) */ 608 609 #define MIIROM_PMAC_LED0SEL 0x10000000 /* 0 == LED0 activity (def) 610 1 == LED0 speed */ 611 #define MIIROM_PMAC_LED1SEL 0x20000000 /* 0 == LED1 link (def) 612 1 == LED1 link/act */ 613 #define MIIROM_PMAC_LED2SEL 0x40000000 /* 0 == LED2 speed (def) 614 1 == LED2 collision */ 615 #define MIIROM_PMAC_LED3SEL 0x80000000 /* 0 == LED3 receive (def) 616 1 == LED3 full duplex */ 617 618 /* SROM opcodes */ 619 #define TULIP_SROM_OPC_ERASE 0x04 620 #define TULIP_SROM_OPC_WRITE 0x05 621 #define TULIP_SROM_OPC_READ 0x06 622 623 /* The Lite-On PNIC does this completely differently */ 624 #define PNIC_MIIROM_DATA 0x0000ffff /* mask of data bits ??? */ 625 #define PNIC_MIIROM_BUSY 0x80000000 /* EEPROM is busy */ 626 627 628 /* CSR10 - Boot ROM address register (21041+). */ 629 #define CSR_ROMADDR TULIP_CSR10 630 #define ROMADDR_MASK 0x000003ff /* boot rom address */ 631 632 633 /* CSR11 - General Purpose Timer (21041+). */ 634 #define CSR_GPT TULIP_CSR11 635 #define GPT_VALUE 0x0000ffff /* timer value */ 636 #define GPT_CON 0x00010000 /* continuous mode */ 637 /* 21143-PD and 21143-TD Interrupt Mitigation bits */ 638 #define GPT_NRX 0x000e0000 /* number of Rx packets */ 639 #define GPT_RXT 0x00f00000 /* Rx timer */ 640 #define GPT_NTX 0x07000000 /* number of Tx packets */ 641 #define GPT_TXT 0x78000000 /* Tx timer */ 642 #define GPT_CYCLE 0x80000000 /* cycle size */ 643 644 645 /* CSR12 - SIA Status Register. */ 646 #define CSR_SIASTAT TULIP_CSR12 647 #define SIASTAT_PAUI 0x00000001 /* pin AUI/TP indication 648 (21040) */ 649 #define SIASTAT_MRA 0x00000001 /* MII receive activity 650 (21142) */ 651 #define SIASTAT_NCR 0x00000002 /* network connection error */ 652 #define SIASTAT_LS100 0x00000002 /* 100baseT link status 653 0 == pass (21142) */ 654 #define SIASTAT_LKF 0x00000004 /* link fail status */ 655 #define SIASTAT_LS10 0x00000004 /* 10baseT link status 656 0 == pass (21142) */ 657 #define SIASTAT_APS 0x00000008 /* auto polarity status */ 658 #define SIASTAT_DSD 0x00000010 /* PLL self test done */ 659 #define SIASTAT_DSP 0x00000020 /* PLL self test pass */ 660 #define SIASTAT_DAZ 0x00000040 /* PLL all zero */ 661 #define SIASTAT_DAO 0x00000080 /* PLL all one */ 662 #define SIASTAT_SRA 0x00000100 /* selected port receive 663 activity (21041) */ 664 #define SIASTAT_ARA 0x00000100 /* AUI receive activity 665 (21142) */ 666 #define SIASTAT_NRA 0x00000200 /* non-selected port 667 receive activity (21041) */ 668 #define SIASTAT_TRA 0x00000200 /* 10base-T receive activity 669 (21142) */ 670 #define SIASTAT_NSN 0x00000400 /* non-stable NLPs detected 671 (21041) */ 672 #define SIASTAT_TRF 0x00000800 /* transmit remote fault 673 (21041) */ 674 #define SIASTAT_ANS 0x00007000 /* autonegotiation state 675 (21041) */ 676 #define SIASTAT_ANS_DIS 0x00000000 /* disabled */ 677 #define SIASTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 678 #define SIASTAT_ANS_ABD 0x00002000 /* ability detect */ 679 #define SIASTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 680 #define SIASTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 681 #define SIASTAT_ANS_FLPGOOD 0x00005000 /* FLP link good */ 682 #define SIASTAT_ANS_LINKCHECK 0x00006000 /* link check */ 683 #define SIASTAT_LPN 0x00008000 /* link partner negotiable 684 (21041) */ 685 #define SIASTAT_LPC 0xffff0000 /* link partner code word */ 686 687 #define SIASTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 688 689 690 /* CSR13 - SIA Connectivity Register. */ 691 #define CSR_SIACONN TULIP_CSR13 692 #define SIACONN_SRL 0x00000001 /* SIA reset 693 (0 == reset) */ 694 #define SIACONN_PS 0x00000002 /* pin AUI/TP selection 695 (21040) */ 696 #define SIACONN_CAC 0x00000004 /* CSR autoconfiguration */ 697 #define SIACONN_AUI 0x00000008 /* select AUI (0 = TP) */ 698 #define SIACONN_EDP 0x00000010 /* SIA PLL external input 699 enable (21040) */ 700 #define SIACONN_ENI 0x00000020 /* encoder input multiplexer 701 (21040) */ 702 #define SIACONN_SIM 0x00000040 /* serial interface input 703 multiplexer (21040) */ 704 #define SIACONN_ASE 0x00000080 /* APLL start enable 705 (21040) */ 706 #define SIACONN_SEL 0x00000f00 /* external port output 707 multiplexer select 708 (21040) */ 709 #define SIACONN_IE 0x00001000 /* input enable (21040) */ 710 #define SIACONN_OE1_3 0x00002000 /* output enable 1, 3 711 (21040) */ 712 #define SIACONN_OE2_4 0x00004000 /* output enable 2, 4 713 (21040) */ 714 #define SIACONN_OE5_6_7 0x00008000 /* output enable 5, 6, 7 715 (21040) */ 716 #define SIACONN_SDM 0x0000ef00 /* SIA diagnostic mode; 717 always set to this value 718 for normal operation 719 (21041) */ 720 721 722 /* CSR14 - SIA Transmit Receive Register. */ 723 #define CSR_SIATXRX TULIP_CSR14 724 #define SIATXRX_ECEN 0x00000001 /* encoder enable */ 725 #define SIATXRX_LBK 0x00000002 /* loopback enable */ 726 #define SIATXRX_DREN 0x00000004 /* driver enable */ 727 #define SIATXRX_LSE 0x00000008 /* link pulse send enable */ 728 #define SIATXRX_CPEN 0x00000030 /* compensation enable */ 729 #define SIATXRX_CPEN_DIS0 0x00000000 /* disabled */ 730 #define SIATXRX_CPEN_DIS1 0x00000010 /* disabled */ 731 #define SIATXRX_CPEN_HIGHPWR 0x00000020 /* high power */ 732 #define SIATXRX_CPEN_NORMAL 0x00000030 /* normal */ 733 #define SIATXRX_MBO 0x00000040 /* must be one (21041 pass 2) */ 734 #define SIATXRX_TH 0x00000040 /* 10baseT HDX enable (21142) */ 735 #define SIATXRX_ANE 0x00000080 /* autonegotiation enable 736 (21041/21142) */ 737 #define SIATXRX_RSQ 0x00000100 /* receive squelch enable */ 738 #define SIATXRX_CSQ 0x00000200 /* collision squelch enable */ 739 #define SIATXRX_CLD 0x00000400 /* collision detect enable */ 740 #define SIATXRX_SQE 0x00000800 /* signal quality generation 741 enable */ 742 #define SIATXRX_LTE 0x00001000 /* link test enable */ 743 #define SIATXRX_APE 0x00002000 /* auto-polarity enable */ 744 #define SIATXRX_SPP 0x00004000 /* set plarity plus */ 745 #define SIATXRX_TAS 0x00008000 /* 10base-T/AUI autosensing 746 enable (21041/21142) */ 747 #define SIATXRX_THX 0x00010000 /* 100baseTX-HDX (21142) */ 748 #define SIATXRX_TXF 0x00020000 /* 100baseTX-FDX (21142) */ 749 #define SIATXRX_T4 0x00040000 /* 100baseT4 (21142) */ 750 751 752 /* CSR15 - SIA General Register. */ 753 #define CSR_SIAGEN TULIP_CSR15 754 #define SIAGEN_JBD 0x00000001 /* jabber disable */ 755 #define SIAGEN_HUJ 0x00000002 /* host unjab */ 756 #define SIAGEN_JCK 0x00000004 /* jabber clock */ 757 #define SIAGEN_ABM 0x00000008 /* BNC select (21041) */ 758 #define SIAGEN_RWD 0x00000010 /* receive watchdog disable */ 759 #define SIAGEN_RWR 0x00000020 /* receive watchdog release */ 760 #define SIAGEN_LE1 0x00000040 /* LED 1 enable (21041) */ 761 #define SIAGEN_LV1 0x00000080 /* LED 1 value (21041) */ 762 #define SIAGEN_TSCK 0x00000100 /* test clock */ 763 #define SIAGEN_FUSQ 0x00000200 /* force unsquelch */ 764 #define SIAGEN_FLF 0x00000400 /* force link fail */ 765 #define SIAGEN_LSD 0x00000800 /* LED stretch disable 766 (21041) */ 767 #define SIAGEN_LEE 0x00000800 /* Link extend enable (21142) */ 768 #define SIAGEN_DPST 0x00001000 /* PLL self-test start */ 769 #define SIAGEN_FRL 0x00002000 /* force receiver low */ 770 #define SIAGEN_LE2 0x00004000 /* LED 2 enable (21041) */ 771 #define SIAGEN_RMP 0x00004000 /* received magic packet 772 (21143) */ 773 #define SIAGEN_LV2 0x00008000 /* LED 2 value (21041) */ 774 #define SIAGEN_HCKR 0x00008000 /* hacker (21143) */ 775 #define SIAGEN_MD 0x000f0000 /* general purpose mode/data */ 776 #define SIAGEN_LGS 0x00f00000 /* LED/GEP select */ 777 #define SIAGEN_GEI0 0x01000000 /* GEP pin 0 intr enable */ 778 #define SIAGEN_GEI1 0x02000000 /* GEP pin 1 intr enable */ 779 #define SIAGEN_RME 0x04000000 /* receive match enable */ 780 #define SIAGEN_CWE 0x08000000 /* control write enable */ 781 #define SIAGEN_GI0 0x10000000 /* GEP pin 0 interrupt */ 782 #define SIAGEN_GI1 0x20000000 /* GEP pin 1 interrupt */ 783 #define SIAGEN_RMI 0x40000000 /* receive match interrupt */ 784 785 786 /* CSR12 - General Purpose Port (21140+). */ 787 #define CSR_GPP TULIP_CSR12 788 #define GPP_MD 0x000000ff /* general purpose mode/data */ 789 #define GPP_GPC 0x00000100 /* general purpose control */ 790 #define GPP_PNIC_GPD 0x0000000f /* general purpose data */ 791 #define GPP_PNIC_GPC 0x000000f0 /* general purpose control */ 792 793 #define GPP_PNIC_IN(x) (1 << (x)) 794 #define GPP_PNIC_OUT(x, on) (((on) << (x)) | (1 << ((x) + 4))) 795 796 /* 797 * The Lite-On PNIC manual recommends the following for the General Purpose 798 * I/O pins: 799 * 800 * 0 Speed Relay 1 == 100mbps 801 * 1 100mbps loopback 1 == loopback 802 * 2 BNC DC-DC converter 1 == select BNC 803 * 3 Link 100 1 == 100baseTX link status 804 */ 805 #define GPP_PNIC_PIN_SPEED_RLY 0 806 #define GPP_PNIC_PIN_100M_LPKB 1 807 #define GPP_PNIC_PIN_BNC_XMER 2 808 #define GPP_PNIC_PIN_LNK100X 3 809 810 811 /* 812 * Digital Semiconductor 21040 registers. 813 */ 814 815 /* CSR11 - Full Duplex Register */ 816 #define CSR_21040_FDX TULIP_CSR11 817 #define FDX21040_FDXACV 0x0000ffff /* full duplex 818 autoconfiguration value */ 819 820 821 /* SIA configuration for 10base-T (from the 21040 manual) */ 822 #define SIACONN_21040_10BASET 0x0000ef01 823 #define SIATXRX_21040_10BASET 0x0000ffff 824 #define SIAGEN_21040_10BASET 0x00000000 825 826 827 /* SIA configuration for 10base-T full-duplex (from the 21040 manual) */ 828 #define SIACONN_21040_10BASET_FDX 0x0000ef01 829 #define SIATXRX_21040_10BASET_FDX 0x0000fffd 830 #define SIAGEN_21040_10BASET_FDX 0x00000000 831 832 833 /* SIA configuration for 10base-5 (from the 21040 manual) */ 834 #define SIACONN_21040_AUI 0x0000ef09 835 #define SIATXRX_21040_AUI 0x00000705 836 #define SIAGEN_21040_AUI 0x00000006 837 838 839 /* SIA configuration for External SIA (from the 21040 manual) */ 840 #define SIACONN_21040_EXTSIA 0x00003041 841 #define SIATXRX_21040_EXTSIA 0x00000000 842 #define SIAGEN_21040_EXTSIA 0x00000006 843 844 845 /* 846 * Digital Semiconductor 21041 registers. 847 */ 848 849 /* SIA configuration for 10base-T (from the 21041 manual) */ 850 #define SIACONN_21041_10BASET 0x0000ef01 851 #define SIATXRX_21041_10BASET 0x0000ff3f 852 #define SIAGEN_21041_10BASET 0x00000000 853 854 #define SIACONN_21041P2_10BASET SIACONN_21041_10BASET 855 #define SIATXRX_21041P2_10BASET 0x0000ffff 856 #define SIAGEN_21041P2_10BASET SIAGEN_21041_10BASET 857 858 859 /* SIA configuration for 10base-T full-duplex (from the 21041 manual) */ 860 #define SIACONN_21041_10BASET_FDX 0x0000ef01 861 #define SIATXRX_21041_10BASET_FDX 0x0000ff3d 862 #define SIAGEN_21041_10BASET_FDX 0x00000000 863 864 #define SIACONN_21041P2_10BASET_FDX SIACONN_21041_10BASET_FDX 865 #define SIATXRX_21041P2_10BASET_FDX 0x0000ffff 866 #define SIAGEN_21041P2_10BASET_FDX SIAGEN_21041_10BASET_FDX 867 868 869 /* SIA configuration for 10base-5 (from the 21041 manual) */ 870 #define SIACONN_21041_AUI 0x0000ef09 871 #define SIATXRX_21041_AUI 0x0000f73d 872 #define SIAGEN_21041_AUI 0x0000000e 873 874 #define SIACONN_21041P2_AUI SIACONN_21041_AUI 875 #define SIATXRX_21041P2_AUI 0x0000f7fd 876 #define SIAGEN_21041P2_AUI SIAGEN_21041_AUI 877 878 879 /* SIA configuration for 10base-2 (from the 21041 manual) */ 880 #define SIACONN_21041_BNC 0x0000ef09 881 #define SIATXRX_21041_BNC 0x0000f73d 882 #define SIAGEN_21041_BNC 0x00000006 883 884 #define SIACONN_21041P2_BNC SIACONN_21041_BNC 885 #define SIATXRX_21041P2_BNC 0x0000f7fd 886 #define SIAGEN_21041P2_BNC SIAGEN_21041_BNC 887 888 889 /* 890 * Digital Semiconductor 21142/21143 registers. 891 */ 892 893 /* SIA configuration for 10baseT (from the 21143 manual) */ 894 #define SIACONN_21142_10BASET 0x00000001 895 #define SIATXRX_21142_10BASET 0x00007f3f 896 #define SIAGEN_21142_10BASET 0x00000008 897 898 899 /* SIA configuration for 10baseT full-duplex (from the 21143 manual) */ 900 #define SIACONN_21142_10BASET_FDX 0x00000001 901 #define SIATXRX_21142_10BASET_FDX 0x00007f3d 902 #define SIAGEN_21142_10BASET_FDX 0x00000008 903 904 905 /* SIA configuration for 10base5 (from the 21143 manual) */ 906 #define SIACONN_21142_AUI 0x00000009 907 #define SIATXRX_21142_AUI 0x00004705 908 #define SIAGEN_21142_AUI 0x0000000e 909 910 911 /* SIA configuration for 10base2 (from the 21143 manual) */ 912 #define SIACONN_21142_BNC 0x00000009 913 #define SIATXRX_21142_BNC 0x00004705 914 #define SIAGEN_21142_BNC 0x00000006 915 916 917 /* 918 * Lite-On 82C168/82C169 registers. 919 */ 920 921 /* ENDEC General Register */ 922 #define CSR_PNIC_ENDEC 0x78 923 #define PNIC_ENDEC_JDIS 0x00000001 /* jabber disable */ 924 925 /* SROM Power Register */ 926 #define CSR_PNIC_SROMPWR 0x90 927 #define PNIC_SROMPWR_MRLE 0x00000001 /* Memory-Read-Line enable */ 928 #define PNIC_SROMPWR_CB 0x00000002 /* cache boundary alignment 929 burst type; 1 == burst to 930 boundary, 0 == single-cycle 931 to boundary */ 932 933 /* SROM Control Register */ 934 #define CSR_PNIC_SROMCTL 0x98 935 #define PNIC_SROMCTL_addr 0x0000003f /* mask of address bits */ 936 /* XXX THESE ARE WRONG ACCORDING TO THE MANUAL! */ 937 #define PNIC_SROMCTL_READ 0x00000600 /* read command */ 938 939 /* MII Access Register */ 940 #define CSR_PNIC_MII 0xa0 941 #define PNIC_MII_DATA 0x0000ffff /* mask of data bits */ 942 #define PNIC_MII_REG 0x007c0000 /* register mask */ 943 #define PNIC_MII_REGSHIFT 18 944 #define PNIC_MII_PHY 0x0f800000 /* phy mask */ 945 #define PNIC_MII_PHYSHIFT 23 946 #define PNIC_MII_OPCODE 0x30000000 /* opcode mask */ 947 #define PNIC_MII_RESERVED 0x00020000 /* must be one/must be zero; 948 2 bits are described here */ 949 #define PNIC_MII_MBO 0x40000000 /* must be one */ 950 #define PNIC_MII_BUSY 0x80000000 /* MII is busy */ 951 952 #define PNIC_MII_WRITE 0x10000000 /* write PHY command */ 953 #define PNIC_MII_READ 0x20000000 /* read PHY command */ 954 955 /* NWAY Register */ 956 #define CSR_PNIC_NWAY 0xb8 957 #define PNIC_NWAY_RS 0x00000001 /* reset NWay block */ 958 #define PNIC_NWAY_PD 0x00000002 /* power down NWay block */ 959 #define PNIC_NWAY_BX 0x00000004 /* bypass transciever */ 960 #define PNIC_NWAY_LC 0x00000008 /* AUI low current mode */ 961 #define PNIC_NWAY_UV 0x00000010 /* low squelch voltage */ 962 #define PNIC_NWAY_DX 0x00000020 /* disable TP pol. correction */ 963 #define PNIC_NWAY_TW 0x00000040 /* select TP (0 == AUI) */ 964 #define PNIC_NWAY_AF 0x00000080 /* AUI full/half step input 965 voltage */ 966 #define PNIC_NWAY_FD 0x00000100 /* full duplex mode */ 967 #define PNIC_NWAY_DL 0x00000200 /* disable link integrity 968 test */ 969 #define PNIC_NWAY_DM 0x00000400 /* disable AUI/TP autodetect */ 970 #define PNIC_NWAY_100 0x00000800 /* 1 == 100mbps, 0 == 10mbps */ 971 #define PNIC_NWAY_NW 0x00001000 /* enable NWay block */ 972 #define PNIC_NWAY_CAP10T 0x00002000 /* adv. 10baseT */ 973 #define PNIC_NWAY_CAP10TFDX 0x00004000 /* adv. 10baseT-FDX */ 974 #define PNIC_NWAY_CAP100TXFDX 0x00008000 /* adv. 100baseTX-FDX */ 975 #define PNIC_NWAY_CAP100TX 0x00010000 /* adv. 100baseTX */ 976 #define PNIC_NWAY_CAP100T4 0x00020000 /* adv. 100base-T4 */ 977 #define PNIC_NWAY_RN 0x02000000 /* re-negotiate enable */ 978 #define PNIC_NWAY_RF 0x04000000 /* remote fault detected */ 979 #define PNIC_NWAY_LPAR10T 0x08000000 /* link part. 10baseT */ 980 #define PNIC_NWAY_LPAR10TFDX 0x10000000 /* link part. 10baseT-FDX */ 981 #define PNIC_NWAY_LPAR100TXFDX 0x20000000 /* link part. 100baseTX-FDX */ 982 #define PNIC_NWAY_LPAR100TX 0x40000000 /* link part. 100baseTX */ 983 #define PNIC_NWAY_LPAR100T4 0x80000000 /* link part. 100base-T4 */ 984 #define PNIC_NWAY_LPAR_MASK 0xf8000000 985 986 987 /* 988 * Macronix 98713, 98713A, 98715, 98715A, 98725 and 989 * Lite-On 82C115 registers. 990 */ 991 992 /* 993 * Note, the MX98713 is very Tulip-like: 994 * 995 * CSR12 General Purpose Port (like 21140) 996 * CSR13 reserved 997 * CSR14 reserved 998 * CSR15 Watchdog Timer (like 21140) 999 * 1000 * The Macronix CSR12, CSR13, CSR14, and CSR15 exist only 1001 * on the MX98713A and higher. 1002 */ 1003 1004 /* CSR12 - 10base-T Status Port (similar to SIASTAT) */ 1005 /* See SIASTAT 21142/21143 bits */ 1006 #define CSR_PMAC_10TSTAT TULIP_CSR12 1007 #define PMAC_SIASTAT_MASK (SIASTAT_LS100|SIASTAT_LS10| \ 1008 SIASTAT_APS|SIASTAT_TRF|SIASTAT_ANS| \ 1009 SIASTAT_LPN|SIASTAT_LPC) 1010 1011 1012 /* CSR13 - NWAY Reset Register */ 1013 #define CSR_PMAC_NWAYRESET TULIP_CSR13 1014 /* See SIACONN 21142/21143 bits */ 1015 #define PMAC_SIACONN_MASK (SIACONN_SRL) 1016 #define PMAC_NWAYRESET_100TXRESET 0x00000002 /* 100base PMD reset */ 1017 1018 1019 /* CSR14 - 10base-T Control Port */ 1020 #define CSR_PMAC_10TCTL TULIP_CSR14 1021 /* See SIATXRX 21142/21143 bits */ 1022 #define PMAC_SIATXRX_MASK (SIATXRX_LBK|SIATXRX_DREN|SIATXRX_TH| \ 1023 SIATXRX_ANE|SIATXRX_RSQ|SIATXRX_LTE| \ 1024 SIATXRX_THX|SIATXRX_TXF|SIATXRX_T4) 1025 1026 1027 /* CSR15 - Watchdog Timer Register */ 1028 /* MX98713: see 21140 CSR15 */ 1029 /* others: see SIAGEN 21142/21143 bits */ 1030 #define PMAC_SIAGEN_MASK (SIAGEN_JBD|SIAGEN_HUJ|SIAGEN_JCK| \ 1031 SIAGEN_RWD|SIAGEN_RWR) 1032 1033 1034 /* CSR16 - Test Operation Register (a.k.a. Magic Packet Register) */ 1035 #define CSR_PMAC_TOR TULIP_CSR16 1036 #define PMAC_TOR_98713 0x0F370000 1037 #define PMAC_TOR_98715 0x0B3C0000 1038 1039 1040 /* CSR20 - NWAY Status */ 1041 #define CSR_PMAC_NWAYSTAT TULIP_CSR20 1042 /* 1043 * Note: the MX98715A manual claims that EQTEST and PCITEST 1044 * must be set to 1 by software for normal operation, but 1045 * this does not appear to be necessary. This is probably 1046 * one of the things that frobbing the Test Operation Register 1047 * does. 1048 */ 1049 #define PMAC_NWAYSTAT_EQTEST 0x00001000 /* EQ test */ 1050 #define PMAC_NWAYSTAT_PCITEST 0x00010000 /* PCI test */ 1051 #define PMAC_NWAYSTAT_10TXH 0x08000000 /* 10t accepted */ 1052 #define PMAC_NWAYSTAT_10TXF 0x10000000 /* 10t-fdx accepted */ 1053 #define PMAC_NWAYSTAT_100TXH 0x20000000 /* 100tx accepted */ 1054 #define PMAC_NWAYSTAT_100TXF 0x40000000 /* 100tx-fdx accepted */ 1055 #define PMAC_NWAYSTAT_T4 0x80000000 /* 100t4 accepted */ 1056 1057 1058 /* CSR21 - Flow Control Register */ 1059 #define CSR_PNICII_FLOWCTL TULIP_CSR21 1060 #define PNICII_FLOWCTL_WKFCATEN 0x00000010 /* enable wake-up frame 1061 catenation feature */ 1062 #define PNICII_FLOWCTL_NFCE 0x00000020 /* accept flow control result 1063 from NWay */ 1064 #define PNICII_FLOWCTL_FCTH0 0x00000040 /* rx flow control thresh 0 */ 1065 #define PNICII_FLOWCTL_FCTH1 0x00000080 /* rx flow control thresh 1 */ 1066 #define PNICII_FLOWCTL_REJECTFC 0x00000100 /* abort rx flow control */ 1067 #define PNICII_FLOWCTL_STOPTX 0x00000200 /* tx flow stopped */ 1068 #define PNICII_FLOWCTL_RUFCEN 0x00000400 /* send flow control when 1069 RU interrupt occurs */ 1070 #define PNICII_FLOWCTL_RXFCEN 0x00000800 /* rx flow control enable */ 1071 #define PNICII_FLOWCTL_TXFCEN 0x00001000 /* tx flow control enable */ 1072 #define PNICII_FLOWCTL_RESTOP 0x00002000 /* restop mode */ 1073 #define PNICII_FLOWCTL_RESTART 0x00004000 /* restart mode */ 1074 #define PNICII_FLOWCTL_TEST 0x00008000 /* test flow control timer */ 1075 #define PNICII_FLOWCTL_TMVAL 0xffff0000 /* timer value in flow 1076 control frame */ 1077 1078 #define PNICII_FLOWCTL_TH_512 (PNICII_FLOWCTL_FCTH0|PNICII_FLOWCTL_FCTH1) 1079 #define PNICII_FLOWCTL_TH_256 (PNICII_FLOWCTL_FCTH1) 1080 #define PNICII_FLOWCTL_TH_128 (PNICII_FLOWCTL_FCTH0) 1081 #define PNICII_FLOWCTL_TH_OVFLW (0) 1082 1083 1084 /* CSR22 - MAC ID Byte 3-0 Register */ 1085 #define CSR_PNICII_MACID0 TULIP_CSR22 1086 #define PNICII_MACID_1 0 /* shift */ 1087 #define PNICII_MACID_0 8 /* shift */ 1088 #define PNICII_MACID_3 16 /* shift */ 1089 #define PNICII_MACID_2 24 /* shift */ 1090 1091 1092 /* CSR23 - Magic ID Byte 5,4/MACID Byte 5,4 Register */ 1093 #define PNICII_MACID_5 0 /* shift */ 1094 #define PNICII_MACID_4 8 /* shift */ 1095 #define PNICII_MAGID_5 16 /* shift */ 1096 #define PNICII_MAGIC_4 24 /* shift */ 1097 1098 1099 /* CSR24 - Magic ID Byte 3-0 Register */ 1100 #define PNICII_MAGID_1 0 /* shift */ 1101 #define PNICII_MAGID_0 8 /* shift */ 1102 #define PNICII_MAGID_3 16 /* shift */ 1103 #define PNICII_MAGID_2 24 /* shift */ 1104 1105 1106 /* CSR25 - CSR28 - Filter Byte Mask Registers */ 1107 #define CSR_PNICII_MASK0 TULIP_CSR25 1108 1109 #define CSR_PNICII_MASK1 TULIP_CSR26 1110 1111 #define CSR_PNICII_MASK2 TULIP_CSR27 1112 1113 #define CSR_PNICII_MASK3 TULIP_CSR28 1114 1115 1116 /* CSR29 - Filter Offset Register */ 1117 #define CSR_PNICII_FILOFF TULIP_CSR29 1118 #define PNICII_FILOFF_PAT0 0x0000007f /* pattern 0 offset */ 1119 #define PNICII_FILOFF_EN0 0x00000080 /* enable pattern 0 */ 1120 #define PNICII_FILOFF_PAT1 0x00007f00 /* pattern 1 offset */ 1121 #define PNICII_FILOFF_EN1 0x00008000 /* enable pattern 1 */ 1122 #define PNICII_FILOFF_PAT2 0x007f0000 /* pattern 2 offset */ 1123 #define PNICII_FILOFF_EN2 0x00800000 /* enable pattern 2 */ 1124 #define PNICII_FILOFF_PAT3 0x7f000000 /* pattern 3 offset */ 1125 #define PNICII_FILOFF_EN3 0x80000000 /* enable pattern 3 */ 1126 1127 1128 /* CSR30 - Filter 1 and 0 CRC-16 Register */ 1129 #define CSR_PNICII_FIL01 TULIP_CSR30 1130 #define PNICII_FIL01_CRC0 0x0000ffff /* CRC-16 of pattern 0 */ 1131 #define PNICII_FIL01_CRC1 0xffff0000 /* CRC-16 of pattern 1 */ 1132 1133 1134 /* CSR31 = Filter 3 and 2 CRC-16 Register */ 1135 #define CSR_PNICII_FIL23 TULIP_CSR31 1136 #define PNICII_FIL23_CRC2 0x0000ffff /* CRC-16 of pattern 2 */ 1137 #define PNICII_FIL23_CRC3 0xffff0000 /* CRC-16 of pattern 3 */ 1138 1139 1140 /* 1141 * Winbond 89C840F registers. 1142 */ 1143 1144 /* CSR12 - Current Receive Descriptor Register */ 1145 #define CSR_WINB_CRDAR TULIP_CSR12 1146 1147 1148 /* CSR13 - Current Receive Buffer Register */ 1149 #define CSR_WINB_CCRBAR TULIP_CSR13 1150 1151 1152 /* CSR14 - Multicast Address Register 0 */ 1153 #define CSR_WINB_CMA0 TULIP_CSR14 1154 1155 1156 /* CSR15 - Multicast Address Register 1 */ 1157 #define CSR_WINB_CMA1 TULIP_CSR15 1158 1159 1160 /* CSR16 - Physical Address Register 0 */ 1161 #define CSR_WINB_CPA0 TULIP_CSR16 1162 1163 1164 /* CSR17 - Physical Address Register 1 */ 1165 #define CSR_WINB_CPA1 TULIP_CSR17 1166 1167 1168 /* CSR18 - Boot ROM Size Register */ 1169 #define CSR_WINB_CBRCR TULIP_CSR18 1170 #define WINB_CBRCR_NONE 0x00000000 /* no boot rom */ 1171 /* 0x00000001 also no boot rom */ 1172 #define WINB_CBRCR_8K 0x00000002 /* 8k */ 1173 #define WINB_CBRCR_16K 0x00000003 /* 16k */ 1174 #define WINB_CBRCR_32K 0x00000004 /* 32k */ 1175 #define WINB_CBRCR_64K 0x00000005 /* 64k */ 1176 #define WINB_CBRCR_128K 0x00000006 /* 128k */ 1177 #define WINB_CBRCR_256K 0x00000007 1178 1179 1180 /* CSR19 - Current Transmit Descriptor Register */ 1181 #define CSR_WINB_CTDAR TULIP_CSR19 1182 1183 1184 /* CSR20 - Current Transmit Buffer Register */ 1185 #define CSR_WINB_CTBAR TULIP_CSR20 1186 1187 1188 /* 1189 * ADMtek AL981 registers 1190 * 1191 * We define these as strict byte offsets into PCI space, since 1192 * not all of them have consistent access rules. 1193 */ 1194 1195 /* CSR13 - Wake-up Control/Status Register */ 1196 #define CSR_ADM_WCSR 0x68 1197 #define ADM_WCSR_LSC 0x00000001 /* link status changed */ 1198 #define ADM_WCSR_MPR 0x00000002 /* magic packet received */ 1199 #define ADM_WCSR_WFR 0x00000004 /* wake up frame received */ 1200 #define ADM_WCSR_LSCE 0x00000100 /* link status changed en. */ 1201 #define ADM_WCSR_MPRE 0x00000200 /* magic packet receive en. */ 1202 #define ADM_WCSR_WFRE 0x00000400 /* wake up frame receive en. */ 1203 #define ADM_WCSR_LINKON 0x00010000 /* link-on detect en. */ 1204 #define ADM_WCSR_LINKOFF 0x00020000 /* link-off detect en. */ 1205 #define ADM_WCSR_WP5E 0x02000000 /* wake up pat. 5 en. */ 1206 #define ADM_WCSR_WP4E 0x04000000 /* wake up pat. 4 en. */ 1207 #define ADM_WCSR_WP3E 0x08000000 /* wake up pat. 3 en. */ 1208 #define ADM_WCSR_WP2E 0x10000000 /* wake up pat. 2 en. */ 1209 #define ADM_WCSR_WP1E 0x20000000 /* wake up pat. 1 en. */ 1210 #define ADM_WCSR_CRCT 0x40000000 /* CRC-16 type: 1211 0 == 0000 initial 1212 1 == ffff initial */ 1213 1214 1215 /* CSR14 - Wake-up Pattern Data Register */ 1216 #define CSR_ADM_WPDR 0x70 1217 1218 /* 1219 * 25 consecutive longword writes are issued to WPDR to 1220 * program the wake-up pattern filter. The data written 1221 * is as follows: 1222 * 1223 * XXX 1224 */ 1225 1226 1227 /* CSR15 - see 21140 CSR15 (Watchdog Timer) */ 1228 1229 1230 /* CSR16 - Assistant CSR5 (Status Register 2) */ 1231 #define CSR_ADM_ASR 0x80 1232 /* 0 - 14: same as CSR5 */ 1233 #define ADM_ASR_AAISS 0x00080000 /* added abnormal int. sum. */ 1234 #define ADM_ASR_ANISS 0x00010000 /* added normal int. sum. */ 1235 /* XXX Receive state */ 1236 /* XXX Transmit state */ 1237 #define ADM_ASR_BET 0x03800000 /* bus error type */ 1238 #define ADM_ASR_BET_PERR 0x00000000 /* parity error */ 1239 #define ADM_ASR_BET_MABT 0x00800000 /* master abort */ 1240 #define ADM_ASR_BET_TABT 0x01000000 /* target abort */ 1241 #define ADM_ASR_PFR 0x04000000 /* PAUSE frame received */ 1242 #define ADM_ASR_TDIS 0x10000000 /* transmit def. int. status */ 1243 #define ADM_ASR_XIS 0x20000000 /* xcvr int. status */ 1244 #define ADM_ASR_REIS 0x40000000 /* receive early int. status */ 1245 #define ADM_ASR_TEIS 0x80000000 /* transmit early int. status */ 1246 1247 1248 /* CSR17 - Assistant CSR7 (Interrupt Enable Register 2) */ 1249 #define CSR_ADM_AIE 0x84 1250 /* See CSR16 for valid bits */ 1251 1252 1253 /* CSR18 - Command Register */ 1254 #define CSR_ADM_CR 0x88 1255 #define ADM_CR_ATUR 0x00000001 /* auto. tx underrun recover */ 1256 #define ADM_CR_SINT 0x00000002 /* software interrupt */ 1257 #define ADM_CR_DRT 0x0000000c /* drain recieve threshold */ 1258 #define ADM_CR_DRT_8LW 0x00000000 /* 8 longwords */ 1259 #define ADM_CR_DRT_16LW 0x00000004 /* 16 longwords */ 1260 #define ADM_CR_DRT_SF 0x00000008 /* store-and-forward */ 1261 #define ADM_CR_RTE 0x00000010 /* receive threshold enable */ 1262 #define ADM_CR_PAUSE 0x00000020 /* enable PAUSE function */ 1263 #define ADM_CR_RWP 0x00000040 /* reset wake-up pattern 1264 data register pointer */ 1265 /* 16 - 31 are automatically recalled from the EEPROM */ 1266 #define ADM_CR_WOL 0x00040000 /* wake-on-lan enable */ 1267 #define ADM_CR_PM 0x00080000 /* power management enable */ 1268 #define ADM_CR_RFS 0x00600000 /* Receive FIFO size */ 1269 #define ADM_CR_RFS_1K 0x00600000 /* 1K FIFO */ 1270 #define ADM_CR_RFS_2K 0x00400000 /* 2K FIFO */ 1271 #define ADM_CR_LEDMODE 0x00800000 /* LED mode */ 1272 #define ADM_CR_AUXCL 0x30000000 /* aux current load */ 1273 #define ADM_CR_D3CS 0x80000000 /* D3 cold wake up enable */ 1274 1275 1276 /* CSR19 - PCI bus performance counter */ 1277 #define CSR_ADM_PCIC 0x8c 1278 #define ADM_PCIC_DWCNT 0x000000ff /* double-word count of 1279 last bus-master 1280 transaction */ 1281 #define ADM_PCIC_CLKCNT 0xffff0000 /* number of PCI clocks 1282 between read request 1283 and access completed */ 1284 1285 /* CSR20 - Power Management Control/Status Register */ 1286 #define CSR_ADM_PMCSR 0x90 1287 /* 1288 * This register is also mapped into the PCI configuration 1289 * space as the PMCSR. 1290 */ 1291 1292 1293 /* CSR23 - Transmit Burst Count/Time Out Register */ 1294 #define CSR_ADM_TXBR 0x9c 1295 #define ADM_TXBR_TTO 0x00000fff /* transmit timeout */ 1296 #define ADM_TXBR_TBCNT 0x001f0000 /* transmit burst count */ 1297 1298 1299 /* CSR24 - Flash ROM Port Register */ 1300 #define CSR_ADM_FROM 0xa0 1301 #define ADM_FROM_DATA 0x000000ff /* data to/from Flash */ 1302 #define ADM_FROM_ADDR 0x01ffff00 /* Flash address */ 1303 #define ADM_FROM_ADDR_SHIFT 8 1304 #define ADM_FROM_WEN 0x04000000 /* write enable */ 1305 #define ADM_FROM_REN 0x08000000 /* read enable */ 1306 #define ADM_FROM_bra16on 0x80000000 /* pin 87 is brA16, else 1307 pin 87 is fd/col LED pin */ 1308 1309 1310 /* CSR25 - Physical Address Register 0 */ 1311 #define CSR_ADM_PAR0 0xa4 1312 1313 1314 /* CSR26 - Physical Address Register 1 */ 1315 #define CSR_ADM_PAR1 0xa8 1316 1317 1318 /* CSR27 - Multicast Address Register 0 */ 1319 #define CSR_ADM_MAR0 0xac 1320 1321 1322 /* CSR28 - Multicast Address Register 1 */ 1323 #define CSR_ADM_MAR1 0xb0 1324 1325 1326 /* Internal PHY registers are mapped here (lower 16 bits valid) */ 1327 1328 #define CSR_ADM_BMCR 0xb4 1329 #define CSR_ADM_BMSR 0xb8 1330 #define CSR_ADM_PHYIDR1 0xbc 1331 #define CSR_ADM_PHYIDR2 0xc0 1332 #define CSR_ADM_ANAR 0xc4 1333 #define CSR_ADM_ANLPAR 0xc8 1334 #define CSR_ADM_ANER 0xcc 1335 1336 /* XCVR Mode Control Register */ 1337 #define CSR_ADM_XMC 0xd0 1338 #define ADM_XMC_LD 0x00000800 /* long distance mode 1339 (low squelch enable) */ 1340 1341 1342 /* XCVR Configuration Information and Interrupt Status Register */ 1343 #define CSR_ADM_XCIIS 0xd4 1344 #define ADM_XCIIS_REF 0x0001 /* 64 error packets received */ 1345 #define ADM_XCIIS_ANPR 0x0002 /* autoneg page received */ 1346 #define ADM_XCIIS_PDF 0x0004 /* parallel detection fault */ 1347 #define ADM_XCIIS_ANAR 0x0008 /* autoneg ACK */ 1348 #define ADM_XCIIS_LS 0x0010 /* link status (1 == fail) */ 1349 #define ADM_XCIIS_RFD 0x0020 /* remote fault */ 1350 #define ADM_XCIIS_ANC 0x0040 /* autoneg completed */ 1351 #define ADM_XCIIS_PAUSE 0x0080 /* PAUSE enabled */ 1352 #define ADM_XCIIS_DUPLEX 0x0100 /* full duplex */ 1353 #define ADM_XCIIS_SPEED 0x0200 /* 100Mb/s */ 1354 1355 1356 /* XCVR Interrupt Enable Register */ 1357 #define CSR_ADM_XIE 0xd8 1358 /* Bits are as for XCIIS */ 1359 1360 1361 /* XCVR 100baseTX PHY Control/Status Register */ 1362 #define CSR_ADM_100CTR 0xdc 1363 #define ADM_100CTR_DISCRM 0x0001 /* disable scrambler */ 1364 #define ADM_100CTR_DISMLT 0x0002 /* disable MLT3 ENDEC */ 1365 #define ADM_100CTR_CMODE 0x001c /* current operating mode */ 1366 #define ADM_100CTR_CMODE_AUTO 0x0000 /* in autoneg */ 1367 #define ADM_100CTR_CMODE_10 0x0004 /* 10baseT */ 1368 #define ADM_100CTR_CMODE_100 0x0008 /* 100baseTX */ 1369 /* 0x000c reserved */ 1370 /* 0x0010 reserved */ 1371 #define ADM_100CTR_CMODE_10FD 0x0014 /* 10baseT-FDX */ 1372 #define ADM_100CTR_CMODE_100FD 0x0018 /* 100baseTX-FDX */ 1373 #define ADM_100CTR_CMODE_ISO 0x001c /* isolated */ 1374 #define ADM_100CTR_ISOTX 0x0020 /* transmit isolation */ 1375 #define ADM_100CTR_ENRZI 0x0080 /* enable NRZ <> NRZI conv. */ 1376 #define ADM_100CTR_ENDCR 0x0100 /* enable DC restoration */ 1377 #define ADM_100CTR_ENRLB 0x0200 /* enable remote loopback */ 1378 #define ADM_100CTR_RXVPP 0x0800 /* peak Rx voltage: 1379 0 == 1.0 VPP 1380 1 == 1.4 VPP */ 1381 #define ADM_100CTR_ANC 0x1000 /* autoneg completed */ 1382 #define ADM_100CTR_DISRER 0x2000 /* disable Rx error counter */ 1383 1384 #endif /* _DEV_IC_TULIPREG_H_ */ 1385
Indexes created Tue Sep 30 11:09:46 GMT 2025