tulipreg.h revision 1.18
1 /* $NetBSD: tulipreg.h,v 1.18 2000/04/04 19:22:52 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_IC_TULIPREG_H_ 41 #define _DEV_IC_TULIPREG_H_ 42 43 /* 44 * Register description for the Digital Semiconductor ``Tulip'' (21x4x) 45 * Ethernet controller family, and a variety of clone chips, including: 46 * 47 * - Macronix 98713, 98713A, 98715, 98715A, 98725 (PMAC): 48 * 49 * These chips are fairly straight-forward Tulip clones. 50 * The 98713 is a very close 21140A clone. It has GPR 51 * and MII media, and a GPIO facility, and uses the ISV 52 * SROM format (or, at least, should, because of the GPIO 53 * facility). The 98713A has MII, no GPIO facility, and 54 * an internal NWay block. The 98715, 98715A, and 98725 55 * have only GPR media and the NWay block. The 98715, 56 * 98715A, and 98725 support power management. 57 * 58 * - Lite-On 82C115 (PNIC II): 59 * 60 * A clone of the Macronix MX98725, with the following differences: 61 * 62 * - Wake-On-LAN support 63 * - 128-bit multicast hash table rather than the 64 * standard 512-bit hash table 65 * - 802.3x flow control 66 * 67 * - Lite-On 82C168, 82C169 (PNIC): 68 * 69 * Pretty close, with only a few minor differences: 70 * 71 * - EEPROM is accessed completely differently. 72 * - MII is accessed completely differently. 73 * - No SIO facility (due to the above two differences). 74 * - GPIO interface is different than the 21140's. 75 * - Boards that lack PHYs use the internal NWay block 76 * and transciever. 77 * 78 * - Winbond 89C840F 79 * 80 * Less similar, but still roughly compatible (enough so 81 * that the driver can be adapted, at least): 82 * 83 * - Registers lack the pad word between them. 84 * - Instead of a setup frame, there are two station 85 * address registers and two multicast hash table 86 * registers (64-bit multicast hash table). 87 * - Only supported media interface is MII-over-SIO. 88 * - Different OPMODE register bits for various things 89 * (mostly media related). 90 * 91 * - ADMtek AL981 92 * 93 * Another pretty-close clone: 94 * 95 * - Wake-On-LAN support 96 * - Instead of a setup frame, there are two station 97 * address registers and two multicast hash table 98 * registers (64-bit multicast hash table). 99 * - 802.3x flow control 100 * - Only supported media interface is built-in PHY 101 * which is accessed through a set of special registers. 102 * - Not all registers have the pad word between them, 103 * but luckily, there are all AL981-specific registers, 104 * so this is easy to deal with. 105 * 106 * - Xircom X3201-3 107 * 108 * CardBus 21143 clone, with a few differences: 109 * 110 * - No MicroWire SROM; Ethernet address must come 111 * from CIS. 112 * - Transmit buffers must also be 32-bit aligned. 113 * - The BUSMODE_SWR bit is not self-clearing. 114 * - SIA is not 21143-like, and all media attachments 115 * are MII-on-SIO. 116 * 117 * Some of the clone chips have different registers, and some have 118 * different bits in the same registers. These will be denoted by 119 * PMAC, PNICII, PNIC, WINB, and ADM in the register/bit names. 120 */ 121 122 /* 123 * Tulip buffer descriptor. Must be 4-byte aligned. 124 * 125 * Note for receive descriptors, the byte count fields must 126 * be a multiple of 4. 127 */ 128 struct tulip_desc { 129 __volatile u_int32_t td_status; /* Status */ 130 __volatile u_int32_t td_ctl; /* Control and Byte Counts */ 131 __volatile u_int32_t td_bufaddr1; /* Buffer Address 1 */ 132 __volatile u_int32_t td_bufaddr2; /* Buffer Address 2 */ 133 }; 134 135 /* 136 * Descriptor Status bits common to transmit and receive. 137 */ 138 #define TDSTAT_OWN 0x80000000 /* Tulip owns descriptor */ 139 #define TDSTAT_ES 0x00008000 /* Error Summary */ 140 141 /* 142 * Descriptor Status bits for Receive Descriptor. 143 */ 144 #define TDSTAT_Rx_FF 0x40000000 /* Filtering Fail */ 145 #define TDSTAT_WINB_Rx_RCMP 0x40000000 /* Receive Complete */ 146 #define TDSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */ 147 #define TDSTAT_Rx_DE 0x00004000 /* Descriptor Error */ 148 #define TDSTAT_Rx_DT 0x00003000 /* Data Type */ 149 #define TDSTAT_Rx_RF 0x00000800 /* Runt Frame */ 150 #define TDSTAT_Rx_MF 0x00000400 /* Multicast Frame */ 151 #define TDSTAT_Rx_FS 0x00000200 /* First Descriptor */ 152 #define TDSTAT_Rx_LS 0x00000100 /* Last Descriptor */ 153 #define TDSTAT_Rx_TL 0x00000080 /* Frame Too Long */ 154 #define TDSTAT_Rx_CS 0x00000040 /* Collision Seen */ 155 #define TDSTAT_Rx_RT 0x00000020 /* Frame Type */ 156 #define TDSTAT_Rx_RW 0x00000010 /* Receive Watchdog */ 157 #define TDSTAT_Rx_RE 0x00000008 /* Report on MII Error */ 158 #define TDSTAT_Rx_DB 0x00000004 /* Dribbling Bit */ 159 #define TDSTAT_Rx_CE 0x00000002 /* CRC Error */ 160 #define TDSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */ 161 162 #define TDSTAT_Rx_LENGTH(x) (((x) & TDSTAT_Rx_FL) >> 16) 163 164 #define TDSTAT_Rx_DT_SR 0x00000000 /* Serial Received Frame */ 165 #define TDSTAT_Rx_DT_IL 0x00001000 /* Internal Loopback Frame */ 166 #define TDSTAT_Rx_DT_EL 0x00002000 /* External Loopback Frame */ 167 #define TDSTAT_Rx_DT_r 0x00003000 /* Reserved */ 168 169 /* 170 * Descriptor Status bits for Transmit Descriptor. 171 */ 172 #define TDSTAT_WINB_Tx_TE 0x00008000 /* Transmit Error */ 173 #define TDSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */ 174 #define TDSTAT_Tx_LO 0x00000800 /* Loss of Carrier */ 175 #define TDSTAT_Tx_NC 0x00000400 /* No Carrier */ 176 #define TDSTAT_Tx_LC 0x00000200 /* Late Collision */ 177 #define TDSTAT_Tx_EC 0x00000100 /* Excessive Collisions */ 178 #define TDSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */ 179 #define TDSTAT_Tx_CC 0x00000078 /* Collision Count */ 180 #define TDSTAT_Tx_LF 0x00000004 /* Link Fail */ 181 #define TDSTAT_Tx_UF 0x00000002 /* Underflow Error */ 182 #define TDSTAT_Tx_DE 0x00000001 /* Deferred */ 183 184 #define TDSTAT_Tx_COLLISIONS(x) (((x) & TDSTAT_Tx_CC) >> 3) 185 186 /* 187 * Descriptor Control bits common to transmit and receive. 188 */ 189 #define TDCTL_SIZE1 0x000007ff /* Size of buffer 1 */ 190 #define TDCTL_SIZE1_SHIFT 0 191 192 #define TDCTL_SIZE2 0x003ff800 /* Size of buffer 2 */ 193 #define TDCTL_SIZE2_SHIFT 11 194 195 #define TDCTL_ER 0x02000000 /* End of Ring */ 196 #define TDCTL_CH 0x01000000 /* Second Address Chained */ 197 198 /* 199 * Descriptor Control bits for Transmit Descriptor. 200 */ 201 #define TDCTL_Tx_IC 0x80000000 /* Interrupt on Completion */ 202 #define TDCTL_Tx_LS 0x40000000 /* Last Segment */ 203 #define TDCTL_Tx_FS 0x20000000 /* First Segment */ 204 #define TDCTL_Tx_FT1 0x10000000 /* Filtering Type 1 */ 205 #define TDCTL_Tx_SET 0x08000000 /* Setup Packet */ 206 #define TDCTL_Tx_AC 0x04000000 /* Add CRC Disable */ 207 #define TDCTL_Tx_DPD 0x00800000 /* Disabled Padding */ 208 #define TDCTL_Tx_FT0 0x00400000 /* Filtering Type 0 */ 209 210 /* 211 * The Tulip filter is programmed by "transmitting" a Setup Packet 212 * (indicated by TDCTL_Tx_SET). The filtering type is indicated 213 * as follows: 214 * 215 * FT1 FT0 Description 216 * --- --- ----------- 217 * 0 0 Perfect Filtering: The Tulip interprets the 218 * descriptor buffer as a table of 16 MAC addresses 219 * that the Tulip should receive. 220 * 221 * 0 1 Hash Filtering: The Tulip interprets the 222 * descriptor buffer as a 512-bit hash table 223 * plus one perfect address. If the incoming 224 * address is Multicast, the hash table filters 225 * the address, else the address is filtered by 226 * the perfect address. 227 * 228 * 1 0 Inverse Filtering: Like Perfect Filtering, except 229 * the table is addresses that the Tulip does NOT 230 * receive. 231 * 232 * 1 1 Hash-only Filtering: Like Hash Filtering, but 233 * physical addresses are matched by the hash table 234 * as well, and not by matching a single perfect 235 * address. 236 * 237 * A Setup Packet must always be 192 bytes long. The Tulip can store 238 * 16 MAC addresses. If not all 16 are specified in Perfect Filtering 239 * or Inverse Filtering mode, then unused entries should duplicate 240 * one of the valid entries. 241 */ 242 #define TDCTL_Tx_FT_PERFECT 0 243 #define TDCTL_Tx_FT_HASH TDCTL_Tx_FT0 244 #define TDCTL_Tx_FT_INVERSE TDCTL_Tx_FT1 245 #define TDCTL_Tx_FT_HASHONLY (TDCTL_Tx_FT1|TDCTL_Tx_FT0) 246 247 #define TULIP_SETUP_PACKET_LEN 192 248 #define TULIP_MAXADDRS 16 249 #define TULIP_MCHASHSIZE 512 250 #define TULIP_PNICII_HASHSIZE 128 251 252 /* 253 * Maximum size of a Tulip Ethernet Address ROM or SROM. 254 */ 255 #define TULIP_ROM_SIZE(bits) (2 << (bits)) 256 #define TULIP_MAX_ROM_SIZE 512 257 258 /* 259 * Format of the standard Tulip SROM information: 260 * 261 * Byte offset Size Usage 262 * 0 18 reserved 263 * 18 1 SROM Format Version 264 * 19 1 Chip Count 265 * 20 6 IEEE Network Address 266 * 26 1 Chip 0 Device Number 267 * 27 2 Chip 0 Info Leaf Offset 268 * 29 1 Chip 1 Device Number 269 * 30 2 Chip 1 Info Leaf Offset 270 * 32 1 Chip 2 Device Number 271 * 33 2 Chip 2 Info Leaf Offset 272 * ... 1 Chip n Device Number 273 * ... 2 Chip n Info Leaf Offset 274 * ... ... ... 275 * Chip Info Leaf Information 276 * ... 277 * ... 278 * ... 279 * 126 2 CRC32 checksum 280 */ 281 #define TULIP_ROM_SROM_FORMAT_VERION 18 /* B */ 282 #define TULIP_ROM_CHIP_COUNT 19 /* B */ 283 #define TULIP_ROM_IEEE_NETWORK_ADDRESS 20 284 #define TULIP_ROM_CHIPn_DEVICE_NUMBER(n) (26 + ((n) * 3))/* B */ 285 #define TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(n) (27 + ((n) * 3))/* W */ 286 #define TULIP_ROM_CRC32_CHECKSUM 126 /* W */ 287 #define TULIP_ROM_CRC32_CHECKSUM1 94 /* W */ 288 289 #define TULIP_ROM_IL_SELECT_CONN_TYPE 0 /* W */ 290 #define TULIP_ROM_IL_MEDIA_COUNT 2 /* B */ 291 #define TULIP_ROM_IL_MEDIAn_BLOCK_BASE 3 292 293 #define SELECT_CONN_TYPE_TP 0x0000 294 #define SELECT_CONN_TYPE_BNC 0x0001 295 #define SELECT_CONN_TYPE_AUI 0x0002 296 #define SELECT_CONN_TYPE_100TX 0x0003 297 #define SELECT_CONN_TYPE_100T4 0x0006 298 #define SELECT_CONN_TYPE_100FX 0x0007 299 #define SELECT_CONN_TYPE MII_10T 0x0009 300 #define SELECT_CONN_TYPE_MII_100TX 0x000d 301 #define SELECT_CONN_TYPE_MII_100T4 0x000f 302 #define SELECT_CONN_TYPE_MII_100FX 0x0010 303 #define SELECT_CONN_TYPE_TP_AUTONEG 0x0100 304 #define SELECT_CONN_TYPE_TP_FDX 0x0204 305 #define SELECT_CONN_TYPE_MII_10T_FDX 0x020a 306 #define SELECT_CONN_TYPE_100TX_FDX 0x020e 307 #define SELECT_CONN_TYPE_MII_100TX_FDX 0x0211 308 #define SELECT_CONN_TYPE_TP_NOLINKPASS 0x0400 309 #define SELECT_CONN_TYPE_ASENSE 0x0800 310 #define SELECT_CONN_TYPE_ASENSE_POWERUP 0x8800 311 #define SELECT_CONN_TYPE_ASENSE_AUTONEG 0x0900 312 313 #define TULIP_ROM_MB_MEDIA_CODE 0x3f 314 #define TULIP_ROM_MB_MEDIA_TP 0x00 315 #define TULIP_ROM_MB_MEDIA_BNC 0x01 316 #define TULIP_ROM_MB_MEDIA_AUI 0x02 317 #define TULIP_ROM_MB_MEDIA_100TX 0x03 318 #define TULIP_ROM_MB_MEDIA_TP_FDX 0x04 319 #define TULIP_ROM_MB_MEDIA_100TX_FDX 0x05 320 #define TULIP_ROM_MB_MEDIA_100T4 0x06 321 #define TULIP_ROM_MB_MEDIA_100FX 0x07 322 #define TULIP_ROM_MB_MEDIA_100FX_FDX 0x08 323 324 #define TULIP_ROM_MB_EXT 0x40 325 326 #define TULIP_ROM_MB_CSR13 1 /* W */ 327 #define TULIP_ROM_MB_CSR14 3 /* W */ 328 #define TULIP_ROM_MB_CSR15 5 /* W */ 329 330 #define TULIP_ROM_MB_SIZE(mc) (((mc) & TULIP_ROM_MB_EXT) ? 7 : 1) 331 332 #define TULIP_ROM_MB_NOINDICATOR 0x8000 333 #define TULIP_ROM_MB_DEFAULT 0x4000 334 #define TULIP_ROM_MB_POLARITY 0x0080 335 #define TULIP_ROM_MB_OPMODE(x) (((x) & 0x71) << 18) 336 #define TULIP_ROM_MB_BITPOS(x) (1 << (((x) & 0x0e) >> 1)) 337 338 #define TULIP_ROM_MB_21140_GPR 0 /* 21140[A] GPR block */ 339 #define TULIP_ROM_MB_21140_MII 1 /* 21140[A] MII block */ 340 #define TULIP_ROM_MB_21142_SIA 2 /* 2114[23] SIA block */ 341 #define TULIP_ROM_MB_21142_MII 3 /* 2114[23] MII block */ 342 #define TULIP_ROM_MB_21143_SYM 4 /* 21143 SYM block */ 343 #define TULIP_ROM_MB_21143_RESET 5 /* 21143 reset block */ 344 345 #define TULIP_ROM_GETW(data, off) ((data)[(off)] | ((data)[(off) + 1]) << 8) 346 347 /* 348 * Tulip control registers. 349 */ 350 351 #define TULIP_CSR0 0x00 352 #define TULIP_CSR1 0x08 353 #define TULIP_CSR2 0x10 354 #define TULIP_CSR3 0x18 355 #define TULIP_CSR4 0x20 356 #define TULIP_CSR5 0x28 357 #define TULIP_CSR6 0x30 358 #define TULIP_CSR7 0x38 359 #define TULIP_CSR8 0x40 360 #define TULIP_CSR9 0x48 361 #define TULIP_CSR10 0x50 362 #define TULIP_CSR11 0x58 363 #define TULIP_CSR12 0x60 364 #define TULIP_CSR13 0x68 365 #define TULIP_CSR14 0x70 366 #define TULIP_CSR15 0x78 367 #define TULIP_CSR16 0x80 368 #define TULIP_CSR17 0x88 369 #define TULIP_CSR18 0x90 370 #define TULIP_CSR19 0x98 371 #define TULIP_CSR20 0xa0 372 #define TULIP_CSR21 0xa8 373 #define TULIP_CSR22 0xb0 374 #define TULIP_CSR23 0xb8 375 #define TULIP_CSR24 0xc0 376 #define TULIP_CSR25 0xc8 377 #define TULIP_CSR26 0xd0 378 #define TULIP_CSR27 0xd8 379 #define TULIP_CSR28 0xe0 380 #define TULIP_CSR29 0xe8 381 #define TULIP_CSR30 0xf0 382 #define TULIP_CSR31 0xf8 383 384 #define TULIP_CSR_INDEX(csr) ((csr) >> 3) 385 386 /* CSR0 - Bus Mode */ 387 #define CSR_BUSMODE TULIP_CSR0 388 #define BUSMODE_SWR 0x00000001 /* software reset */ 389 #define BUSMODE_BAR 0x00000002 /* bus arbitration */ 390 #define BUSMODE_DSL 0x0000007c /* descriptor skip length */ 391 #define BUSMODE_BLE 0x00000080 /* big endian */ 392 /* programmable burst length */ 393 #define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */ 394 #define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */ 395 #define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */ 396 #define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */ 397 #define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */ 398 #define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */ 399 #define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */ 400 /* cache alignment */ 401 #define BUSMODE_CAL_NONE 0x00000000 /* no alignment */ 402 #define BUSMODE_CAL_8LW 0x00004000 /* 8 longwords */ 403 #define BUSMODE_CAL_16LW 0x00008000 /* 16 longwords */ 404 #define BUSMODE_CAL_32LW 0x0000c000 /* 32 longwords */ 405 #define BUSMODE_DAS 0x00010000 /* diagnostic address space */ 406 /* must be zero on most */ 407 /* transmit auto-poll */ 408 /* 409 * Transmit auto-polling not supported on: 410 * Winbond 89C040F 411 * Xircom X3201-3 412 */ 413 #define BUSMODE_TAP_NONE 0x00000000 /* no auto-polling */ 414 #define BUSMODE_TAP_200us 0x00020000 /* 200 uS */ 415 #define BUSMODE_TAP_800us 0x00040000 /* 400 uS */ 416 #define BUSMODE_TAP_1_6ms 0x00060000 /* 1.6 mS */ 417 #define BUSMODE_TAP_12_8us 0x00080000 /* 12.8 uS (21041+) */ 418 #define BUSMODE_TAP_25_6us 0x000a0000 /* 25.6 uS (21041+) */ 419 #define BUSMODE_TAP_51_2us 0x000c0000 /* 51.2 uS (21041+) */ 420 #define BUSMODE_TAP_102_4us 0x000e0000 /* 102.4 uS (21041+) */ 421 #define BUSMODE_DBO 0x00100000 /* desc-only b/e (21041+) */ 422 #define BUSMODE_RME 0x00200000 /* rd/mult enab (21140+) */ 423 #define BUSMODE_WINB_WAIT 0x00200000 /* wait state insertion */ 424 #define BUSMODE_RLE 0x00800000 /* rd/line enab (21140+) */ 425 #define BUSMODE_WLE 0x01000000 /* wt/line enab (21140+) */ 426 #define BUSMODE_PNIC_MBO 0x04000000 /* magic `must be one' bit */ 427 /* on Lite-On PNIC */ 428 429 430 /* CSR1 - Transmit Poll Demand */ 431 #define CSR_TXPOLL TULIP_CSR1 432 #define TXPOLL_TPD 0x00000001 /* transmit poll demand */ 433 434 435 /* CSR2 - Receive Poll Demand */ 436 #define CSR_RXPOLL TULIP_CSR2 437 #define RXPOLL_RPD 0x00000001 /* receive poll demand */ 438 439 440 /* CSR3 - Receive List Base Address */ 441 #define CSR_RXLIST TULIP_CSR3 442 443 /* CSR4 - Transmit List Base Address */ 444 #define CSR_TXLIST TULIP_CSR4 445 446 /* CSR5 - Status */ 447 #define CSR_STATUS TULIP_CSR5 448 #define STATUS_TI 0x00000001 /* transmit interrupt */ 449 #define STATUS_TPS 0x00000002 /* transmit process stopped */ 450 #define STATUS_TU 0x00000004 /* transmit buffer unavail */ 451 #define STATUS_TJT 0x00000008 /* transmit jabber timeout */ 452 #define STATUS_WINB_REI 0x00000008 /* receive early interrupt */ 453 #define STATUS_LNPANC 0x00000010 /* link pass (21041) */ 454 #define STATUS_WINB_RERR 0x00000010 /* receive error */ 455 #define STATUS_UNF 0x00000020 /* transmit underflow */ 456 #define STATUS_RI 0x00000040 /* receive interrupt */ 457 #define STATUS_RU 0x00000080 /* receive buffer unavail */ 458 #define STATUS_RPS 0x00000100 /* receive process stopped */ 459 #define STATUS_RWT 0x00000200 /* receive watchdog timeout */ 460 #define STATUS_AT 0x00000400 /* SIA AUI/TP pin changed 461 (21040) */ 462 #define STATUS_ETI 0x00000400 /* early transmit interrupt 463 (21142/PMAC/Winbond) */ 464 #define STATUS_FD 0x00000800 /* full duplex short frame 465 received (21040) */ 466 #define STATUS_TM 0x00000800 /* timer expired (21041) */ 467 #define STATUS_LNF 0x00001000 /* link fail (21040) */ 468 #define STATUS_SE 0x00002000 /* system error */ 469 #define STATUS_ER 0x00004000 /* early receive (21041) */ 470 #define STATUS_AIS 0x00008000 /* abnormal interrupt summary */ 471 #define STATUS_NIS 0x00010000 /* normal interrupt summary */ 472 #define STATUS_RS 0x000e0000 /* receive process state */ 473 #define STATUS_RS_STOPPED 0x00000000 /* Stopped */ 474 #define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive 475 descriptor */ 476 #define STATUS_RS_CHECK 0x00040000 /* Running - check for end 477 of receive */ 478 #define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */ 479 #define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */ 480 #define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive 481 descriptor */ 482 #define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current 483 frame from FIFO */ 484 #define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current 485 frame from FIFO into 486 buffer */ 487 #define STATUS_TS 0x00700000 /* transmit process state */ 488 #define STATUS_TS_STOPPED 0x00000000 /* Stopped */ 489 #define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit 490 descriptor */ 491 #define STATUS_TS_WAIT 0x00200000 /* Running - wait for end 492 of transmission */ 493 #define STATUS_TS_READING 0x00300000 /* Running - read buffer from 494 memory and queue into 495 FIFO */ 496 #define STATUS_TS_RESERVED 0x00400000 /* RESERVED */ 497 #define STATUS_TS_SETUP 0x00500000 /* Running - Setup packet */ 498 #define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */ 499 #define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit 500 descriptor */ 501 #define STATUS_EB 0x03800000 /* error bits */ 502 #define STATUS_EB_PARITY 0x00000000 /* parity errror */ 503 #define STATUS_EB_MABT 0x00800000 /* master abort */ 504 #define STATUS_EB_TABT 0x01000000 /* target abort */ 505 #define STATUS_GPPI 0x04000000 /* GPIO interrupt (21142) */ 506 #define STATUS_PNIC_TXABORT 0x04000000 /* transmit aborted */ 507 #define STATUS_LC 0x08000000 /* 100baseTX link change 508 (21142/PMAC) */ 509 #define STATUS_PMAC_WKUPI 0x10000000 /* wake up event */ 510 #define STATUS_X3201_PMEIS 0x10000000 /* power management event 511 interrupt summary */ 512 #define STATUS_X3201_SFIS 0x80000000 /* second function (Modem) 513 interrupt status */ 514 515 516 /* CSR6 - Operation Mode */ 517 #define CSR_OPMODE TULIP_CSR6 518 #define OPMODE_HP 0x00000001 /* hash/perfect mode (ro) */ 519 #define OPMODE_SR 0x00000002 /* start receive */ 520 #define OPMODE_HO 0x00000004 /* hash only mode (ro) */ 521 #define OPMODE_PB 0x00000008 /* pass bad frames */ 522 #define OPMODE_WINB_APP 0x00000008 /* accept all physcal packet */ 523 #define OPMODE_IF 0x00000010 /* inverse filter mode (ro) */ 524 #define OPMODE_WINB_AMP 0x00000010 /* accept multicast packet */ 525 #define OPMODE_SB 0x00000020 /* start backoff counter */ 526 #define OPMODE_WINB_ABP 0x00000020 /* accept broadcast packet */ 527 #define OPMODE_PR 0x00000040 /* promiscuous mode */ 528 #define OPMODE_WINB_ARP 0x00000040 /* accept runt packet */ 529 #define OPMODE_PM 0x00000080 /* pass all multicast */ 530 #define OPMODE_WINB_AEP 0x00000080 /* accept error packet */ 531 #define OPMODE_FKD 0x00000100 /* flaky oscillator disable */ 532 #define OPMODE_FD 0x00000200 /* full-duplex mode */ 533 #define OPMODE_OM 0x00000c00 /* operating mode */ 534 #define OPMODE_OM_NORMAL 0x00000000 /* normal mode */ 535 #define OPMODE_OM_INTLOOP 0x00000400 /* internal loopback */ 536 #define OPMODE_OM_EXTLOOP 0x00000800 /* external loopback */ 537 #define OPMODE_FC 0x00001000 /* force collision */ 538 #define OPMODE_ST 0x00002000 /* start transmitter */ 539 #define OPMODE_TR 0x0000c000 /* threshold control */ 540 #define OPMODE_TR_72 0x00000000 /* 72 bytes */ 541 #define OPMODE_TR_96 0x00004000 /* 96 bytes */ 542 #define OPMODE_TR_128 0x00008000 /* 128 bytes */ 543 #define OPMODE_TR_160 0x0000c000 /* 160 bytes */ 544 #define OPMODE_WINB_TTH 0x001fc000 /* transmit threshold */ 545 #define OPMODE_WINB_TTH_SHIFT 14 546 #define OPMODE_BP 0x00010000 /* backpressure enable */ 547 #define OPMODE_CA 0x00020000 /* capture effect enable */ 548 #define OPMODE_PNIC_TBEN 0x00020000 /* Tx backoff offset enable */ 549 /* 550 * On Davicom DM9102, OPMODE_PS and OPMODE_HBD must 551 * always be set. 552 */ 553 #define OPMODE_PS 0x00040000 /* port select: 554 1 = MII/SYM, 0 = SRL 555 (21140) */ 556 #define OPMODE_HBD 0x00080000 /* heartbeat disable: 557 set in MII/SYM 100mbps, 558 set according to PHY 559 in MII 10mbps mode 560 (21140) */ 561 #define OPMODE_PNIC_IT 0x00100000 /* immediate transmit */ 562 #define OPMODE_SF 0x00200000 /* store and forward mode 563 (21140) */ 564 #define OPMODE_WINB_REIT 0x1fe00000 /* receive eartly intr thresh */ 565 #define OPMODE_WINB_REIT_SHIFT 21 566 #define OPMODE_TTM 0x00400000 /* Transmit Threshold Mode: 567 1 = 10mbps, 0 = 100mbps 568 (21140) */ 569 #define OPMODE_PCS 0x00800000 /* PCS function (21140) */ 570 #define OPMODE_SCR 0x01000000 /* scrambler mode (21140) */ 571 #define OPMODE_MBO 0x02000000 /* must be one (21140, 572 DM9102) */ 573 #define OPMODE_IDAMSB 0x04000000 /* ignore dest addr MSB 574 (21142) */ 575 #define OPMODE_PNIC_DRC 0x20000000 /* don't include CRC in Rx 576 frames (PNIC) */ 577 #define OPMODE_WINB_FES 0x20000000 /* fast ethernet select */ 578 #define OPMODE_RA 0x40000000 /* receive all (21140) */ 579 #define OPMODE_PNIC_EED 0x40000000 /* 1 == ext, 0 == int ENDEC 580 (PNIC) */ 581 #define OPMODE_WINB_TEIO 0x40000000 /* transmit early intr on */ 582 #define OPMODE_SC 0x80000000 /* special capture effect 583 enable (21041+) */ 584 #define OPMODE_WINB_REIO 0x80000000 /* receive early intr on */ 585 586 /* Shorthand for media-related OPMODE bits */ 587 #define OPMODE_MEDIA_BITS (OPMODE_FD|OPMODE_PS|OPMODE_PCS|OPMODE_SCR) 588 589 /* CSR7 - Interrupt Enable */ 590 #define CSR_INTEN TULIP_CSR7 591 /* See bits for CSR5 -- Status */ 592 593 594 /* CSR8 - Missed Frames */ 595 #define CSR_MISSED TULIP_CSR8 596 #define MISSED_MFC 0x0000ffff /* missed packet count */ 597 #define MISSED_MFO 0x00010000 /* missed packet count 598 overflowed */ 599 #define MISSED_FOC 0x0ffe0000 /* fifo overflow counter 600 (21140) */ 601 #define MISSED_OCO 0x10000000 /* overflow counter overflowed 602 (21140) */ 603 604 #define MISSED_GETMFC(x) ((x) & MISSED_MFC) 605 #define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 17) 606 607 608 /* CSR9 - MII, SROM, Boot ROM, Ethernet Address ROM register. */ 609 #define CSR_MIIROM TULIP_CSR9 610 #define MIIROM_DATA 0x000000ff /* byte of data from 611 Ethernet Address ROM 612 (21040), byte of data 613 to/from Boot ROM (21041+) */ 614 #define MIIROM_SROMCS 0x00000001 /* SROM chip select */ 615 #define MIIROM_SROMSK 0x00000002 /* SROM clock */ 616 #define MIIROM_SROMDI 0x00000004 /* SROM data in (to) */ 617 #define MIIROM_SROMDO 0x00000008 /* SROM data out (from) */ 618 #define MIIROM_REG 0x00000400 /* external register select */ 619 #define MIIROM_SR 0x00000800 /* SROM select */ 620 #define MIIROM_BR 0x00001000 /* boot ROM select */ 621 #define MIIROM_WR 0x00002000 /* write to boot ROM */ 622 #define MIIROM_RD 0x00004000 /* read from boot ROM */ 623 #define MIIROM_MOD 0x00008000 /* mode select (ro) (21041) */ 624 #define MIIROM_MDC 0x00010000 /* MII clock */ 625 #define MIIROM_MDO 0x00020000 /* MII data out */ 626 #define MIIROM_MIIDIR 0x00040000 /* MII direction mode 627 1 = PHY in read, 628 0 = PHY in write */ 629 #define MIIROM_MDI 0x00080000 /* MII data in */ 630 #define MIIROM_DN 0x80000000 /* data not valid (21040) */ 631 632 #define MIIROM_PMAC_LED0SEL 0x10000000 /* 0 == LED0 activity (def) 633 1 == LED0 speed */ 634 #define MIIROM_PMAC_LED1SEL 0x20000000 /* 0 == LED1 link (def) 635 1 == LED1 link/act */ 636 #define MIIROM_PMAC_LED2SEL 0x40000000 /* 0 == LED2 speed (def) 637 1 == LED2 collision */ 638 #define MIIROM_PMAC_LED3SEL 0x80000000 /* 0 == LED3 receive (def) 639 1 == LED3 full duplex */ 640 641 /* SROM opcodes */ 642 #define TULIP_SROM_OPC_ERASE 0x04 643 #define TULIP_SROM_OPC_WRITE 0x05 644 #define TULIP_SROM_OPC_READ 0x06 645 646 /* The Lite-On PNIC does this completely differently */ 647 #define PNIC_MIIROM_DATA 0x0000ffff /* mask of data bits ??? */ 648 #define PNIC_MIIROM_BUSY 0x80000000 /* EEPROM is busy */ 649 650 651 /* CSR10 - Boot ROM address register (21041+). */ 652 #define CSR_ROMADDR TULIP_CSR10 653 #define ROMADDR_MASK 0x000003ff /* boot rom address */ 654 655 656 /* CSR11 - General Purpose Timer (21041+). */ 657 #define CSR_GPT TULIP_CSR11 658 #define GPT_VALUE 0x0000ffff /* timer value */ 659 #define GPT_CON 0x00010000 /* continuous mode */ 660 /* 21143-PD and 21143-TD Interrupt Mitigation bits */ 661 #define GPT_NRX 0x000e0000 /* number of Rx packets */ 662 #define GPT_RXT 0x00f00000 /* Rx timer */ 663 #define GPT_NTX 0x07000000 /* number of Tx packets */ 664 #define GPT_TXT 0x78000000 /* Tx timer */ 665 #define GPT_CYCLE 0x80000000 /* cycle size */ 666 667 668 /* CSR12 - SIA Status Register. */ 669 #define CSR_SIASTAT TULIP_CSR12 670 #define SIASTAT_PAUI 0x00000001 /* pin AUI/TP indication 671 (21040) */ 672 #define SIASTAT_MRA 0x00000001 /* MII receive activity 673 (21142) */ 674 #define SIASTAT_NCR 0x00000002 /* network connection error */ 675 #define SIASTAT_LS100 0x00000002 /* 100baseT link status 676 0 == pass (21142) */ 677 #define SIASTAT_LKF 0x00000004 /* link fail status */ 678 #define SIASTAT_LS10 0x00000004 /* 10baseT link status 679 0 == pass (21142) */ 680 #define SIASTAT_APS 0x00000008 /* auto polarity status */ 681 #define SIASTAT_DSD 0x00000010 /* PLL self test done */ 682 #define SIASTAT_DSP 0x00000020 /* PLL self test pass */ 683 #define SIASTAT_DAZ 0x00000040 /* PLL all zero */ 684 #define SIASTAT_DAO 0x00000080 /* PLL all one */ 685 #define SIASTAT_SRA 0x00000100 /* selected port receive 686 activity (21041) */ 687 #define SIASTAT_ARA 0x00000100 /* AUI receive activity 688 (21142) */ 689 #define SIASTAT_NRA 0x00000200 /* non-selected port 690 receive activity (21041) */ 691 #define SIASTAT_TRA 0x00000200 /* 10base-T receive activity 692 (21142) */ 693 #define SIASTAT_NSN 0x00000400 /* non-stable NLPs detected 694 (21041) */ 695 #define SIASTAT_TRF 0x00000800 /* transmit remote fault 696 (21041) */ 697 #define SIASTAT_ANS 0x00007000 /* autonegotiation state 698 (21041) */ 699 #define SIASTAT_ANS_DIS 0x00000000 /* disabled */ 700 #define SIASTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 701 #define SIASTAT_ANS_ABD 0x00002000 /* ability detect */ 702 #define SIASTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 703 #define SIASTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 704 #define SIASTAT_ANS_FLPGOOD 0x00005000 /* FLP link good */ 705 #define SIASTAT_ANS_LINKCHECK 0x00006000 /* link check */ 706 #define SIASTAT_LPN 0x00008000 /* link partner negotiable 707 (21041) */ 708 #define SIASTAT_LPC 0xffff0000 /* link partner code word */ 709 710 #define SIASTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 711 712 713 /* CSR13 - SIA Connectivity Register. */ 714 #define CSR_SIACONN TULIP_CSR13 715 #define SIACONN_SRL 0x00000001 /* SIA reset 716 (0 == reset) */ 717 #define SIACONN_PS 0x00000002 /* pin AUI/TP selection 718 (21040) */ 719 #define SIACONN_CAC 0x00000004 /* CSR autoconfiguration */ 720 #define SIACONN_AUI 0x00000008 /* select AUI (0 = TP) */ 721 #define SIACONN_EDP 0x00000010 /* SIA PLL external input 722 enable (21040) */ 723 #define SIACONN_ENI 0x00000020 /* encoder input multiplexer 724 (21040) */ 725 #define SIACONN_SIM 0x00000040 /* serial interface input 726 multiplexer (21040) */ 727 #define SIACONN_ASE 0x00000080 /* APLL start enable 728 (21040) */ 729 #define SIACONN_SEL 0x00000f00 /* external port output 730 multiplexer select 731 (21040) */ 732 #define SIACONN_IE 0x00001000 /* input enable (21040) */ 733 #define SIACONN_OE1_3 0x00002000 /* output enable 1, 3 734 (21040) */ 735 #define SIACONN_OE2_4 0x00004000 /* output enable 2, 4 736 (21040) */ 737 #define SIACONN_OE5_6_7 0x00008000 /* output enable 5, 6, 7 738 (21040) */ 739 #define SIACONN_SDM 0x0000ef00 /* SIA diagnostic mode; 740 always set to this value 741 for normal operation 742 (21041) */ 743 744 745 /* CSR14 - SIA Transmit Receive Register. */ 746 #define CSR_SIATXRX TULIP_CSR14 747 #define SIATXRX_ECEN 0x00000001 /* encoder enable */ 748 #define SIATXRX_LBK 0x00000002 /* loopback enable */ 749 #define SIATXRX_DREN 0x00000004 /* driver enable */ 750 #define SIATXRX_LSE 0x00000008 /* link pulse send enable */ 751 #define SIATXRX_CPEN 0x00000030 /* compensation enable */ 752 #define SIATXRX_CPEN_DIS0 0x00000000 /* disabled */ 753 #define SIATXRX_CPEN_DIS1 0x00000010 /* disabled */ 754 #define SIATXRX_CPEN_HIGHPWR 0x00000020 /* high power */ 755 #define SIATXRX_CPEN_NORMAL 0x00000030 /* normal */ 756 #define SIATXRX_MBO 0x00000040 /* must be one (21041 pass 2) */ 757 #define SIATXRX_TH 0x00000040 /* 10baseT HDX enable (21142) */ 758 #define SIATXRX_ANE 0x00000080 /* autonegotiation enable 759 (21041/21142) */ 760 #define SIATXRX_RSQ 0x00000100 /* receive squelch enable */ 761 #define SIATXRX_CSQ 0x00000200 /* collision squelch enable */ 762 #define SIATXRX_CLD 0x00000400 /* collision detect enable */ 763 #define SIATXRX_SQE 0x00000800 /* signal quality generation 764 enable */ 765 #define SIATXRX_LTE 0x00001000 /* link test enable */ 766 #define SIATXRX_APE 0x00002000 /* auto-polarity enable */ 767 #define SIATXRX_SPP 0x00004000 /* set plarity plus */ 768 #define SIATXRX_TAS 0x00008000 /* 10base-T/AUI autosensing 769 enable (21041/21142) */ 770 #define SIATXRX_THX 0x00010000 /* 100baseTX-HDX (21142) */ 771 #define SIATXRX_TXF 0x00020000 /* 100baseTX-FDX (21142) */ 772 #define SIATXRX_T4 0x00040000 /* 100baseT4 (21142) */ 773 774 775 /* CSR15 - SIA General Register. */ 776 #define CSR_SIAGEN TULIP_CSR15 777 #define SIAGEN_JBD 0x00000001 /* jabber disable */ 778 #define SIAGEN_HUJ 0x00000002 /* host unjab */ 779 #define SIAGEN_JCK 0x00000004 /* jabber clock */ 780 #define SIAGEN_ABM 0x00000008 /* BNC select (21041) */ 781 #define SIAGEN_RWD 0x00000010 /* receive watchdog disable */ 782 #define SIAGEN_RWR 0x00000020 /* receive watchdog release */ 783 #define SIAGEN_LE1 0x00000040 /* LED 1 enable (21041) */ 784 #define SIAGEN_LV1 0x00000080 /* LED 1 value (21041) */ 785 #define SIAGEN_TSCK 0x00000100 /* test clock */ 786 #define SIAGEN_FUSQ 0x00000200 /* force unsquelch */ 787 #define SIAGEN_FLF 0x00000400 /* force link fail */ 788 #define SIAGEN_LSD 0x00000800 /* LED stretch disable 789 (21041) */ 790 #define SIAGEN_LEE 0x00000800 /* Link extend enable (21142) */ 791 #define SIAGEN_DPST 0x00001000 /* PLL self-test start */ 792 #define SIAGEN_FRL 0x00002000 /* force receiver low */ 793 #define SIAGEN_LE2 0x00004000 /* LED 2 enable (21041) */ 794 #define SIAGEN_RMP 0x00004000 /* received magic packet 795 (21143) */ 796 #define SIAGEN_LV2 0x00008000 /* LED 2 value (21041) */ 797 #define SIAGEN_HCKR 0x00008000 /* hacker (21143) */ 798 #define SIAGEN_MD 0x000f0000 /* general purpose mode/data */ 799 #define SIAGEN_LGS0 0x00100000 /* LED/GEP 0 select */ 800 #define SIAGEN_LGS1 0x00200000 /* LED/GEP 1 select */ 801 #define SIAGEN_LGS2 0x00400000 /* LED/GEP 2 select */ 802 #define SIAGEN_LGS3 0x00800000 /* LED/GEP 3 select */ 803 #define SIAGEN_GEI0 0x01000000 /* GEP pin 0 intr enable */ 804 #define SIAGEN_GEI1 0x02000000 /* GEP pin 1 intr enable */ 805 #define SIAGEN_RME 0x04000000 /* receive match enable */ 806 #define SIAGEN_CWE 0x08000000 /* control write enable */ 807 #define SIAGEN_GI0 0x10000000 /* GEP pin 0 interrupt */ 808 #define SIAGEN_GI1 0x20000000 /* GEP pin 1 interrupt */ 809 #define SIAGEN_RMI 0x40000000 /* receive match interrupt */ 810 811 812 /* CSR12 - General Purpose Port (21140+). */ 813 #define CSR_GPP TULIP_CSR12 814 #define GPP_MD 0x000000ff /* general purpose mode/data */ 815 #define GPP_GPC 0x00000100 /* general purpose control */ 816 #define GPP_PNIC_GPD 0x0000000f /* general purpose data */ 817 #define GPP_PNIC_GPC 0x000000f0 /* general purpose control */ 818 819 #define GPP_PNIC_IN(x) (1 << (x)) 820 #define GPP_PNIC_OUT(x, on) (((on) << (x)) | (1 << ((x) + 4))) 821 822 /* 823 * The Lite-On PNIC manual recommends the following for the General Purpose 824 * I/O pins: 825 * 826 * 0 Speed Relay 1 == 100mbps 827 * 1 100mbps loopback 1 == loopback 828 * 2 BNC DC-DC converter 1 == select BNC 829 * 3 Link 100 1 == 100baseTX link status 830 */ 831 #define GPP_PNIC_PIN_SPEED_RLY 0 832 #define GPP_PNIC_PIN_100M_LPKB 1 833 #define GPP_PNIC_PIN_BNC_XMER 2 834 #define GPP_PNIC_PIN_LNK100X 3 835 836 837 /* 838 * Digital Semiconductor 21040 registers. 839 */ 840 841 /* CSR11 - Full Duplex Register */ 842 #define CSR_21040_FDX TULIP_CSR11 843 #define FDX21040_FDXACV 0x0000ffff /* full duplex 844 autoconfiguration value */ 845 846 847 /* SIA configuration for 10base-T (from the 21040 manual) */ 848 #define SIACONN_21040_10BASET 0x0000ef01 849 #define SIATXRX_21040_10BASET 0x0000ffff 850 #define SIAGEN_21040_10BASET 0x00000000 851 852 853 /* SIA configuration for 10base-T full-duplex (from the 21040 manual) */ 854 #define SIACONN_21040_10BASET_FDX 0x0000ef01 855 #define SIATXRX_21040_10BASET_FDX 0x0000fffd 856 #define SIAGEN_21040_10BASET_FDX 0x00000000 857 858 859 /* SIA configuration for 10base-5 (from the 21040 manual) */ 860 #define SIACONN_21040_AUI 0x0000ef09 861 #define SIATXRX_21040_AUI 0x00000705 862 #define SIAGEN_21040_AUI 0x00000006 863 864 865 /* SIA configuration for External SIA (from the 21040 manual) */ 866 #define SIACONN_21040_EXTSIA 0x00003041 867 #define SIATXRX_21040_EXTSIA 0x00000000 868 #define SIAGEN_21040_EXTSIA 0x00000006 869 870 871 /* 872 * Digital Semiconductor 21041 registers. 873 */ 874 875 /* SIA configuration for 10base-T (from the 21041 manual) */ 876 #define SIACONN_21041_10BASET 0x0000ef01 877 #define SIATXRX_21041_10BASET 0x0000ff3f 878 #define SIAGEN_21041_10BASET 0x00000000 879 880 #define SIACONN_21041P2_10BASET SIACONN_21041_10BASET 881 #define SIATXRX_21041P2_10BASET 0x0000ffff 882 #define SIAGEN_21041P2_10BASET SIAGEN_21041_10BASET 883 884 885 /* SIA configuration for 10base-T full-duplex (from the 21041 manual) */ 886 #define SIACONN_21041_10BASET_FDX 0x0000ef01 887 #define SIATXRX_21041_10BASET_FDX 0x0000ff3d 888 #define SIAGEN_21041_10BASET_FDX 0x00000000 889 890 #define SIACONN_21041P2_10BASET_FDX SIACONN_21041_10BASET_FDX 891 #define SIATXRX_21041P2_10BASET_FDX 0x0000ffff 892 #define SIAGEN_21041P2_10BASET_FDX SIAGEN_21041_10BASET_FDX 893 894 895 /* SIA configuration for 10base-5 (from the 21041 manual) */ 896 #define SIACONN_21041_AUI 0x0000ef09 897 #define SIATXRX_21041_AUI 0x0000f73d 898 #define SIAGEN_21041_AUI 0x0000000e 899 900 #define SIACONN_21041P2_AUI SIACONN_21041_AUI 901 #define SIATXRX_21041P2_AUI 0x0000f7fd 902 #define SIAGEN_21041P2_AUI SIAGEN_21041_AUI 903 904 905 /* SIA configuration for 10base-2 (from the 21041 manual) */ 906 #define SIACONN_21041_BNC 0x0000ef09 907 #define SIATXRX_21041_BNC 0x0000f73d 908 #define SIAGEN_21041_BNC 0x00000006 909 910 #define SIACONN_21041P2_BNC SIACONN_21041_BNC 911 #define SIATXRX_21041P2_BNC 0x0000f7fd 912 #define SIAGEN_21041P2_BNC SIAGEN_21041_BNC 913 914 915 /* 916 * Digital Semiconductor 21142/21143 registers. 917 */ 918 919 /* SIA configuration for 10baseT (from the 21143 manual) */ 920 #define SIACONN_21142_10BASET 0x00000001 921 #define SIATXRX_21142_10BASET 0x00007f3f 922 #define SIAGEN_21142_10BASET 0x00000008 923 924 925 /* SIA configuration for 10baseT full-duplex (from the 21143 manual) */ 926 #define SIACONN_21142_10BASET_FDX 0x00000001 927 #define SIATXRX_21142_10BASET_FDX 0x00007f3d 928 #define SIAGEN_21142_10BASET_FDX 0x00000008 929 930 931 /* SIA configuration for 10base5 (from the 21143 manual) */ 932 #define SIACONN_21142_AUI 0x00000009 933 #define SIATXRX_21142_AUI 0x00004705 934 #define SIAGEN_21142_AUI 0x0000000e 935 936 937 /* SIA configuration for 10base2 (from the 21143 manual) */ 938 #define SIACONN_21142_BNC 0x00000009 939 #define SIATXRX_21142_BNC 0x00004705 940 #define SIAGEN_21142_BNC 0x00000006 941 942 943 /* 944 * Lite-On 82C168/82C169 registers. 945 */ 946 947 /* ENDEC General Register */ 948 #define CSR_PNIC_ENDEC 0x78 949 #define PNIC_ENDEC_JDIS 0x00000001 /* jabber disable */ 950 951 /* SROM Power Register */ 952 #define CSR_PNIC_SROMPWR 0x90 953 #define PNIC_SROMPWR_MRLE 0x00000001 /* Memory-Read-Line enable */ 954 #define PNIC_SROMPWR_CB 0x00000002 /* cache boundary alignment 955 burst type; 1 == burst to 956 boundary, 0 == single-cycle 957 to boundary */ 958 959 /* SROM Control Register */ 960 #define CSR_PNIC_SROMCTL 0x98 961 #define PNIC_SROMCTL_addr 0x0000003f /* mask of address bits */ 962 /* XXX THESE ARE WRONG ACCORDING TO THE MANUAL! */ 963 #define PNIC_SROMCTL_READ 0x00000600 /* read command */ 964 965 /* MII Access Register */ 966 #define CSR_PNIC_MII 0xa0 967 #define PNIC_MII_DATA 0x0000ffff /* mask of data bits */ 968 #define PNIC_MII_REG 0x007c0000 /* register mask */ 969 #define PNIC_MII_REGSHIFT 18 970 #define PNIC_MII_PHY 0x0f800000 /* phy mask */ 971 #define PNIC_MII_PHYSHIFT 23 972 #define PNIC_MII_OPCODE 0x30000000 /* opcode mask */ 973 #define PNIC_MII_RESERVED 0x00020000 /* must be one/must be zero; 974 2 bits are described here */ 975 #define PNIC_MII_MBO 0x40000000 /* must be one */ 976 #define PNIC_MII_BUSY 0x80000000 /* MII is busy */ 977 978 #define PNIC_MII_WRITE 0x10000000 /* write PHY command */ 979 #define PNIC_MII_READ 0x20000000 /* read PHY command */ 980 981 /* NWAY Register */ 982 #define CSR_PNIC_NWAY 0xb8 983 #define PNIC_NWAY_RS 0x00000001 /* reset NWay block */ 984 #define PNIC_NWAY_PD 0x00000002 /* power down NWay block */ 985 #define PNIC_NWAY_BX 0x00000004 /* bypass transciever */ 986 #define PNIC_NWAY_LC 0x00000008 /* AUI low current mode */ 987 #define PNIC_NWAY_UV 0x00000010 /* low squelch voltage */ 988 #define PNIC_NWAY_DX 0x00000020 /* disable TP pol. correction */ 989 #define PNIC_NWAY_TW 0x00000040 /* select TP (0 == AUI) */ 990 #define PNIC_NWAY_AF 0x00000080 /* AUI full/half step input 991 voltage */ 992 #define PNIC_NWAY_FD 0x00000100 /* full duplex mode */ 993 #define PNIC_NWAY_DL 0x00000200 /* disable link integrity 994 test */ 995 #define PNIC_NWAY_DM 0x00000400 /* disable AUI/TP autodetect */ 996 #define PNIC_NWAY_100 0x00000800 /* 1 == 100mbps, 0 == 10mbps */ 997 #define PNIC_NWAY_NW 0x00001000 /* enable NWay block */ 998 #define PNIC_NWAY_CAP10T 0x00002000 /* adv. 10baseT */ 999 #define PNIC_NWAY_CAP10TFDX 0x00004000 /* adv. 10baseT-FDX */ 1000 #define PNIC_NWAY_CAP100TXFDX 0x00008000 /* adv. 100baseTX-FDX */ 1001 #define PNIC_NWAY_CAP100TX 0x00010000 /* adv. 100baseTX */ 1002 #define PNIC_NWAY_CAP100T4 0x00020000 /* adv. 100base-T4 */ 1003 #define PNIC_NWAY_RN 0x02000000 /* re-negotiate enable */ 1004 #define PNIC_NWAY_RF 0x04000000 /* remote fault detected */ 1005 #define PNIC_NWAY_LPAR10T 0x08000000 /* link part. 10baseT */ 1006 #define PNIC_NWAY_LPAR10TFDX 0x10000000 /* link part. 10baseT-FDX */ 1007 #define PNIC_NWAY_LPAR100TXFDX 0x20000000 /* link part. 100baseTX-FDX */ 1008 #define PNIC_NWAY_LPAR100TX 0x40000000 /* link part. 100baseTX */ 1009 #define PNIC_NWAY_LPAR100T4 0x80000000 /* link part. 100base-T4 */ 1010 #define PNIC_NWAY_LPAR_MASK 0xf8000000 1011 1012 1013 /* 1014 * Macronix 98713, 98713A, 98715, 98715A, 98725 and 1015 * Lite-On 82C115 registers. 1016 */ 1017 1018 /* 1019 * Note, the MX98713 is very Tulip-like: 1020 * 1021 * CSR12 General Purpose Port (like 21140) 1022 * CSR13 reserved 1023 * CSR14 reserved 1024 * CSR15 Watchdog Timer (like 21140) 1025 * 1026 * The Macronix CSR12, CSR13, CSR14, and CSR15 exist only 1027 * on the MX98713A and higher. 1028 */ 1029 1030 /* CSR12 - 10base-T Status Port (similar to SIASTAT) */ 1031 /* See SIASTAT 21142/21143 bits */ 1032 #define CSR_PMAC_10TSTAT TULIP_CSR12 1033 #define PMAC_SIASTAT_MASK (SIASTAT_LS100|SIASTAT_LS10| \ 1034 SIASTAT_APS|SIASTAT_TRF|SIASTAT_ANS| \ 1035 SIASTAT_LPN|SIASTAT_LPC) 1036 1037 1038 /* CSR13 - NWAY Reset Register */ 1039 #define CSR_PMAC_NWAYRESET TULIP_CSR13 1040 /* See SIACONN 21142/21143 bits */ 1041 #define PMAC_SIACONN_MASK (SIACONN_SRL) 1042 #define PMAC_NWAYRESET_100TXRESET 0x00000002 /* 100base PMD reset */ 1043 1044 1045 /* CSR14 - 10base-T Control Port */ 1046 #define CSR_PMAC_10TCTL TULIP_CSR14 1047 /* See SIATXRX 21142/21143 bits */ 1048 #define PMAC_SIATXRX_MASK (SIATXRX_LBK|SIATXRX_DREN|SIATXRX_TH| \ 1049 SIATXRX_ANE|SIATXRX_RSQ|SIATXRX_LTE| \ 1050 SIATXRX_THX|SIATXRX_TXF|SIATXRX_T4) 1051 1052 1053 /* CSR15 - Watchdog Timer Register */ 1054 /* MX98713: see 21140 CSR15 */ 1055 /* others: see SIAGEN 21142/21143 bits */ 1056 #define PMAC_SIAGEN_MASK (SIAGEN_JBD|SIAGEN_HUJ|SIAGEN_JCK| \ 1057 SIAGEN_RWD|SIAGEN_RWR) 1058 1059 1060 /* CSR16 - Test Operation Register (a.k.a. Magic Packet Register) */ 1061 #define CSR_PMAC_TOR TULIP_CSR16 1062 #define PMAC_TOR_98713 0x0F370000 1063 #define PMAC_TOR_98715 0x0B3C0000 1064 1065 1066 /* CSR20 - NWAY Status */ 1067 #define CSR_PMAC_NWAYSTAT TULIP_CSR20 1068 /* 1069 * Note: the MX98715A manual claims that EQTEST and PCITEST 1070 * must be set to 1 by software for normal operation, but 1071 * this does not appear to be necessary. This is probably 1072 * one of the things that frobbing the Test Operation Register 1073 * does. 1074 */ 1075 #define PMAC_NWAYSTAT_EQTEST 0x00001000 /* EQ test */ 1076 #define PMAC_NWAYSTAT_PCITEST 0x00010000 /* PCI test */ 1077 #define PMAC_NWAYSTAT_10TXH 0x08000000 /* 10t accepted */ 1078 #define PMAC_NWAYSTAT_10TXF 0x10000000 /* 10t-fdx accepted */ 1079 #define PMAC_NWAYSTAT_100TXH 0x20000000 /* 100tx accepted */ 1080 #define PMAC_NWAYSTAT_100TXF 0x40000000 /* 100tx-fdx accepted */ 1081 #define PMAC_NWAYSTAT_T4 0x80000000 /* 100t4 accepted */ 1082 1083 1084 /* CSR21 - Flow Control Register */ 1085 #define CSR_PNICII_FLOWCTL TULIP_CSR21 1086 #define PNICII_FLOWCTL_WKFCATEN 0x00000010 /* enable wake-up frame 1087 catenation feature */ 1088 #define PNICII_FLOWCTL_NFCE 0x00000020 /* accept flow control result 1089 from NWay */ 1090 #define PNICII_FLOWCTL_FCTH0 0x00000040 /* rx flow control thresh 0 */ 1091 #define PNICII_FLOWCTL_FCTH1 0x00000080 /* rx flow control thresh 1 */ 1092 #define PNICII_FLOWCTL_REJECTFC 0x00000100 /* abort rx flow control */ 1093 #define PNICII_FLOWCTL_STOPTX 0x00000200 /* tx flow stopped */ 1094 #define PNICII_FLOWCTL_RUFCEN 0x00000400 /* send flow control when 1095 RU interrupt occurs */ 1096 #define PNICII_FLOWCTL_RXFCEN 0x00000800 /* rx flow control enable */ 1097 #define PNICII_FLOWCTL_TXFCEN 0x00001000 /* tx flow control enable */ 1098 #define PNICII_FLOWCTL_RESTOP 0x00002000 /* restop mode */ 1099 #define PNICII_FLOWCTL_RESTART 0x00004000 /* restart mode */ 1100 #define PNICII_FLOWCTL_TEST 0x00008000 /* test flow control timer */ 1101 #define PNICII_FLOWCTL_TMVAL 0xffff0000 /* timer value in flow 1102 control frame */ 1103 1104 #define PNICII_FLOWCTL_TH_512 (PNICII_FLOWCTL_FCTH0|PNICII_FLOWCTL_FCTH1) 1105 #define PNICII_FLOWCTL_TH_256 (PNICII_FLOWCTL_FCTH1) 1106 #define PNICII_FLOWCTL_TH_128 (PNICII_FLOWCTL_FCTH0) 1107 #define PNICII_FLOWCTL_TH_OVFLW (0) 1108 1109 1110 /* CSR22 - MAC ID Byte 3-0 Register */ 1111 #define CSR_PNICII_MACID0 TULIP_CSR22 1112 #define PNICII_MACID_1 0 /* shift */ 1113 #define PNICII_MACID_0 8 /* shift */ 1114 #define PNICII_MACID_3 16 /* shift */ 1115 #define PNICII_MACID_2 24 /* shift */ 1116 1117 1118 /* CSR23 - Magic ID Byte 5,4/MACID Byte 5,4 Register */ 1119 #define PNICII_MACID_5 0 /* shift */ 1120 #define PNICII_MACID_4 8 /* shift */ 1121 #define PNICII_MAGID_5 16 /* shift */ 1122 #define PNICII_MAGIC_4 24 /* shift */ 1123 1124 1125 /* CSR24 - Magic ID Byte 3-0 Register */ 1126 #define PNICII_MAGID_1 0 /* shift */ 1127 #define PNICII_MAGID_0 8 /* shift */ 1128 #define PNICII_MAGID_3 16 /* shift */ 1129 #define PNICII_MAGID_2 24 /* shift */ 1130 1131 1132 /* CSR25 - CSR28 - Filter Byte Mask Registers */ 1133 #define CSR_PNICII_MASK0 TULIP_CSR25 1134 1135 #define CSR_PNICII_MASK1 TULIP_CSR26 1136 1137 #define CSR_PNICII_MASK2 TULIP_CSR27 1138 1139 #define CSR_PNICII_MASK3 TULIP_CSR28 1140 1141 1142 /* CSR29 - Filter Offset Register */ 1143 #define CSR_PNICII_FILOFF TULIP_CSR29 1144 #define PNICII_FILOFF_PAT0 0x0000007f /* pattern 0 offset */ 1145 #define PNICII_FILOFF_EN0 0x00000080 /* enable pattern 0 */ 1146 #define PNICII_FILOFF_PAT1 0x00007f00 /* pattern 1 offset */ 1147 #define PNICII_FILOFF_EN1 0x00008000 /* enable pattern 1 */ 1148 #define PNICII_FILOFF_PAT2 0x007f0000 /* pattern 2 offset */ 1149 #define PNICII_FILOFF_EN2 0x00800000 /* enable pattern 2 */ 1150 #define PNICII_FILOFF_PAT3 0x7f000000 /* pattern 3 offset */ 1151 #define PNICII_FILOFF_EN3 0x80000000 /* enable pattern 3 */ 1152 1153 1154 /* CSR30 - Filter 1 and 0 CRC-16 Register */ 1155 #define CSR_PNICII_FIL01 TULIP_CSR30 1156 #define PNICII_FIL01_CRC0 0x0000ffff /* CRC-16 of pattern 0 */ 1157 #define PNICII_FIL01_CRC1 0xffff0000 /* CRC-16 of pattern 1 */ 1158 1159 1160 /* CSR31 = Filter 3 and 2 CRC-16 Register */ 1161 #define CSR_PNICII_FIL23 TULIP_CSR31 1162 #define PNICII_FIL23_CRC2 0x0000ffff /* CRC-16 of pattern 2 */ 1163 #define PNICII_FIL23_CRC3 0xffff0000 /* CRC-16 of pattern 3 */ 1164 1165 1166 /* 1167 * Winbond 89C840F registers. 1168 */ 1169 1170 /* CSR12 - Current Receive Descriptor Register */ 1171 #define CSR_WINB_CRDAR TULIP_CSR12 1172 1173 1174 /* CSR13 - Current Receive Buffer Register */ 1175 #define CSR_WINB_CCRBAR TULIP_CSR13 1176 1177 1178 /* CSR14 - Multicast Address Register 0 */ 1179 #define CSR_WINB_CMA0 TULIP_CSR14 1180 1181 1182 /* CSR15 - Multicast Address Register 1 */ 1183 #define CSR_WINB_CMA1 TULIP_CSR15 1184 1185 1186 /* CSR16 - Physical Address Register 0 */ 1187 #define CSR_WINB_CPA0 TULIP_CSR16 1188 1189 1190 /* CSR17 - Physical Address Register 1 */ 1191 #define CSR_WINB_CPA1 TULIP_CSR17 1192 1193 1194 /* CSR18 - Boot ROM Size Register */ 1195 #define CSR_WINB_CBRCR TULIP_CSR18 1196 #define WINB_CBRCR_NONE 0x00000000 /* no boot rom */ 1197 /* 0x00000001 also no boot rom */ 1198 #define WINB_CBRCR_8K 0x00000002 /* 8k */ 1199 #define WINB_CBRCR_16K 0x00000003 /* 16k */ 1200 #define WINB_CBRCR_32K 0x00000004 /* 32k */ 1201 #define WINB_CBRCR_64K 0x00000005 /* 64k */ 1202 #define WINB_CBRCR_128K 0x00000006 /* 128k */ 1203 #define WINB_CBRCR_256K 0x00000007 1204 1205 1206 /* CSR19 - Current Transmit Descriptor Register */ 1207 #define CSR_WINB_CTDAR TULIP_CSR19 1208 1209 1210 /* CSR20 - Current Transmit Buffer Register */ 1211 #define CSR_WINB_CTBAR TULIP_CSR20 1212 1213 1214 /* 1215 * ADMtek AL981 registers 1216 * 1217 * We define these as strict byte offsets into PCI space, since 1218 * not all of them have consistent access rules. 1219 */ 1220 1221 /* CSR13 - Wake-up Control/Status Register */ 1222 #define CSR_ADM_WCSR 0x68 1223 #define ADM_WCSR_LSC 0x00000001 /* link status changed */ 1224 #define ADM_WCSR_MPR 0x00000002 /* magic packet received */ 1225 #define ADM_WCSR_WFR 0x00000004 /* wake up frame received */ 1226 #define ADM_WCSR_LSCE 0x00000100 /* link status changed en. */ 1227 #define ADM_WCSR_MPRE 0x00000200 /* magic packet receive en. */ 1228 #define ADM_WCSR_WFRE 0x00000400 /* wake up frame receive en. */ 1229 #define ADM_WCSR_LINKON 0x00010000 /* link-on detect en. */ 1230 #define ADM_WCSR_LINKOFF 0x00020000 /* link-off detect en. */ 1231 #define ADM_WCSR_WP5E 0x02000000 /* wake up pat. 5 en. */ 1232 #define ADM_WCSR_WP4E 0x04000000 /* wake up pat. 4 en. */ 1233 #define ADM_WCSR_WP3E 0x08000000 /* wake up pat. 3 en. */ 1234 #define ADM_WCSR_WP2E 0x10000000 /* wake up pat. 2 en. */ 1235 #define ADM_WCSR_WP1E 0x20000000 /* wake up pat. 1 en. */ 1236 #define ADM_WCSR_CRCT 0x40000000 /* CRC-16 type: 1237 0 == 0000 initial 1238 1 == ffff initial */ 1239 1240 1241 /* CSR14 - Wake-up Pattern Data Register */ 1242 #define CSR_ADM_WPDR 0x70 1243 1244 /* 1245 * 25 consecutive longword writes are issued to WPDR to 1246 * program the wake-up pattern filter. The data written 1247 * is as follows: 1248 * 1249 * XXX 1250 */ 1251 1252 1253 /* CSR15 - see 21140 CSR15 (Watchdog Timer) */ 1254 1255 1256 /* CSR16 - Assistant CSR5 (Status Register 2) */ 1257 #define CSR_ADM_ASR 0x80 1258 /* 0 - 14: same as CSR5 */ 1259 #define ADM_ASR_AAISS 0x00080000 /* added abnormal int. sum. */ 1260 #define ADM_ASR_ANISS 0x00010000 /* added normal int. sum. */ 1261 /* XXX Receive state */ 1262 /* XXX Transmit state */ 1263 #define ADM_ASR_BET 0x03800000 /* bus error type */ 1264 #define ADM_ASR_BET_PERR 0x00000000 /* parity error */ 1265 #define ADM_ASR_BET_MABT 0x00800000 /* master abort */ 1266 #define ADM_ASR_BET_TABT 0x01000000 /* target abort */ 1267 #define ADM_ASR_PFR 0x04000000 /* PAUSE frame received */ 1268 #define ADM_ASR_TDIS 0x10000000 /* transmit def. int. status */ 1269 #define ADM_ASR_XIS 0x20000000 /* xcvr int. status */ 1270 #define ADM_ASR_REIS 0x40000000 /* receive early int. status */ 1271 #define ADM_ASR_TEIS 0x80000000 /* transmit early int. status */ 1272 1273 1274 /* CSR17 - Assistant CSR7 (Interrupt Enable Register 2) */ 1275 #define CSR_ADM_AIE 0x84 1276 /* See CSR16 for valid bits */ 1277 1278 1279 /* CSR18 - Command Register */ 1280 #define CSR_ADM_CR 0x88 1281 #define ADM_CR_ATUR 0x00000001 /* auto. tx underrun recover */ 1282 #define ADM_CR_SINT 0x00000002 /* software interrupt */ 1283 #define ADM_CR_DRT 0x0000000c /* drain recieve threshold */ 1284 #define ADM_CR_DRT_8LW 0x00000000 /* 8 longwords */ 1285 #define ADM_CR_DRT_16LW 0x00000004 /* 16 longwords */ 1286 #define ADM_CR_DRT_SF 0x00000008 /* store-and-forward */ 1287 #define ADM_CR_RTE 0x00000010 /* receive threshold enable */ 1288 #define ADM_CR_PAUSE 0x00000020 /* enable PAUSE function */ 1289 #define ADM_CR_RWP 0x00000040 /* reset wake-up pattern 1290 data register pointer */ 1291 /* 16 - 31 are automatically recalled from the EEPROM */ 1292 #define ADM_CR_WOL 0x00040000 /* wake-on-lan enable */ 1293 #define ADM_CR_PM 0x00080000 /* power management enable */ 1294 #define ADM_CR_RFS 0x00600000 /* Receive FIFO size */ 1295 #define ADM_CR_RFS_1K 0x00600000 /* 1K FIFO */ 1296 #define ADM_CR_RFS_2K 0x00400000 /* 2K FIFO */ 1297 #define ADM_CR_LEDMODE 0x00800000 /* LED mode */ 1298 #define ADM_CR_AUXCL 0x30000000 /* aux current load */ 1299 #define ADM_CR_D3CS 0x80000000 /* D3 cold wake up enable */ 1300 1301 1302 /* CSR19 - PCI bus performance counter */ 1303 #define CSR_ADM_PCIC 0x8c 1304 #define ADM_PCIC_DWCNT 0x000000ff /* double-word count of 1305 last bus-master 1306 transaction */ 1307 #define ADM_PCIC_CLKCNT 0xffff0000 /* number of PCI clocks 1308 between read request 1309 and access completed */ 1310 1311 /* CSR20 - Power Management Control/Status Register */ 1312 #define CSR_ADM_PMCSR 0x90 1313 /* 1314 * This register is also mapped into the PCI configuration 1315 * space as the PMCSR. 1316 */ 1317 1318 1319 /* CSR23 - Transmit Burst Count/Time Out Register */ 1320 #define CSR_ADM_TXBR 0x9c 1321 #define ADM_TXBR_TTO 0x00000fff /* transmit timeout */ 1322 #define ADM_TXBR_TBCNT 0x001f0000 /* transmit burst count */ 1323 1324 1325 /* CSR24 - Flash ROM Port Register */ 1326 #define CSR_ADM_FROM 0xa0 1327 #define ADM_FROM_DATA 0x000000ff /* data to/from Flash */ 1328 #define ADM_FROM_ADDR 0x01ffff00 /* Flash address */ 1329 #define ADM_FROM_ADDR_SHIFT 8 1330 #define ADM_FROM_WEN 0x04000000 /* write enable */ 1331 #define ADM_FROM_REN 0x08000000 /* read enable */ 1332 #define ADM_FROM_bra16on 0x80000000 /* pin 87 is brA16, else 1333 pin 87 is fd/col LED pin */ 1334 1335 1336 /* CSR25 - Physical Address Register 0 */ 1337 #define CSR_ADM_PAR0 0xa4 1338 1339 1340 /* CSR26 - Physical Address Register 1 */ 1341 #define CSR_ADM_PAR1 0xa8 1342 1343 1344 /* CSR27 - Multicast Address Register 0 */ 1345 #define CSR_ADM_MAR0 0xac 1346 1347 1348 /* CSR28 - Multicast Address Register 1 */ 1349 #define CSR_ADM_MAR1 0xb0 1350 1351 1352 /* Internal PHY registers are mapped here (lower 16 bits valid) */ 1353 1354 #define CSR_ADM_BMCR 0xb4 1355 #define CSR_ADM_BMSR 0xb8 1356 #define CSR_ADM_PHYIDR1 0xbc 1357 #define CSR_ADM_PHYIDR2 0xc0 1358 #define CSR_ADM_ANAR 0xc4 1359 #define CSR_ADM_ANLPAR 0xc8 1360 #define CSR_ADM_ANER 0xcc 1361 1362 /* XCVR Mode Control Register */ 1363 #define CSR_ADM_XMC 0xd0 1364 #define ADM_XMC_LD 0x00000800 /* long distance mode 1365 (low squelch enable) */ 1366 1367 1368 /* XCVR Configuration Information and Interrupt Status Register */ 1369 #define CSR_ADM_XCIIS 0xd4 1370 #define ADM_XCIIS_REF 0x0001 /* 64 error packets received */ 1371 #define ADM_XCIIS_ANPR 0x0002 /* autoneg page received */ 1372 #define ADM_XCIIS_PDF 0x0004 /* parallel detection fault */ 1373 #define ADM_XCIIS_ANAR 0x0008 /* autoneg ACK */ 1374 #define ADM_XCIIS_LS 0x0010 /* link status (1 == fail) */ 1375 #define ADM_XCIIS_RFD 0x0020 /* remote fault */ 1376 #define ADM_XCIIS_ANC 0x0040 /* autoneg completed */ 1377 #define ADM_XCIIS_PAUSE 0x0080 /* PAUSE enabled */ 1378 #define ADM_XCIIS_DUPLEX 0x0100 /* full duplex */ 1379 #define ADM_XCIIS_SPEED 0x0200 /* 100Mb/s */ 1380 1381 1382 /* XCVR Interrupt Enable Register */ 1383 #define CSR_ADM_XIE 0xd8 1384 /* Bits are as for XCIIS */ 1385 1386 1387 /* XCVR 100baseTX PHY Control/Status Register */ 1388 #define CSR_ADM_100CTR 0xdc 1389 #define ADM_100CTR_DISCRM 0x0001 /* disable scrambler */ 1390 #define ADM_100CTR_DISMLT 0x0002 /* disable MLT3 ENDEC */ 1391 #define ADM_100CTR_CMODE 0x001c /* current operating mode */ 1392 #define ADM_100CTR_CMODE_AUTO 0x0000 /* in autoneg */ 1393 #define ADM_100CTR_CMODE_10 0x0004 /* 10baseT */ 1394 #define ADM_100CTR_CMODE_100 0x0008 /* 100baseTX */ 1395 /* 0x000c reserved */ 1396 /* 0x0010 reserved */ 1397 #define ADM_100CTR_CMODE_10FD 0x0014 /* 10baseT-FDX */ 1398 #define ADM_100CTR_CMODE_100FD 0x0018 /* 100baseTX-FDX */ 1399 #define ADM_100CTR_CMODE_ISO 0x001c /* isolated */ 1400 #define ADM_100CTR_ISOTX 0x0020 /* transmit isolation */ 1401 #define ADM_100CTR_ENRZI 0x0080 /* enable NRZ <> NRZI conv. */ 1402 #define ADM_100CTR_ENDCR 0x0100 /* enable DC restoration */ 1403 #define ADM_100CTR_ENRLB 0x0200 /* enable remote loopback */ 1404 #define ADM_100CTR_RXVPP 0x0800 /* peak Rx voltage: 1405 0 == 1.0 VPP 1406 1 == 1.4 VPP */ 1407 #define ADM_100CTR_ANC 0x1000 /* autoneg completed */ 1408 #define ADM_100CTR_DISRER 0x2000 /* disable Rx error counter */ 1409 1410 /* 1411 * Xircom X3201-3 registers 1412 */ 1413 1414 /* Power Management Register */ 1415 #define CSR_X3201_PMR TULIP_CSR16 1416 #define X3201_PMR_EDINT 0x0000000f /* energy detect interval */ 1417 #define X3201_PMR_EDEN 0x00000100 /* energy detect enable */ 1418 #define X3201_PMR_MPEN 0x00000200 /* magic packet enable */ 1419 #define X3201_PMR_WOLEN 0x00000400 /* Wake On Lan enable */ 1420 #define X3201_PMR_PMGP0EN 0x00001000 /* GP0 change enable */ 1421 #define X3201_PMR_PMLCEN 0x00002000 /* link change enable */ 1422 #define X3201_PMR_WOLTMEN 0x00008000 /* WOL template mem enable */ 1423 #define X3201_PMR_EP 0x00010000 /* energy present */ 1424 #define X3201_PMR_LP 0x00200000 /* link present */ 1425 #define X3201_PMR_EDES 0x01000000 /* ED event status */ 1426 #define X3201_PMR_MPES 0x02000000 /* MP event status */ 1427 #define X3201_PMR_WOLES 0x04000000 /* WOL event status */ 1428 #define X3201_PMR_WOLPS 0x08000000 /* WOL process status */ 1429 #define X3201_PMR_GP0ES 0x10000000 /* GP0 event status */ 1430 #define X3201_PMR_LCES 0x20000000 /* LC event status */ 1431 1432 #endif /* _DEV_IC_TULIPREG_H_ */ 1433
Indexes created Tue Sep 30 11:09:46 GMT 2025