tulipreg.h revision 1.21
1 /* $NetBSD: tulipreg.h,v 1.21 2000/08/03 03:07:30 castor Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_IC_TULIPREG_H_ 41 #define _DEV_IC_TULIPREG_H_ 42 43 /* 44 * Register description for the Digital Semiconductor ``Tulip'' (21x4x) 45 * Ethernet controller family, and a variety of clone chips, including: 46 * 47 * - Macronix 98713, 98713A, 98715, 98715A, 98725 (PMAC): 48 * 49 * These chips are fairly straight-forward Tulip clones. 50 * The 98713 is a very close 21140A clone. It has GPR 51 * and MII media, and a GPIO facility, and uses the ISV 52 * SROM format (or, at least, should, because of the GPIO 53 * facility). The 98713A has MII, no GPIO facility, and 54 * an internal NWay block. The 98715, 98715A, and 98725 55 * have only GPR media and the NWay block. The 98715, 56 * 98715A, and 98725 support power management. 57 * 58 * The 98715AEC adds 802.3x flow Frame based Flow Control to the 59 * 98715A. 60 * 61 * - Lite-On 82C115 (PNIC II): 62 * 63 * A clone of the Macronix MX98725, with the following differences: 64 * 65 * - Wake-On-LAN support 66 * - 128-bit multicast hash table rather than the 67 * standard 512-bit hash table 68 * - 802.3x flow control 69 * 70 * - Lite-On 82C168, 82C169 (PNIC): 71 * 72 * Pretty close, with only a few minor differences: 73 * 74 * - EEPROM is accessed completely differently. 75 * - MII is accessed completely differently. 76 * - No SIO facility (due to the above two differences). 77 * - GPIO interface is different than the 21140's. 78 * - Boards that lack PHYs use the internal NWay block 79 * and transciever. 80 * 81 * - Winbond 89C840F 82 * 83 * Less similar, but still roughly compatible (enough so 84 * that the driver can be adapted, at least): 85 * 86 * - Registers lack the pad word between them. 87 * - Instead of a setup frame, there are two station 88 * address registers and two multicast hash table 89 * registers (64-bit multicast hash table). 90 * - Only supported media interface is MII-over-SIO. 91 * - Different OPMODE register bits for various things 92 * (mostly media related). 93 * 94 * - ADMtek AL981 95 * 96 * Another pretty-close clone: 97 * 98 * - Wake-On-LAN support 99 * - Instead of a setup frame, there are two station 100 * address registers and two multicast hash table 101 * registers (64-bit multicast hash table). 102 * - 802.3x flow control 103 * - Only supported media interface is built-in PHY 104 * which is accessed through a set of special registers. 105 * - Not all registers have the pad word between them, 106 * but luckily, there are all AL981-specific registers, 107 * so this is easy to deal with. 108 * 109 * - Xircom X3201-3 110 * 111 * CardBus 21143 clone, with a few differences: 112 * 113 * - No MicroWire SROM; Ethernet address must come 114 * from CIS. 115 * - Transmit buffers must also be 32-bit aligned. 116 * - The BUSMODE_SWR bit is not self-clearing. 117 * - Must include FS|LS in setup packet descriptor. 118 * - SIA is not 21143-like, and all media attachments 119 * are MII-on-SIO. 120 * 121 * - Davicom DM9102 and DM9102A 122 * 123 * Pretty similar to the 21140A, with a few differences: 124 * 125 * - Wake-On-LAN support 126 * - DM9102 has built-in 10/100 PHY on MII interface. 127 * - DM9102A has built-in 10/100 PHY on MII interface, 128 * as well as a HomePNA 1 PHY on an alternate MII 129 * interface (selected by clearing OPMODE_PS). 130 * - The chip has a bug in the transmit DMA logic, 131 * requiring that the packet be comprised of only 132 * one DMA segment. 133 * - The bus interface is buggy, and the BUSMODE register 134 * must be initialized to 0. 135 * - There seems to be an interrupt logic bug, requiring 136 * that interrupts be disabled on the chip during the 137 * interrupt handler. 138 * 139 * Some of the clone chips have different registers, and some have 140 * different bits in the same registers. These will be denoted by 141 * PMAC, PNICII, PNIC, DM, WINB, and ADM in the register/bit names. 142 */ 143 144 /* 145 * Tulip buffer descriptor. Must be 4-byte aligned. 146 * 147 * Note for receive descriptors, the byte count fields must 148 * be a multiple of 4. 149 */ 150 struct tulip_desc { 151 __volatile u_int32_t td_status; /* Status */ 152 __volatile u_int32_t td_ctl; /* Control and Byte Counts */ 153 __volatile u_int32_t td_bufaddr1; /* Buffer Address 1 */ 154 __volatile u_int32_t td_bufaddr2; /* Buffer Address 2 */ 155 }; 156 157 /* 158 * Descriptor Status bits common to transmit and receive. 159 */ 160 #define TDSTAT_OWN 0x80000000 /* Tulip owns descriptor */ 161 #define TDSTAT_ES 0x00008000 /* Error Summary */ 162 163 /* 164 * Descriptor Status bits for Receive Descriptor. 165 */ 166 #define TDSTAT_Rx_FF 0x40000000 /* Filtering Fail */ 167 #define TDSTAT_WINB_Rx_RCMP 0x40000000 /* Receive Complete */ 168 #define TDSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */ 169 #define TDSTAT_Rx_DE 0x00004000 /* Descriptor Error */ 170 #define TDSTAT_Rx_DT 0x00003000 /* Data Type */ 171 #define TDSTAT_Rx_RF 0x00000800 /* Runt Frame */ 172 #define TDSTAT_Rx_MF 0x00000400 /* Multicast Frame */ 173 #define TDSTAT_Rx_FS 0x00000200 /* First Descriptor */ 174 #define TDSTAT_Rx_LS 0x00000100 /* Last Descriptor */ 175 #define TDSTAT_Rx_TL 0x00000080 /* Frame Too Long */ 176 #define TDSTAT_Rx_CS 0x00000040 /* Collision Seen */ 177 #define TDSTAT_Rx_RT 0x00000020 /* Frame Type */ 178 #define TDSTAT_Rx_RW 0x00000010 /* Receive Watchdog */ 179 #define TDSTAT_Rx_RE 0x00000008 /* Report on MII Error */ 180 #define TDSTAT_Rx_DB 0x00000004 /* Dribbling Bit */ 181 #define TDSTAT_Rx_CE 0x00000002 /* CRC Error */ 182 #define TDSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */ 183 184 #define TDSTAT_Rx_LENGTH(x) (((x) & TDSTAT_Rx_FL) >> 16) 185 186 #define TDSTAT_Rx_DT_SR 0x00000000 /* Serial Received Frame */ 187 #define TDSTAT_Rx_DT_IL 0x00001000 /* Internal Loopback Frame */ 188 #define TDSTAT_Rx_DT_EL 0x00002000 /* External Loopback Frame */ 189 #define TDSTAT_Rx_DT_r 0x00003000 /* Reserved */ 190 191 /* 192 * Descriptor Status bits for Transmit Descriptor. 193 */ 194 #define TDSTAT_WINB_Tx_TE 0x00008000 /* Transmit Error */ 195 #define TDSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */ 196 #define TDSTAT_Tx_LO 0x00000800 /* Loss of Carrier */ 197 #define TDSTAT_Tx_NC 0x00000400 /* No Carrier */ 198 #define TDSTAT_Tx_LC 0x00000200 /* Late Collision */ 199 #define TDSTAT_Tx_EC 0x00000100 /* Excessive Collisions */ 200 #define TDSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */ 201 #define TDSTAT_Tx_CC 0x00000078 /* Collision Count */ 202 #define TDSTAT_Tx_LF 0x00000004 /* Link Fail */ 203 #define TDSTAT_Tx_UF 0x00000002 /* Underflow Error */ 204 #define TDSTAT_Tx_DE 0x00000001 /* Deferred */ 205 206 #define TDSTAT_Tx_COLLISIONS(x) (((x) & TDSTAT_Tx_CC) >> 3) 207 208 /* 209 * Descriptor Control bits common to transmit and receive. 210 */ 211 #define TDCTL_SIZE1 0x000007ff /* Size of buffer 1 */ 212 #define TDCTL_SIZE1_SHIFT 0 213 214 #define TDCTL_SIZE2 0x003ff800 /* Size of buffer 2 */ 215 #define TDCTL_SIZE2_SHIFT 11 216 217 #define TDCTL_ER 0x02000000 /* End of Ring */ 218 #define TDCTL_CH 0x01000000 /* Second Address Chained */ 219 220 /* 221 * Descriptor Control bits for Transmit Descriptor. 222 */ 223 #define TDCTL_Tx_IC 0x80000000 /* Interrupt on Completion */ 224 #define TDCTL_Tx_LS 0x40000000 /* Last Segment */ 225 #define TDCTL_Tx_FS 0x20000000 /* First Segment */ 226 #define TDCTL_Tx_FT1 0x10000000 /* Filtering Type 1 */ 227 #define TDCTL_Tx_SET 0x08000000 /* Setup Packet */ 228 #define TDCTL_Tx_AC 0x04000000 /* Add CRC Disable */ 229 #define TDCTL_Tx_DPD 0x00800000 /* Disabled Padding */ 230 #define TDCTL_Tx_FT0 0x00400000 /* Filtering Type 0 */ 231 232 /* 233 * The Tulip filter is programmed by "transmitting" a Setup Packet 234 * (indicated by TDCTL_Tx_SET). The filtering type is indicated 235 * as follows: 236 * 237 * FT1 FT0 Description 238 * --- --- ----------- 239 * 0 0 Perfect Filtering: The Tulip interprets the 240 * descriptor buffer as a table of 16 MAC addresses 241 * that the Tulip should receive. 242 * 243 * 0 1 Hash Filtering: The Tulip interprets the 244 * descriptor buffer as a 512-bit hash table 245 * plus one perfect address. If the incoming 246 * address is Multicast, the hash table filters 247 * the address, else the address is filtered by 248 * the perfect address. 249 * 250 * 1 0 Inverse Filtering: Like Perfect Filtering, except 251 * the table is addresses that the Tulip does NOT 252 * receive. 253 * 254 * 1 1 Hash-only Filtering: Like Hash Filtering, but 255 * physical addresses are matched by the hash table 256 * as well, and not by matching a single perfect 257 * address. 258 * 259 * A Setup Packet must always be 192 bytes long. The Tulip can store 260 * 16 MAC addresses. If not all 16 are specified in Perfect Filtering 261 * or Inverse Filtering mode, then unused entries should duplicate 262 * one of the valid entries. 263 */ 264 #define TDCTL_Tx_FT_PERFECT 0 265 #define TDCTL_Tx_FT_HASH TDCTL_Tx_FT0 266 #define TDCTL_Tx_FT_INVERSE TDCTL_Tx_FT1 267 #define TDCTL_Tx_FT_HASHONLY (TDCTL_Tx_FT1|TDCTL_Tx_FT0) 268 269 #define TULIP_SETUP_PACKET_LEN 192 270 #define TULIP_MAXADDRS 16 271 #define TULIP_MCHASHSIZE 512 272 #define TULIP_PNICII_HASHSIZE 128 273 274 /* 275 * Maximum size of a Tulip Ethernet Address ROM or SROM. 276 */ 277 #define TULIP_ROM_SIZE(bits) (2 << (bits)) 278 #define TULIP_MAX_ROM_SIZE 512 279 280 /* 281 * Format of the standard Tulip SROM information: 282 * 283 * Byte offset Size Usage 284 * 0 18 reserved 285 * 18 1 SROM Format Version 286 * 19 1 Chip Count 287 * 20 6 IEEE Network Address 288 * 26 1 Chip 0 Device Number 289 * 27 2 Chip 0 Info Leaf Offset 290 * 29 1 Chip 1 Device Number 291 * 30 2 Chip 1 Info Leaf Offset 292 * 32 1 Chip 2 Device Number 293 * 33 2 Chip 2 Info Leaf Offset 294 * ... 1 Chip n Device Number 295 * ... 2 Chip n Info Leaf Offset 296 * ... ... ... 297 * Chip Info Leaf Information 298 * ... 299 * ... 300 * ... 301 * 126 2 CRC32 checksum 302 */ 303 #define TULIP_ROM_SROM_FORMAT_VERION 18 /* B */ 304 #define TULIP_ROM_CHIP_COUNT 19 /* B */ 305 #define TULIP_ROM_IEEE_NETWORK_ADDRESS 20 306 #define TULIP_ROM_CHIPn_DEVICE_NUMBER(n) (26 + ((n) * 3))/* B */ 307 #define TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(n) (27 + ((n) * 3))/* W */ 308 #define TULIP_ROM_CRC32_CHECKSUM 126 /* W */ 309 #define TULIP_ROM_CRC32_CHECKSUM1 94 /* W */ 310 311 #define TULIP_ROM_IL_SELECT_CONN_TYPE 0 /* W */ 312 #define TULIP_ROM_IL_MEDIA_COUNT 2 /* B */ 313 #define TULIP_ROM_IL_MEDIAn_BLOCK_BASE 3 314 315 #define SELECT_CONN_TYPE_TP 0x0000 316 #define SELECT_CONN_TYPE_BNC 0x0001 317 #define SELECT_CONN_TYPE_AUI 0x0002 318 #define SELECT_CONN_TYPE_100TX 0x0003 319 #define SELECT_CONN_TYPE_100T4 0x0006 320 #define SELECT_CONN_TYPE_100FX 0x0007 321 #define SELECT_CONN_TYPE MII_10T 0x0009 322 #define SELECT_CONN_TYPE_MII_100TX 0x000d 323 #define SELECT_CONN_TYPE_MII_100T4 0x000f 324 #define SELECT_CONN_TYPE_MII_100FX 0x0010 325 #define SELECT_CONN_TYPE_TP_AUTONEG 0x0100 326 #define SELECT_CONN_TYPE_TP_FDX 0x0204 327 #define SELECT_CONN_TYPE_MII_10T_FDX 0x020a 328 #define SELECT_CONN_TYPE_100TX_FDX 0x020e 329 #define SELECT_CONN_TYPE_MII_100TX_FDX 0x0211 330 #define SELECT_CONN_TYPE_TP_NOLINKPASS 0x0400 331 #define SELECT_CONN_TYPE_ASENSE 0x0800 332 #define SELECT_CONN_TYPE_ASENSE_POWERUP 0x8800 333 #define SELECT_CONN_TYPE_ASENSE_AUTONEG 0x0900 334 335 #define TULIP_ROM_MB_MEDIA_CODE 0x3f 336 #define TULIP_ROM_MB_MEDIA_TP 0x00 337 #define TULIP_ROM_MB_MEDIA_BNC 0x01 338 #define TULIP_ROM_MB_MEDIA_AUI 0x02 339 #define TULIP_ROM_MB_MEDIA_100TX 0x03 340 #define TULIP_ROM_MB_MEDIA_TP_FDX 0x04 341 #define TULIP_ROM_MB_MEDIA_100TX_FDX 0x05 342 #define TULIP_ROM_MB_MEDIA_100T4 0x06 343 #define TULIP_ROM_MB_MEDIA_100FX 0x07 344 #define TULIP_ROM_MB_MEDIA_100FX_FDX 0x08 345 346 #define TULIP_ROM_MB_EXT 0x40 347 348 #define TULIP_ROM_MB_CSR13 1 /* W */ 349 #define TULIP_ROM_MB_CSR14 3 /* W */ 350 #define TULIP_ROM_MB_CSR15 5 /* W */ 351 352 #define TULIP_ROM_MB_SIZE(mc) (((mc) & TULIP_ROM_MB_EXT) ? 7 : 1) 353 354 #define TULIP_ROM_MB_NOINDICATOR 0x8000 355 #define TULIP_ROM_MB_DEFAULT 0x4000 356 #define TULIP_ROM_MB_POLARITY 0x0080 357 #define TULIP_ROM_MB_OPMODE(x) (((x) & 0x71) << 18) 358 #define TULIP_ROM_MB_BITPOS(x) (1 << (((x) & 0x0e) >> 1)) 359 360 #define TULIP_ROM_MB_21140_GPR 0 /* 21140[A] GPR block */ 361 #define TULIP_ROM_MB_21140_MII 1 /* 21140[A] MII block */ 362 #define TULIP_ROM_MB_21142_SIA 2 /* 2114[23] SIA block */ 363 #define TULIP_ROM_MB_21142_MII 3 /* 2114[23] MII block */ 364 #define TULIP_ROM_MB_21143_SYM 4 /* 21143 SYM block */ 365 #define TULIP_ROM_MB_21143_RESET 5 /* 21143 reset block */ 366 367 #define TULIP_ROM_GETW(data, off) ((data)[(off)] | ((data)[(off) + 1]) << 8) 368 369 /* 370 * Tulip control registers. 371 */ 372 373 #define TULIP_CSR0 0x00 374 #define TULIP_CSR1 0x08 375 #define TULIP_CSR2 0x10 376 #define TULIP_CSR3 0x18 377 #define TULIP_CSR4 0x20 378 #define TULIP_CSR5 0x28 379 #define TULIP_CSR6 0x30 380 #define TULIP_CSR7 0x38 381 #define TULIP_CSR8 0x40 382 #define TULIP_CSR9 0x48 383 #define TULIP_CSR10 0x50 384 #define TULIP_CSR11 0x58 385 #define TULIP_CSR12 0x60 386 #define TULIP_CSR13 0x68 387 #define TULIP_CSR14 0x70 388 #define TULIP_CSR15 0x78 389 #define TULIP_CSR16 0x80 390 #define TULIP_CSR17 0x88 391 #define TULIP_CSR18 0x90 392 #define TULIP_CSR19 0x98 393 #define TULIP_CSR20 0xa0 394 #define TULIP_CSR21 0xa8 395 #define TULIP_CSR22 0xb0 396 #define TULIP_CSR23 0xb8 397 #define TULIP_CSR24 0xc0 398 #define TULIP_CSR25 0xc8 399 #define TULIP_CSR26 0xd0 400 #define TULIP_CSR27 0xd8 401 #define TULIP_CSR28 0xe0 402 #define TULIP_CSR29 0xe8 403 #define TULIP_CSR30 0xf0 404 #define TULIP_CSR31 0xf8 405 406 #define TULIP_CSR_INDEX(csr) ((csr) >> 3) 407 408 /* CSR0 - Bus Mode */ 409 #define CSR_BUSMODE TULIP_CSR0 410 #define BUSMODE_SWR 0x00000001 /* software reset */ 411 #define BUSMODE_BAR 0x00000002 /* bus arbitration */ 412 #define BUSMODE_DSL 0x0000007c /* descriptor skip length */ 413 #define BUSMODE_BLE 0x00000080 /* big endian */ 414 /* programmable burst length */ 415 #define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */ 416 #define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */ 417 #define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */ 418 #define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */ 419 #define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */ 420 #define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */ 421 #define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */ 422 /* cache alignment */ 423 #define BUSMODE_CAL_NONE 0x00000000 /* no alignment */ 424 #define BUSMODE_CAL_8LW 0x00004000 /* 8 longwords */ 425 #define BUSMODE_CAL_16LW 0x00008000 /* 16 longwords */ 426 #define BUSMODE_CAL_32LW 0x0000c000 /* 32 longwords */ 427 #define BUSMODE_DAS 0x00010000 /* diagnostic address space */ 428 /* must be zero on most */ 429 /* transmit auto-poll */ 430 /* 431 * Transmit auto-polling not supported on: 432 * Winbond 89C040F 433 * Xircom X3201-3 434 * Davicom DM9102 (buggy BUSMODE register) 435 */ 436 #define BUSMODE_TAP_NONE 0x00000000 /* no auto-polling */ 437 #define BUSMODE_TAP_200us 0x00020000 /* 200 uS */ 438 #define BUSMODE_TAP_800us 0x00040000 /* 400 uS */ 439 #define BUSMODE_TAP_1_6ms 0x00060000 /* 1.6 mS */ 440 #define BUSMODE_TAP_12_8us 0x00080000 /* 12.8 uS (21041+) */ 441 #define BUSMODE_TAP_25_6us 0x000a0000 /* 25.6 uS (21041+) */ 442 #define BUSMODE_TAP_51_2us 0x000c0000 /* 51.2 uS (21041+) */ 443 #define BUSMODE_TAP_102_4us 0x000e0000 /* 102.4 uS (21041+) */ 444 #define BUSMODE_DBO 0x00100000 /* desc-only b/e (21041+) */ 445 #define BUSMODE_RME 0x00200000 /* rd/mult enab (21140+) */ 446 #define BUSMODE_WINB_WAIT 0x00200000 /* wait state insertion */ 447 #define BUSMODE_RLE 0x00800000 /* rd/line enab (21140+) */ 448 #define BUSMODE_WLE 0x01000000 /* wt/line enab (21140+) */ 449 #define BUSMODE_PNIC_MBO 0x04000000 /* magic `must be one' bit */ 450 /* on Lite-On PNIC */ 451 452 453 /* CSR1 - Transmit Poll Demand */ 454 #define CSR_TXPOLL TULIP_CSR1 455 #define TXPOLL_TPD 0x00000001 /* transmit poll demand */ 456 457 458 /* CSR2 - Receive Poll Demand */ 459 #define CSR_RXPOLL TULIP_CSR2 460 #define RXPOLL_RPD 0x00000001 /* receive poll demand */ 461 462 463 /* CSR3 - Receive List Base Address */ 464 #define CSR_RXLIST TULIP_CSR3 465 466 /* CSR4 - Transmit List Base Address */ 467 #define CSR_TXLIST TULIP_CSR4 468 469 /* CSR5 - Status */ 470 #define CSR_STATUS TULIP_CSR5 471 #define STATUS_TI 0x00000001 /* transmit interrupt */ 472 #define STATUS_TPS 0x00000002 /* transmit process stopped */ 473 #define STATUS_TU 0x00000004 /* transmit buffer unavail */ 474 #define STATUS_TJT 0x00000008 /* transmit jabber timeout */ 475 #define STATUS_WINB_REI 0x00000008 /* receive early interrupt */ 476 #define STATUS_LNPANC 0x00000010 /* link pass (21041) */ 477 #define STATUS_WINB_RERR 0x00000010 /* receive error */ 478 #define STATUS_UNF 0x00000020 /* transmit underflow */ 479 #define STATUS_RI 0x00000040 /* receive interrupt */ 480 #define STATUS_RU 0x00000080 /* receive buffer unavail */ 481 #define STATUS_RPS 0x00000100 /* receive process stopped */ 482 #define STATUS_RWT 0x00000200 /* receive watchdog timeout */ 483 #define STATUS_AT 0x00000400 /* SIA AUI/TP pin changed 484 (21040) */ 485 #define STATUS_ETI 0x00000400 /* early transmit interrupt 486 (21142/PMAC/Winbond) */ 487 #define STATUS_FD 0x00000800 /* full duplex short frame 488 received (21040) */ 489 #define STATUS_TM 0x00000800 /* timer expired (21041) */ 490 #define STATUS_LNF 0x00001000 /* link fail (21040) */ 491 #define STATUS_SE 0x00002000 /* system error */ 492 #define STATUS_ER 0x00004000 /* early receive (21041) */ 493 #define STATUS_AIS 0x00008000 /* abnormal interrupt summary */ 494 #define STATUS_NIS 0x00010000 /* normal interrupt summary */ 495 #define STATUS_RS 0x000e0000 /* receive process state */ 496 #define STATUS_RS_STOPPED 0x00000000 /* Stopped */ 497 #define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive 498 descriptor */ 499 #define STATUS_RS_CHECK 0x00040000 /* Running - check for end 500 of receive */ 501 #define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */ 502 #define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */ 503 #define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive 504 descriptor */ 505 #define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current 506 frame from FIFO */ 507 #define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current 508 frame from FIFO into 509 buffer */ 510 #define STATUS_DM_RS_STOPPED 0x00000000 /* Stopped */ 511 #define STATUS_DM_RS_FETCH 0x00020000 /* Running - fetch receive 512 descriptor */ 513 #define STATUS_DM_RS_WAIT 0x00040000 /* Running - wait for packet */ 514 #define STATUS_DM_RS_QUEUE 0x00060000 /* Running - queue current 515 frame from FIFO into 516 buffer */ 517 #define STATUS_DM_RS_CLOSE_OWN 0x00080000 /* Running - close receive 518 descriptor, clear own */ 519 #define STATUS_DM_RS_CLOSE_ST 0x000a0000 /* Running - close receive 520 descriptor, write status */ 521 #define STATUS_DM_RS_SUSPENDED 0x000c0000 /* Suspended */ 522 #define STATUS_DM_RS_FLUSH 0x000e0000 /* Running - flush current 523 frame from FIFO */ 524 #define STATUS_TS 0x00700000 /* transmit process state */ 525 #define STATUS_TS_STOPPED 0x00000000 /* Stopped */ 526 #define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit 527 descriptor */ 528 #define STATUS_TS_WAIT 0x00200000 /* Running - wait for end 529 of transmission */ 530 #define STATUS_TS_READING 0x00300000 /* Running - read buffer from 531 memory and queue into 532 FIFO */ 533 #define STATUS_TS_RESERVED 0x00400000 /* RESERVED */ 534 #define STATUS_TS_SETUP 0x00500000 /* Running - Setup packet */ 535 #define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */ 536 #define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit 537 descriptor */ 538 #define STATUS_DM_TS_STOPPED 0x00000000 /* Stopped */ 539 #define STATUS_DM_TS_FETCH 0x00100000 /* Running - fetch transmit 540 descriptor */ 541 #define STATUS_DM_TS_SETUP 0x00200000 /* Running - Setup packet */ 542 #define STATUS_DM_TS_READING 0x00300000 /* Running - read buffer from 543 memory and queue into 544 FIFO */ 545 #define STATUS_DM_TS_CLOSE_OWN 0x00400000 /* Running - close transmit 546 descriptor, clear own */ 547 #define STATUS_DM_TS_WAIT 0x00500000 /* Running - wait for end 548 of transmission */ 549 #define STATUS_DM_TS_CLOSE_ST 0x00600000 /* Running - close transmit 550 descriptor, write status */ 551 #define STATUS_DM_TS_SUSPENDED 0x00700000 /* Suspended */ 552 #define STATUS_EB 0x03800000 /* error bits */ 553 #define STATUS_EB_PARITY 0x00000000 /* parity errror */ 554 #define STATUS_EB_MABT 0x00800000 /* master abort */ 555 #define STATUS_EB_TABT 0x01000000 /* target abort */ 556 #define STATUS_GPPI 0x04000000 /* GPIO interrupt (21142) */ 557 #define STATUS_PNIC_TXABORT 0x04000000 /* transmit aborted */ 558 #define STATUS_LC 0x08000000 /* 100baseTX link change 559 (21142/PMAC) */ 560 #define STATUS_PMAC_WKUPI 0x10000000 /* wake up event */ 561 #define STATUS_X3201_PMEIS 0x10000000 /* power management event 562 interrupt summary */ 563 #define STATUS_X3201_SFIS 0x80000000 /* second function (Modem) 564 interrupt status */ 565 566 567 /* CSR6 - Operation Mode */ 568 #define CSR_OPMODE TULIP_CSR6 569 #define OPMODE_HP 0x00000001 /* hash/perfect mode (ro) */ 570 #define OPMODE_SR 0x00000002 /* start receive */ 571 #define OPMODE_HO 0x00000004 /* hash only mode (ro) */ 572 #define OPMODE_PB 0x00000008 /* pass bad frames */ 573 #define OPMODE_WINB_APP 0x00000008 /* accept all physcal packet */ 574 #define OPMODE_IF 0x00000010 /* inverse filter mode (ro) */ 575 #define OPMODE_WINB_AMP 0x00000010 /* accept multicast packet */ 576 #define OPMODE_SB 0x00000020 /* start backoff counter */ 577 #define OPMODE_WINB_ABP 0x00000020 /* accept broadcast packet */ 578 #define OPMODE_PR 0x00000040 /* promiscuous mode */ 579 #define OPMODE_WINB_ARP 0x00000040 /* accept runt packet */ 580 #define OPMODE_PM 0x00000080 /* pass all multicast */ 581 #define OPMODE_WINB_AEP 0x00000080 /* accept error packet */ 582 #define OPMODE_FKD 0x00000100 /* flaky oscillator disable */ 583 #define OPMODE_FD 0x00000200 /* full-duplex mode */ 584 #define OPMODE_OM 0x00000c00 /* operating mode */ 585 #define OPMODE_OM_NORMAL 0x00000000 /* normal mode */ 586 #define OPMODE_OM_INTLOOP 0x00000400 /* internal loopback */ 587 #define OPMODE_OM_EXTLOOP 0x00000800 /* external loopback */ 588 #define OPMODE_FC 0x00001000 /* force collision */ 589 #define OPMODE_ST 0x00002000 /* start transmitter */ 590 #define OPMODE_TR 0x0000c000 /* threshold control */ 591 #define OPMODE_TR_72 0x00000000 /* 72 bytes */ 592 #define OPMODE_TR_96 0x00004000 /* 96 bytes */ 593 #define OPMODE_TR_128 0x00008000 /* 128 bytes */ 594 #define OPMODE_TR_160 0x0000c000 /* 160 bytes */ 595 #define OPMODE_WINB_TTH 0x001fc000 /* transmit threshold */ 596 #define OPMODE_WINB_TTH_SHIFT 14 597 #define OPMODE_BP 0x00010000 /* backpressure enable */ 598 #define OPMODE_CA 0x00020000 /* capture effect enable */ 599 #define OPMODE_PNIC_TBEN 0x00020000 /* Tx backoff offset enable */ 600 /* 601 * On Davicom DM9102, OPMODE_PS and OPMODE_HBD must 602 * always be set. 603 */ 604 #define OPMODE_PS 0x00040000 /* port select: 605 1 = MII/SYM, 0 = SRL 606 (21140) */ 607 #define OPMODE_HBD 0x00080000 /* heartbeat disable: 608 set in MII/SYM 100mbps, 609 set according to PHY 610 in MII 10mbps mode 611 (21140) */ 612 #define OPMODE_PNIC_IT 0x00100000 /* immediate transmit */ 613 #define OPMODE_SF 0x00200000 /* store and forward mode 614 (21140) */ 615 #define OPMODE_WINB_REIT 0x1fe00000 /* receive eartly intr thresh */ 616 #define OPMODE_WINB_REIT_SHIFT 21 617 #define OPMODE_TTM 0x00400000 /* Transmit Threshold Mode: 618 1 = 10mbps, 0 = 100mbps 619 (21140) */ 620 #define OPMODE_PCS 0x00800000 /* PCS function (21140) */ 621 #define OPMODE_SCR 0x01000000 /* scrambler mode (21140) */ 622 #define OPMODE_MBO 0x02000000 /* must be one (21140, 623 DM9102) */ 624 #define OPMODE_IDAMSB 0x04000000 /* ignore dest addr MSB 625 (21142) */ 626 #define OPMODE_PNIC_DRC 0x20000000 /* don't include CRC in Rx 627 frames (PNIC) */ 628 #define OPMODE_WINB_FES 0x20000000 /* fast ethernet select */ 629 #define OPMODE_RA 0x40000000 /* receive all (21140) */ 630 #define OPMODE_PNIC_EED 0x40000000 /* 1 == ext, 0 == int ENDEC 631 (PNIC) */ 632 #define OPMODE_WINB_TEIO 0x40000000 /* transmit early intr on */ 633 #define OPMODE_SC 0x80000000 /* special capture effect 634 enable (21041+) */ 635 #define OPMODE_WINB_REIO 0x80000000 /* receive early intr on */ 636 637 /* Shorthand for media-related OPMODE bits */ 638 #define OPMODE_MEDIA_BITS (OPMODE_FD|OPMODE_PS|OPMODE_PCS|OPMODE_SCR) 639 640 /* CSR7 - Interrupt Enable */ 641 #define CSR_INTEN TULIP_CSR7 642 /* See bits for CSR5 -- Status */ 643 644 645 /* CSR8 - Missed Frames */ 646 #define CSR_MISSED TULIP_CSR8 647 #define MISSED_MFC 0x0000ffff /* missed packet count */ 648 #define MISSED_MFO 0x00010000 /* missed packet count 649 overflowed */ 650 #define MISSED_FOC 0x0ffe0000 /* fifo overflow counter 651 (21140) */ 652 #define MISSED_OCO 0x10000000 /* overflow counter overflowed 653 (21140) */ 654 655 #define MISSED_GETMFC(x) ((x) & MISSED_MFC) 656 #define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 17) 657 658 659 /* CSR9 - MII, SROM, Boot ROM, Ethernet Address ROM register. */ 660 #define CSR_MIIROM TULIP_CSR9 661 #define MIIROM_DATA 0x000000ff /* byte of data from 662 Ethernet Address ROM 663 (21040), byte of data 664 to/from Boot ROM (21041+) */ 665 #define MIIROM_SROMCS 0x00000001 /* SROM chip select */ 666 #define MIIROM_SROMSK 0x00000002 /* SROM clock */ 667 #define MIIROM_SROMDI 0x00000004 /* SROM data in (to) */ 668 #define MIIROM_SROMDO 0x00000008 /* SROM data out (from) */ 669 #define MIIROM_REG 0x00000400 /* external register select */ 670 #define MIIROM_SR 0x00000800 /* SROM select */ 671 #define MIIROM_BR 0x00001000 /* boot ROM select */ 672 #define MIIROM_WR 0x00002000 /* write to boot ROM */ 673 #define MIIROM_RD 0x00004000 /* read from boot ROM */ 674 #define MIIROM_MOD 0x00008000 /* mode select (ro) (21041) */ 675 #define MIIROM_MDC 0x00010000 /* MII clock */ 676 #define MIIROM_MDO 0x00020000 /* MII data out */ 677 #define MIIROM_MIIDIR 0x00040000 /* MII direction mode 678 1 = PHY in read, 679 0 = PHY in write */ 680 #define MIIROM_MDI 0x00080000 /* MII data in */ 681 #define MIIROM_DN 0x80000000 /* data not valid (21040) */ 682 683 #define MIIROM_PMAC_LED0SEL 0x10000000 /* 0 == LED0 activity (def) 684 1 == LED0 speed */ 685 #define MIIROM_PMAC_LED1SEL 0x20000000 /* 0 == LED1 link (def) 686 1 == LED1 link/act */ 687 #define MIIROM_PMAC_LED2SEL 0x40000000 /* 0 == LED2 speed (def) 688 1 == LED2 collision */ 689 #define MIIROM_PMAC_LED3SEL 0x80000000 /* 0 == LED3 receive (def) 690 1 == LED3 full duplex */ 691 692 /* SROM opcodes */ 693 #define TULIP_SROM_OPC_ERASE 0x04 694 #define TULIP_SROM_OPC_WRITE 0x05 695 #define TULIP_SROM_OPC_READ 0x06 696 697 /* The Lite-On PNIC does this completely differently */ 698 #define PNIC_MIIROM_DATA 0x0000ffff /* mask of data bits ??? */ 699 #define PNIC_MIIROM_BUSY 0x80000000 /* EEPROM is busy */ 700 701 702 /* CSR10 - Boot ROM address register (21041+). */ 703 #define CSR_ROMADDR TULIP_CSR10 704 #define ROMADDR_MASK 0x000003ff /* boot rom address */ 705 706 707 /* CSR11 - General Purpose Timer (21041+). */ 708 #define CSR_GPT TULIP_CSR11 709 #define GPT_VALUE 0x0000ffff /* timer value */ 710 #define GPT_CON 0x00010000 /* continuous mode */ 711 /* 21143-PD and 21143-TD Interrupt Mitigation bits */ 712 #define GPT_NRX 0x000e0000 /* number of Rx packets */ 713 #define GPT_RXT 0x00f00000 /* Rx timer */ 714 #define GPT_NTX 0x07000000 /* number of Tx packets */ 715 #define GPT_TXT 0x78000000 /* Tx timer */ 716 #define GPT_CYCLE 0x80000000 /* cycle size */ 717 718 719 /* CSR12 - SIA Status Register. */ 720 #define CSR_SIASTAT TULIP_CSR12 721 #define SIASTAT_PAUI 0x00000001 /* pin AUI/TP indication 722 (21040) */ 723 #define SIASTAT_MRA 0x00000001 /* MII receive activity 724 (21142) */ 725 #define SIASTAT_NCR 0x00000002 /* network connection error */ 726 #define SIASTAT_LS100 0x00000002 /* 100baseT link status 727 0 == pass (21142) */ 728 #define SIASTAT_LKF 0x00000004 /* link fail status */ 729 #define SIASTAT_LS10 0x00000004 /* 10baseT link status 730 0 == pass (21142) */ 731 #define SIASTAT_APS 0x00000008 /* auto polarity status */ 732 #define SIASTAT_DSD 0x00000010 /* PLL self test done */ 733 #define SIASTAT_DSP 0x00000020 /* PLL self test pass */ 734 #define SIASTAT_DAZ 0x00000040 /* PLL all zero */ 735 #define SIASTAT_DAO 0x00000080 /* PLL all one */ 736 #define SIASTAT_SRA 0x00000100 /* selected port receive 737 activity (21041) */ 738 #define SIASTAT_ARA 0x00000100 /* AUI receive activity 739 (21142) */ 740 #define SIASTAT_NRA 0x00000200 /* non-selected port 741 receive activity (21041) */ 742 #define SIASTAT_TRA 0x00000200 /* 10base-T receive activity 743 (21142) */ 744 #define SIASTAT_NSN 0x00000400 /* non-stable NLPs detected 745 (21041) */ 746 #define SIASTAT_TRF 0x00000800 /* transmit remote fault 747 (21041) */ 748 #define SIASTAT_ANS 0x00007000 /* autonegotiation state 749 (21041) */ 750 #define SIASTAT_ANS_DIS 0x00000000 /* disabled */ 751 #define SIASTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 752 #define SIASTAT_ANS_START 0x00001000 /* (MX98715AEC) */ 753 #define SIASTAT_ANS_ABD 0x00002000 /* ability detect */ 754 #define SIASTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 755 #define SIASTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 756 #define SIASTAT_ANS_FLPGOOD 0x00005000 /* FLP link good */ 757 #define SIASTAT_ANS_LINKCHECK 0x00006000 /* link check */ 758 #define SIASTAT_LPN 0x00008000 /* link partner negotiable 759 (21041) */ 760 #define SIASTAT_LPC 0xffff0000 /* link partner code word */ 761 762 #define SIASTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 763 764 765 /* CSR13 - SIA Connectivity Register. */ 766 #define CSR_SIACONN TULIP_CSR13 767 #define SIACONN_SRL 0x00000001 /* SIA reset 768 (0 == reset) */ 769 #define SIACONN_PS 0x00000002 /* pin AUI/TP selection 770 (21040) */ 771 #define SIACONN_CAC 0x00000004 /* CSR autoconfiguration */ 772 #define SIACONN_AUI 0x00000008 /* select AUI (0 = TP) */ 773 #define SIACONN_EDP 0x00000010 /* SIA PLL external input 774 enable (21040) */ 775 #define SIACONN_ENI 0x00000020 /* encoder input multiplexer 776 (21040) */ 777 #define SIACONN_SIM 0x00000040 /* serial interface input 778 multiplexer (21040) */ 779 #define SIACONN_ASE 0x00000080 /* APLL start enable 780 (21040) */ 781 #define SIACONN_SEL 0x00000f00 /* external port output 782 multiplexer select 783 (21040) */ 784 #define SIACONN_IE 0x00001000 /* input enable (21040) */ 785 #define SIACONN_OE1_3 0x00002000 /* output enable 1, 3 786 (21040) */ 787 #define SIACONN_OE2_4 0x00004000 /* output enable 2, 4 788 (21040) */ 789 #define SIACONN_OE5_6_7 0x00008000 /* output enable 5, 6, 7 790 (21040) */ 791 #define SIACONN_SDM 0x0000ef00 /* SIA diagnostic mode; 792 always set to this value 793 for normal operation 794 (21041) */ 795 796 797 /* CSR14 - SIA Transmit Receive Register. */ 798 #define CSR_SIATXRX TULIP_CSR14 799 #define SIATXRX_ECEN 0x00000001 /* encoder enable */ 800 #define SIATXRX_LBK 0x00000002 /* loopback enable */ 801 #define SIATXRX_DREN 0x00000004 /* driver enable */ 802 #define SIATXRX_LSE 0x00000008 /* link pulse send enable */ 803 #define SIATXRX_CPEN 0x00000030 /* compensation enable */ 804 #define SIATXRX_CPEN_DIS0 0x00000000 /* disabled */ 805 #define SIATXRX_CPEN_DIS1 0x00000010 /* disabled */ 806 #define SIATXRX_CPEN_HIGHPWR 0x00000020 /* high power */ 807 #define SIATXRX_CPEN_NORMAL 0x00000030 /* normal */ 808 #define SIATXRX_MBO 0x00000040 /* must be one (21041 pass 2) */ 809 #define SIATXRX_TH 0x00000040 /* 10baseT HDX enable (21142) */ 810 #define SIATXRX_ANE 0x00000080 /* autonegotiation enable 811 (21041/21142) */ 812 #define SIATXRX_RSQ 0x00000100 /* receive squelch enable */ 813 #define SIATXRX_CSQ 0x00000200 /* collision squelch enable */ 814 #define SIATXRX_CLD 0x00000400 /* collision detect enable */ 815 #define SIATXRX_SQE 0x00000800 /* signal quality generation 816 enable */ 817 #define SIATXRX_LTE 0x00001000 /* link test enable */ 818 #define SIATXRX_APE 0x00002000 /* auto-polarity enable */ 819 #define SIATXRX_SPP 0x00004000 /* set plarity plus */ 820 #define SIATXRX_TAS 0x00008000 /* 10base-T/AUI autosensing 821 enable (21041/21142) */ 822 #define SIATXRX_THX 0x00010000 /* 100baseTX-HDX (21142) */ 823 #define SIATXRX_TXF 0x00020000 /* 100baseTX-FDX (21142) */ 824 #define SIATXRX_T4 0x00040000 /* 100baseT4 (21142) */ 825 826 827 /* CSR15 - SIA General Register. */ 828 #define CSR_SIAGEN TULIP_CSR15 829 #define SIAGEN_JBD 0x00000001 /* jabber disable */ 830 #define SIAGEN_HUJ 0x00000002 /* host unjab */ 831 #define SIAGEN_JCK 0x00000004 /* jabber clock */ 832 #define SIAGEN_ABM 0x00000008 /* BNC select (21041) */ 833 #define SIAGEN_RWD 0x00000010 /* receive watchdog disable */ 834 #define SIAGEN_RWR 0x00000020 /* receive watchdog release */ 835 #define SIAGEN_LE1 0x00000040 /* LED 1 enable (21041) */ 836 #define SIAGEN_LV1 0x00000080 /* LED 1 value (21041) */ 837 #define SIAGEN_TSCK 0x00000100 /* test clock */ 838 #define SIAGEN_FUSQ 0x00000200 /* force unsquelch */ 839 #define SIAGEN_FLF 0x00000400 /* force link fail */ 840 #define SIAGEN_LSD 0x00000800 /* LED stretch disable 841 (21041) */ 842 #define SIAGEN_LEE 0x00000800 /* Link extend enable (21142) */ 843 #define SIAGEN_DPST 0x00001000 /* PLL self-test start */ 844 #define SIAGEN_FRL 0x00002000 /* force receiver low */ 845 #define SIAGEN_LE2 0x00004000 /* LED 2 enable (21041) */ 846 #define SIAGEN_RMP 0x00004000 /* received magic packet 847 (21143) */ 848 #define SIAGEN_LV2 0x00008000 /* LED 2 value (21041) */ 849 #define SIAGEN_HCKR 0x00008000 /* hacker (21143) */ 850 #define SIAGEN_MD 0x000f0000 /* general purpose mode/data */ 851 #define SIAGEN_LGS0 0x00100000 /* LED/GEP 0 select */ 852 #define SIAGEN_LGS1 0x00200000 /* LED/GEP 1 select */ 853 #define SIAGEN_LGS2 0x00400000 /* LED/GEP 2 select */ 854 #define SIAGEN_LGS3 0x00800000 /* LED/GEP 3 select */ 855 #define SIAGEN_GEI0 0x01000000 /* GEP pin 0 intr enable */ 856 #define SIAGEN_GEI1 0x02000000 /* GEP pin 1 intr enable */ 857 #define SIAGEN_RME 0x04000000 /* receive match enable */ 858 #define SIAGEN_CWE 0x08000000 /* control write enable */ 859 #define SIAGEN_GI0 0x10000000 /* GEP pin 0 interrupt */ 860 #define SIAGEN_GI1 0x20000000 /* GEP pin 1 interrupt */ 861 #define SIAGEN_RMI 0x40000000 /* receive match interrupt */ 862 863 864 /* CSR12 - General Purpose Port (21140+). */ 865 #define CSR_GPP TULIP_CSR12 866 #define GPP_MD 0x000000ff /* general purpose mode/data */ 867 #define GPP_GPC 0x00000100 /* general purpose control */ 868 #define GPP_PNIC_GPD 0x0000000f /* general purpose data */ 869 #define GPP_PNIC_GPC 0x000000f0 /* general purpose control */ 870 871 #define GPP_PNIC_IN(x) (1 << (x)) 872 #define GPP_PNIC_OUT(x, on) (((on) << (x)) | (1 << ((x) + 4))) 873 874 /* 875 * The Lite-On PNIC manual recommends the following for the General Purpose 876 * I/O pins: 877 * 878 * 0 Speed Relay 1 == 100mbps 879 * 1 100mbps loopback 1 == loopback 880 * 2 BNC DC-DC converter 1 == select BNC 881 * 3 Link 100 1 == 100baseTX link status 882 */ 883 #define GPP_PNIC_PIN_SPEED_RLY 0 884 #define GPP_PNIC_PIN_100M_LPKB 1 885 #define GPP_PNIC_PIN_BNC_XMER 2 886 #define GPP_PNIC_PIN_LNK100X 3 887 888 889 /* 890 * Digital Semiconductor 21040 registers. 891 */ 892 893 /* CSR11 - Full Duplex Register */ 894 #define CSR_21040_FDX TULIP_CSR11 895 #define FDX21040_FDXACV 0x0000ffff /* full duplex 896 autoconfiguration value */ 897 898 899 /* SIA configuration for 10base-T (from the 21040 manual) */ 900 #define SIACONN_21040_10BASET 0x0000ef01 901 #define SIATXRX_21040_10BASET 0x0000ffff 902 #define SIAGEN_21040_10BASET 0x00000000 903 904 905 /* SIA configuration for 10base-T full-duplex (from the 21040 manual) */ 906 #define SIACONN_21040_10BASET_FDX 0x0000ef01 907 #define SIATXRX_21040_10BASET_FDX 0x0000fffd 908 #define SIAGEN_21040_10BASET_FDX 0x00000000 909 910 911 /* SIA configuration for 10base-5 (from the 21040 manual) */ 912 #define SIACONN_21040_AUI 0x0000ef09 913 #define SIATXRX_21040_AUI 0x00000705 914 #define SIAGEN_21040_AUI 0x00000006 915 916 917 /* SIA configuration for External SIA (from the 21040 manual) */ 918 #define SIACONN_21040_EXTSIA 0x00003041 919 #define SIATXRX_21040_EXTSIA 0x00000000 920 #define SIAGEN_21040_EXTSIA 0x00000006 921 922 923 /* 924 * Digital Semiconductor 21041 registers. 925 */ 926 927 /* SIA configuration for 10base-T (from the 21041 manual) */ 928 #define SIACONN_21041_10BASET 0x0000ef01 929 #define SIATXRX_21041_10BASET 0x0000ff3f 930 #define SIAGEN_21041_10BASET 0x00000000 931 932 #define SIACONN_21041P2_10BASET SIACONN_21041_10BASET 933 #define SIATXRX_21041P2_10BASET 0x0000ffff 934 #define SIAGEN_21041P2_10BASET SIAGEN_21041_10BASET 935 936 937 /* SIA configuration for 10base-T full-duplex (from the 21041 manual) */ 938 #define SIACONN_21041_10BASET_FDX 0x0000ef01 939 #define SIATXRX_21041_10BASET_FDX 0x0000ff3d 940 #define SIAGEN_21041_10BASET_FDX 0x00000000 941 942 #define SIACONN_21041P2_10BASET_FDX SIACONN_21041_10BASET_FDX 943 #define SIATXRX_21041P2_10BASET_FDX 0x0000ffff 944 #define SIAGEN_21041P2_10BASET_FDX SIAGEN_21041_10BASET_FDX 945 946 947 /* SIA configuration for 10base-5 (from the 21041 manual) */ 948 #define SIACONN_21041_AUI 0x0000ef09 949 #define SIATXRX_21041_AUI 0x0000f73d 950 #define SIAGEN_21041_AUI 0x0000000e 951 952 #define SIACONN_21041P2_AUI SIACONN_21041_AUI 953 #define SIATXRX_21041P2_AUI 0x0000f7fd 954 #define SIAGEN_21041P2_AUI SIAGEN_21041_AUI 955 956 957 /* SIA configuration for 10base-2 (from the 21041 manual) */ 958 #define SIACONN_21041_BNC 0x0000ef09 959 #define SIATXRX_21041_BNC 0x0000f73d 960 #define SIAGEN_21041_BNC 0x00000006 961 962 #define SIACONN_21041P2_BNC SIACONN_21041_BNC 963 #define SIATXRX_21041P2_BNC 0x0000f7fd 964 #define SIAGEN_21041P2_BNC SIAGEN_21041_BNC 965 966 967 /* 968 * Digital Semiconductor 21142/21143 registers. 969 */ 970 971 /* SIA configuration for 10baseT (from the 21143 manual) */ 972 #define SIACONN_21142_10BASET 0x00000001 973 #define SIATXRX_21142_10BASET 0x00007f3f 974 #define SIAGEN_21142_10BASET 0x00000008 975 976 977 /* SIA configuration for 10baseT full-duplex (from the 21143 manual) */ 978 #define SIACONN_21142_10BASET_FDX 0x00000001 979 #define SIATXRX_21142_10BASET_FDX 0x00007f3d 980 #define SIAGEN_21142_10BASET_FDX 0x00000008 981 982 983 /* SIA configuration for 10base5 (from the 21143 manual) */ 984 #define SIACONN_21142_AUI 0x00000009 985 #define SIATXRX_21142_AUI 0x00004705 986 #define SIAGEN_21142_AUI 0x0000000e 987 988 989 /* SIA configuration for 10base2 (from the 21143 manual) */ 990 #define SIACONN_21142_BNC 0x00000009 991 #define SIATXRX_21142_BNC 0x00004705 992 #define SIAGEN_21142_BNC 0x00000006 993 994 995 /* 996 * Lite-On 82C168/82C169 registers. 997 */ 998 999 /* ENDEC General Register */ 1000 #define CSR_PNIC_ENDEC 0x78 1001 #define PNIC_ENDEC_JDIS 0x00000001 /* jabber disable */ 1002 1003 /* SROM Power Register */ 1004 #define CSR_PNIC_SROMPWR 0x90 1005 #define PNIC_SROMPWR_MRLE 0x00000001 /* Memory-Read-Line enable */ 1006 #define PNIC_SROMPWR_CB 0x00000002 /* cache boundary alignment 1007 burst type; 1 == burst to 1008 boundary, 0 == single-cycle 1009 to boundary */ 1010 1011 /* SROM Control Register */ 1012 #define CSR_PNIC_SROMCTL 0x98 1013 #define PNIC_SROMCTL_addr 0x0000003f /* mask of address bits */ 1014 /* XXX THESE ARE WRONG ACCORDING TO THE MANUAL! */ 1015 #define PNIC_SROMCTL_READ 0x00000600 /* read command */ 1016 1017 /* MII Access Register */ 1018 #define CSR_PNIC_MII 0xa0 1019 #define PNIC_MII_DATA 0x0000ffff /* mask of data bits */ 1020 #define PNIC_MII_REG 0x007c0000 /* register mask */ 1021 #define PNIC_MII_REGSHIFT 18 1022 #define PNIC_MII_PHY 0x0f800000 /* phy mask */ 1023 #define PNIC_MII_PHYSHIFT 23 1024 #define PNIC_MII_OPCODE 0x30000000 /* opcode mask */ 1025 #define PNIC_MII_RESERVED 0x00020000 /* must be one/must be zero; 1026 2 bits are described here */ 1027 #define PNIC_MII_MBO 0x40000000 /* must be one */ 1028 #define PNIC_MII_BUSY 0x80000000 /* MII is busy */ 1029 1030 #define PNIC_MII_WRITE 0x10000000 /* write PHY command */ 1031 #define PNIC_MII_READ 0x20000000 /* read PHY command */ 1032 1033 /* NWAY Register */ 1034 #define CSR_PNIC_NWAY 0xb8 1035 #define PNIC_NWAY_RS 0x00000001 /* reset NWay block */ 1036 #define PNIC_NWAY_PD 0x00000002 /* power down NWay block */ 1037 #define PNIC_NWAY_BX 0x00000004 /* bypass transciever */ 1038 #define PNIC_NWAY_LC 0x00000008 /* AUI low current mode */ 1039 #define PNIC_NWAY_UV 0x00000010 /* low squelch voltage */ 1040 #define PNIC_NWAY_DX 0x00000020 /* disable TP pol. correction */ 1041 #define PNIC_NWAY_TW 0x00000040 /* select TP (0 == AUI) */ 1042 #define PNIC_NWAY_AF 0x00000080 /* AUI full/half step input 1043 voltage */ 1044 #define PNIC_NWAY_FD 0x00000100 /* full duplex mode */ 1045 #define PNIC_NWAY_DL 0x00000200 /* disable link integrity 1046 test */ 1047 #define PNIC_NWAY_DM 0x00000400 /* disable AUI/TP autodetect */ 1048 #define PNIC_NWAY_100 0x00000800 /* 1 == 100mbps, 0 == 10mbps */ 1049 #define PNIC_NWAY_NW 0x00001000 /* enable NWay block */ 1050 #define PNIC_NWAY_CAP10T 0x00002000 /* adv. 10baseT */ 1051 #define PNIC_NWAY_CAP10TFDX 0x00004000 /* adv. 10baseT-FDX */ 1052 #define PNIC_NWAY_CAP100TXFDX 0x00008000 /* adv. 100baseTX-FDX */ 1053 #define PNIC_NWAY_CAP100TX 0x00010000 /* adv. 100baseTX */ 1054 #define PNIC_NWAY_CAP100T4 0x00020000 /* adv. 100base-T4 */ 1055 #define PNIC_NWAY_RN 0x02000000 /* re-negotiate enable */ 1056 #define PNIC_NWAY_RF 0x04000000 /* remote fault detected */ 1057 #define PNIC_NWAY_LPAR10T 0x08000000 /* link part. 10baseT */ 1058 #define PNIC_NWAY_LPAR10TFDX 0x10000000 /* link part. 10baseT-FDX */ 1059 #define PNIC_NWAY_LPAR100TXFDX 0x20000000 /* link part. 100baseTX-FDX */ 1060 #define PNIC_NWAY_LPAR100TX 0x40000000 /* link part. 100baseTX */ 1061 #define PNIC_NWAY_LPAR100T4 0x80000000 /* link part. 100base-T4 */ 1062 #define PNIC_NWAY_LPAR_MASK 0xf8000000 1063 1064 1065 /* 1066 * Macronix 98713, 98713A, 98715, 98715A, 98715AEC, 98725 and 1067 * Lite-On 82C115 registers. 1068 */ 1069 1070 /* 1071 * Note, the MX98713 is very Tulip-like: 1072 * 1073 * CSR12 General Purpose Port (like 21140) 1074 * CSR13 reserved 1075 * CSR14 reserved 1076 * CSR15 Watchdog Timer (like 21140) 1077 * 1078 * The Macronix CSR12, CSR13, CSR14, and CSR15 exist only 1079 * on the MX98713A and higher. 1080 */ 1081 1082 /* CSR12 - 10base-T Status Port (similar to SIASTAT) */ 1083 /* See SIASTAT 21142/21143 bits */ 1084 #define CSR_PMAC_10TSTAT TULIP_CSR12 1085 #define PMAC_SIASTAT_MASK (SIASTAT_LS100|SIASTAT_LS10| \ 1086 SIASTAT_APS|SIASTAT_TRF|SIASTAT_ANS| \ 1087 SIASTAT_LPN|SIASTAT_LPC) 1088 1089 1090 /* CSR13 - NWAY Reset Register */ 1091 #define CSR_PMAC_NWAYRESET TULIP_CSR13 1092 /* See SIACONN 21142/21143 bits */ 1093 #define PMAC_SIACONN_MASK (SIACONN_SRL) 1094 #define PMAC_NWAYRESET_100TXRESET 0x00000002 /* 100base PMD reset */ 1095 1096 1097 /* CSR14 - 10base-T Control Port */ 1098 #define CSR_PMAC_10TCTL TULIP_CSR14 1099 /* See SIATXRX 21142/21143 bits */ 1100 #define PMAC_SIATXRX_MASK (SIATXRX_LBK|SIATXRX_DREN|SIATXRX_TH| \ 1101 SIATXRX_ANE|SIATXRX_RSQ|SIATXRX_LTE| \ 1102 SIATXRX_THX|SIATXRX_TXF|SIATXRX_T4) 1103 1104 1105 /* CSR15 - Watchdog Timer Register */ 1106 /* MX98713: see 21140 CSR15 */ 1107 /* others: see SIAGEN 21142/21143 bits */ 1108 #define PMAC_SIAGEN_MASK (SIAGEN_JBD|SIAGEN_HUJ|SIAGEN_JCK| \ 1109 SIAGEN_RWD|SIAGEN_RWR) 1110 1111 1112 /* CSR16 - Test Operation Register (a.k.a. Magic Packet Register) */ 1113 #define CSR_PMAC_TOR TULIP_CSR16 1114 #define PMAC_TOR_98713 0x0F370000 1115 #define PMAC_TOR_98715 0x0B3C0000 1116 1117 1118 /* CSR20 - NWAY Status */ 1119 #define CSR_PMAC_NWAYSTAT TULIP_CSR20 1120 /* 1121 * Note: the MX98715A manual claims that EQTEST and PCITEST 1122 * must be set to 1 by software for normal operation, but 1123 * this does not appear to be necessary. This is probably 1124 * one of the things that frobbing the Test Operation Register 1125 * does. 1126 * 1127 * MX98715AEC uses this register for Auto Compensation. 1128 * CSR20<14> and CSR20<9> are called DS130 and DS120 1129 */ 1130 #define PMAC_NWAYSTAT_DS120 0x00000200 /* Auto-compensation circ */ 1131 #define PMAC_NWAYSTAT_DS130 0x00004000 /* Auto-compensation circ */ 1132 #define PMAC_NWAYSTAT_EQTEST 0x00001000 /* EQ test */ 1133 #define PMAC_NWAYSTAT_PCITEST 0x00010000 /* PCI test */ 1134 #define PMAC_NWAYSTAT_10TXH 0x08000000 /* 10t accepted */ 1135 #define PMAC_NWAYSTAT_10TXF 0x10000000 /* 10t-fdx accepted */ 1136 #define PMAC_NWAYSTAT_100TXH 0x20000000 /* 100tx accepted */ 1137 #define PMAC_NWAYSTAT_100TXF 0x40000000 /* 100tx-fdx accepted */ 1138 #define PMAC_NWAYSTAT_T4 0x80000000 /* 100t4 accepted */ 1139 1140 1141 /* CSR21 - Flow Control Register */ 1142 #define CSR_PNICII_FLOWCTL TULIP_CSR21 1143 #define PNICII_FLOWCTL_WKFCATEN 0x00000010 /* enable wake-up frame 1144 catenation feature */ 1145 #define PNICII_FLOWCTL_NFCE 0x00000020 /* accept flow control result 1146 from NWay */ 1147 #define PNICII_FLOWCTL_FCTH0 0x00000040 /* rx flow control thresh 0 */ 1148 #define PNICII_FLOWCTL_FCTH1 0x00000080 /* rx flow control thresh 1 */ 1149 #define PNICII_FLOWCTL_REJECTFC 0x00000100 /* abort rx flow control */ 1150 #define PNICII_FLOWCTL_STOPTX 0x00000200 /* tx flow stopped */ 1151 #define PNICII_FLOWCTL_RUFCEN 0x00000400 /* send flow control when 1152 RU interrupt occurs */ 1153 #define PNICII_FLOWCTL_RXFCEN 0x00000800 /* rx flow control enable */ 1154 #define PNICII_FLOWCTL_TXFCEN 0x00001000 /* tx flow control enable */ 1155 #define PNICII_FLOWCTL_RESTOP 0x00002000 /* restop mode */ 1156 #define PNICII_FLOWCTL_RESTART 0x00004000 /* restart mode */ 1157 #define PNICII_FLOWCTL_TEST 0x00008000 /* test flow control timer */ 1158 #define PNICII_FLOWCTL_TMVAL 0xffff0000 /* timer value in flow 1159 control frame */ 1160 1161 #define PNICII_FLOWCTL_TH_512 (PNICII_FLOWCTL_FCTH0|PNICII_FLOWCTL_FCTH1) 1162 #define PNICII_FLOWCTL_TH_256 (PNICII_FLOWCTL_FCTH1) 1163 #define PNICII_FLOWCTL_TH_128 (PNICII_FLOWCTL_FCTH0) 1164 #define PNICII_FLOWCTL_TH_OVFLW (0) 1165 1166 1167 /* CSR22 - MAC ID Byte 3-0 Register */ 1168 #define CSR_PNICII_MACID0 TULIP_CSR22 1169 #define PNICII_MACID_1 0 /* shift */ 1170 #define PNICII_MACID_0 8 /* shift */ 1171 #define PNICII_MACID_3 16 /* shift */ 1172 #define PNICII_MACID_2 24 /* shift */ 1173 1174 1175 /* CSR23 - Magic ID Byte 5,4/MACID Byte 5,4 Register */ 1176 #define PNICII_MACID_5 0 /* shift */ 1177 #define PNICII_MACID_4 8 /* shift */ 1178 #define PNICII_MAGID_5 16 /* shift */ 1179 #define PNICII_MAGIC_4 24 /* shift */ 1180 1181 1182 /* CSR24 - Magic ID Byte 3-0 Register */ 1183 #define PNICII_MAGID_1 0 /* shift */ 1184 #define PNICII_MAGID_0 8 /* shift */ 1185 #define PNICII_MAGID_3 16 /* shift */ 1186 #define PNICII_MAGID_2 24 /* shift */ 1187 1188 1189 /* CSR25 - CSR28 - Filter Byte Mask Registers */ 1190 #define CSR_PNICII_MASK0 TULIP_CSR25 1191 1192 #define CSR_PNICII_MASK1 TULIP_CSR26 1193 1194 #define CSR_PNICII_MASK2 TULIP_CSR27 1195 1196 #define CSR_PNICII_MASK3 TULIP_CSR28 1197 1198 1199 /* CSR29 - Filter Offset Register */ 1200 #define CSR_PNICII_FILOFF TULIP_CSR29 1201 #define PNICII_FILOFF_PAT0 0x0000007f /* pattern 0 offset */ 1202 #define PNICII_FILOFF_EN0 0x00000080 /* enable pattern 0 */ 1203 #define PNICII_FILOFF_PAT1 0x00007f00 /* pattern 1 offset */ 1204 #define PNICII_FILOFF_EN1 0x00008000 /* enable pattern 1 */ 1205 #define PNICII_FILOFF_PAT2 0x007f0000 /* pattern 2 offset */ 1206 #define PNICII_FILOFF_EN2 0x00800000 /* enable pattern 2 */ 1207 #define PNICII_FILOFF_PAT3 0x7f000000 /* pattern 3 offset */ 1208 #define PNICII_FILOFF_EN3 0x80000000 /* enable pattern 3 */ 1209 1210 1211 /* CSR30 - Filter 1 and 0 CRC-16 Register */ 1212 #define CSR_PNICII_FIL01 TULIP_CSR30 1213 #define PNICII_FIL01_CRC0 0x0000ffff /* CRC-16 of pattern 0 */ 1214 #define PNICII_FIL01_CRC1 0xffff0000 /* CRC-16 of pattern 1 */ 1215 1216 1217 /* CSR31 = Filter 3 and 2 CRC-16 Register */ 1218 #define CSR_PNICII_FIL23 TULIP_CSR31 1219 #define PNICII_FIL23_CRC2 0x0000ffff /* CRC-16 of pattern 2 */ 1220 #define PNICII_FIL23_CRC3 0xffff0000 /* CRC-16 of pattern 3 */ 1221 1222 1223 /* 1224 * Winbond 89C840F registers. 1225 */ 1226 1227 /* CSR12 - Current Receive Descriptor Register */ 1228 #define CSR_WINB_CRDAR TULIP_CSR12 1229 1230 1231 /* CSR13 - Current Receive Buffer Register */ 1232 #define CSR_WINB_CCRBAR TULIP_CSR13 1233 1234 1235 /* CSR14 - Multicast Address Register 0 */ 1236 #define CSR_WINB_CMA0 TULIP_CSR14 1237 1238 1239 /* CSR15 - Multicast Address Register 1 */ 1240 #define CSR_WINB_CMA1 TULIP_CSR15 1241 1242 1243 /* CSR16 - Physical Address Register 0 */ 1244 #define CSR_WINB_CPA0 TULIP_CSR16 1245 1246 1247 /* CSR17 - Physical Address Register 1 */ 1248 #define CSR_WINB_CPA1 TULIP_CSR17 1249 1250 1251 /* CSR18 - Boot ROM Size Register */ 1252 #define CSR_WINB_CBRCR TULIP_CSR18 1253 #define WINB_CBRCR_NONE 0x00000000 /* no boot rom */ 1254 /* 0x00000001 also no boot rom */ 1255 #define WINB_CBRCR_8K 0x00000002 /* 8k */ 1256 #define WINB_CBRCR_16K 0x00000003 /* 16k */ 1257 #define WINB_CBRCR_32K 0x00000004 /* 32k */ 1258 #define WINB_CBRCR_64K 0x00000005 /* 64k */ 1259 #define WINB_CBRCR_128K 0x00000006 /* 128k */ 1260 #define WINB_CBRCR_256K 0x00000007 1261 1262 1263 /* CSR19 - Current Transmit Descriptor Register */ 1264 #define CSR_WINB_CTDAR TULIP_CSR19 1265 1266 1267 /* CSR20 - Current Transmit Buffer Register */ 1268 #define CSR_WINB_CTBAR TULIP_CSR20 1269 1270 1271 /* 1272 * ADMtek AL981 registers 1273 * 1274 * We define these as strict byte offsets into PCI space, since 1275 * not all of them have consistent access rules. 1276 */ 1277 1278 /* CSR13 - Wake-up Control/Status Register */ 1279 #define CSR_ADM_WCSR 0x68 1280 #define ADM_WCSR_LSC 0x00000001 /* link status changed */ 1281 #define ADM_WCSR_MPR 0x00000002 /* magic packet received */ 1282 #define ADM_WCSR_WFR 0x00000004 /* wake up frame received */ 1283 #define ADM_WCSR_LSCE 0x00000100 /* link status changed en. */ 1284 #define ADM_WCSR_MPRE 0x00000200 /* magic packet receive en. */ 1285 #define ADM_WCSR_WFRE 0x00000400 /* wake up frame receive en. */ 1286 #define ADM_WCSR_LINKON 0x00010000 /* link-on detect en. */ 1287 #define ADM_WCSR_LINKOFF 0x00020000 /* link-off detect en. */ 1288 #define ADM_WCSR_WP5E 0x02000000 /* wake up pat. 5 en. */ 1289 #define ADM_WCSR_WP4E 0x04000000 /* wake up pat. 4 en. */ 1290 #define ADM_WCSR_WP3E 0x08000000 /* wake up pat. 3 en. */ 1291 #define ADM_WCSR_WP2E 0x10000000 /* wake up pat. 2 en. */ 1292 #define ADM_WCSR_WP1E 0x20000000 /* wake up pat. 1 en. */ 1293 #define ADM_WCSR_CRCT 0x40000000 /* CRC-16 type: 1294 0 == 0000 initial 1295 1 == ffff initial */ 1296 1297 1298 /* CSR14 - Wake-up Pattern Data Register */ 1299 #define CSR_ADM_WPDR 0x70 1300 1301 /* 1302 * 25 consecutive longword writes are issued to WPDR to 1303 * program the wake-up pattern filter. The data written 1304 * is as follows: 1305 * 1306 * XXX 1307 */ 1308 1309 1310 /* CSR15 - see 21140 CSR15 (Watchdog Timer) */ 1311 1312 1313 /* CSR16 - Assistant CSR5 (Status Register 2) */ 1314 #define CSR_ADM_ASR 0x80 1315 /* 0 - 14: same as CSR5 */ 1316 #define ADM_ASR_AAISS 0x00080000 /* added abnormal int. sum. */ 1317 #define ADM_ASR_ANISS 0x00010000 /* added normal int. sum. */ 1318 /* XXX Receive state */ 1319 /* XXX Transmit state */ 1320 #define ADM_ASR_BET 0x03800000 /* bus error type */ 1321 #define ADM_ASR_BET_PERR 0x00000000 /* parity error */ 1322 #define ADM_ASR_BET_MABT 0x00800000 /* master abort */ 1323 #define ADM_ASR_BET_TABT 0x01000000 /* target abort */ 1324 #define ADM_ASR_PFR 0x04000000 /* PAUSE frame received */ 1325 #define ADM_ASR_TDIS 0x10000000 /* transmit def. int. status */ 1326 #define ADM_ASR_XIS 0x20000000 /* xcvr int. status */ 1327 #define ADM_ASR_REIS 0x40000000 /* receive early int. status */ 1328 #define ADM_ASR_TEIS 0x80000000 /* transmit early int. status */ 1329 1330 1331 /* CSR17 - Assistant CSR7 (Interrupt Enable Register 2) */ 1332 #define CSR_ADM_AIE 0x84 1333 /* See CSR16 for valid bits */ 1334 1335 1336 /* CSR18 - Command Register */ 1337 #define CSR_ADM_CR 0x88 1338 #define ADM_CR_ATUR 0x00000001 /* auto. tx underrun recover */ 1339 #define ADM_CR_SINT 0x00000002 /* software interrupt */ 1340 #define ADM_CR_DRT 0x0000000c /* drain recieve threshold */ 1341 #define ADM_CR_DRT_8LW 0x00000000 /* 8 longwords */ 1342 #define ADM_CR_DRT_16LW 0x00000004 /* 16 longwords */ 1343 #define ADM_CR_DRT_SF 0x00000008 /* store-and-forward */ 1344 #define ADM_CR_RTE 0x00000010 /* receive threshold enable */ 1345 #define ADM_CR_PAUSE 0x00000020 /* enable PAUSE function */ 1346 #define ADM_CR_RWP 0x00000040 /* reset wake-up pattern 1347 data register pointer */ 1348 /* 16 - 31 are automatically recalled from the EEPROM */ 1349 #define ADM_CR_WOL 0x00040000 /* wake-on-lan enable */ 1350 #define ADM_CR_PM 0x00080000 /* power management enable */ 1351 #define ADM_CR_RFS 0x00600000 /* Receive FIFO size */ 1352 #define ADM_CR_RFS_1K 0x00600000 /* 1K FIFO */ 1353 #define ADM_CR_RFS_2K 0x00400000 /* 2K FIFO */ 1354 #define ADM_CR_LEDMODE 0x00800000 /* LED mode */ 1355 #define ADM_CR_AUXCL 0x30000000 /* aux current load */ 1356 #define ADM_CR_D3CS 0x80000000 /* D3 cold wake up enable */ 1357 1358 1359 /* CSR19 - PCI bus performance counter */ 1360 #define CSR_ADM_PCIC 0x8c 1361 #define ADM_PCIC_DWCNT 0x000000ff /* double-word count of 1362 last bus-master 1363 transaction */ 1364 #define ADM_PCIC_CLKCNT 0xffff0000 /* number of PCI clocks 1365 between read request 1366 and access completed */ 1367 1368 /* CSR20 - Power Management Control/Status Register */ 1369 #define CSR_ADM_PMCSR 0x90 1370 /* 1371 * This register is also mapped into the PCI configuration 1372 * space as the PMCSR. 1373 */ 1374 1375 1376 /* CSR23 - Transmit Burst Count/Time Out Register */ 1377 #define CSR_ADM_TXBR 0x9c 1378 #define ADM_TXBR_TTO 0x00000fff /* transmit timeout */ 1379 #define ADM_TXBR_TBCNT 0x001f0000 /* transmit burst count */ 1380 1381 1382 /* CSR24 - Flash ROM Port Register */ 1383 #define CSR_ADM_FROM 0xa0 1384 #define ADM_FROM_DATA 0x000000ff /* data to/from Flash */ 1385 #define ADM_FROM_ADDR 0x01ffff00 /* Flash address */ 1386 #define ADM_FROM_ADDR_SHIFT 8 1387 #define ADM_FROM_WEN 0x04000000 /* write enable */ 1388 #define ADM_FROM_REN 0x08000000 /* read enable */ 1389 #define ADM_FROM_bra16on 0x80000000 /* pin 87 is brA16, else 1390 pin 87 is fd/col LED pin */ 1391 1392 1393 /* CSR25 - Physical Address Register 0 */ 1394 #define CSR_ADM_PAR0 0xa4 1395 1396 1397 /* CSR26 - Physical Address Register 1 */ 1398 #define CSR_ADM_PAR1 0xa8 1399 1400 1401 /* CSR27 - Multicast Address Register 0 */ 1402 #define CSR_ADM_MAR0 0xac 1403 1404 1405 /* CSR28 - Multicast Address Register 1 */ 1406 #define CSR_ADM_MAR1 0xb0 1407 1408 1409 /* Internal PHY registers are mapped here (lower 16 bits valid) */ 1410 1411 #define CSR_ADM_BMCR 0xb4 1412 #define CSR_ADM_BMSR 0xb8 1413 #define CSR_ADM_PHYIDR1 0xbc 1414 #define CSR_ADM_PHYIDR2 0xc0 1415 #define CSR_ADM_ANAR 0xc4 1416 #define CSR_ADM_ANLPAR 0xc8 1417 #define CSR_ADM_ANER 0xcc 1418 1419 /* XCVR Mode Control Register */ 1420 #define CSR_ADM_XMC 0xd0 1421 #define ADM_XMC_LD 0x00000800 /* long distance mode 1422 (low squelch enable) */ 1423 1424 1425 /* XCVR Configuration Information and Interrupt Status Register */ 1426 #define CSR_ADM_XCIIS 0xd4 1427 #define ADM_XCIIS_REF 0x0001 /* 64 error packets received */ 1428 #define ADM_XCIIS_ANPR 0x0002 /* autoneg page received */ 1429 #define ADM_XCIIS_PDF 0x0004 /* parallel detection fault */ 1430 #define ADM_XCIIS_ANAR 0x0008 /* autoneg ACK */ 1431 #define ADM_XCIIS_LS 0x0010 /* link status (1 == fail) */ 1432 #define ADM_XCIIS_RFD 0x0020 /* remote fault */ 1433 #define ADM_XCIIS_ANC 0x0040 /* autoneg completed */ 1434 #define ADM_XCIIS_PAUSE 0x0080 /* PAUSE enabled */ 1435 #define ADM_XCIIS_DUPLEX 0x0100 /* full duplex */ 1436 #define ADM_XCIIS_SPEED 0x0200 /* 100Mb/s */ 1437 1438 1439 /* XCVR Interrupt Enable Register */ 1440 #define CSR_ADM_XIE 0xd8 1441 /* Bits are as for XCIIS */ 1442 1443 1444 /* XCVR 100baseTX PHY Control/Status Register */ 1445 #define CSR_ADM_100CTR 0xdc 1446 #define ADM_100CTR_DISCRM 0x0001 /* disable scrambler */ 1447 #define ADM_100CTR_DISMLT 0x0002 /* disable MLT3 ENDEC */ 1448 #define ADM_100CTR_CMODE 0x001c /* current operating mode */ 1449 #define ADM_100CTR_CMODE_AUTO 0x0000 /* in autoneg */ 1450 #define ADM_100CTR_CMODE_10 0x0004 /* 10baseT */ 1451 #define ADM_100CTR_CMODE_100 0x0008 /* 100baseTX */ 1452 /* 0x000c reserved */ 1453 /* 0x0010 reserved */ 1454 #define ADM_100CTR_CMODE_10FD 0x0014 /* 10baseT-FDX */ 1455 #define ADM_100CTR_CMODE_100FD 0x0018 /* 100baseTX-FDX */ 1456 #define ADM_100CTR_CMODE_ISO 0x001c /* isolated */ 1457 #define ADM_100CTR_ISOTX 0x0020 /* transmit isolation */ 1458 #define ADM_100CTR_ENRZI 0x0080 /* enable NRZ <> NRZI conv. */ 1459 #define ADM_100CTR_ENDCR 0x0100 /* enable DC restoration */ 1460 #define ADM_100CTR_ENRLB 0x0200 /* enable remote loopback */ 1461 #define ADM_100CTR_RXVPP 0x0800 /* peak Rx voltage: 1462 0 == 1.0 VPP 1463 1 == 1.4 VPP */ 1464 #define ADM_100CTR_ANC 0x1000 /* autoneg completed */ 1465 #define ADM_100CTR_DISRER 0x2000 /* disable Rx error counter */ 1466 1467 /* 1468 * Xircom X3201-3 registers 1469 */ 1470 1471 /* Power Management Register */ 1472 #define CSR_X3201_PMR TULIP_CSR16 1473 #define X3201_PMR_EDINT 0x0000000f /* energy detect interval */ 1474 #define X3201_PMR_EDEN 0x00000100 /* energy detect enable */ 1475 #define X3201_PMR_MPEN 0x00000200 /* magic packet enable */ 1476 #define X3201_PMR_WOLEN 0x00000400 /* Wake On Lan enable */ 1477 #define X3201_PMR_PMGP0EN 0x00001000 /* GP0 change enable */ 1478 #define X3201_PMR_PMLCEN 0x00002000 /* link change enable */ 1479 #define X3201_PMR_WOLTMEN 0x00008000 /* WOL template mem enable */ 1480 #define X3201_PMR_EP 0x00010000 /* energy present */ 1481 #define X3201_PMR_LP 0x00200000 /* link present */ 1482 #define X3201_PMR_EDES 0x01000000 /* ED event status */ 1483 #define X3201_PMR_MPES 0x02000000 /* MP event status */ 1484 #define X3201_PMR_WOLES 0x04000000 /* WOL event status */ 1485 #define X3201_PMR_WOLPS 0x08000000 /* WOL process status */ 1486 #define X3201_PMR_GP0ES 0x10000000 /* GP0 event status */ 1487 #define X3201_PMR_LCES 0x20000000 /* LC event status */ 1488 1489 /* 1490 * Davicom DM9102 registers. 1491 */ 1492 1493 /* PHY Status Register */ 1494 #define CSR_DM_PHYSTAT TULIP_CSR12 1495 #define DM_PHYSTAT_10 0x00000001 /* 10Mb/s */ 1496 #define DM_PHYSTAT_100 0x00000002 /* 100Mb/s */ 1497 #define DM_PHYSTAT_FDX 0x00000004 /* full-duplex */ 1498 #define DM_PHYSTAT_LINK 0x00000008 /* link up */ 1499 #define DM_PHYSTAT_RXLOCK 0x00000010 /* RX-lock */ 1500 #define DM_PHYSTAT_SIGNAL 0x00000020 /* signal detection */ 1501 #define DM_PHYSTAT_UTPSIG 0x00000040 /* UTP SIG */ 1502 #define DM_PHYSTAT_GPED 0x00000080 /* general PHY reset control */ 1503 #define DM_PHYSTAT_GEPC 0x00000100 /* GPED bits control */ 1504 1505 1506 /* Sample Frame Access Register */ 1507 #define CSR_DM_SFAR TULIP_CSR13 1508 1509 1510 /* Sample Frame Data Register */ 1511 #define CSR_DM_SFDR TULIP_CSR14 1512 /* See 21143 SIAGEN register */ 1513 1514 #endif /* _DEV_IC_TULIPREG_H_ */ 1515
Indexes created Mon Sep 29 21:09:56 GMT 2025