tulipreg.h revision 1.3
1 /* $NetBSD: tulipreg.h,v 1.3 1999/09/09 21:48:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_IC_TULIPREG_H_ 41 #define _DEV_IC_TULIPREG_H_ 42 43 /* 44 * Register description for the Digital Semiconductor ``Tulip'' (21x4x) 45 * Ethernet controller family, and a variety of clone chips, including: 46 * 47 * - Macronix 98713, 98713A, 98715, 98715A, 98725 (PMAC): 48 * 49 * These chips are fairly straight-forward Tulip clones. 50 * The 98713 and 98713A have an MII. All have an internal 51 * transciever capable of NWAY. The 98713A, 98715A, and 52 * 98725 support power management. 53 * 54 * - Lite-On 82C168, 82C169 (PNIC): 55 * 56 * These are Tulip clones with a few small differences; the 57 * EEPROM is accessed totally differently, as is the MII. 58 * The PNIC also has a built-in NWAY transciever. 59 * 60 * - Winbond 89C840F 61 * 62 * Fairly straight-forward Tulip clone, with the exception 63 * that registers don't have a pad longword between them, 64 * and the receive filter is set up differently: instead of 65 * a setup packet, we have 2 32-bit multicast hash table 66 * registers, and 2 station address registers. 67 * 68 * Some of the clone chips have different registers, and some have 69 * different bits in the same registers. These will be denoted by 70 * PMAC, PNIC, and WINB in the register/bit names. 71 */ 72 73 /* 74 * Tulip buffer descriptor. Must be 4-byte aligned. 75 * 76 * Note for receive descriptors, the byte count fields must 77 * be a multiple of 4. 78 */ 79 struct tulip_desc { 80 __volatile u_int32_t td_status; /* Status */ 81 __volatile u_int32_t td_ctl; /* Control and Byte Counts */ 82 __volatile u_int32_t td_bufaddr1; /* Buffer Address 1 */ 83 __volatile u_int32_t td_bufaddr2; /* Buffer Address 2 */ 84 }; 85 86 /* 87 * Descriptor Status bits common to transmit and receive. 88 */ 89 #define TDSTAT_OWN 0x80000000 /* Tulip owns descriptor */ 90 #define TDSTAT_ES 0x00008000 /* Error Summary */ 91 92 /* 93 * Descriptor Status bits for Receive Descriptor. 94 */ 95 #define TDSTAT_Rx_FF 0x40000000 /* Filtering Fail */ 96 #define TDSTAT_WINB_Rx_RCMP 0x40000000 /* Receive Complete */ 97 #define TDSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */ 98 #define TDSTAT_Rx_DE 0x00004000 /* Descriptor Error */ 99 #define TDSTAT_Rx_DT 0x00003000 /* Data Type */ 100 #define TDSTAT_Rx_RF 0x00000800 /* Runt Frame */ 101 #define TDSTAT_Rx_MF 0x00000400 /* Multicast Frame */ 102 #define TDSTAT_Rx_FS 0x00000200 /* First Descriptor */ 103 #define TDSTAT_Rx_LS 0x00000100 /* Last Descriptor */ 104 #define TDSTAT_Rx_TL 0x00000080 /* Frame Too Long */ 105 #define TDSTAT_Rx_CS 0x00000040 /* Collision Seen */ 106 #define TDSTAT_Rx_RT 0x00000020 /* Frame Type */ 107 #define TDSTAT_Rx_RW 0x00000010 /* Receive Watchdog */ 108 #define TDSTAT_Rx_RE 0x00000008 /* Report on MII Error */ 109 #define TDSTAT_Rx_DB 0x00000004 /* Dribbling Bit */ 110 #define TDSTAT_Rx_CE 0x00000002 /* CRC Error */ 111 #define TDSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */ 112 113 #define TDSTAT_Rx_LENGTH(x) (((x) & TDSTAT_Rx_FL) >> 16) 114 115 #define TDSTAT_Rx_DT_SR 0x00000000 /* Serial Received Frame */ 116 #define TDSTAT_Rx_DT_IL 0x00001000 /* Internal Loopback Frame */ 117 #define TDSTAT_Rx_DT_EL 0x00002000 /* External Loopback Frame */ 118 #define TDSTAT_Rx_DT_r 0x00003000 /* Reserved */ 119 120 /* 121 * Descriptor Status bits for Transmit Descriptor. 122 */ 123 #define TDSTAT_WINB_Tx_TE 0x00008000 /* Transmit Error */ 124 #define TDSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */ 125 #define TDSTAT_Tx_LO 0x00000800 /* Loss of Carrier */ 126 #define TDSTAT_Tx_NC 0x00000400 /* No Carrier */ 127 #define TDSTAT_Tx_LC 0x00000200 /* Late Collision */ 128 #define TDSTAT_Tx_EC 0x00000100 /* Excessive Collisions */ 129 #define TDSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */ 130 #define TDSTAT_Tx_CC 0x00000078 /* Collision Count */ 131 #define TDSTAT_Tx_LF 0x00000004 /* Link Fail */ 132 #define TDSTAT_Tx_UF 0x00000002 /* Underflow Error */ 133 #define TDSTAT_Tx_DE 0x00000001 /* Deferred */ 134 135 #define TDSTAT_Tx_COLLISIONS(x) (((x) & TDSTAT_Tx_CC) >> 3) 136 137 /* 138 * Descriptor Control bits common to transmit and receive. 139 */ 140 #define TDCTL_SIZE1 0x000007ff /* Size of buffer 1 */ 141 #define TDCTL_SIZE1_SHIFT 0 142 143 #define TDCTL_SIZE2 0x003ff800 /* Size of buffer 2 */ 144 #define TDCTL_SIZE2_SHIFT 11 145 146 #define TDCTL_ER 0x02000000 /* End of Ring */ 147 #define TDCTL_CH 0x01000000 /* Second Address Chained */ 148 149 /* 150 * Descriptor Control bits for Transmit Descriptor. 151 */ 152 #define TDCTL_Tx_IC 0x80000000 /* Interrupt on Completion */ 153 #define TDCTL_Tx_LS 0x40000000 /* Last Segment */ 154 #define TDCTL_Tx_FS 0x20000000 /* First Segment */ 155 #define TDCTL_Tx_FT1 0x10000000 /* Filtering Type 1 */ 156 #define TDCTL_Tx_SET 0x08000000 /* Setup Packet */ 157 #define TDCTL_Tx_AC 0x04000000 /* Add CRC Disable */ 158 #define TDCTL_Tx_DPD 0x00800000 /* Disabled Padding */ 159 #define TDCTL_Tx_FT0 0x00400000 /* Filtering Type 0 */ 160 161 /* 162 * The Tulip filter is programmed by "transmitting" a Setup Packet 163 * (indicated by TDCTL_Tx_SET). The filtering type is indicated 164 * as follows: 165 * 166 * FT1 FT0 Description 167 * --- --- ----------- 168 * 0 0 Perfect Filtering: The Tulip interprets the 169 * descriptor buffer as a table of 16 MAC addresses 170 * that the Tulip should receive. 171 * 172 * 0 1 Hash Filtering: The Tulip interprets the 173 * descriptor buffer as a 512-bit hash table 174 * plus one perfect address. If the incoming 175 * address is Multicast, the hash table filters 176 * the address, else the address is filtered by 177 * the perfect address. 178 * 179 * 1 0 Inverse Filtering: Like Perfect Filtering, except 180 * the table is addresses that the Tulip does NOT 181 * receive. 182 * 183 * 1 1 Hash-only Filtering: Like Hash Filtering, but 184 * physical addresses are matched by the hash table 185 * as well, and not by matching a single perfect 186 * address. 187 * 188 * A Setup Packet must always be 192 bytes long. The Tulip can store 189 * 16 MAC addresses. If not all 16 are specified in Perfect Filtering 190 * or Inverse Filtering mode, then unused entries should duplicate 191 * one of the valid entries. 192 */ 193 #define TDCTL_Tx_FT_PERFECT 0 194 #define TDCTL_Tx_FT_HASH TDCTL_Tx_FT0 195 #define TDCTL_Tx_FT_INVERSE TDCTL_Tx_FT1 196 #define TDCTL_Tx_FT_HASHONLY (TDCTL_Tx_FT1|TDCTL_Tx_FT0) 197 198 #define TULIP_SETUP_PACKET_LEN 192 199 #define TULIP_MAXADDRS 16 200 #define TULIP_MCHASHSIZE 512 201 202 /* 203 * Maximum size of a Tulip Ethernet Address ROM or SROM. 204 */ 205 #define TULIP_MAX_ROM_SIZE 128 206 207 /* 208 * Tulip control registers. 209 */ 210 211 #define TULIP_CSR0 0x00 212 #define TULIP_CSR1 0x08 213 #define TULIP_CSR2 0x10 214 #define TULIP_CSR3 0x18 215 #define TULIP_CSR4 0x20 216 #define TULIP_CSR5 0x28 217 #define TULIP_CSR6 0x30 218 #define TULIP_CSR7 0x38 219 #define TULIP_CSR8 0x40 220 #define TULIP_CSR9 0x48 221 #define TULIP_CSR10 0x50 222 #define TULIP_CSR11 0x58 223 #define TULIP_CSR12 0x60 224 #define TULIP_CSR13 0x68 225 #define TULIP_CSR14 0x70 226 #define TULIP_CSR15 0x78 227 #define TULIP_CSR16 0x80 228 #define TULIP_CSR17 0x88 229 #define TULIP_CSR18 0x90 230 #define TULIP_CSR19 0x98 231 #define TULIP_CSR20 0xa0 232 233 /* CSR0 - Bus Mode */ 234 #define CSR_BUSMODE TULIP_CSR0 235 #define BUSMODE_SWR 0x00000001 /* software reset */ 236 #define BUSMODE_BAR 0x00000002 /* bus arbitration */ 237 #define BUSMODE_DSL 0x0000007c /* descriptor skip length */ 238 #define BUSMODE_BLE 0x00000080 /* big endian */ 239 /* programmable burst length */ 240 #define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */ 241 #define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */ 242 #define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */ 243 #define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */ 244 #define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */ 245 #define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */ 246 #define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */ 247 /* cache alignment */ 248 #define BUSMODE_CAL_NONE 0x00000000 /* no alignment */ 249 #define BUSMODE_CAL_8LW 0x00004000 /* 8 longwords */ 250 #define BUSMODE_CAL_16LW 0x00008000 /* 16 longwords */ 251 #define BUSMODE_CAL_32LW 0x0000c000 /* 32 longwords */ 252 #define BUSMODE_DAS 0x00010000 /* diagnostic address space */ 253 /* must be zero on most */ 254 /* transmit auto-poll */ 255 /* 256 * Transmit auto-polling not supported on: 257 * Winbond 89C040F 258 */ 259 #define BUSMODE_TAP_NONE 0x00000000 /* no auto-polling */ 260 #define BUSMODE_TAP_200us 0x00020000 /* 200 uS */ 261 #define BUSMODE_TAP_800us 0x00040000 /* 400 uS */ 262 #define BUSMODE_TAP_1_6ms 0x00060000 /* 1.6 mS */ 263 #define BUSMODE_TAP_12_8us 0x00080000 /* 12.8 uS (21041+) */ 264 #define BUSMODE_TAP_25_6us 0x000a0000 /* 25.6 uS (21041+) */ 265 #define BUSMODE_TAP_51_2us 0x000c0000 /* 51.2 uS (21041+) */ 266 #define BUSMODE_TAP_102_4us 0x000e0000 /* 102.4 uS (21041+) */ 267 #define BUSMODE_DBO 0x00100000 /* desc-only b/e (21041+) */ 268 #define BUSMODE_RME 0x00200000 /* rd/mult enab (21140+) */ 269 #define BUSMODE_WINB_WAIT 0x00200000 /* wait state insertion */ 270 #define BUSMODE_RLE 0x00800000 /* rd/line enab (21140+) */ 271 #define BUSMODE_WLE 0x01000000 /* wt/line enab (21140+) */ 272 #define BUSMODE_PNIC_MBO 0x04000000 /* magic `must be one' bit */ 273 /* on Lite-On PNIC */ 274 275 276 /* CSR1 - Transmit Poll Demand */ 277 #define CSR_TXPOLL TULIP_CSR1 278 #define TXPOLL_TPD 0x00000001 /* transmit poll demand */ 279 280 281 /* CSR2 - Receive Poll Demand */ 282 #define CSR_RXPOLL TULIP_CSR2 283 #define RXPOLL_RPD 0x00000001 /* receive poll demand */ 284 285 286 /* CSR3 - Receive List Base Address */ 287 #define CSR_RXLIST TULIP_CSR3 288 289 /* CSR4 - Transmit List Base Address */ 290 #define CSR_TXLIST TULIP_CSR4 291 292 /* CSR5 - Status */ 293 #define CSR_STATUS TULIP_CSR5 294 #define STATUS_TI 0x00000001 /* transmit interrupt */ 295 #define STATUS_TPS 0x00000002 /* transmit process stopped */ 296 #define STATUS_TU 0x00000004 /* transmit buffer unavail */ 297 #define STATUS_TJT 0x00000008 /* transmit jabber timeout */ 298 #define STATUS_WINB_REI 0x00000008 /* receive early interrupt */ 299 #define STATUS_LNPANC 0x00000010 /* link pass (21041) */ 300 #define STATUS_WINB_RERR 0x00000010 /* receive error */ 301 #define STATUS_UNF 0x00000020 /* transmit underflow */ 302 #define STATUS_RI 0x00000040 /* receive interrupt */ 303 #define STATUS_RU 0x00000080 /* receive buffer unavail */ 304 #define STATUS_RPS 0x00000100 /* receive process stopped */ 305 #define STATUS_RWT 0x00000200 /* receive watchdog timeout */ 306 #define STATUS_AT 0x00000400 /* SIA AUI/TP pin changed 307 (21040) */ 308 #define STATUS_WINB_TEI 0x00000400 /* transmit early interrupt */ 309 #define STATUS_FD 0x00000800 /* full duplex short frame 310 received (21040) */ 311 #define STATUS_TM 0x00000800 /* timer expired (21041) */ 312 #define STATUS_LNF 0x00001000 /* link fail (21040) */ 313 #define STATUS_SE 0x00002000 /* system error */ 314 #define STATUS_ER 0x00004000 /* early receive (21041) */ 315 #define STATUS_AIS 0x00008000 /* abnormal interrupt summary */ 316 #define STATUS_NIS 0x00010000 /* normal interrupt summary */ 317 #define STATUS_RS 0x000e0000 /* receive process state */ 318 #define STATUS_RS_STOPPED 0x00000000 /* Stopped */ 319 #define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive 320 descriptor */ 321 #define STATUS_RS_CHECK 0x00040000 /* Running - check for end 322 of receive */ 323 #define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */ 324 #define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */ 325 #define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive 326 descriptor */ 327 #define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current 328 frame from FIFO */ 329 #define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current 330 frame from FIFO into 331 buffer */ 332 #define STATUS_TS 0x00700000 /* transmit process state */ 333 #define STATUS_TS_STOPPED 0x00000000 /* Stopped */ 334 #define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit 335 descriptor */ 336 #define STATUS_TS_WAIT 0x00200000 /* Running - wait for end 337 of transmission */ 338 #define STATUS_TS_READING 0x00300000 /* Running - read buffer from 339 memory and queue into 340 FIFO */ 341 #define STATUS_TS_RESERVED 0x00400000 /* RESERVED */ 342 #define STATUS_TS_SETUP 0x00500000 /* Running - Setup packet */ 343 #define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */ 344 #define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit 345 descriptor */ 346 #define STATUS_EB 0x03800000 /* error bits */ 347 #define STATUS_EB_PARITY 0x00000000 /* parity errror */ 348 #define STATUS_EB_MABT 0x00800000 /* master abort */ 349 #define STATUS_EB_TABT 0x01000000 /* target abort */ 350 #define STATUS_PNIC_TXABORT 0x04000000 /* transmit aborted */ 351 352 353 /* CSR6 - Operation Mode */ 354 #define CSR_OPMODE TULIP_CSR6 355 #define OPMODE_HP 0x00000001 /* hash/perfect mode (ro) */ 356 #define OPMODE_SR 0x00000002 /* start receive */ 357 #define OPMODE_HO 0x00000004 /* hash only mode (ro) */ 358 #define OPMODE_PB 0x00000008 /* pass bad frames */ 359 #define OPMODE_WINB_APP 0x00000008 /* accept all physcal packet */ 360 #define OPMODE_IF 0x00000010 /* inverse filter mode (ro) */ 361 #define OPMODE_WINB_AMP 0x00000010 /* accept multicast packet */ 362 #define OPMODE_SB 0x00000020 /* start backoff counter */ 363 #define OPMODE_WINB_ABP 0x00000020 /* accept broadcast packet */ 364 #define OPMODE_PR 0x00000040 /* promiscuous mode */ 365 #define OPMODE_WINB_ARP 0x00000040 /* accept runt packet */ 366 #define OPMODE_PM 0x00000080 /* pass all multicast */ 367 #define OPMODE_WINB_AEP 0x00000080 /* accept error packet */ 368 #define OPMODE_FKD 0x00000100 /* flaky oscillator disable */ 369 #define OPMODE_FD 0x00000200 /* full-duplex mode */ 370 #define OPMODE_OM 0x00000c00 /* operating mode */ 371 #define OPMODE_OM_NORMAL 0x00000000 /* normal mode */ 372 #define OPMODE_OM_INTLOOP 0x00000400 /* internal loopback */ 373 #define OPMODE_OM_EXTLOOP 0x00000800 /* external loopback */ 374 #define OPMODE_FC 0x00001000 /* force collision */ 375 #define OPMODE_ST 0x00002000 /* start transmitter */ 376 #define OPMODE_TR 0x0000c000 /* threshold control */ 377 #define OPMODE_TR_72 0x00000000 /* 72 bytes */ 378 #define OPMODE_TR_96 0x00004000 /* 96 bytes */ 379 #define OPMODE_TR_128 0x00008000 /* 128 bytes */ 380 #define OPMODE_TR_160 0x0000c000 /* 160 bytes */ 381 #define OPMODE_WINB_TTH 0x001fc000 /* transmit threshold */ 382 #define OPMODE_WINB_TTH_SHIFT 14 383 #define OPMODE_BP 0x00010000 /* backpressure enable */ 384 #define OPMODE_CA 0x00020000 /* capture effect enable */ 385 #define OPMODE_PMAC_TBEN 0x00020000 /* Tx backoff offset enable */ 386 #define OPMODE_PS 0x00040000 /* port select: 387 1 = MII/SYM, 0 = SRL 388 (21140) */ 389 #define OPMODE_HBD 0x00080000 /* heartbeat disable: 390 set in MII/SYM 100mbps, 391 set according to PHY 392 in MII 10mbps mode 393 (21140) */ 394 #define OPMODE_PNIC_IT 0x00100000 /* immediate transmit */ 395 #define OPMODE_SF 0x00200000 /* store and forward mode 396 (21140) */ 397 #define OPMODE_WINB_REIT 0x1fe00000 /* receive eartly intr thresh */ 398 #define OPMODE_WINB_REIT_SHIFT 21 399 #define OPMODE_TTM 0x00400000 /* Transmit Threshold Mode: 400 1 = 10mbps, 0 = 100mbps 401 (21140) */ 402 #define OPMODE_PCS 0x00800000 /* PCS function (21140) */ 403 #define OPMODE_SCR 0x01000000 /* scrambler mode (21140) */ 404 #define OPMODE_MBO 0x02000000 /* must be one (21140) */ 405 #define OPMODE_PNIC_DRC 0x20000000 /* don't include CRC in Rx 406 frames (PNIC) */ 407 #define OPMODE_WINB_FES 0x20000000 /* fast ethernet select */ 408 #define OPMODE_RA 0x40000000 /* receive all (21140) */ 409 #define OPMODE_PNIC_EED 0x40000000 /* 1 == ext, 0 == int ENDEC 410 (PNIC) */ 411 #define OPMODE_WINB_TEIO 0x40000000 /* transmit early intr on */ 412 #define OPMODE_SC 0x80000000 /* special capture effect 413 enable (21041+) */ 414 #define OPMODE_WINB_REIO 0x80000000 /* receive early intr on */ 415 416 /* CSR7 - Interrupt Enable */ 417 #define CSR_INTEN TULIP_CSR7 418 /* See bits for CSR5 -- Status */ 419 420 421 /* CSR8 - Missed Frames */ 422 #define CSR_MISSED TULIP_CSR8 423 #define MISSED_MFC 0x0000ffff /* missed packet count */ 424 #define MISSED_MFO 0x00010000 /* missed packet count 425 overflowed */ 426 #define MISSED_FOC 0x0ffe0000 /* fifo overflow counter 427 (21140) */ 428 #define MISSED_OCO 0x10000000 /* overflow counter overflowed 429 (21140) */ 430 431 #define MISSED_GETMFC(x) ((x) & MISSED_MFC) 432 #define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 17) 433 434 435 /* CSR9 - MII, SROM, Boot ROM, Ethernet Address ROM register. */ 436 #define CSR_MIIROM TULIP_CSR9 437 #define MIIROM_DATA 0x000000ff /* byte of data from 438 Ethernet Address ROM 439 (21040), byte of data 440 to/from Boot ROM (21041+) */ 441 #define MIIROM_SROMCS 0x00000001 /* SROM chip select */ 442 #define MIIROM_SROMSK 0x00000002 /* SROM clock */ 443 #define MIIROM_SROMDI 0x00000004 /* SROM data in (to) */ 444 #define MIIROM_SROMDO 0x00000008 /* SROM data out (from) */ 445 #define MIIROM_REG 0x00000400 /* external register select */ 446 #define MIIROM_SR 0x00000800 /* SROM select */ 447 #define MIIROM_BR 0x00001000 /* boot ROM select */ 448 #define MIIROM_WR 0x00002000 /* write to boot ROM */ 449 #define MIIROM_RD 0x00004000 /* read from boot ROM */ 450 #define MIIROM_MOD 0x00008000 /* mode select (ro) (21041) */ 451 #define MIIROM_MDC 0x00010000 /* MII clock */ 452 #define MIIROM_MDO 0x00020000 /* MII data out */ 453 #define MIIROM_MIIDIR 0x00040000 /* MII direction mode 454 1 = PHY in read, 455 0 = PHY in write */ 456 #define MIIROM_MDI 0x00080000 /* MII data in */ 457 #define MIIROM_DN 0x80000000 /* data not valid (21040) */ 458 459 /* SROM opcodes */ 460 #define TULIP_SROM_OPC_ERASE 0x04 461 #define TULIP_SROM_OPC_WRITE 0x05 462 #define TULIP_SROM_OPC_READ 0x06 463 464 /* The Lite-On PNIC does this completely differently */ 465 #define PNIC_MIIROM_DATA 0x0000ffff /* mask of data bits ??? */ 466 #define PNIC_MIIROM_BUSY 0x80000000 /* EEPROM is busy */ 467 468 469 /* CSR10 - Boot ROM address register (21041+). */ 470 #define CSR_ROMADDR TULIP_CSR10 471 #define ROMADDR_MASK 0x000003ff /* boot rom address */ 472 473 474 /* CSR11 - General Purpose Timer (21041+). */ 475 #define CSR_GPT TULIP_CSR11 476 #define GPT_VALUE 0x0000ffff /* timer value */ 477 #define GPT_CON 0x00010000 /* continuous mode */ 478 479 480 /* CSR12 - SIA Status Register (21040, 21041). */ 481 #define CSR_SIASTAT TULIP_CSR12 482 #define SIASTAT_PAUI 0x00000001 /* pin AUI/TP indication 483 (21040) */ 484 #define SIASTAT_NCR 0x00000002 /* network connection error */ 485 #define SIASTAT_LKF 0x00000004 /* link fail status */ 486 #define SIASTAT_APS 0x00000008 /* auto polarity status */ 487 #define SIASTAT_DSD 0x00000010 /* PLL self test done */ 488 #define SIASTAT_DSP 0x00000020 /* PLL self test pass */ 489 #define SIASTAT_DAZ 0x00000040 /* PLL all zero */ 490 #define SIASTAT_DAO 0x00000080 /* PLL all one */ 491 #define SIASTAT_SRA 0x00000100 /* selected port receive 492 activity (21041) */ 493 #define SIASTAT_NRA 0x00000200 /* non-selected port 494 receive activity (21041) */ 495 #define SIASTAT_NSN 0x00000400 /* non-stable NLPs detected 496 (21041) */ 497 #define SIASTAT_TRF 0x00000800 /* transmit remote fault 498 (21041) */ 499 #define SIASTAT_ANS 0x00007000 /* autonegotiation state 500 (21041) */ 501 #define SIASTAT_ANS_DIS 0x00000000 /* disabled */ 502 #define SIASTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 503 #define SIASTAT_ANS_ABD 0x00002000 /* ability detect */ 504 #define SIASTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 505 #define SIASTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 506 #define SIASTAT_ANS_FPLGOOD 0x00005000 /* FLP link good */ 507 #define SIASTAT_ANS_LINKCHECK 0x00006000 /* link check */ 508 #define SIASTAT_LPN 0x00008000 /* link partner negotiable 509 (21041) */ 510 #define SIASTAT_LPC 0xffff0000 /* link partner code word */ 511 512 #define SIASTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 513 514 515 /* CSR13 - SIA Connectivity Register (21040, 21041). */ 516 #define CSR_SIACONN TULIP_CSR13 517 #define SIACONN_SRL 0x00000001 /* SIA reset */ 518 #define SIACONN_PS 0x00000002 /* pin AUI/TP selection 519 (21040) */ 520 #define SIACONN_CAC 0x00000004 /* CSR autoconfiguration */ 521 #define SIACONN_AUI 0x00000008 /* select AUI (0 = TP) */ 522 #define SIACONN_EDP 0x00000010 /* SIA PLL external input 523 enable (21040) */ 524 #define SIACONN_ENI 0x00000020 /* encoder input multiplexer 525 (21040) */ 526 #define SIACONN_SIM 0x00000040 /* serial interface input 527 multiplexer (21040) */ 528 #define SIACONN_ASE 0x00000080 /* APLL start enable 529 (21040) */ 530 #define SIACONN_SEL 0x00000f00 /* external port output 531 multiplexer select 532 (21040) */ 533 #define SIACONN_IE 0x00001000 /* input enable (21040) */ 534 #define SIACONN_OE1_3 0x00002000 /* output enable 1, 3 535 (21040) */ 536 #define SIACONN_OE2_4 0x00004000 /* output enable 2, 4 537 (21040) */ 538 #define SIACONN_OE5_6_7 0x00008000 /* output enable 5, 6, 7 539 (21040) */ 540 #define SIACONN_SDM 0x0000ef00 /* SIA diagnostic mode; 541 always set to this value 542 for normal operation 543 (21041) */ 544 545 546 /* CSR14 - SIA Transmit Receive Register (21040, 21041). */ 547 #define CSR_SIATXRX TULIP_CSR14 548 #define SIATXRX_ECEN 0x00000001 /* encoder enable */ 549 #define SIATXRX_LBK 0x00000002 /* loopback enable */ 550 #define SIATXRX_DREN 0x00000004 /* driver enable */ 551 #define SIATXRX_LSE 0x00000008 /* link pulse send enable */ 552 #define SIATXRX_CPEN 0x00000030 /* compensation enable */ 553 #define SIATXRX_CPEN_DIS0 0x00000000 /* disabled */ 554 #define SIATXRX_CPEN_DIS1 0x00000010 /* disabled */ 555 #define SIATXRX_CPEN_HIGHPWR 0x00000020 /* high power */ 556 #define SIATXRX_CPEN_NORMAL 0x00000030 /* normal */ 557 #define SIATXRX_MBO 0x00000040 /* must be one (21041 pass 2) */ 558 #define SIATXRX_ANE 0x00000080 /* autonegotiation enable 559 (21041) */ 560 #define SIATXRX_RSQ 0x00000100 /* receive squelch enable */ 561 #define SIATXRX_CSQ 0x00000200 /* collision squelch enable */ 562 #define SIATXRX_CLD 0x00000400 /* collision detect enable */ 563 #define SIATXRX_SQE 0x00000800 /* signal quality generation 564 enable */ 565 #define SIATXRX_LTE 0x00001000 /* link test enable */ 566 #define SIATXRX_APE 0x00002000 /* auto-polarity enable */ 567 #define SIATXRX_SPP 0x00004000 /* set plarity plus */ 568 #define SIATXRX_TAS 0x00008000 /* 10base-T/AUI autosensing 569 enable (21041) */ 570 571 572 /* CSR15 - SIA General Register (21040, 21041). */ 573 #define CSR_SIAGEN TULIP_CSR15 574 #define SIAGEN_JBD 0x00000001 /* jabber disable */ 575 #define SIAGEN_HUJ 0x00000002 /* host unjab */ 576 #define SIAGEN_JCK 0x00000004 /* jabber clock */ 577 #define SIAGEN_ABM 0x00000008 /* BNC select (21041) */ 578 #define SIAGEN_RWD 0x00000010 /* receive watchdog disable */ 579 #define SIAGEN_RWR 0x00000020 /* receive watchdog release */ 580 #define SIAGEN_LE1 0x00000040 /* LED 1 enable (21041) */ 581 #define SIAGEN_LV1 0x00000080 /* LED 1 value (21041) */ 582 #define SIAGEN_TSCK 0x00000100 /* test clock */ 583 #define SIAGEN_FUSQ 0x00000200 /* force unsquelch */ 584 #define SIAGEN_FLF 0x00000400 /* force link fail */ 585 #define SIAGEN_LSD 0x00000800 /* LED stretch disable 586 (21041) */ 587 #define SIAGEN_DPST 0x00001000 /* PLL self-test start */ 588 #define SIAGEN_FRL 0x00002000 /* force receiver low */ 589 #define SIAGEN_LE2 0x00004000 /* LED 2 enable (21041) */ 590 #define SIAGEN_LV2 0x00008000 /* LED 2 value (21041) */ 591 592 593 /* CSR12 - General Purpose Port (21140+). */ 594 #define CSR_GPP TULIP_CSR12 595 #define GPP_MD 0x000000ff /* general purpose mode/data */ 596 #define GPP_GPC 0x00000100 /* general purpose control */ 597 #define GPP_PNIC_GPD 0x0000000f /* general purpose data */ 598 #define GPP_PNIC_GPC 0x000000f0 /* general purpose control */ 599 600 #define GPP_PNIC_IN(x) (1 << (x)) 601 #define GPP_PNIC_OUT(x) ((1 << (x)) | (1 << ((x) + 4))) 602 603 /* 604 * The Lite-On PNIC manual recommends the following for the General Purpose 605 * I/O pins: 606 * 607 * 0 Speed Relay 1 == 100mbps 608 * 1 100mbps loopback 1 == loopback 609 * 2 BNC DC-DC converter 1 == select BNC 610 * 3 Link 100 1 == 100baseTX link status 611 */ 612 #define GPP_PNIC_PIN_SPEED_RLY 0 613 #define GPP_PNIC_PIN_100M_LPKB 1 614 #define GPP_PNIC_PIN_BNC_XMER 2 615 #define GPP_PNIC_PIN_LNK100X 3 616 617 618 /* CSR15 - Watchdog timer (21140+). */ 619 #define CSR_WATCHDOG TULIP_CSR15 620 #define WATCHDOG_JBD 0x00000001 /* jabber disable */ 621 #define WATCHDOG_HUJ 0x00000002 /* host unjab */ 622 #define WATCHDOG_JCK 0x00000004 /* jabber clock */ 623 #define WATCHDOG_RWD 0x00000010 /* receive watchdog disable */ 624 #define WATCHDOG_RWR 0x00000020 /* receive watchdog release */ 625 626 627 /* 628 * Digital Semiconductor 21040 registers. 629 */ 630 631 /* CSR11 - Full Duplex Register */ 632 #define CSR_21040_FDX TULIP_CSR11 633 #define FDX21040_FDXACV 0x0000ffff /* full duplex 634 autoconfiguration value */ 635 636 637 /* SIA configuration for 10base-T (from the 21040 manual) */ 638 #define SIACONN_21040_10BASET 0x0000ef01 639 #define SIATXRX_21040_10BASET 0x0000ffff 640 #define SIAGEN_21040_10BASET 0x00000000 641 642 643 /* SIA configuration for 10base-T full-duplex (from the 21040 manual) */ 644 #define SIACONN_21040_10BASET_FDX 0x0000ef01 645 #define SIATXRX_21040_10BASET_FDX 0x0000fffd 646 #define SIAGEN_21040_10BASET_FDX 0x00000000 647 648 649 /* SIA configuration for 10base-5 (from the 21040 manual) */ 650 #define SIACONN_21040_AUI 0x0000ef09 651 #define SIATXRX_21040_AUI 0x00000705 652 #define SIAGEN_21040_AUI 0x00000006 653 654 655 /* SIA configuration for External SIA (from the 21040 manual) */ 656 #define SIACONN_21040_EXTSIA 0x00003041 657 #define SIATXRX_21040_EXTSIA 0x00000000 658 #define SIAGEN_21040_EXTSIA 0x00000006 659 660 661 /* 662 * Digital Semiconductor 21041 registers. 663 */ 664 665 /* SIA configuration for 10base-T (from the 21041 manual) */ 666 #define SIACONN_21041_10BASET 0x0000ef01 667 #define SIATXRX_21041_10BASET 0x0000ff3f 668 #define SIAGEN_21041_10BASET 0x00000000 669 670 #define SIACONN_21041P2_10BASET SIACONN_21041_10BASET 671 #define SIATXRX_21041P2_10BASET 0x0000ffff 672 #define SIAGEN_21041P2_10BASET SIAGEN_21041_10BASET 673 674 675 /* SIA configuration for 10base-T full-duplex (from the 21041 manual) */ 676 #define SIACONN_21041_10BASET_FDX 0x0000ef01 677 #define SIATXRX_21041_10BASET_FDX 0x0000ff3d 678 #define SIAGEN_21041_10BASET_FDX 0x00000000 679 680 #define SIACONN_21041P2_10BASET_FDX SIACONN_21041_10BASET_FDX 681 #define SIATXRX_21041P2_10BASET_FDX 0x0000ffff 682 #define SIAGEN_21041P2_10BASET_FDX SIAGEN_21041_10BASET_FDX 683 684 685 /* SIA configuration for 10base-5 (from the 21041 manual) */ 686 #define SIACONN_21041_AUI 0x0000ef09 687 #define SIATXRX_21041_AUI 0x0000f73d 688 #define SIAGEN_21041_AUI 0x0000000e 689 690 #define SIACONN_21041P2_AUI SIACONN_21041_AUI 691 #define SIATXRX_21041P2_AUI 0x0000f7fd 692 #define SIAGEN_21041P2_AUI SIAGEN_21041_AUI 693 694 695 /* SIA configuration for 10base-2 (from the 21041 manual) */ 696 #define SIACONN_21041_BNC 0x0000ef09 697 #define SIATXRX_21041_BNC 0x0000f73d 698 #define SIAGEN_21041_BNC 0x00000006 699 700 #define SIACONN_21041P2_BNC SIACONN_21041_BNC 701 #define SIATXRX_21041P2_BNC 0x0000f7fd 702 #define SIAGEN_21041P2_BNC SIAGEN_21041_BNC 703 704 705 /* 706 * Digital Semiconductor 21142/21143 registers. 707 */ 708 709 /* XXX */ 710 711 /* 712 * Lite-On 82C168/82C169 registers. 713 */ 714 715 /* ENDEC General Register */ 716 #define CSR_PNIC_ENDEC 0x78 717 #define PNIC_ENDEC_JDIS 0x00000001 /* jabber disable */ 718 719 /* SROM Power Register */ 720 #define CSR_PNIC_SROMPWR 0x90 721 #define PNIC_SROMPWR_MRLE 0x00000001 /* Memory-Read-Line enable */ 722 #define PNIC_SROMPWR_CB 0x00000002 /* cache boundary alignment 723 burst type; 1 == burst to 724 boundary, 0 == single-cycle 725 to boundary */ 726 727 /* SROM Control Register */ 728 #define CSR_PNIC_SROMCTL 0x98 729 #define PNIC_SROMCTL_addr 0x0000003f /* mask of address bits */ 730 /* XXX THESE ARE WRONG ACCORDING TO THE MANUAL! */ 731 #define PNIC_SROMCTL_READ 0x00000600 /* read command */ 732 733 /* MII Access Register */ 734 #define CSR_PNIC_MII 0xa0 735 #define PNIC_MII_DATA 0x0000ffff /* mask of data bits */ 736 #define PNIC_MII_REG 0x007c0000 /* register mask */ 737 #define PNIC_MII_REGSHIFT 18 738 #define PNIC_MII_PHY 0x0f800000 /* phy mask */ 739 #define PNIC_MII_PHYSHIFT 23 740 #define PNIC_MII_OPCODE 0x30000000 /* opcode mask */ 741 #define PNIC_MII_RESERVED 0x00020000 /* must be one/must be zero; 742 2 bits are described here */ 743 #define PNIC_MII_MBO 0x40000000 /* must be one */ 744 #define PNIC_MII_BUSY 0x80000000 /* MII is busy */ 745 746 #define PNIC_MII_WRITE 0x10000000 /* write PHY command */ 747 #define PNIC_MII_READ 0x20000000 /* read PHY command */ 748 749 /* NWAY Register */ 750 #define CSR_PNIC_NWAY 0xb8 751 #define PNIC_NWAY_RS 0x00000001 /* reset NWay block */ 752 #define PNIC_NWAY_PD 0x00000002 /* power down NWay block */ 753 #define PNIC_NWAY_BX 0x00000004 /* bypass transciever */ 754 #define PNIC_NWAY_LC 0x00000008 /* AUI low current mode */ 755 #define PNIC_NWAY_UV 0x00000010 /* low squelch voltage */ 756 #define PNIC_NWAY_DX 0x00000020 /* disable TP pol. correction */ 757 #define PNIC_NWAY_TW 0x00000040 /* select TP (0 == AUI) */ 758 #define PNIC_NWAY_AF 0x00000080 /* AUI full/half step input 759 voltage */ 760 #define PNIC_NWAY_FD 0x00000100 /* full duplex mode */ 761 #define PNIC_NWAY_DL 0x00000200 /* disable link integrity 762 test */ 763 #define PNIC_NWAY_DM 0x00000400 /* disable AUI/TP autodetect */ 764 #define PNIC_NWAY_100 0x00000800 /* 1 == 100mbps, 0 == 10mbps */ 765 #define PNIC_NWAY_NW 0x00001000 /* enable NWay block */ 766 #define PNIC_NWAY_CAP10T 0x00002000 /* adv. 10baseT */ 767 #define PNIC_NWAY_CAP10TFDX 0x00004000 /* adv. 10baseT-FDX */ 768 #define PNIC_NWAY_CAP100TXFDX 0x00008000 /* adv. 100baseTX-FDX */ 769 #define PNIC_NWAY_CAP100TX 0x00010000 /* adv. 100baseTX */ 770 #define PNIC_NWAY_CAP100T4 0x00020000 /* adv. 100base-T4 */ 771 #define PNIC_NWAY_RN 0x02000000 /* re-negotiate enable */ 772 #define PNIC_NWAY_RF 0x04000000 /* remote fault detected */ 773 #define PNIC_NWAY_LPAR10T 0x08000000 /* link part. 10baseT */ 774 #define PNIC_NWAY_LPAR10TFDX 0x10000000 /* link part. 10baseT-FDX */ 775 #define PNIC_NWAY_LPAR100TXFDX 0x20000000 /* link part. 100baseTX-FDX */ 776 #define PNIC_NWAY_LPAR100TX 0x40000000 /* link part. 100baseTX */ 777 #define PNIC_NWAY_LPAR100T4 0x80000000 /* link part. 100base-T4 */ 778 #define PNIC_NWAY_LPAR_MASK 0xf8000000 779 780 781 /* 782 * Macronix 98713, 98713A, 98715, 98715A, 98725 registers. 783 */ 784 785 /* CSR12 - 10base-T Status Port (similar to SIASTAT) */ 786 #define CSR_PMAC_10TSTAT TULIP_CSR12 787 #define PMAC_10TSTAT_LS100 0x00000002 /* link status 100TX 788 0 = link up */ 789 #define PMAC_10TSTAT_LS10 0x00000004 /* link status 10T 790 0 = link up */ 791 #define PMAC_10TSTAT_APS 0x00000008 /* auto polarity status */ 792 #define PMAC_10TSTAT_TRF 0x00000800 /* transmit remote fault 793 (21041) */ 794 #define PMAC_10TSTAT_ANS 0x00007000 /* autonegotiation state 795 (21041) */ 796 #define PMAC_10TSTAT_ANS_DIS 0x00000000 /* disabled */ 797 #define PMAC_10TSTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 798 #define PMAC_10TSTAT_ANS_ABD 0x00002000 /* ability detect */ 799 #define PMAC_10TSTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 800 #define PMAC_10TSTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 801 #define PMAC_10TSTAT_ANS_FPLGOOD 0x00005000 /* FLP link good */ 802 #define PMAC_10TSTAT_ANS_LINKCHECK 0x00006000 /* link check */ 803 #define PMAC_10TSTAT_LPN 0x00008000 /* link partner negotiable 804 (21041) */ 805 #define PMAC_10TSTAT_LPC 0xffff0000 /* link partner code word */ 806 807 #define PMAC_10TSTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 808 809 810 /* CSR13 - NWAY Reset Register */ 811 #define CSR_PMAC_NWAYRESET TULIP_CSR13 812 #define PMAC_NWAYRESET_RESET 0x00000000 /* NWAY reset */ 813 814 815 /* CSR14 - 10base-T Control Port */ 816 #define CSR_PMAC_10TCTL TULIP_CSR14 817 #define PMAC_10TCTL_LBK 0x00000002 /* loopback */ 818 #define PMAC_10TCTL_PWD10 0x00000004 /* power down 10base-T */ 819 #define PMAC_10TCTL_HDE 0x00000040 /* half-duplex enable */ 820 #define PMAC_10TCTL_ANE 0x00000080 /* autonegotiation enable */ 821 #define PMAC_10TCTL_RSQ 0x00000100 /* receive squelch enable */ 822 #define PMAC_10TCTL_LTE 0x00001000 /* link test enable */ 823 #define PMAC_10TCTL_TXH 0x00010000 /* adv. 100tx */ 824 #define PMAC_10TCTL_TXF 0x00020000 /* adv. 100tx-fdx */ 825 #define PMAC_10TCTL_T4 0x00040000 /* adv. 100t4 */ 826 827 828 /* CSR16 - Test Operation Register (a.k.a. Magic Packet Register) */ 829 #define CSR_PMAC_TOR TULIP_CSR16 830 #define PMAC_TOR_98713 0x0F370000 831 #define PMAC_TOR_98715 0x0B3C0000 832 833 834 /* CSR20 - NWAY Status */ 835 #define CSR_PMAC_NWAYSTAT TULIP_CSR20 836 #define PMAC_NWAYSTAT_10TXH 0x08000000 /* 10t accepted */ 837 #define PMAC_NWAYSTAT_10TXF 0x10000000 /* 10t-fdx accepted */ 838 #define PMAC_NWAYSTAT_100TXH 0x20000000 /* 100tx accepted */ 839 #define PMAC_NWAYSTAT_100TXF 0x40000000 /* 100tx-fdx accepted */ 840 #define PMAC_NWAYSTAT_T4 0x80000000 /* 100t4 accepted */ 841 842 843 /* 844 * Winbond 89C840F registers. 845 */ 846 847 /* CSR12 - Current Receive Descriptor Register */ 848 #define CSR_WINB_CRDAR TULIP_CSR12 849 850 851 /* CSR13 - Current Receive Buffer Register */ 852 #define CSR_WINB_CCRBAR TULIP_CSR13 853 854 855 /* CSR14 - Multicast Address Register 0 */ 856 #define CSR_WINB_CMA0 TULIP_CSR14 857 858 859 /* CSR15 - Multicast Address Register 1 */ 860 #define CSR_WINB_CMA1 TULIP_CSR15 861 862 863 /* CSR16 - Physical Address Register 0 */ 864 #define CSR_WINB_CPA0 TULIP_CSR16 865 866 867 /* CSR17 - Physical Address Register 1 */ 868 #define CSR_WINB_CPA1 TULIP_CSR17 869 870 871 /* CSR18 - Boot ROM Size Register */ 872 #define CSR_WINB_CBRCR TULIP_CSR18 873 #define WINB_CBRCR_NONE 0x00000000 /* no boot rom */ 874 /* 0x00000001 also no boot rom */ 875 #define WINB_CBRCR_8K 0x00000002 /* 8k */ 876 #define WINB_CBRCR_16K 0x00000003 /* 16k */ 877 #define WINB_CBRCR_32K 0x00000004 /* 32k */ 878 #define WINB_CBRCR_64K 0x00000005 /* 64k */ 879 #define WINB_CBRCR_128K 0x00000006 /* 128k */ 880 #define WINB_CBRCR_256K 0x00000007 881 882 883 /* CSR19 - Current Transmit Descriptor Register */ 884 #define CSR_WINB_CTDAR TULIP_CSR19 885 886 887 /* CSR20 - Current Transmit Buffer Register */ 888 #define CSR_WINB_CTBAR TULIP_CSR20 889 890 #endif /* _DEV_IC_TULIPREG_H_ */ 891
Indexes created Mon Sep 29 03:10:08 GMT 2025