tulipreg.h revision 1.7
1 /* $NetBSD: tulipreg.h,v 1.7 1999/09/24 18:27:22 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_IC_TULIPREG_H_ 41 #define _DEV_IC_TULIPREG_H_ 42 43 /* 44 * Register description for the Digital Semiconductor ``Tulip'' (21x4x) 45 * Ethernet controller family, and a variety of clone chips, including: 46 * 47 * - Macronix 98713, 98713A, 98715, 98715A, 98725 (PMAC): 48 * 49 * These chips are fairly straight-forward Tulip clones. 50 * The 98713 and 98713A have an MII. All have an internal 51 * transciever capable of NWAY. The 98713A, 98715A, and 52 * 98725 support power management. 53 * 54 * - Lite-On 82C168, 82C169 (PNIC): 55 * 56 * These are Tulip clones with a few small differences; the 57 * EEPROM is accessed totally differently, as is the MII. 58 * The PNIC also has a built-in NWAY transciever. 59 * 60 * - Winbond 89C840F 61 * 62 * Fairly straight-forward Tulip clone, with the exception 63 * that registers don't have a pad longword between them, 64 * and the receive filter is set up differently: instead of 65 * a setup packet, we have 2 32-bit multicast hash table 66 * registers, and 2 station address registers. 67 * 68 * Some of the clone chips have different registers, and some have 69 * different bits in the same registers. These will be denoted by 70 * PMAC, PNIC, and WINB in the register/bit names. 71 */ 72 73 /* 74 * Tulip buffer descriptor. Must be 4-byte aligned. 75 * 76 * Note for receive descriptors, the byte count fields must 77 * be a multiple of 4. 78 */ 79 struct tulip_desc { 80 __volatile u_int32_t td_status; /* Status */ 81 __volatile u_int32_t td_ctl; /* Control and Byte Counts */ 82 __volatile u_int32_t td_bufaddr1; /* Buffer Address 1 */ 83 __volatile u_int32_t td_bufaddr2; /* Buffer Address 2 */ 84 }; 85 86 /* 87 * Descriptor Status bits common to transmit and receive. 88 */ 89 #define TDSTAT_OWN 0x80000000 /* Tulip owns descriptor */ 90 #define TDSTAT_ES 0x00008000 /* Error Summary */ 91 92 /* 93 * Descriptor Status bits for Receive Descriptor. 94 */ 95 #define TDSTAT_Rx_FF 0x40000000 /* Filtering Fail */ 96 #define TDSTAT_WINB_Rx_RCMP 0x40000000 /* Receive Complete */ 97 #define TDSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */ 98 #define TDSTAT_Rx_DE 0x00004000 /* Descriptor Error */ 99 #define TDSTAT_Rx_DT 0x00003000 /* Data Type */ 100 #define TDSTAT_Rx_RF 0x00000800 /* Runt Frame */ 101 #define TDSTAT_Rx_MF 0x00000400 /* Multicast Frame */ 102 #define TDSTAT_Rx_FS 0x00000200 /* First Descriptor */ 103 #define TDSTAT_Rx_LS 0x00000100 /* Last Descriptor */ 104 #define TDSTAT_Rx_TL 0x00000080 /* Frame Too Long */ 105 #define TDSTAT_Rx_CS 0x00000040 /* Collision Seen */ 106 #define TDSTAT_Rx_RT 0x00000020 /* Frame Type */ 107 #define TDSTAT_Rx_RW 0x00000010 /* Receive Watchdog */ 108 #define TDSTAT_Rx_RE 0x00000008 /* Report on MII Error */ 109 #define TDSTAT_Rx_DB 0x00000004 /* Dribbling Bit */ 110 #define TDSTAT_Rx_CE 0x00000002 /* CRC Error */ 111 #define TDSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */ 112 113 #define TDSTAT_Rx_LENGTH(x) (((x) & TDSTAT_Rx_FL) >> 16) 114 115 #define TDSTAT_Rx_DT_SR 0x00000000 /* Serial Received Frame */ 116 #define TDSTAT_Rx_DT_IL 0x00001000 /* Internal Loopback Frame */ 117 #define TDSTAT_Rx_DT_EL 0x00002000 /* External Loopback Frame */ 118 #define TDSTAT_Rx_DT_r 0x00003000 /* Reserved */ 119 120 /* 121 * Descriptor Status bits for Transmit Descriptor. 122 */ 123 #define TDSTAT_WINB_Tx_TE 0x00008000 /* Transmit Error */ 124 #define TDSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */ 125 #define TDSTAT_Tx_LO 0x00000800 /* Loss of Carrier */ 126 #define TDSTAT_Tx_NC 0x00000400 /* No Carrier */ 127 #define TDSTAT_Tx_LC 0x00000200 /* Late Collision */ 128 #define TDSTAT_Tx_EC 0x00000100 /* Excessive Collisions */ 129 #define TDSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */ 130 #define TDSTAT_Tx_CC 0x00000078 /* Collision Count */ 131 #define TDSTAT_Tx_LF 0x00000004 /* Link Fail */ 132 #define TDSTAT_Tx_UF 0x00000002 /* Underflow Error */ 133 #define TDSTAT_Tx_DE 0x00000001 /* Deferred */ 134 135 #define TDSTAT_Tx_COLLISIONS(x) (((x) & TDSTAT_Tx_CC) >> 3) 136 137 /* 138 * Descriptor Control bits common to transmit and receive. 139 */ 140 #define TDCTL_SIZE1 0x000007ff /* Size of buffer 1 */ 141 #define TDCTL_SIZE1_SHIFT 0 142 143 #define TDCTL_SIZE2 0x003ff800 /* Size of buffer 2 */ 144 #define TDCTL_SIZE2_SHIFT 11 145 146 #define TDCTL_ER 0x02000000 /* End of Ring */ 147 #define TDCTL_CH 0x01000000 /* Second Address Chained */ 148 149 /* 150 * Descriptor Control bits for Transmit Descriptor. 151 */ 152 #define TDCTL_Tx_IC 0x80000000 /* Interrupt on Completion */ 153 #define TDCTL_Tx_LS 0x40000000 /* Last Segment */ 154 #define TDCTL_Tx_FS 0x20000000 /* First Segment */ 155 #define TDCTL_Tx_FT1 0x10000000 /* Filtering Type 1 */ 156 #define TDCTL_Tx_SET 0x08000000 /* Setup Packet */ 157 #define TDCTL_Tx_AC 0x04000000 /* Add CRC Disable */ 158 #define TDCTL_Tx_DPD 0x00800000 /* Disabled Padding */ 159 #define TDCTL_Tx_FT0 0x00400000 /* Filtering Type 0 */ 160 161 /* 162 * The Tulip filter is programmed by "transmitting" a Setup Packet 163 * (indicated by TDCTL_Tx_SET). The filtering type is indicated 164 * as follows: 165 * 166 * FT1 FT0 Description 167 * --- --- ----------- 168 * 0 0 Perfect Filtering: The Tulip interprets the 169 * descriptor buffer as a table of 16 MAC addresses 170 * that the Tulip should receive. 171 * 172 * 0 1 Hash Filtering: The Tulip interprets the 173 * descriptor buffer as a 512-bit hash table 174 * plus one perfect address. If the incoming 175 * address is Multicast, the hash table filters 176 * the address, else the address is filtered by 177 * the perfect address. 178 * 179 * 1 0 Inverse Filtering: Like Perfect Filtering, except 180 * the table is addresses that the Tulip does NOT 181 * receive. 182 * 183 * 1 1 Hash-only Filtering: Like Hash Filtering, but 184 * physical addresses are matched by the hash table 185 * as well, and not by matching a single perfect 186 * address. 187 * 188 * A Setup Packet must always be 192 bytes long. The Tulip can store 189 * 16 MAC addresses. If not all 16 are specified in Perfect Filtering 190 * or Inverse Filtering mode, then unused entries should duplicate 191 * one of the valid entries. 192 */ 193 #define TDCTL_Tx_FT_PERFECT 0 194 #define TDCTL_Tx_FT_HASH TDCTL_Tx_FT0 195 #define TDCTL_Tx_FT_INVERSE TDCTL_Tx_FT1 196 #define TDCTL_Tx_FT_HASHONLY (TDCTL_Tx_FT1|TDCTL_Tx_FT0) 197 198 #define TULIP_SETUP_PACKET_LEN 192 199 #define TULIP_MAXADDRS 16 200 #define TULIP_MCHASHSIZE 512 201 202 /* 203 * Maximum size of a Tulip Ethernet Address ROM or SROM. 204 */ 205 #define TULIP_MAX_ROM_SIZE 128 206 207 /* 208 * Format of the standard Tulip SROM information: 209 * 210 * Byte offset Size Usage 211 * 0 18 reserved 212 * 18 1 SROM Format Version 213 * 19 1 Chip Count 214 * 20 6 IEEE Network Address 215 * 26 1 Chip 0 Device Number 216 * 27 2 Chip 0 Info Leaf Offset 217 * 29 1 Chip 1 Device Number 218 * 30 2 Chip 1 Info Leaf Offset 219 * 32 1 Chip 2 Device Number 220 * 33 2 Chip 2 Info Leaf Offset 221 * ... 1 Chip n Device Number 222 * ... 2 Chip n Info Leaf Offset 223 * ... ... ... 224 * Chip Info Leaf Information 225 * ... 226 * ... 227 * ... 228 * 126 2 CRC32 checksum 229 */ 230 #define TULIP_ROM_SROM_FORMAT_VERION 18 /* B */ 231 #define TULIP_ROM_CHIP_COUNT 19 /* B */ 232 #define TULIP_ROM_IEEE_NETWORK_ADDRESS 20 233 #define TULIP_ROM_CHIPn_DEVICE_NUMBER(n) (26 + ((n) * 3))/* B */ 234 #define TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(n) (27 + ((n) * 3))/* W */ 235 #define TULIP_ROM_CRC32_CHECKSUM 126 /* W */ 236 237 #define TULIP_ROM_IL_SELECT_CONN_TYPE 0 /* W */ 238 #define TULIP_ROM_IL_MEDIA_COUNT 2 /* B */ 239 #define TULIP_ROM_IL_MEDIAn_BLOCK_BASE 3 240 241 #define SELECT_CONN_TYPE_TP 0x0000 242 #define SELECT_CONN_TYPE_TP_AUTONEG 0x0100 243 #define SELECT_CONN_TYPE_TP_FDX 0x0204 244 #define SELECT_CONN_TYPE_TP_NOLINKPASS 0x0400 245 #define SELECT_CONN_TYPE_BNC 0x0001 246 #define SELECT_CONN_TYPE_AUI 0x0002 247 #define SELECT_CONN_TYPE_ASENSE 0x0800 248 #define SELECT_CONN_TYPE_ASENSE_AUTONEG 0x0900 249 250 #define TULIP_ROM_MB_MEDIA_CODE 0x3f 251 #define TULIP_ROM_MB_MEDIA_TP 0x00 252 #define TULIP_ROM_MB_MEDIA_BNC 0x01 253 #define TULIP_ROM_MB_MEDIA_AUI 0x02 254 #define TULIP_ROM_MB_MEDIA_TP_FDX 0x04 255 256 #define TULIP_ROM_MB_EXT 0x40 257 258 #define TULIP_ROM_MB_CSR13 1 /* W */ 259 #define TULIP_ROM_MB_CSR14 3 /* W */ 260 #define TULIP_ROM_MB_CSR15 5 /* W */ 261 262 #define TULIP_ROM_MB_SIZE(mc) (((mc) & TULIP_ROM_MB_EXT) ? 7 : 1) 263 264 #define TULIP_ROM_MB_21140_GPR 0 /* 21140[A] GPR block */ 265 #define TULIP_ROM_MB_21140_MII 1 /* 21140[A] MII block */ 266 #define TULIP_ROM_MB_21142_SIA 2 /* 2114[23] SIA block */ 267 #define TULIP_ROM_MB_21142_MII 3 /* 2114[23] MII block */ 268 #define TULIP_ROM_MB_21143_SYM 4 /* 21143 SYM block */ 269 #define TULIP_ROM_MB_21143_RESET 5 /* 21143 reset block */ 270 271 #define TULIP_ROM_GETW(data, off) ((data)[(off)] | ((data)[(off) + 1]) << 8) 272 273 /* 274 * Tulip control registers. 275 */ 276 277 #define TULIP_CSR0 0x00 278 #define TULIP_CSR1 0x08 279 #define TULIP_CSR2 0x10 280 #define TULIP_CSR3 0x18 281 #define TULIP_CSR4 0x20 282 #define TULIP_CSR5 0x28 283 #define TULIP_CSR6 0x30 284 #define TULIP_CSR7 0x38 285 #define TULIP_CSR8 0x40 286 #define TULIP_CSR9 0x48 287 #define TULIP_CSR10 0x50 288 #define TULIP_CSR11 0x58 289 #define TULIP_CSR12 0x60 290 #define TULIP_CSR13 0x68 291 #define TULIP_CSR14 0x70 292 #define TULIP_CSR15 0x78 293 #define TULIP_CSR16 0x80 294 #define TULIP_CSR17 0x88 295 #define TULIP_CSR18 0x90 296 #define TULIP_CSR19 0x98 297 #define TULIP_CSR20 0xa0 298 299 #define TULIP_CSR_INDEX(csr) ((csr) >> 3) 300 301 /* CSR0 - Bus Mode */ 302 #define CSR_BUSMODE TULIP_CSR0 303 #define BUSMODE_SWR 0x00000001 /* software reset */ 304 #define BUSMODE_BAR 0x00000002 /* bus arbitration */ 305 #define BUSMODE_DSL 0x0000007c /* descriptor skip length */ 306 #define BUSMODE_BLE 0x00000080 /* big endian */ 307 /* programmable burst length */ 308 #define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */ 309 #define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */ 310 #define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */ 311 #define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */ 312 #define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */ 313 #define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */ 314 #define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */ 315 /* cache alignment */ 316 #define BUSMODE_CAL_NONE 0x00000000 /* no alignment */ 317 #define BUSMODE_CAL_8LW 0x00004000 /* 8 longwords */ 318 #define BUSMODE_CAL_16LW 0x00008000 /* 16 longwords */ 319 #define BUSMODE_CAL_32LW 0x0000c000 /* 32 longwords */ 320 #define BUSMODE_DAS 0x00010000 /* diagnostic address space */ 321 /* must be zero on most */ 322 /* transmit auto-poll */ 323 /* 324 * Transmit auto-polling not supported on: 325 * Winbond 89C040F 326 */ 327 #define BUSMODE_TAP_NONE 0x00000000 /* no auto-polling */ 328 #define BUSMODE_TAP_200us 0x00020000 /* 200 uS */ 329 #define BUSMODE_TAP_800us 0x00040000 /* 400 uS */ 330 #define BUSMODE_TAP_1_6ms 0x00060000 /* 1.6 mS */ 331 #define BUSMODE_TAP_12_8us 0x00080000 /* 12.8 uS (21041+) */ 332 #define BUSMODE_TAP_25_6us 0x000a0000 /* 25.6 uS (21041+) */ 333 #define BUSMODE_TAP_51_2us 0x000c0000 /* 51.2 uS (21041+) */ 334 #define BUSMODE_TAP_102_4us 0x000e0000 /* 102.4 uS (21041+) */ 335 #define BUSMODE_DBO 0x00100000 /* desc-only b/e (21041+) */ 336 #define BUSMODE_RME 0x00200000 /* rd/mult enab (21140+) */ 337 #define BUSMODE_WINB_WAIT 0x00200000 /* wait state insertion */ 338 #define BUSMODE_RLE 0x00800000 /* rd/line enab (21140+) */ 339 #define BUSMODE_WLE 0x01000000 /* wt/line enab (21140+) */ 340 #define BUSMODE_PNIC_MBO 0x04000000 /* magic `must be one' bit */ 341 /* on Lite-On PNIC */ 342 343 344 /* CSR1 - Transmit Poll Demand */ 345 #define CSR_TXPOLL TULIP_CSR1 346 #define TXPOLL_TPD 0x00000001 /* transmit poll demand */ 347 348 349 /* CSR2 - Receive Poll Demand */ 350 #define CSR_RXPOLL TULIP_CSR2 351 #define RXPOLL_RPD 0x00000001 /* receive poll demand */ 352 353 354 /* CSR3 - Receive List Base Address */ 355 #define CSR_RXLIST TULIP_CSR3 356 357 /* CSR4 - Transmit List Base Address */ 358 #define CSR_TXLIST TULIP_CSR4 359 360 /* CSR5 - Status */ 361 #define CSR_STATUS TULIP_CSR5 362 #define STATUS_TI 0x00000001 /* transmit interrupt */ 363 #define STATUS_TPS 0x00000002 /* transmit process stopped */ 364 #define STATUS_TU 0x00000004 /* transmit buffer unavail */ 365 #define STATUS_TJT 0x00000008 /* transmit jabber timeout */ 366 #define STATUS_WINB_REI 0x00000008 /* receive early interrupt */ 367 #define STATUS_LNPANC 0x00000010 /* link pass (21041) */ 368 #define STATUS_WINB_RERR 0x00000010 /* receive error */ 369 #define STATUS_UNF 0x00000020 /* transmit underflow */ 370 #define STATUS_RI 0x00000040 /* receive interrupt */ 371 #define STATUS_RU 0x00000080 /* receive buffer unavail */ 372 #define STATUS_RPS 0x00000100 /* receive process stopped */ 373 #define STATUS_RWT 0x00000200 /* receive watchdog timeout */ 374 #define STATUS_AT 0x00000400 /* SIA AUI/TP pin changed 375 (21040) */ 376 #define STATUS_WINB_TEI 0x00000400 /* transmit early interrupt */ 377 #define STATUS_FD 0x00000800 /* full duplex short frame 378 received (21040) */ 379 #define STATUS_TM 0x00000800 /* timer expired (21041) */ 380 #define STATUS_LNF 0x00001000 /* link fail (21040) */ 381 #define STATUS_SE 0x00002000 /* system error */ 382 #define STATUS_ER 0x00004000 /* early receive (21041) */ 383 #define STATUS_AIS 0x00008000 /* abnormal interrupt summary */ 384 #define STATUS_NIS 0x00010000 /* normal interrupt summary */ 385 #define STATUS_RS 0x000e0000 /* receive process state */ 386 #define STATUS_RS_STOPPED 0x00000000 /* Stopped */ 387 #define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive 388 descriptor */ 389 #define STATUS_RS_CHECK 0x00040000 /* Running - check for end 390 of receive */ 391 #define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */ 392 #define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */ 393 #define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive 394 descriptor */ 395 #define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current 396 frame from FIFO */ 397 #define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current 398 frame from FIFO into 399 buffer */ 400 #define STATUS_TS 0x00700000 /* transmit process state */ 401 #define STATUS_TS_STOPPED 0x00000000 /* Stopped */ 402 #define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit 403 descriptor */ 404 #define STATUS_TS_WAIT 0x00200000 /* Running - wait for end 405 of transmission */ 406 #define STATUS_TS_READING 0x00300000 /* Running - read buffer from 407 memory and queue into 408 FIFO */ 409 #define STATUS_TS_RESERVED 0x00400000 /* RESERVED */ 410 #define STATUS_TS_SETUP 0x00500000 /* Running - Setup packet */ 411 #define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */ 412 #define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit 413 descriptor */ 414 #define STATUS_EB 0x03800000 /* error bits */ 415 #define STATUS_EB_PARITY 0x00000000 /* parity errror */ 416 #define STATUS_EB_MABT 0x00800000 /* master abort */ 417 #define STATUS_EB_TABT 0x01000000 /* target abort */ 418 #define STATUS_PNIC_TXABORT 0x04000000 /* transmit aborted */ 419 420 421 /* CSR6 - Operation Mode */ 422 #define CSR_OPMODE TULIP_CSR6 423 #define OPMODE_HP 0x00000001 /* hash/perfect mode (ro) */ 424 #define OPMODE_SR 0x00000002 /* start receive */ 425 #define OPMODE_HO 0x00000004 /* hash only mode (ro) */ 426 #define OPMODE_PB 0x00000008 /* pass bad frames */ 427 #define OPMODE_WINB_APP 0x00000008 /* accept all physcal packet */ 428 #define OPMODE_IF 0x00000010 /* inverse filter mode (ro) */ 429 #define OPMODE_WINB_AMP 0x00000010 /* accept multicast packet */ 430 #define OPMODE_SB 0x00000020 /* start backoff counter */ 431 #define OPMODE_WINB_ABP 0x00000020 /* accept broadcast packet */ 432 #define OPMODE_PR 0x00000040 /* promiscuous mode */ 433 #define OPMODE_WINB_ARP 0x00000040 /* accept runt packet */ 434 #define OPMODE_PM 0x00000080 /* pass all multicast */ 435 #define OPMODE_WINB_AEP 0x00000080 /* accept error packet */ 436 #define OPMODE_FKD 0x00000100 /* flaky oscillator disable */ 437 #define OPMODE_FD 0x00000200 /* full-duplex mode */ 438 #define OPMODE_OM 0x00000c00 /* operating mode */ 439 #define OPMODE_OM_NORMAL 0x00000000 /* normal mode */ 440 #define OPMODE_OM_INTLOOP 0x00000400 /* internal loopback */ 441 #define OPMODE_OM_EXTLOOP 0x00000800 /* external loopback */ 442 #define OPMODE_FC 0x00001000 /* force collision */ 443 #define OPMODE_ST 0x00002000 /* start transmitter */ 444 #define OPMODE_TR 0x0000c000 /* threshold control */ 445 #define OPMODE_TR_72 0x00000000 /* 72 bytes */ 446 #define OPMODE_TR_96 0x00004000 /* 96 bytes */ 447 #define OPMODE_TR_128 0x00008000 /* 128 bytes */ 448 #define OPMODE_TR_160 0x0000c000 /* 160 bytes */ 449 #define OPMODE_WINB_TTH 0x001fc000 /* transmit threshold */ 450 #define OPMODE_WINB_TTH_SHIFT 14 451 #define OPMODE_BP 0x00010000 /* backpressure enable */ 452 #define OPMODE_CA 0x00020000 /* capture effect enable */ 453 #define OPMODE_PNIC_TBEN 0x00020000 /* Tx backoff offset enable */ 454 #define OPMODE_PS 0x00040000 /* port select: 455 1 = MII/SYM, 0 = SRL 456 (21140) */ 457 #define OPMODE_HBD 0x00080000 /* heartbeat disable: 458 set in MII/SYM 100mbps, 459 set according to PHY 460 in MII 10mbps mode 461 (21140) */ 462 #define OPMODE_PNIC_IT 0x00100000 /* immediate transmit */ 463 #define OPMODE_SF 0x00200000 /* store and forward mode 464 (21140) */ 465 #define OPMODE_WINB_REIT 0x1fe00000 /* receive eartly intr thresh */ 466 #define OPMODE_WINB_REIT_SHIFT 21 467 #define OPMODE_TTM 0x00400000 /* Transmit Threshold Mode: 468 1 = 10mbps, 0 = 100mbps 469 (21140) */ 470 #define OPMODE_PCS 0x00800000 /* PCS function (21140) */ 471 #define OPMODE_SCR 0x01000000 /* scrambler mode (21140) */ 472 #define OPMODE_MBO 0x02000000 /* must be one (21140) */ 473 #define OPMODE_PNIC_DRC 0x20000000 /* don't include CRC in Rx 474 frames (PNIC) */ 475 #define OPMODE_WINB_FES 0x20000000 /* fast ethernet select */ 476 #define OPMODE_RA 0x40000000 /* receive all (21140) */ 477 #define OPMODE_PNIC_EED 0x40000000 /* 1 == ext, 0 == int ENDEC 478 (PNIC) */ 479 #define OPMODE_WINB_TEIO 0x40000000 /* transmit early intr on */ 480 #define OPMODE_SC 0x80000000 /* special capture effect 481 enable (21041+) */ 482 #define OPMODE_WINB_REIO 0x80000000 /* receive early intr on */ 483 484 /* CSR7 - Interrupt Enable */ 485 #define CSR_INTEN TULIP_CSR7 486 /* See bits for CSR5 -- Status */ 487 488 489 /* CSR8 - Missed Frames */ 490 #define CSR_MISSED TULIP_CSR8 491 #define MISSED_MFC 0x0000ffff /* missed packet count */ 492 #define MISSED_MFO 0x00010000 /* missed packet count 493 overflowed */ 494 #define MISSED_FOC 0x0ffe0000 /* fifo overflow counter 495 (21140) */ 496 #define MISSED_OCO 0x10000000 /* overflow counter overflowed 497 (21140) */ 498 499 #define MISSED_GETMFC(x) ((x) & MISSED_MFC) 500 #define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 17) 501 502 503 /* CSR9 - MII, SROM, Boot ROM, Ethernet Address ROM register. */ 504 #define CSR_MIIROM TULIP_CSR9 505 #define MIIROM_DATA 0x000000ff /* byte of data from 506 Ethernet Address ROM 507 (21040), byte of data 508 to/from Boot ROM (21041+) */ 509 #define MIIROM_SROMCS 0x00000001 /* SROM chip select */ 510 #define MIIROM_SROMSK 0x00000002 /* SROM clock */ 511 #define MIIROM_SROMDI 0x00000004 /* SROM data in (to) */ 512 #define MIIROM_SROMDO 0x00000008 /* SROM data out (from) */ 513 #define MIIROM_REG 0x00000400 /* external register select */ 514 #define MIIROM_SR 0x00000800 /* SROM select */ 515 #define MIIROM_BR 0x00001000 /* boot ROM select */ 516 #define MIIROM_WR 0x00002000 /* write to boot ROM */ 517 #define MIIROM_RD 0x00004000 /* read from boot ROM */ 518 #define MIIROM_MOD 0x00008000 /* mode select (ro) (21041) */ 519 #define MIIROM_MDC 0x00010000 /* MII clock */ 520 #define MIIROM_MDO 0x00020000 /* MII data out */ 521 #define MIIROM_MIIDIR 0x00040000 /* MII direction mode 522 1 = PHY in read, 523 0 = PHY in write */ 524 #define MIIROM_MDI 0x00080000 /* MII data in */ 525 #define MIIROM_DN 0x80000000 /* data not valid (21040) */ 526 527 /* SROM opcodes */ 528 #define TULIP_SROM_OPC_ERASE 0x04 529 #define TULIP_SROM_OPC_WRITE 0x05 530 #define TULIP_SROM_OPC_READ 0x06 531 532 /* The Lite-On PNIC does this completely differently */ 533 #define PNIC_MIIROM_DATA 0x0000ffff /* mask of data bits ??? */ 534 #define PNIC_MIIROM_BUSY 0x80000000 /* EEPROM is busy */ 535 536 537 /* CSR10 - Boot ROM address register (21041+). */ 538 #define CSR_ROMADDR TULIP_CSR10 539 #define ROMADDR_MASK 0x000003ff /* boot rom address */ 540 541 542 /* CSR11 - General Purpose Timer (21041+). */ 543 #define CSR_GPT TULIP_CSR11 544 #define GPT_VALUE 0x0000ffff /* timer value */ 545 #define GPT_CON 0x00010000 /* continuous mode */ 546 547 548 /* CSR12 - SIA Status Register (21040, 21041). */ 549 #define CSR_SIASTAT TULIP_CSR12 550 #define SIASTAT_PAUI 0x00000001 /* pin AUI/TP indication 551 (21040) */ 552 #define SIASTAT_NCR 0x00000002 /* network connection error */ 553 #define SIASTAT_LKF 0x00000004 /* link fail status */ 554 #define SIASTAT_APS 0x00000008 /* auto polarity status */ 555 #define SIASTAT_DSD 0x00000010 /* PLL self test done */ 556 #define SIASTAT_DSP 0x00000020 /* PLL self test pass */ 557 #define SIASTAT_DAZ 0x00000040 /* PLL all zero */ 558 #define SIASTAT_DAO 0x00000080 /* PLL all one */ 559 #define SIASTAT_SRA 0x00000100 /* selected port receive 560 activity (21041) */ 561 #define SIASTAT_NRA 0x00000200 /* non-selected port 562 receive activity (21041) */ 563 #define SIASTAT_NSN 0x00000400 /* non-stable NLPs detected 564 (21041) */ 565 #define SIASTAT_TRF 0x00000800 /* transmit remote fault 566 (21041) */ 567 #define SIASTAT_ANS 0x00007000 /* autonegotiation state 568 (21041) */ 569 #define SIASTAT_ANS_DIS 0x00000000 /* disabled */ 570 #define SIASTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 571 #define SIASTAT_ANS_ABD 0x00002000 /* ability detect */ 572 #define SIASTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 573 #define SIASTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 574 #define SIASTAT_ANS_FPLGOOD 0x00005000 /* FLP link good */ 575 #define SIASTAT_ANS_LINKCHECK 0x00006000 /* link check */ 576 #define SIASTAT_LPN 0x00008000 /* link partner negotiable 577 (21041) */ 578 #define SIASTAT_LPC 0xffff0000 /* link partner code word */ 579 580 #define SIASTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 581 582 583 /* CSR13 - SIA Connectivity Register (21040, 21041). */ 584 #define CSR_SIACONN TULIP_CSR13 585 #define SIACONN_SRL 0x00000001 /* SIA reset */ 586 #define SIACONN_PS 0x00000002 /* pin AUI/TP selection 587 (21040) */ 588 #define SIACONN_CAC 0x00000004 /* CSR autoconfiguration */ 589 #define SIACONN_AUI 0x00000008 /* select AUI (0 = TP) */ 590 #define SIACONN_EDP 0x00000010 /* SIA PLL external input 591 enable (21040) */ 592 #define SIACONN_ENI 0x00000020 /* encoder input multiplexer 593 (21040) */ 594 #define SIACONN_SIM 0x00000040 /* serial interface input 595 multiplexer (21040) */ 596 #define SIACONN_ASE 0x00000080 /* APLL start enable 597 (21040) */ 598 #define SIACONN_SEL 0x00000f00 /* external port output 599 multiplexer select 600 (21040) */ 601 #define SIACONN_IE 0x00001000 /* input enable (21040) */ 602 #define SIACONN_OE1_3 0x00002000 /* output enable 1, 3 603 (21040) */ 604 #define SIACONN_OE2_4 0x00004000 /* output enable 2, 4 605 (21040) */ 606 #define SIACONN_OE5_6_7 0x00008000 /* output enable 5, 6, 7 607 (21040) */ 608 #define SIACONN_SDM 0x0000ef00 /* SIA diagnostic mode; 609 always set to this value 610 for normal operation 611 (21041) */ 612 613 614 /* CSR14 - SIA Transmit Receive Register (21040, 21041). */ 615 #define CSR_SIATXRX TULIP_CSR14 616 #define SIATXRX_ECEN 0x00000001 /* encoder enable */ 617 #define SIATXRX_LBK 0x00000002 /* loopback enable */ 618 #define SIATXRX_DREN 0x00000004 /* driver enable */ 619 #define SIATXRX_LSE 0x00000008 /* link pulse send enable */ 620 #define SIATXRX_CPEN 0x00000030 /* compensation enable */ 621 #define SIATXRX_CPEN_DIS0 0x00000000 /* disabled */ 622 #define SIATXRX_CPEN_DIS1 0x00000010 /* disabled */ 623 #define SIATXRX_CPEN_HIGHPWR 0x00000020 /* high power */ 624 #define SIATXRX_CPEN_NORMAL 0x00000030 /* normal */ 625 #define SIATXRX_MBO 0x00000040 /* must be one (21041 pass 2) */ 626 #define SIATXRX_ANE 0x00000080 /* autonegotiation enable 627 (21041) */ 628 #define SIATXRX_RSQ 0x00000100 /* receive squelch enable */ 629 #define SIATXRX_CSQ 0x00000200 /* collision squelch enable */ 630 #define SIATXRX_CLD 0x00000400 /* collision detect enable */ 631 #define SIATXRX_SQE 0x00000800 /* signal quality generation 632 enable */ 633 #define SIATXRX_LTE 0x00001000 /* link test enable */ 634 #define SIATXRX_APE 0x00002000 /* auto-polarity enable */ 635 #define SIATXRX_SPP 0x00004000 /* set plarity plus */ 636 #define SIATXRX_TAS 0x00008000 /* 10base-T/AUI autosensing 637 enable (21041) */ 638 639 640 /* CSR15 - SIA General Register (21040, 21041). */ 641 #define CSR_SIAGEN TULIP_CSR15 642 #define SIAGEN_JBD 0x00000001 /* jabber disable */ 643 #define SIAGEN_HUJ 0x00000002 /* host unjab */ 644 #define SIAGEN_JCK 0x00000004 /* jabber clock */ 645 #define SIAGEN_ABM 0x00000008 /* BNC select (21041) */ 646 #define SIAGEN_RWD 0x00000010 /* receive watchdog disable */ 647 #define SIAGEN_RWR 0x00000020 /* receive watchdog release */ 648 #define SIAGEN_LE1 0x00000040 /* LED 1 enable (21041) */ 649 #define SIAGEN_LV1 0x00000080 /* LED 1 value (21041) */ 650 #define SIAGEN_TSCK 0x00000100 /* test clock */ 651 #define SIAGEN_FUSQ 0x00000200 /* force unsquelch */ 652 #define SIAGEN_FLF 0x00000400 /* force link fail */ 653 #define SIAGEN_LSD 0x00000800 /* LED stretch disable 654 (21041) */ 655 #define SIAGEN_DPST 0x00001000 /* PLL self-test start */ 656 #define SIAGEN_FRL 0x00002000 /* force receiver low */ 657 #define SIAGEN_LE2 0x00004000 /* LED 2 enable (21041) */ 658 #define SIAGEN_LV2 0x00008000 /* LED 2 value (21041) */ 659 660 661 /* CSR12 - General Purpose Port (21140+). */ 662 #define CSR_GPP TULIP_CSR12 663 #define GPP_MD 0x000000ff /* general purpose mode/data */ 664 #define GPP_GPC 0x00000100 /* general purpose control */ 665 #define GPP_PNIC_GPD 0x0000000f /* general purpose data */ 666 #define GPP_PNIC_GPC 0x000000f0 /* general purpose control */ 667 668 #define GPP_PNIC_IN(x) (1 << (x)) 669 #define GPP_PNIC_OUT(x, on) (((on) << (x)) | (1 << ((x) + 4))) 670 671 /* 672 * The Lite-On PNIC manual recommends the following for the General Purpose 673 * I/O pins: 674 * 675 * 0 Speed Relay 1 == 100mbps 676 * 1 100mbps loopback 1 == loopback 677 * 2 BNC DC-DC converter 1 == select BNC 678 * 3 Link 100 1 == 100baseTX link status 679 */ 680 #define GPP_PNIC_PIN_SPEED_RLY 0 681 #define GPP_PNIC_PIN_100M_LPKB 1 682 #define GPP_PNIC_PIN_BNC_XMER 2 683 #define GPP_PNIC_PIN_LNK100X 3 684 685 686 /* CSR15 - Watchdog timer (21140+). */ 687 #define CSR_WATCHDOG TULIP_CSR15 688 #define WATCHDOG_JBD 0x00000001 /* jabber disable */ 689 #define WATCHDOG_HUJ 0x00000002 /* host unjab */ 690 #define WATCHDOG_JCK 0x00000004 /* jabber clock */ 691 #define WATCHDOG_RWD 0x00000010 /* receive watchdog disable */ 692 #define WATCHDOG_RWR 0x00000020 /* receive watchdog release */ 693 694 695 /* 696 * Digital Semiconductor 21040 registers. 697 */ 698 699 /* CSR11 - Full Duplex Register */ 700 #define CSR_21040_FDX TULIP_CSR11 701 #define FDX21040_FDXACV 0x0000ffff /* full duplex 702 autoconfiguration value */ 703 704 705 /* SIA configuration for 10base-T (from the 21040 manual) */ 706 #define SIACONN_21040_10BASET 0x0000ef01 707 #define SIATXRX_21040_10BASET 0x0000ffff 708 #define SIAGEN_21040_10BASET 0x00000000 709 710 711 /* SIA configuration for 10base-T full-duplex (from the 21040 manual) */ 712 #define SIACONN_21040_10BASET_FDX 0x0000ef01 713 #define SIATXRX_21040_10BASET_FDX 0x0000fffd 714 #define SIAGEN_21040_10BASET_FDX 0x00000000 715 716 717 /* SIA configuration for 10base-5 (from the 21040 manual) */ 718 #define SIACONN_21040_AUI 0x0000ef09 719 #define SIATXRX_21040_AUI 0x00000705 720 #define SIAGEN_21040_AUI 0x00000006 721 722 723 /* SIA configuration for External SIA (from the 21040 manual) */ 724 #define SIACONN_21040_EXTSIA 0x00003041 725 #define SIATXRX_21040_EXTSIA 0x00000000 726 #define SIAGEN_21040_EXTSIA 0x00000006 727 728 729 /* 730 * Digital Semiconductor 21041 registers. 731 */ 732 733 /* SIA configuration for 10base-T (from the 21041 manual) */ 734 #define SIACONN_21041_10BASET 0x0000ef01 735 #define SIATXRX_21041_10BASET 0x0000ff3f 736 #define SIAGEN_21041_10BASET 0x00000000 737 738 #define SIACONN_21041P2_10BASET SIACONN_21041_10BASET 739 #define SIATXRX_21041P2_10BASET 0x0000ffff 740 #define SIAGEN_21041P2_10BASET SIAGEN_21041_10BASET 741 742 743 /* SIA configuration for 10base-T full-duplex (from the 21041 manual) */ 744 #define SIACONN_21041_10BASET_FDX 0x0000ef01 745 #define SIATXRX_21041_10BASET_FDX 0x0000ff3d 746 #define SIAGEN_21041_10BASET_FDX 0x00000000 747 748 #define SIACONN_21041P2_10BASET_FDX SIACONN_21041_10BASET_FDX 749 #define SIATXRX_21041P2_10BASET_FDX 0x0000ffff 750 #define SIAGEN_21041P2_10BASET_FDX SIAGEN_21041_10BASET_FDX 751 752 753 /* SIA configuration for 10base-5 (from the 21041 manual) */ 754 #define SIACONN_21041_AUI 0x0000ef09 755 #define SIATXRX_21041_AUI 0x0000f73d 756 #define SIAGEN_21041_AUI 0x0000000e 757 758 #define SIACONN_21041P2_AUI SIACONN_21041_AUI 759 #define SIATXRX_21041P2_AUI 0x0000f7fd 760 #define SIAGEN_21041P2_AUI SIAGEN_21041_AUI 761 762 763 /* SIA configuration for 10base-2 (from the 21041 manual) */ 764 #define SIACONN_21041_BNC 0x0000ef09 765 #define SIATXRX_21041_BNC 0x0000f73d 766 #define SIAGEN_21041_BNC 0x00000006 767 768 #define SIACONN_21041P2_BNC SIACONN_21041_BNC 769 #define SIATXRX_21041P2_BNC 0x0000f7fd 770 #define SIAGEN_21041P2_BNC SIAGEN_21041_BNC 771 772 773 /* 774 * Digital Semiconductor 21142/21143 registers. 775 */ 776 777 /* XXX */ 778 779 /* 780 * Lite-On 82C168/82C169 registers. 781 */ 782 783 /* ENDEC General Register */ 784 #define CSR_PNIC_ENDEC 0x78 785 #define PNIC_ENDEC_JDIS 0x00000001 /* jabber disable */ 786 787 /* SROM Power Register */ 788 #define CSR_PNIC_SROMPWR 0x90 789 #define PNIC_SROMPWR_MRLE 0x00000001 /* Memory-Read-Line enable */ 790 #define PNIC_SROMPWR_CB 0x00000002 /* cache boundary alignment 791 burst type; 1 == burst to 792 boundary, 0 == single-cycle 793 to boundary */ 794 795 /* SROM Control Register */ 796 #define CSR_PNIC_SROMCTL 0x98 797 #define PNIC_SROMCTL_addr 0x0000003f /* mask of address bits */ 798 /* XXX THESE ARE WRONG ACCORDING TO THE MANUAL! */ 799 #define PNIC_SROMCTL_READ 0x00000600 /* read command */ 800 801 /* MII Access Register */ 802 #define CSR_PNIC_MII 0xa0 803 #define PNIC_MII_DATA 0x0000ffff /* mask of data bits */ 804 #define PNIC_MII_REG 0x007c0000 /* register mask */ 805 #define PNIC_MII_REGSHIFT 18 806 #define PNIC_MII_PHY 0x0f800000 /* phy mask */ 807 #define PNIC_MII_PHYSHIFT 23 808 #define PNIC_MII_OPCODE 0x30000000 /* opcode mask */ 809 #define PNIC_MII_RESERVED 0x00020000 /* must be one/must be zero; 810 2 bits are described here */ 811 #define PNIC_MII_MBO 0x40000000 /* must be one */ 812 #define PNIC_MII_BUSY 0x80000000 /* MII is busy */ 813 814 #define PNIC_MII_WRITE 0x10000000 /* write PHY command */ 815 #define PNIC_MII_READ 0x20000000 /* read PHY command */ 816 817 /* NWAY Register */ 818 #define CSR_PNIC_NWAY 0xb8 819 #define PNIC_NWAY_RS 0x00000001 /* reset NWay block */ 820 #define PNIC_NWAY_PD 0x00000002 /* power down NWay block */ 821 #define PNIC_NWAY_BX 0x00000004 /* bypass transciever */ 822 #define PNIC_NWAY_LC 0x00000008 /* AUI low current mode */ 823 #define PNIC_NWAY_UV 0x00000010 /* low squelch voltage */ 824 #define PNIC_NWAY_DX 0x00000020 /* disable TP pol. correction */ 825 #define PNIC_NWAY_TW 0x00000040 /* select TP (0 == AUI) */ 826 #define PNIC_NWAY_AF 0x00000080 /* AUI full/half step input 827 voltage */ 828 #define PNIC_NWAY_FD 0x00000100 /* full duplex mode */ 829 #define PNIC_NWAY_DL 0x00000200 /* disable link integrity 830 test */ 831 #define PNIC_NWAY_DM 0x00000400 /* disable AUI/TP autodetect */ 832 #define PNIC_NWAY_100 0x00000800 /* 1 == 100mbps, 0 == 10mbps */ 833 #define PNIC_NWAY_NW 0x00001000 /* enable NWay block */ 834 #define PNIC_NWAY_CAP10T 0x00002000 /* adv. 10baseT */ 835 #define PNIC_NWAY_CAP10TFDX 0x00004000 /* adv. 10baseT-FDX */ 836 #define PNIC_NWAY_CAP100TXFDX 0x00008000 /* adv. 100baseTX-FDX */ 837 #define PNIC_NWAY_CAP100TX 0x00010000 /* adv. 100baseTX */ 838 #define PNIC_NWAY_CAP100T4 0x00020000 /* adv. 100base-T4 */ 839 #define PNIC_NWAY_RN 0x02000000 /* re-negotiate enable */ 840 #define PNIC_NWAY_RF 0x04000000 /* remote fault detected */ 841 #define PNIC_NWAY_LPAR10T 0x08000000 /* link part. 10baseT */ 842 #define PNIC_NWAY_LPAR10TFDX 0x10000000 /* link part. 10baseT-FDX */ 843 #define PNIC_NWAY_LPAR100TXFDX 0x20000000 /* link part. 100baseTX-FDX */ 844 #define PNIC_NWAY_LPAR100TX 0x40000000 /* link part. 100baseTX */ 845 #define PNIC_NWAY_LPAR100T4 0x80000000 /* link part. 100base-T4 */ 846 #define PNIC_NWAY_LPAR_MASK 0xf8000000 847 848 849 /* 850 * Macronix 98713, 98713A, 98715, 98715A, 98725 registers. 851 */ 852 853 /* CSR12 - 10base-T Status Port (similar to SIASTAT) */ 854 #define CSR_PMAC_10TSTAT TULIP_CSR12 855 #define PMAC_10TSTAT_LS100 0x00000002 /* link status 100TX 856 0 = link up */ 857 #define PMAC_10TSTAT_LS10 0x00000004 /* link status 10T 858 0 = link up */ 859 #define PMAC_10TSTAT_APS 0x00000008 /* auto polarity status */ 860 #define PMAC_10TSTAT_TRF 0x00000800 /* transmit remote fault 861 (21041) */ 862 #define PMAC_10TSTAT_ANS 0x00007000 /* autonegotiation state 863 (21041) */ 864 #define PMAC_10TSTAT_ANS_DIS 0x00000000 /* disabled */ 865 #define PMAC_10TSTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ 866 #define PMAC_10TSTAT_ANS_ABD 0x00002000 /* ability detect */ 867 #define PMAC_10TSTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ 868 #define PMAC_10TSTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ 869 #define PMAC_10TSTAT_ANS_FPLGOOD 0x00005000 /* FLP link good */ 870 #define PMAC_10TSTAT_ANS_LINKCHECK 0x00006000 /* link check */ 871 #define PMAC_10TSTAT_LPN 0x00008000 /* link partner negotiable 872 (21041) */ 873 #define PMAC_10TSTAT_LPC 0xffff0000 /* link partner code word */ 874 875 #define PMAC_10TSTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) 876 877 878 /* CSR13 - NWAY Reset Register */ 879 #define CSR_PMAC_NWAYRESET TULIP_CSR13 880 #define PMAC_NWAYRESET_RESET 0x00000000 /* NWAY reset */ 881 882 883 /* CSR14 - 10base-T Control Port */ 884 #define CSR_PMAC_10TCTL TULIP_CSR14 885 #define PMAC_10TCTL_LBK 0x00000002 /* loopback */ 886 #define PMAC_10TCTL_PWD10 0x00000004 /* power down 10base-T */ 887 #define PMAC_10TCTL_HDE 0x00000040 /* half-duplex enable */ 888 #define PMAC_10TCTL_ANE 0x00000080 /* autonegotiation enable */ 889 #define PMAC_10TCTL_RSQ 0x00000100 /* receive squelch enable */ 890 #define PMAC_10TCTL_LTE 0x00001000 /* link test enable */ 891 #define PMAC_10TCTL_TXH 0x00010000 /* adv. 100tx */ 892 #define PMAC_10TCTL_TXF 0x00020000 /* adv. 100tx-fdx */ 893 #define PMAC_10TCTL_T4 0x00040000 /* adv. 100t4 */ 894 895 896 /* CSR16 - Test Operation Register (a.k.a. Magic Packet Register) */ 897 #define CSR_PMAC_TOR TULIP_CSR16 898 #define PMAC_TOR_98713 0x0F370000 899 #define PMAC_TOR_98715 0x0B3C0000 900 901 902 /* CSR20 - NWAY Status */ 903 #define CSR_PMAC_NWAYSTAT TULIP_CSR20 904 #define PMAC_NWAYSTAT_10TXH 0x08000000 /* 10t accepted */ 905 #define PMAC_NWAYSTAT_10TXF 0x10000000 /* 10t-fdx accepted */ 906 #define PMAC_NWAYSTAT_100TXH 0x20000000 /* 100tx accepted */ 907 #define PMAC_NWAYSTAT_100TXF 0x40000000 /* 100tx-fdx accepted */ 908 #define PMAC_NWAYSTAT_T4 0x80000000 /* 100t4 accepted */ 909 910 911 /* 912 * Winbond 89C840F registers. 913 */ 914 915 /* CSR12 - Current Receive Descriptor Register */ 916 #define CSR_WINB_CRDAR TULIP_CSR12 917 918 919 /* CSR13 - Current Receive Buffer Register */ 920 #define CSR_WINB_CCRBAR TULIP_CSR13 921 922 923 /* CSR14 - Multicast Address Register 0 */ 924 #define CSR_WINB_CMA0 TULIP_CSR14 925 926 927 /* CSR15 - Multicast Address Register 1 */ 928 #define CSR_WINB_CMA1 TULIP_CSR15 929 930 931 /* CSR16 - Physical Address Register 0 */ 932 #define CSR_WINB_CPA0 TULIP_CSR16 933 934 935 /* CSR17 - Physical Address Register 1 */ 936 #define CSR_WINB_CPA1 TULIP_CSR17 937 938 939 /* CSR18 - Boot ROM Size Register */ 940 #define CSR_WINB_CBRCR TULIP_CSR18 941 #define WINB_CBRCR_NONE 0x00000000 /* no boot rom */ 942 /* 0x00000001 also no boot rom */ 943 #define WINB_CBRCR_8K 0x00000002 /* 8k */ 944 #define WINB_CBRCR_16K 0x00000003 /* 16k */ 945 #define WINB_CBRCR_32K 0x00000004 /* 32k */ 946 #define WINB_CBRCR_64K 0x00000005 /* 64k */ 947 #define WINB_CBRCR_128K 0x00000006 /* 128k */ 948 #define WINB_CBRCR_256K 0x00000007 949 950 951 /* CSR19 - Current Transmit Descriptor Register */ 952 #define CSR_WINB_CTDAR TULIP_CSR19 953 954 955 /* CSR20 - Current Transmit Buffer Register */ 956 #define CSR_WINB_CTBAR TULIP_CSR20 957 958 #endif /* _DEV_IC_TULIPREG_H_ */ 959
Indexes created Mon Sep 29 21:09:56 GMT 2025