ug.c revision 1.1
1 /* $NetBSD: ug.c,v 1.1 2007/05/08 16:48:38 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Mihai Chelaru <kefren (at) netbsd.ro> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/proc.h> 34 #include <sys/device.h> 35 #include <sys/malloc.h> 36 #include <sys/errno.h> 37 #include <sys/conf.h> 38 #include <sys/envsys.h> 39 #include <sys/time.h> 40 41 #include <machine/bus.h> 42 #include <machine/intr.h> 43 44 #include <dev/isa/isareg.h> 45 #include <dev/isa/isavar.h> 46 47 #include <dev/sysmon/sysmonvar.h> 48 49 #include <dev/ic/ugreg.h> 50 #include <dev/ic/ugvar.h> 51 52 uint8_t ug_ver; 53 54 /* 55 * Imported from linux driver 56 */ 57 58 struct ug2_motherboard_info ug2_mb[] = { 59 { 0x000C, "unknown. Please send-pr(1)", { 60 { "CPU Core", 0, 0, 10, 1, 0 }, 61 { "DDR", 1, 0, 10, 1, 0 }, 62 { "DDR VTT", 2, 0, 10, 1, 0 }, 63 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 64 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 65 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 66 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 67 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 68 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 69 { "ATX +5V", 9, 0, 30, 1, 0 }, 70 { "+3.3V", 10, 0, 20, 1, 0 }, 71 { "5VSB", 11, 0, 30, 1, 0 }, 72 { "CPU", 24, 1, 1, 1, 0 }, 73 { "System", 25, 1, 1, 1, 0 }, 74 { "PWM", 26, 1, 1, 1, 0 }, 75 { "CPU Fan", 32, 2, 60, 1, 0 }, 76 { "NB Fan", 33, 2, 60, 1, 0 }, 77 { "SYS FAN", 34, 2, 60, 1, 0 }, 78 { "AUX1 Fan", 35, 2, 60, 1, 0 }, 79 { NULL, 0, 0, 0, 0, 0 } } 80 }, 81 { 0x000D, "Abit AW8", { 82 { "CPU Core", 0, 0, 10, 1, 0 }, 83 { "DDR", 1, 0, 10, 1, 0 }, 84 { "DDR VTT", 2, 0, 10, 1, 0 }, 85 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 86 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 87 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 88 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 89 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 90 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 91 { "ATX +5V", 9, 0, 30, 1, 0 }, 92 { "+3.3V", 10, 0, 20, 1, 0 }, 93 { "5VSB", 11, 0, 30, 1, 0 }, 94 { "CPU", 24, 1, 1, 1, 0 }, 95 { "System", 25, 1, 1, 1, 0 }, 96 { "PWM1", 26, 1, 1, 1, 0 }, 97 { "PWM2", 27, 1, 1, 1, 0 }, 98 { "PWM3", 28, 1, 1, 1, 0 }, 99 { "PWM4", 29, 1, 1, 1, 0 }, 100 { "CPU Fan", 32, 2, 60, 1, 0 }, 101 { "NB Fan", 33, 2, 60, 1, 0 }, 102 { "SYS Fan", 34, 2, 60, 1, 0 }, 103 { "AUX1 Fan", 35, 2, 60, 1, 0 }, 104 { "AUX2 Fan", 36, 2, 60, 1, 0 }, 105 { "AUX3 Fan", 37, 2, 60, 1, 0 }, 106 { "AUX4 Fan", 38, 2, 60, 1, 0 }, 107 { "AUX5 Fan", 39, 2, 60, 1, 0 }, 108 { NULL, 0, 0, 0, 0, 0 } } 109 }, 110 { 0x000E, "Abit AL8", { 111 { "CPU Core", 0, 0, 10, 1, 0 }, 112 { "DDR", 1, 0, 10, 1, 0 }, 113 { "DDR VTT", 2, 0, 10, 1, 0 }, 114 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 115 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 116 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 117 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 118 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 119 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 120 { "ATX +5V", 9, 0, 30, 1, 0 }, 121 { "+3.3V", 10, 0, 20, 1, 0 }, 122 { "5VSB", 11, 0, 30, 1, 0 }, 123 { "CPU", 24, 1, 1, 1, 0 }, 124 { "System", 25, 1, 1, 1, 0 }, 125 { "PWM", 26, 1, 1, 1, 0 }, 126 { "CPU Fan", 32, 2, 60, 1, 0 }, 127 { "NB Fan", 33, 2, 60, 1, 0 }, 128 { "SYS Fan", 34, 2, 60, 1, 0 }, 129 { NULL, 0, 0, 0, 0, 0 } } 130 }, 131 { 0x000F, "unknown. Please send-pr(1)", { 132 { "CPU Core", 0, 0, 10, 1, 0 }, 133 { "DDR", 1, 0, 10, 1, 0 }, 134 { "DDR VTT", 2, 0, 10, 1, 0 }, 135 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 136 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 137 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 138 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 139 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 140 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 141 { "ATX +5V", 9, 0, 30, 1, 0 }, 142 { "+3.3V", 10, 0, 20, 1, 0 }, 143 { "5VSB", 11, 0, 30, 1, 0 }, 144 { "CPU", 24, 1, 1, 1, 0 }, 145 { "System", 25, 1, 1, 1, 0 }, 146 { "PWM", 26, 1, 1, 1, 0 }, 147 { "CPU Fan", 32, 2, 60, 1, 0 }, 148 { "NB Fan", 33, 2, 60, 1, 0 }, 149 { "SYS Fan", 34, 2, 60, 1, 0 }, 150 { NULL, 0, 0, 0, 0, 0 } } 151 }, 152 { 0x0010, "Abit NI8 SLI GR", { 153 { "CPU Core", 0, 0, 10, 1, 0 }, 154 { "DDR", 1, 0, 10, 1, 0 }, 155 { "DDR VTT", 2, 0, 10, 1, 0 }, 156 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 157 { "NB 1.4V", 4, 0, 10, 1, 0 }, 158 { "SB 1.5V", 6, 0, 10, 1, 0 }, 159 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 160 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 161 { "ATX +5V", 9, 0, 30, 1, 0 }, 162 { "+3.3V", 10, 0, 20, 1, 0 }, 163 { "5VSB", 11, 0, 30, 1, 0 }, 164 { "CPU", 24, 1, 1, 1, 0 }, 165 { "SYS", 25, 1, 1, 1, 0 }, 166 { "PWM", 26, 1, 1, 1, 0 }, 167 { "CPU Fan", 32, 2, 60, 1, 0 }, 168 { "NB Fan", 33, 2, 60, 1, 0 }, 169 { "SYS Fan", 34, 2, 60, 1, 0 }, 170 { "AUX1 Fan", 35, 2, 60, 1, 0 }, 171 { "OTES1 Fan", 36, 2, 60, 1, 0 }, 172 { NULL, 0, 0, 0, 0, 0 } } 173 }, 174 { 0x0011, "Abit AT8 32X", { 175 { "CPU Core", 0, 0, 10, 1, 0 }, 176 { "DDR", 1, 0, 20, 1, 0 }, 177 { "DDR VTT", 2, 0, 10, 1, 0 }, 178 { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 }, 179 { "NB 1.8V", 4, 0, 10, 1, 0 }, 180 { "NB 1.8V Dual", 5, 0, 10, 1, 0 }, 181 { "HTV 1.2", 3, 0, 10, 1, 0 }, 182 { "PCIE 1.2V", 12, 0, 10, 1, 0 }, 183 { "NB 1.2V", 13, 0, 10, 1, 0 }, 184 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 185 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 186 { "ATX +5V", 9, 0, 30, 1, 0 }, 187 { "+3.3V", 10, 0, 20, 1, 0 }, 188 { "5VSB", 11, 0, 30, 1, 0 }, 189 { "CPU", 24, 1, 1, 1, 0 }, 190 { "NB", 25, 1, 1, 1, 0 }, 191 { "System", 26, 1, 1, 1, 0 }, 192 { "PWM", 27, 1, 1, 1, 0 }, 193 { "CPU Fan", 32, 2, 60, 1, 0 }, 194 { "NB Fan", 33, 2, 60, 1, 0 }, 195 { "SYS Fan", 34, 2, 60, 1, 0 }, 196 { "AUX1 Fan", 35, 2, 60, 1, 0 }, 197 { "AUX2 Fan", 36, 2, 60, 1, 0 }, 198 { NULL, 0, 0, 0, 0, 0 } } 199 }, 200 { 0x0012, "unknown. Please send-pr(1)", { 201 { "CPU Core", 0, 0, 10, 1, 0 }, 202 { "DDR", 1, 0, 20, 1, 0 }, 203 { "DDR VTT", 2, 0, 10, 1, 0 }, 204 { "HyperTransport", 3, 0, 10, 1, 0 }, 205 { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 }, 206 { "NB", 4, 0, 10, 1, 0 }, 207 { "SB", 6, 0, 10, 1, 0 }, 208 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 209 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 210 { "ATX +5V", 9, 0, 30, 1, 0 }, 211 { "+3.3V", 10, 0, 20, 1, 0 }, 212 { "5VSB", 11, 0, 30, 1, 0 }, 213 { "CPU", 24, 1, 1, 1, 0 }, 214 { "SYS", 25, 1, 1, 1, 0 }, 215 { "PWM", 26, 1, 1, 1, 0 }, 216 { "CPU Fan", 32, 2, 60, 1, 0 }, 217 { "NB Fan", 33, 2, 60, 1, 0 }, 218 { "SYS Fan", 34, 2, 60, 1, 0 }, 219 { "AUX1 Fan", 36, 2, 60, 1, 0 }, 220 { NULL, 0, 0, 0, 0, 0 } } 221 }, 222 { 0x0013, "unknown. Please send-pr(1)", { 223 { "CPU Core", 0, 0, 10, 1, 0 }, 224 { "DDR", 1, 0, 10, 1, 0 }, 225 { "DDR VTT", 2, 0, 10, 1, 0 }, 226 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 227 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 228 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 229 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 230 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 231 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 232 { "ATX +5V", 9, 0, 30, 1, 0 }, 233 { "+3.3V", 10, 0, 20, 1, 0 }, 234 { "5VSB", 11, 0, 30, 1, 0 }, 235 { "CPU", 24, 1, 1, 1, 0 }, 236 { "System", 25, 1, 1, 1, 0 }, 237 { "PWM1", 26, 1, 1, 1, 0 }, 238 { "PWM2", 27, 1, 1, 1, 0 }, 239 { "PWM3", 28, 1, 1, 1, 0 }, 240 { "PWM4", 29, 1, 1, 1, 0 }, 241 { "CPU Fan", 32, 2, 60, 1, 0 }, 242 { "NB Fan", 33, 2, 60, 1, 0 }, 243 { "SYS Fan", 34, 2, 60, 1, 0 }, 244 { "AUX1 Fan", 35, 2, 60, 1, 0 }, 245 { "AUX2 Fan", 36, 2, 60, 1, 0 }, 246 { "AUX3 Fan", 37, 2, 60, 1, 0 }, 247 { "AUX4 Fan", 38, 2, 60, 1, 0 }, 248 { NULL, 0, 0, 0, 0, 0 } } 249 }, 250 { 0x0014, "Abit AB9 Pro", { 251 { "CPU Core", 0, 0, 10, 1, 0 }, 252 { "DDR", 1, 0, 10, 1, 0 }, 253 { "DDR VTT", 2, 0, 10, 1, 0 }, 254 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 255 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 256 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 257 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 258 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 259 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 260 { "ATX +5V", 9, 0, 30, 1, 0 }, 261 { "+3.3V", 10, 0, 20, 1, 0 }, 262 { "5VSB", 11, 0, 30, 1, 0 }, 263 { "CPU", 24, 1, 1, 1, 0 }, 264 { "System", 25, 1, 1, 1, 0 }, 265 { "PWM", 26, 1, 1, 1, 0 }, 266 { "CPU Fan", 32, 2, 60, 1, 0 }, 267 { "NB Fan", 33, 2, 60, 1, 0 }, 268 { "SYS Fan", 34, 2, 60, 1, 0 }, 269 { NULL, 0, 0, 0, 0, 0 } } 270 }, 271 { 0x0015, "unknown. Please send-pr(1)", { 272 { "CPU Core", 0, 0, 10, 1, 0 }, 273 { "DDR", 1, 0, 20, 1, 0 }, 274 { "DDR VTT", 2, 0, 10, 1, 0 }, 275 { "HyperTransport", 3, 0, 10, 1, 0 }, 276 { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 }, 277 { "NB", 4, 0, 10, 1, 0 }, 278 { "SB", 6, 0, 10, 1, 0 }, 279 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 280 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 281 { "ATX +5V", 9, 0, 30, 1, 0 }, 282 { "+3.3V", 10, 0, 20, 1, 0 }, 283 { "5VSB", 11, 0, 30, 1, 0 }, 284 { "CPU", 24, 1, 1, 1, 0 }, 285 { "SYS", 25, 1, 1, 1, 0 }, 286 { "PWM", 26, 1, 1, 1, 0 }, 287 { "CPU Fan", 32, 2, 60, 1, 0 }, 288 { "NB Fan", 33, 2, 60, 1, 0 }, 289 { "SYS Fan", 34, 2, 60, 1, 0 }, 290 { "AUX1 Fan", 33, 2, 60, 1, 0 }, 291 { "AUX2 Fan", 35, 2, 60, 1, 0 }, 292 { "AUX3 Fan", 36, 2, 60, 1, 0 }, 293 { NULL, 0, 0, 0, 0, 0 } } 294 }, 295 { 0x0016, "generic", { 296 { "CPU Core", 0, 0, 10, 1, 0 }, 297 { "DDR", 1, 0, 20, 1, 0 }, 298 { "DDR VTT", 2, 0, 10, 1, 0 }, 299 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 300 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 301 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 302 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 303 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 304 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 305 { "ATX +5V", 9, 0, 30, 1, 0 }, 306 { "+3.3V", 10, 0, 20, 1, 0 }, 307 { "5VSB", 11, 0, 30, 1, 0 }, 308 { "CPU", 24, 1, 1, 1, 0 }, 309 { "System", 25, 1, 1, 1, 0 }, 310 { "PWM", 26, 1, 1, 1, 0 }, 311 { "CPU Fan", 32, 2, 60, 1, 0 }, 312 { "NB Fan", 33, 2, 60, 1, 0 }, 313 { "SYS FAN", 34, 2, 60, 1, 0 }, 314 { "AUX1 Fan", 35, 2, 60, 1, 0 }, 315 { NULL, 0, 0, 0, 0, 0 } } 316 }, 317 { 0x0000, NULL, { { NULL, 0, 0, 0, 0, 0 } } } 318 }; 319 320 321 int 322 ug_reset(struct ug_softc *sc) 323 { 324 int cnt = 0; 325 326 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, UG_DATA) != 0x08) { 327 /* 8 meaning Voodoo */ 328 329 if (cnt++ > UG_DELAY_CYCLES) 330 return 0; 331 332 bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_DATA, 0); 333 334 /* Wait for 0x09 at Data Port */ 335 if (!ug_waitfor(sc, UG_DATA, 0x09)) 336 return 0; 337 338 /* Wait for 0xAC at Cmd Port */ 339 if (!ug_waitfor(sc, UG_CMD, 0xAC)) 340 return 0; 341 } 342 343 return 1; 344 } 345 346 uint8_t 347 ug_read(struct ug_softc *sc, unsigned short sensor) 348 { 349 uint8_t bank, sens, rv; 350 351 bank = (sensor & 0xFF00) >> 8; 352 sens = sensor & 0x00FF; 353 354 bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_DATA, bank); 355 356 /* Wait 8 at Data Port */ 357 if (!ug_waitfor(sc, UG_DATA, 8)) 358 return 0; 359 360 bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_CMD, sens); 361 362 /* Wait 1 at Data Port */ 363 if (!ug_waitfor(sc, UG_DATA, 1)) 364 return 0; 365 366 /* Finally read the sensor */ 367 rv = bus_space_read_1(sc->sc_iot, sc->sc_ioh, UG_CMD); 368 369 ug_reset(sc); 370 371 return rv; 372 } 373 374 int 375 ug_waitfor(struct ug_softc *sc, uint16_t offset, uint8_t value) 376 { 377 int cnt = 0; 378 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset) != value) { 379 if (cnt++ > UG_DELAY_CYCLES) 380 return 0; 381 } 382 return 1; 383 } 384 385 void 386 ug_setup_sensors(struct ug_softc *sc) 387 { 388 int i; 389 390 /* Setup Temps */ 391 for (i = 0; i < UG_VOLT_MIN; i++) 392 sc->sc_data[i].units = sc->sc_info[i].units = ENVSYS_STEMP; 393 394 #define COPYDESCR(x, y) \ 395 do { \ 396 strlcpy((x), (y), sizeof(x)); \ 397 } while (0) 398 399 COPYDESCR(sc->sc_info[0].desc, "CPU Temp"); 400 COPYDESCR(sc->sc_info[1].desc, "SYS Temp"); 401 COPYDESCR(sc->sc_info[2].desc, "PWN Temp"); 402 403 /* Right, Now setup U sensors */ 404 405 for (i = UG_VOLT_MIN; i < UG_FAN_MIN; i++) { 406 sc->sc_data[i].units = sc->sc_info[i].units = ENVSYS_SVOLTS_DC; 407 sc->sc_info[i].rfact = UG_RFACT; 408 } 409 410 COPYDESCR(sc->sc_info[3].desc, "HTVdd"); 411 COPYDESCR(sc->sc_info[4].desc, "VCore"); 412 COPYDESCR(sc->sc_info[5].desc, "DDRVdd"); 413 COPYDESCR(sc->sc_info[6].desc, "Vdd3V3"); 414 COPYDESCR(sc->sc_info[7].desc, "Vdd5V"); 415 COPYDESCR(sc->sc_info[8].desc, "NBVdd"); 416 COPYDESCR(sc->sc_info[9].desc, "AGPVdd"); 417 COPYDESCR(sc->sc_info[10].desc, "DDRVtt"); 418 COPYDESCR(sc->sc_info[11].desc, "Vdd5VSB"); 419 COPYDESCR(sc->sc_info[12].desc, "Vdd3VDual"); 420 COPYDESCR(sc->sc_info[13].desc, "SBVdd"); 421 422 /* Fan sensors */ 423 for (i = UG_FAN_MIN; i < UG_NUM_SENSORS; i++) 424 sc->sc_data[i].units = sc->sc_info[i].units = ENVSYS_SFANRPM; 425 426 COPYDESCR(sc->sc_info[14].desc, "CPU Fan"); 427 COPYDESCR(sc->sc_info[15].desc, "NB Fan"); 428 COPYDESCR(sc->sc_info[16].desc, "SYS Fan"); 429 COPYDESCR(sc->sc_info[17].desc, "AUX Fan 1"); 430 COPYDESCR(sc->sc_info[18].desc, "AUX Fan 2"); 431 } 432 433 int 434 ug_gtredata(struct sysmon_envsys *sme, envsys_tre_data_t *tred) 435 { 436 struct ug_softc *sc = sme->sme_cookie; 437 envsys_tre_data_t *t = sc->sc_data; /* For easier read */ 438 439 /* Sensors return C while we need uK */ 440 441 if (tred->sensor < UG_VOLT_MIN - 1) /* CPU and SYS Temps */ 442 t[tred->sensor].cur.data_us = ug_read(sc, UG_CPUTEMP + 443 tred->sensor) * 1000000 + 273150000; 444 else if (tred->sensor == 2) /* PWMTEMP */ 445 t[tred->sensor].cur.data_us = ug_read(sc, UG_PWMTEMP) 446 * 1000000 + 273150000; 447 448 /* Voltages */ 449 450 #define VOLT_SENSOR UG_HTV + tred->sensor - UG_VOLT_MIN 451 452 else 453 if ((tred->sensor >= UG_VOLT_MIN) && (tred->sensor < UG_FAN_MIN)) { 454 t[tred->sensor].cur.data_s = ug_read(sc, VOLT_SENSOR); 455 switch(VOLT_SENSOR) { 456 case UG_5V: /* 6V RFact */ 457 case UG_5VSB: 458 t[tred->sensor].cur.data_s *= UG_RFACT6; 459 break; 460 case UG_3V3: /* 4V RFact */ 461 case UG_3VDUAL: 462 t[tred->sensor].cur.data_s *= UG_RFACT4; 463 break; 464 default: /* 3V RFact */ 465 t[tred->sensor].cur.data_s *= UG_RFACT3; 466 } 467 } else 468 469 #undef VOLT_SENSOR 470 471 /* and Fans */ 472 if (tred->sensor >= UG_FAN_MIN) 473 t[tred->sensor].cur.data_s = ug_read(sc, UG_CPUFAN + 474 tred->sensor - UG_FAN_MIN) * UG_RFACT_FAN; 475 else 476 return ENODEV; /* should I scream and panic ? */ 477 478 *tred = sc->sc_data[tred->sensor]; 479 return 0; 480 } 481 482 int 483 ug_streinfo_ni(struct sysmon_envsys *sme, envsys_basic_info_t *binfo) 484 { 485 /* not implemented */ 486 binfo->validflags = 0; 487 488 return 0; 489 } 490 491 void 492 ug2_attach(struct ug_softc *sc) 493 { 494 uint8_t buf[2]; 495 int i, i2; 496 struct ug2_motherboard_info *ai; 497 struct ug2_sensor_info *si; 498 struct envsys_range ug2_ranges[7]; /* XXX: why only 7 ?! */ 499 500 aprint_normal(": Abit uGuru 2005 system monitor\n"); 501 502 memcpy(ug2_ranges, ug_ranges, 7 * sizeof(struct envsys_range)); 503 504 for (i = 0; i < 7; i++) 505 ug2_ranges[i].low = ug2_ranges[i].high = 0xFF; 506 507 if (ug2_read(sc, UG2_MISC_BANK, UG2_BOARD_ID, 2, buf) != 2) { 508 aprint_error("%s: Cannot detect board ID. Using default\n", 509 sc->sc_dev.dv_xname); 510 buf[0] = UG_MAX_MSB_BOARD; 511 buf[1] = UG_MAX_LSB_BOARD; 512 } 513 514 if (buf[0] > UG_MAX_MSB_BOARD || buf[1] > UG_MAX_LSB_BOARD || 515 buf[1] < UG_MIN_LSB_BOARD) { 516 aprint_error("%s: Invalid board ID(%X,%X). Using default\n", 517 sc->sc_dev.dv_xname, buf[0], buf[1]); 518 buf[0] = UG_MAX_MSB_BOARD; 519 buf[1] = UG_MAX_LSB_BOARD; 520 } 521 522 ai = &ug2_mb[buf[1] - UG_MIN_LSB_BOARD]; 523 524 aprint_normal("%s: mainboard %s (%.2X%.2X)\n", sc->sc_dev.dv_xname, 525 ai->name, buf[0], buf[1]); 526 527 sc->mbsens = (void*)ai->sensors; 528 529 for (i = 0, si = ai->sensors; si && si->name; si++, i++) { 530 COPYDESCR(sc->sc_info[i].desc, si->name); 531 sc->sc_data[i].sensor = sc->sc_info[i].sensor = i; 532 sc->sc_data[i].validflags = (ENVSYS_FVALID|ENVSYS_FCURVALID); 533 sc->sc_info[i].validflags = ENVSYS_FVALID; 534 sc->sc_data[i].warnflags = ENVSYS_WARN_OK; 535 sc->sc_info[i].rfact = 1; 536 switch (si->type) { 537 case UG2_VOLTAGE_SENSOR: 538 sc->sc_data[i].units = sc->sc_info[i].units = 539 ENVSYS_SVOLTS_DC; 540 sc->sc_info[i].rfact = UG_RFACT; 541 ug2_ranges[3].high = i; 542 if (ug2_ranges[3].low == 0xFF) 543 ug2_ranges[3].low = i; 544 break; 545 case UG2_TEMP_SENSOR: 546 sc->sc_data[i].units = sc->sc_info[i].units = 547 ENVSYS_STEMP; 548 ug2_ranges[0].high = i; 549 if (ug2_ranges[0].low == 0xFF) 550 ug2_ranges[0].low = i; 551 break; 552 case UG2_FAN_SENSOR: 553 sc->sc_data[i].units = sc->sc_info[i].units = 554 ENVSYS_SFANRPM; 555 ug2_ranges[1].high = i; 556 if (ug2_ranges[0].low == 0xFF) 557 ug2_ranges[0].low = i; 558 } 559 } 560 #undef COPYDESCR 561 562 for (i2 = 0; i2 < 7; i2++) 563 if (ug2_ranges[i2].low == 0xFF || 564 ug2_ranges[i2].high == 0xFF) { 565 ug2_ranges[i2].low = 1; 566 ug2_ranges[i2].high = 0; 567 } 568 569 sc->sc_sysmon.sme_ranges = ug2_ranges; 570 sc->sc_sysmon.sme_sensor_info = sc->sc_info; 571 sc->sc_sysmon.sme_sensor_data = sc->sc_data; 572 sc->sc_sysmon.sme_cookie = sc; 573 sc->sc_sysmon.sme_gtredata = ug2_gtredata; 574 sc->sc_sysmon.sme_streinfo = ug_streinfo_ni; 575 sc->sc_sysmon.sme_nsensors = i; 576 sc->sc_sysmon.sme_envsys_version = UG_DRV_VERSION; 577 sc->sc_sysmon.sme_flags = 0; 578 579 if (sysmon_envsys_register(&sc->sc_sysmon)) 580 aprint_error("%s: unable to register with sysmon\n", 581 sc->sc_dev.dv_xname); 582 } 583 584 int 585 ug2_gtredata(struct sysmon_envsys *sme, envsys_tre_data_t *tred) 586 { 587 struct ug_softc *sc = sme->sme_cookie; 588 envsys_tre_data_t *t = sc->sc_data; /* makes code readable */ 589 struct ug2_sensor_info *si = (struct ug2_sensor_info *)sc->mbsens; 590 int rfact = 1; 591 uint8_t v; 592 593 if (tred->sensor >= sc->sc_sysmon.sme_nsensors) 594 return ENODEV; /* ?! */ 595 596 si += tred->sensor; 597 598 #define SENSOR_VALUE (v * si->multiplier * rfact / si->divisor + si->offset) 599 600 if (ug2_read(sc, UG2_SENSORS_BANK, UG2_VALUES_OFFSET + 601 si->port, 1, &v) == 1) { 602 switch (si->type) { 603 case UG2_TEMP_SENSOR: 604 t[tred->sensor].cur.data_us = SENSOR_VALUE * 1000000 605 + 273150000; 606 break; 607 case UG2_VOLTAGE_SENSOR: 608 rfact = UG_RFACT; 609 t[tred->sensor].cur.data_us = SENSOR_VALUE; 610 break; 611 default: 612 t[tred->sensor].cur.data_s = SENSOR_VALUE; 613 } 614 } else 615 return ENODEV; 616 617 #undef SENSOR_VALUE 618 619 *tred = sc->sc_data[tred->sensor]; 620 return 0; 621 } 622 623 int 624 ug2_wait_ready(struct ug_softc *sc) 625 { 626 int cnt = 0; 627 628 bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_DATA, 0x1a); 629 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, UG_DATA) & 630 UG2_STATUS_BUSY) { 631 if (cnt++ > UG_DELAY_CYCLES) 632 return 0; 633 } 634 return 1; 635 } 636 637 int 638 ug2_wait_readable(struct ug_softc *sc) 639 { 640 int cnt = 0; 641 642 while (!(bus_space_read_1(sc->sc_iot, sc->sc_ioh, UG_DATA) & 643 UG2_STATUS_READY_FOR_READ)) { 644 if (cnt++ > UG_DELAY_CYCLES) 645 return 0; 646 } 647 return 1; 648 } 649 650 int 651 ug2_sync(struct ug_softc *sc) 652 { 653 int cnt = 0; 654 655 #define UG2_WAIT_READY if(ug2_wait_ready(sc) == 0) return 0; 656 657 /* Don't sync two times in a row */ 658 if(ug_ver != 0) { 659 ug_ver = 0; 660 return 1; 661 } 662 663 UG2_WAIT_READY; 664 bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_DATA, 0x20); 665 UG2_WAIT_READY; 666 bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_CMD, 0x10); 667 UG2_WAIT_READY; 668 bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_CMD, 0x00); 669 UG2_WAIT_READY; 670 if (ug2_wait_readable(sc) == 0) 671 return 0; 672 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, UG_CMD) != 0xAC) 673 if (cnt++ > UG_DELAY_CYCLES) 674 return 0; 675 return 1; 676 } 677 678 int 679 ug2_read(struct ug_softc *sc, uint8_t bank, uint8_t offset, uint8_t count, 680 uint8_t *ret) 681 { 682 int i; 683 684 if (ug2_sync(sc) == 0) 685 return 0; 686 687 bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_DATA, 0x1A); 688 UG2_WAIT_READY; 689 bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_CMD, bank); 690 UG2_WAIT_READY; 691 bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_CMD, offset); 692 UG2_WAIT_READY; 693 bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_CMD, count); 694 UG2_WAIT_READY; 695 696 #undef UG2_WAIT_READY 697 698 /* Now wait for the results */ 699 for (i = 0; i < count; i++) { 700 if (ug2_wait_readable(sc) == 0) 701 break; 702 ret[i] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, UG_CMD); 703 } 704 705 return i; 706 } 707
Indexes created Tue Sep 23 07:09:52 GMT 2025