uhareg.h revision 1.1
1 typedef u_long physaddr; 2 typedef u_long physlen; 3 4 /************************** board definitions *******************************/ 5 /* 6 * I/O Port Interface 7 */ 8 #define U14_LMASK 0x0000 /* local doorbell mask reg */ 9 #define U14_LINT 0x0001 /* local doorbell int/stat reg */ 10 #define U14_SMASK 0x0002 /* system doorbell mask reg */ 11 #define U14_SINT 0x0003 /* system doorbell int/stat reg */ 12 #define U14_ID 0x0004 /* product id reg (2 ports) */ 13 #define U14_CONFIG 0x0006 /* config reg (2 ports) */ 14 #define U14_OGMPTR 0x0008 /* outgoing mail ptr (4 ports) */ 15 #define U14_ICMPTR 0x000c /* incoming mail ptr (4 ports) */ 16 17 #define U24_CONFIG 0x0005 /* config reg (3 ports) */ 18 #define U24_LMASK 0x000c /* local doorbell mask reg */ 19 #define U24_LINT 0x000d /* local doorbell int/stat reg */ 20 #define U24_SMASK 0x000e /* system doorbell mask reg */ 21 #define U24_SINT 0x000f /* system doorbell int/stat reg */ 22 #define U24_OGMCMD 0x0016 /* outgoing commands */ 23 #define U24_OGMPTR 0x0017 /* outgoing mail ptr (4 ports) */ 24 #define U24_ICMCMD 0x001b /* incoming commands */ 25 #define U24_ICMPTR 0x001c /* incoming mail ptr (4 ports) */ 26 27 /* 28 * UHA_LMASK bits (read only) 29 */ 30 #define UHA_LDIE 0x80 /* local doorbell int enabled */ 31 #define UHA_SRSTE 0x40 /* soft reset enabled */ 32 #define UHA_ABORTEN 0x10 /* abort MSCP enabled */ 33 #define UHA_OGMINTEN 0x01 /* outgoing mail interrupt enabled */ 34 35 /* 36 * UHA_LINT bits (read only) 37 */ 38 #define U14_LDIP 0x80 /* local doorbell int pending */ 39 #define U24_LDIP 0x02 /* local doorbell int pending */ 40 41 /* 42 * UHA_LINT bits (write only) 43 */ 44 #define U14_OGMFULL 0x01 /* outgoing mailbox is full */ 45 #define U14_ABORT 0x10 /* abort MSCP */ 46 47 #define U24_OGMFULL 0x02 /* outgoing mailbox is full */ 48 49 #define UHA_SBRST 0x40 /* scsi bus reset */ 50 #define UHA_ADRST 0x80 /* adapter soft reset */ 51 #define UHA_ASRST 0xc0 /* adapter and scsi reset */ 52 53 /* 54 * UHA_SMASK bits (read/write) 55 */ 56 #define UHA_ENSINT 0x80 /* enable system doorbell interrupt */ 57 #define UHA_EN_ABORT_COMPLETE 0x10 /* enable abort MSCP complete int */ 58 #define UHA_ENICM 0x01 /* enable ICM interrupt */ 59 60 /* 61 * UHA_SINT bits (read) 62 */ 63 #define U14_SDIP 0x80 /* system doorbell int pending */ 64 #define U24_SDIP 0x02 /* system doorbell int pending */ 65 66 #define UHA_ABORT_SUCC 0x10 /* abort MSCP successful */ 67 #define UHA_ABORT_FAIL 0x18 /* abort MSCP failed */ 68 69 /* 70 * UHA_SINT bits (write) 71 */ 72 #define U14_ICM_ACK 0x01 /* acknowledge ICM and clear */ 73 #define U24_ICM_ACK 0x02 /* acknowledge ICM and clear */ 74 75 #define UHA_ABORT_ACK 0x18 /* acknowledge status and clear */ 76 77 /* 78 * U14_CONFIG bits (read only) 79 */ 80 #define U14_DMA_CH5 0x0000 /* DMA channel 5 */ 81 #define U14_DMA_CH6 0x4000 /* 6 */ 82 #define U14_DMA_CH7 0x8000 /* 7 */ 83 #define U14_DMA_MASK 0xc000 84 #define U14_IRQ15 0x0000 /* IRQ 15 */ 85 #define U14_IRQ14 0x1000 /* 14 */ 86 #define U14_IRQ11 0x2000 /* 11 */ 87 #define U14_IRQ10 0x3000 /* 10 */ 88 #define U14_IRQ_MASK 0x3000 89 #define U14_HOSTID_MASK 0x0007 90 91 /* 92 * U24_CONFIG bits (read only) 93 */ 94 #define U24_MAGIC1 0x08 95 #define U24_IRQ15 0x10 96 #define U24_IRQ14 0x20 97 #define U24_IRQ11 0x40 98 #define U24_IRQ10 0x80 99 #define U24_IRQ_MASK 0xf0 100 101 #define U24_MAGIC2 0x04 102 103 #define U24_HOSTID_MASK 0x07 104 105 /* 106 * EISA registers (offset from slot base) 107 */ 108 #define EISA_VENDOR 0x0c80 /* vendor ID (2 ports) */ 109 #define EISA_MODEL 0x0c82 /* model number (2 ports) */ 110 #define EISA_CONTROL 0x0c84 111 #define EISA_RESET 0x04 112 #define EISA_ERROR 0x02 113 #define EISA_ENABLE 0x01 114 115 /* 116 * host_stat error codes 117 */ 118 #define UHA_NO_ERR 0x00 /* No error supposedly */ 119 #define UHA_SBUS_ABORT_ERR 0x84 /* scsi bus abort error */ 120 #define UHA_SBUS_TIMEOUT 0x91 /* scsi bus selection timeout */ 121 #define UHA_SBUS_OVER_UNDER 0x92 /* scsi bus over/underrun */ 122 #define UHA_BAD_SCSI_CMD 0x96 /* illegal scsi command */ 123 #define UHA_AUTO_SENSE_ERR 0x9b /* auto request sense err */ 124 #define UHA_SBUS_RES_ERR 0xa3 /* scsi bus reset error */ 125 #define UHA_BAD_SG_LIST 0xff /* invalid scatter gath list */ 126 127 #define UHA_NSEG 33 /* number of dma segments supported */ 128 129 struct uha_dma_seg { 130 physaddr seg_addr; 131 physlen seg_len; 132 }; 133 134 #pragma pack(1) 135 struct uha_mscp { 136 u_char opcode:3; 137 #define UHA_HAC 0x01 /* host adapter command */ 138 #define UHA_TSP 0x02 /* target scsi pass through command */ 139 #define UHA_SDR 0x04 /* scsi device reset */ 140 u_char xdir:2; /* xfer direction */ 141 #define UHA_SDET 0x00 /* determined by scsi command */ 142 #define UHA_SDIN 0x01 /* scsi data in */ 143 #define UHA_SDOUT 0x02 /* scsi data out */ 144 #define UHA_NODATA 0x03 /* no data xfer */ 145 u_char dcn:1; /* disable disconnect for this command */ 146 u_char ca:1; /* cache control */ 147 u_char sgth:1; /* scatter gather flag */ 148 u_char target:3; 149 u_char chan:2; /* scsi channel (always 0 for 14f) */ 150 u_char lun:3; 151 physaddr data_addr; 152 physlen data_length; 153 physaddr link_addr; 154 u_char link_id; 155 u_char sg_num; /* number of scat gath segs */ 156 /*in s-g list if sg flag is */ 157 /*set. starts at 1, 8bytes per */ 158 u_char req_sense_length; 159 u_char scsi_cmd_length; 160 struct scsi_generic scsi_cmd; 161 u_char host_stat; 162 u_char target_stat; 163 physaddr sense_ptr; /* if 0 no auto sense */ 164 165 struct uha_dma_seg uha_dma[UHA_NSEG]; 166 struct scsi_sense_data mscp_sense; 167 /*-----------------end of hardware supported fields----------------*/ 168 TAILQ_ENTRY(uha_mscp) chain; 169 struct uha_mscp *nexthash; 170 long hashkey; 171 struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ 172 int flags; 173 #define MSCP_ALLOC 0x01 174 #define MSCP_ABORT 0x02 175 int timeout; 176 }; 177 #pragma pack(4) 178 179
Indexes created Fri Sep 26 20:09:58 GMT 2025