vga_subr.c revision 1.14
1 /* $NetBSD: vga_subr.c,v 1.14 2003/01/31 21:57:26 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1998 5 * Matthias Drochner. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project 18 * by Matthias Drochner. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: vga_subr.c,v 1.14 2003/01/31 21:57:26 tsutsui Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/queue.h> 42 #include <machine/bus.h> 43 44 #include <dev/ic/mc6845reg.h> 45 #include <dev/ic/pcdisplay.h> 46 #include <dev/ic/pcdisplayvar.h> 47 #include <dev/ic/vgareg.h> 48 #include <dev/ic/vgavar.h> 49 50 #include <dev/wscons/wsdisplayvar.h> 51 52 static void fontram(struct vga_handle *); 53 static void textram(struct vga_handle *); 54 #ifdef VGA_RESET 55 static void vga_initregs(struct vga_handle *); 56 #endif 57 58 static void 59 fontram(struct vga_handle *vh) 60 { 61 62 /* program sequencer to access character generator */ 63 64 vga_ts_write(vh, syncreset, 0x01); /* synchronous reset */ 65 vga_ts_write(vh, wrplmask, 0x04); /* write to map 2 */ 66 vga_ts_write(vh, memmode, 0x07); /* sequential addressing */ 67 vga_ts_write(vh, syncreset, 0x03); /* clear synchronous reset */ 68 69 /* program graphics controller to access character generator */ 70 71 vga_gdc_write(vh, rdplanesel, 0x02); /* select map 2 for cpu reads */ 72 vga_gdc_write(vh, mode, 0x00); /* disable odd-even addressing */ 73 vga_gdc_write(vh, misc, 0x04); /* map starts at 0xA000 */ 74 } 75 76 static void 77 textram(struct vga_handle *vh) 78 { 79 80 /* program sequencer to access video ram */ 81 82 vga_ts_write(vh, syncreset, 0x01); /* synchronous reset */ 83 vga_ts_write(vh, wrplmask, 0x03); /* write to map 0 & 1 */ 84 vga_ts_write(vh, memmode, 0x03); /* odd-even addressing */ 85 vga_ts_write(vh, syncreset, 0x03); /* clear synchronous reset */ 86 87 /* program graphics controller for text mode */ 88 89 vga_gdc_write(vh, rdplanesel, 0x00); /* select map 0 for cpu reads */ 90 vga_gdc_write(vh, mode, 0x10); /* enable odd-even addressing */ 91 /* map starts at 0xb800 or 0xb000 (mono) */ 92 vga_gdc_write(vh, misc, (vh->vh_mono ? 0x0a : 0x0e)); 93 } 94 95 #ifndef VGA_RASTERCONSOLE 96 void 97 vga_loadchars(struct vga_handle *vh, int fontset, int first, int num, int lpc, 98 char *data) 99 { 100 int offset, i, j, s; 101 102 /* fontset number swizzle done in vga_setfontset() */ 103 offset = (fontset << 13) | (first << 5); 104 105 s = splhigh(); 106 fontram(vh); 107 108 for (i = 0; i < num; i++) 109 for (j = 0; j < lpc; j++) 110 bus_space_write_1(vh->vh_memt, vh->vh_allmemh, 111 offset + (i << 5) + j, data[i * lpc + j]); 112 113 textram(vh); 114 splx(s); 115 } 116 117 void 118 vga_readoutchars(struct vga_handle *vh, int fontset, int first, int num, 119 int lpc, char *data) 120 { 121 int offset, i, j, s; 122 123 /* fontset number swizzle done in vga_setfontset() */ 124 offset = (fontset << 13) | (first << 5); 125 126 s = splhigh(); 127 fontram(vh); 128 129 for (i = 0; i < num; i++) 130 for (j = 0; j < lpc; j++) 131 data[i * lpc + j] = bus_space_read_1(vh->vh_memt, 132 vh->vh_allmemh, offset + (i << 5) + j); 133 134 textram(vh); 135 splx(s); 136 } 137 138 #ifdef VGA_CONSOLE_ATI_BROKEN_FONTSEL 139 void 140 vga_copyfont01(struct vga_handle *vh) 141 { 142 int s; 143 144 s = splhigh(); 145 fontram(vh); 146 147 bus_space_copy_region_1(vh->vh_memt, vh->vh_allmemh, 0, 148 vh->vh_allmemh, 1 << 13, 1 << 13); 149 150 textram(vh); 151 splx(s); 152 } 153 #endif 154 155 void 156 vga_setfontset(struct vga_handle *vh, int fontset1, int fontset2) 157 { 158 u_int8_t cmap; 159 static const u_int8_t cmaptaba[] = { 160 0x00, 0x10, 0x01, 0x11, 161 0x02, 0x12, 0x03, 0x13 162 }; 163 static const u_int8_t cmaptabb[] = { 164 0x00, 0x20, 0x04, 0x24, 165 0x08, 0x28, 0x0c, 0x2c 166 }; 167 168 /* extended font if fontset1 != fontset2 */ 169 cmap = cmaptaba[fontset1] | cmaptabb[fontset2]; 170 171 vga_ts_write(vh, fontsel, cmap); 172 } 173 174 void 175 vga_setscreentype(struct vga_handle *vh, const struct wsscreen_descr *type) 176 { 177 178 vga_6845_write(vh, maxrow, type->fontheight - 1); 179 180 /* lo byte */ 181 vga_6845_write(vh, vde, type->fontheight * type->nrows - 1); 182 183 #ifndef PCDISPLAY_SOFTCURSOR 184 /* set cursor to last 2 lines */ 185 vga_6845_write(vh, curstart, type->fontheight - 2); 186 vga_6845_write(vh, curend, type->fontheight - 1); 187 #endif 188 /* 189 * disable colour plane 3 if needed for font selection 190 */ 191 if (type->capabilities & WSSCREEN_HILIT) { 192 /* 193 * these are the screens which don't support 194 * 512-character fonts 195 */ 196 vga_attr_write(vh, colplen, 0x0f); 197 } else 198 vga_attr_write(vh, colplen, 0x07); 199 } 200 201 #else /* !VGA_RASTERCONSOLE */ 202 void 203 vga_load_builtinfont(struct vga_handle *vh, u_int8_t *font, int firstchar, 204 int numchars) 205 { 206 int i, s; 207 208 s = splhigh(); 209 fontram(vh); 210 211 for (i = firstchar; i < firstchar + numchars; i++) 212 bus_space_read_region_1(vh->vh_memt, vh->vh_allmemh, i * 32, 213 font + i * 16, 16); 214 215 textram(vh); 216 splx(s); 217 } 218 #endif /* !VGA_RASTERCONSOLE */ 219 220 #ifdef VGA_RESET 221 /* 222 * vga_reset(): 223 * Reset VGA registers to put it into 80x25 text mode. (mode 3) 224 * This function should be called from MD consinit() on ports 225 * whose firmware does not use text mode at boot time. 226 */ 227 void 228 vga_reset(vh, md_initfunc) 229 struct vga_handle *vh; 230 void (*md_initfunc)(struct vga_handle *); 231 { 232 u_int8_t reg; 233 234 if (bus_space_map(vh->vh_iot, 0x3c0, 0x10, 0, &vh->vh_ioh_vga)) 235 return; 236 237 reg = bus_space_read_1(vh->vh_iot, vh->vh_ioh_vga, VGA_MISC_DATAR); 238 vh->vh_mono = !(reg & 0x01); 239 240 if (bus_space_map(vh->vh_iot, vh->vh_mono ? 0x3b0 : 0x3d0, 0x10, 241 0, &vh->vh_ioh_6845)) 242 goto out1; 243 244 if (bus_space_map(vh->vh_memt, 0xa0000, 0x20000, 0, &vh->vh_allmemh)) 245 goto out2; 246 247 if (bus_space_subregion(vh->vh_memt, vh->vh_allmemh, 248 vh->vh_mono ? 0x10000 : 0x18000, 0x8000, &vh->vh_memh)) 249 goto out3; 250 251 /* check if VGA already in text mode. */ 252 if ((vga_gdc_read(vh, misc) & 0x01) == 0) 253 goto out3; 254 255 /* initialize common VGA registers */ 256 vga_initregs(vh); 257 258 /* initialize chipset specific registers */ 259 if (md_initfunc != NULL) 260 (*md_initfunc)(vh); 261 262 delay(10000); 263 264 /* clear text buffer RAM */ 265 bus_space_set_region_2(vh->vh_memt, vh->vh_memh, 0, 266 ((BG_BLACK | FG_LIGHTGREY) << 8) | ' ', 80 * 25 /*XXX*/); 267 268 out3: 269 bus_space_unmap(vh->vh_memt, vh->vh_allmemh, 0x20000); 270 out2: 271 bus_space_unmap(vh->vh_iot, vh->vh_ioh_6845, 0x10); 272 out1: 273 bus_space_unmap(vh->vh_iot, vh->vh_ioh_vga, 0x10); 274 } 275 276 /* 277 * values to initialize registers. 278 */ 279 280 /* miscellaneous output register */ 281 #define VGA_MISCOUT 0x66 282 283 /* sequencer registers */ 284 static const u_int8_t vga_ts[] = { 285 0x03, /* 00: reset */ 286 0x00, /* 01: clocking mode */ 287 0x03, /* 02: map mask */ 288 0x00, /* 03: character map select */ 289 0x02 /* 04: memory mode */ 290 }; 291 292 /* CRT controller registers */ 293 static const u_int8_t vga_crtc[] = { 294 0x5f, /* 00: horizontal total */ 295 0x4f, /* 01: horizontal display-enable end */ 296 0x50, /* 02: start horizontal blanking */ 297 0x82, /* 03: display skew control / end horizontal blanking */ 298 0x55, /* 04: start horizontal retrace pulse */ 299 0x81, /* 05: horizontal retrace delay / end horizontal retrace */ 300 0xbf, /* 06: vetical total */ 301 0x1f, /* 07: overflow register */ 302 0x00, /* 08: preset row scan */ 303 0x4f, /* 09: overflow / maximum scan line */ 304 0x0d, /* 0A: cursor off / cursor start */ 305 0x0e, /* 0B: cursor skew / cursor end */ 306 0x00, /* 0C: start regenerative buffer address high */ 307 0x00, /* 0D: start regenerative buffer address low */ 308 0x00, /* 0E: cursor location high */ 309 0x00, /* 0F: cursor location low */ 310 0x9c, /* 10: vertical retrace start */ 311 0x8e, /* 11: vertical interrupt / vertical retrace end */ 312 0x8f, /* 12: vertical display enable end */ 313 0x28, /* 13: logical line width */ 314 0x00, /* 14: underline location */ 315 0x96, /* 15: start vertical blanking */ 316 0xb9, /* 16: end vertical blanking */ 317 0xa3, /* 17: CRT mode control */ 318 0xff /* 18: line compare */ 319 }; 320 321 /* graphics controller registers */ 322 static const u_int8_t vga_gdc[] = { 323 0x00, /* 00: set/reset map */ 324 0x00, /* 01: enable set/reset */ 325 0x00, /* 02: color compare */ 326 0x00, /* 03: data rotate */ 327 0x00, /* 04: read map select */ 328 0x10, /* 05: graphics mode */ 329 0x0e, /* 06: miscellaneous */ 330 0x00, /* 07: color don't care */ 331 0xff /* 08: bit mask */ 332 }; 333 334 /* attribute controller registers */ 335 static const u_int8_t vga_atc[] = { 336 0x00, /* 00: internal palette 0 */ 337 0x01, /* 01: internal palette 1 */ 338 0x02, /* 02: internal palette 2 */ 339 0x03, /* 03: internal palette 3 */ 340 0x04, /* 04: internal palette 4 */ 341 0x05, /* 05: internal palette 5 */ 342 0x14, /* 06: internal palette 6 */ 343 0x07, /* 07: internal palette 7 */ 344 0x38, /* 08: internal palette 8 */ 345 0x39, /* 09: internal palette 9 */ 346 0x3a, /* 0A: internal palette 10 */ 347 0x3b, /* 0B: internal palette 11 */ 348 0x3c, /* 0C: internal palette 12 */ 349 0x3d, /* 0D: internal palette 13 */ 350 0x3e, /* 0E: internal palette 14 */ 351 0x3f, /* 0F: internal palette 15 */ 352 0x0c, /* 10: attribute mode control */ 353 0x00, /* 11: overscan color */ 354 0x0f, /* 12: color plane enable */ 355 0x08, /* 13: horizontal PEL panning */ 356 0x00 /* 14: color select */ 357 }; 358 359 /* video DAC palette registers */ 360 /* XXX only set up 16 colors used by internal palette in ATC regsters */ 361 static const u_int8_t vga_dacpal[] = { 362 /* R G B */ 363 0x00, 0x00, 0x00, /* BLACK */ 364 0x00, 0x00, 0x2a, /* BLUE */ 365 0x00, 0x2a, 0x00, /* GREEN */ 366 0x00, 0x2a, 0x2a, /* CYAN */ 367 0x2a, 0x00, 0x00, /* RED */ 368 0x2a, 0x00, 0x2a, /* MAGENTA */ 369 0x2a, 0x15, 0x00, /* BROWN */ 370 0x2a, 0x2a, 0x2a, /* LIGHTGREY */ 371 0x15, 0x15, 0x15, /* DARKGREY */ 372 0x15, 0x15, 0x3f, /* LIGHTBLUE */ 373 0x15, 0x3f, 0x15, /* LIGHTGREEN */ 374 0x15, 0x3f, 0x3f, /* LIGHTCYAN */ 375 0x3f, 0x15, 0x15, /* LIGHTRED */ 376 0x3f, 0x15, 0x3f, /* LIGHTMAGENTA */ 377 0x3f, 0x3f, 0x15, /* YELLOW */ 378 0x3f, 0x3f, 0x3f /* WHITE */ 379 }; 380 381 static void 382 vga_initregs(vh) 383 struct vga_handle *vh; 384 { 385 int i; 386 387 /* disable video */ 388 vga_ts_write(vh, mode, vga_ts[1] | VGA_TS_MODE_BLANK); 389 390 /* synchronous reset */ 391 vga_ts_write(vh, syncreset, 0x01); 392 /* set TS regsters */ 393 for (i = 2; i < VGA_TS_NREGS; i++) 394 _vga_ts_write(vh, i, vga_ts[i]); 395 /* clear synchronous reset */ 396 vga_ts_write(vh, syncreset, 0x03); 397 398 /* unprotect CRTC regsters */ 399 vga_6845_write(vh, vsynce, vga_6845_read(vh, vsynce) & ~0x80); 400 /* set CRTC regsters */ 401 for (i = 0; i < MC6845_NREGS; i++) 402 _vga_6845_write(vh, i, vga_crtc[i]); 403 404 /* set GDC regsters */ 405 for (i = 0; i < VGA_GDC_NREGS; i++) 406 _vga_gdc_write(vh, i, vga_gdc[i]); 407 408 /* set ATC regsters */ 409 for (i = 0; i < VGA_ATC_NREGS; i++) 410 _vga_attr_write(vh, i, vga_atc[i]); 411 412 /* set DAC palette */ 413 if (!vh->vh_mono) { 414 for (i = 0; i < 16; i++) { 415 bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, 416 VGA_DAC_ADDRW, vga_atc[i]); 417 bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, 418 VGA_DAC_PALETTE, vga_dacpal[i * 3 + 0]); 419 bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, 420 VGA_DAC_PALETTE, vga_dacpal[i * 3 + 1]); 421 bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, 422 VGA_DAC_PALETTE, vga_dacpal[i * 3 + 2]); 423 } 424 } 425 426 /* set misc output register */ 427 bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, 428 VGA_MISC_DATAW, VGA_MISCOUT | (vh->vh_mono ? 0 : 0x01)); 429 430 /* reenable video */ 431 vga_ts_write(vh, mode, vga_ts[1] & ~VGA_TS_MODE_BLANK); 432 } 433 #endif /* VGA_RESET */ 434
Indexes created Tue Sep 23 07:09:52 GMT 2025