wd33c93.c revision 1.12
1 /* $NetBSD: wd33c93.c,v 1.12 2007/05/08 00:20:15 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37 /* 38 * Changes Copyright (c) 2001 Wayne Knowles 39 * Changes Copyright (c) 1996 Steve Woodford 40 * Original Copyright (c) 1994 Christian E. Hopps 41 * 42 * This code is derived from software contributed to Berkeley by 43 * Van Jacobson of Lawrence Berkeley Laboratory. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 74 */ 75 76 /* 77 * This version of the driver is pretty well generic, so should work with 78 * any flavour of WD33C93 chip. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.12 2007/05/08 00:20:15 rumble Exp $"); 83 84 #include "opt_ddb.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> /* For hz */ 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsiconf.h> 96 #include <dev/scsipi/scsi_message.h> 97 98 #include <uvm/uvm_extern.h> 99 100 #include <machine/bus.h> 101 102 #include <dev/ic/wd33c93reg.h> 103 #include <dev/ic/wd33c93var.h> 104 105 /* 106 * SCSI delays 107 * In u-seconds, primarily for state changes on the SPC. 108 */ 109 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 110 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 111 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 112 113 #define STATUS_UNKNOWN 0xff /* uninitialized status */ 114 115 /* 116 * Convenience macro for waiting for a particular wd33c93 event 117 */ 118 #define SBIC_WAIT(regs, until, timeo) wd33c93_wait(regs, until, timeo, __LINE__) 119 120 void wd33c93_init (struct wd33c93_softc *); 121 void wd33c93_reset (struct wd33c93_softc *); 122 int wd33c93_go (struct wd33c93_softc *, struct wd33c93_acb *); 123 int wd33c93_dmaok (struct wd33c93_softc *, struct scsipi_xfer *); 124 int wd33c93_wait (struct wd33c93_softc *, u_char, int , int); 125 u_char wd33c93_selectbus (struct wd33c93_softc *, struct wd33c93_acb *); 126 int wd33c93_xfout (struct wd33c93_softc *, int, void *); 127 int wd33c93_xfin (struct wd33c93_softc *, int, void *); 128 int wd33c93_poll (struct wd33c93_softc *, struct wd33c93_acb *); 129 int wd33c93_nextstate (struct wd33c93_softc *, struct wd33c93_acb *, 130 u_char, u_char); 131 int wd33c93_abort (struct wd33c93_softc *, struct wd33c93_acb *, 132 const char *); 133 void wd33c93_xferdone (struct wd33c93_softc *); 134 void wd33c93_error (struct wd33c93_softc *, struct wd33c93_acb *); 135 void wd33c93_scsidone (struct wd33c93_softc *, struct wd33c93_acb *, int); 136 void wd33c93_sched (struct wd33c93_softc *); 137 void wd33c93_dequeue (struct wd33c93_softc *, struct wd33c93_acb *); 138 void wd33c93_dma_stop (struct wd33c93_softc *); 139 void wd33c93_dma_setup (struct wd33c93_softc *, int); 140 int wd33c93_msgin_phase (struct wd33c93_softc *, int); 141 void wd33c93_msgin (struct wd33c93_softc *, u_char *, int); 142 void wd33c93_reselect (struct wd33c93_softc *, int, int, int, int); 143 void wd33c93_sched_msgout (struct wd33c93_softc *, u_short); 144 void wd33c93_msgout (struct wd33c93_softc *); 145 void wd33c93_timeout (void *arg); 146 void wd33c93_watchdog (void *arg); 147 u_char wd33c93_stp2syn (struct wd33c93_softc *, struct wd33c93_tinfo *); 148 void wd33c93_setsync (struct wd33c93_softc *, struct wd33c93_tinfo *); 149 void wd33c93_update_xfer_mode (struct wd33c93_softc *, int); 150 151 static struct pool wd33c93_pool; /* Adapter Control Blocks */ 152 static int wd33c93_pool_initialized = 0; 153 154 /* 155 * Timeouts 156 */ 157 int wd33c93_cmd_wait = SBIC_CMD_WAIT; 158 int wd33c93_data_wait = SBIC_DATA_WAIT; 159 int wd33c93_init_wait = SBIC_INIT_WAIT; 160 161 int wd33c93_nodma = 0; /* Use polled IO transfers */ 162 int wd33c93_nodisc = 0; /* Allow command queues */ 163 int wd33c93_notags = 0; /* No Tags */ 164 165 /* 166 * Some useful stuff for debugging purposes 167 */ 168 #ifdef DEBUG 169 170 #define QPRINTF(a) SBIC_DEBUG(MISC, a) 171 172 int wd33c93_debug = 0; /* Debug flags */ 173 174 void wd33c93_print_csr (u_char); 175 void wd33c93_hexdump (u_char *, int); 176 177 #else 178 #define QPRINTF(a) /* */ 179 #endif 180 181 static const char *wd33c93_chip_names[] = SBIC_CHIP_LIST; 182 183 /* 184 * Attach instance of driver and probe for sub devices 185 */ 186 void 187 wd33c93_attach(struct wd33c93_softc *dev) 188 { 189 struct scsipi_adapter *adapt = &dev->sc_adapter; 190 struct scsipi_channel *chan = &dev->sc_channel; 191 192 adapt->adapt_dev = &dev->sc_dev; 193 adapt->adapt_nchannels = 1; 194 adapt->adapt_openings = 256; 195 adapt->adapt_max_periph = 256; /* Max tags per device */ 196 adapt->adapt_ioctl = NULL; 197 /* adapt_request initialized by MD interface */ 198 /* adapt_minphys initialized by MD interface */ 199 200 memset(chan, 0, sizeof(*chan)); 201 chan->chan_adapter = &dev->sc_adapter; 202 chan->chan_bustype = &scsi_bustype; 203 chan->chan_channel = 0; 204 chan->chan_ntargets = SBIC_NTARG; 205 chan->chan_nluns = SBIC_NLUN; 206 chan->chan_id = dev->sc_id; 207 208 callout_init(&dev->sc_watchdog); 209 210 dev->sc_maxoffset = SBIC_SYN_MAX_OFFSET; /* Max Sync Offset */ 211 212 /* 213 * Add reference to adapter so that we drop the reference after 214 * config_found() to make sure the adatper is disabled. 215 */ 216 if (scsipi_adapter_addref(&dev->sc_adapter) != 0) { 217 printf("%s: unable to enable controller\n", 218 dev->sc_dev.dv_xname); 219 return; 220 } 221 222 dev->sc_cfflags = device_cfdata(&dev->sc_dev)->cf_flags; 223 wd33c93_init(dev); 224 225 printf(": %s (%d.%d MHz clock, SCSI ID %d)\n", 226 wd33c93_chip_names[dev->sc_chip], 227 dev->sc_clkfreq / 10, dev->sc_clkfreq % 10, 228 dev->sc_channel.chan_id); 229 if (dev->sc_chip == SBIC_CHIP_WD33C93B) { 230 printf("%s: microcode revision 0x%02x", 231 dev->sc_dev.dv_xname, dev->sc_rev); 232 if (dev->sc_minsyncperiod < 50) 233 printf(", Fast SCSI"); 234 printf("\n"); 235 } 236 237 dev->sc_child = config_found(&dev->sc_dev, &dev->sc_channel, 238 scsiprint); 239 scsipi_adapter_delref(&dev->sc_adapter); 240 } 241 242 /* 243 * Initialize driver-private structures 244 */ 245 void 246 wd33c93_init(struct wd33c93_softc *dev) 247 { 248 u_int i; 249 250 if (!wd33c93_pool_initialized) { 251 /* All instances share the same pool */ 252 pool_init(&wd33c93_pool, sizeof(struct wd33c93_acb), 0, 0, 0, 253 "wd33c93_acb", NULL, IPL_BIO); 254 ++wd33c93_pool_initialized; 255 } 256 257 if (dev->sc_state == 0) { 258 TAILQ_INIT(&dev->ready_list); 259 260 dev->sc_nexus = NULL; 261 dev->sc_disc = 0; 262 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 263 264 callout_reset(&dev->sc_watchdog, 60 * hz, wd33c93_watchdog, dev); 265 } else 266 panic("wd33c93: reinitializing driver!"); 267 268 dev->sc_flags = 0; 269 dev->sc_state = SBIC_IDLE; 270 wd33c93_reset(dev); 271 272 for (i = 0; i < 8; i++) { 273 struct wd33c93_tinfo *ti = &dev->sc_tinfo[i]; 274 /* 275 * sc_flags = 0xTTRRSS 276 * 277 * TT = Bitmask to disable Tagged Queues 278 * RR = Bitmask to disable disconnect/reselect 279 * SS = Bitmask to diable Sync negotiation 280 */ 281 ti->flags = T_NEED_RESET; 282 if (dev->sc_cfflags & (1<<(i+8))) 283 ti->flags |= T_NOSYNC; 284 if (dev->sc_cfflags & (1<<i) || wd33c93_nodisc) 285 ti->flags |= T_NODISC; 286 ti->period = dev->sc_minsyncperiod; 287 ti->offset = 0; 288 } 289 } 290 291 void 292 wd33c93_reset(struct wd33c93_softc *dev) 293 { 294 u_int my_id, s, div, i; 295 u_char csr, reg; 296 297 SET_SBIC_cmd(dev, SBIC_CMD_ABORT); 298 WAIT_CIP(dev); 299 300 s = splbio(); 301 302 if (dev->sc_reset != NULL) 303 (*dev->sc_reset)(dev); 304 305 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 306 307 /* Enable advanced features and really(!) advanced features */ 308 #if 1 309 my_id |= (SBIC_ID_EAF | SBIC_ID_RAF); /* XXX - MD Layer */ 310 #endif 311 312 SET_SBIC_myid(dev, my_id); 313 314 /* Reset the chip */ 315 SET_SBIC_cmd(dev, SBIC_CMD_RESET); 316 DELAY(25); 317 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 318 319 /* Set up various chip parameters */ 320 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 321 322 GET_SBIC_csr(dev, csr); /* clears interrupt also */ 323 GET_SBIC_cdb1(dev, dev->sc_rev); /* valid with RAF on wd33c93b */ 324 325 switch (csr) { 326 case SBIC_CSR_RESET: 327 dev->sc_chip = SBIC_CHIP_WD33C93; 328 break; 329 case SBIC_CSR_RESET_AM: 330 SET_SBIC_queue_tag(dev, 0x55); 331 GET_SBIC_queue_tag(dev, reg); 332 dev->sc_chip = (reg == 0x55) ? 333 SBIC_CHIP_WD33C93B : SBIC_CHIP_WD33C93A; 334 SET_SBIC_queue_tag(dev, 0x0); 335 break; 336 default: 337 dev->sc_chip = SBIC_CHIP_UNKNOWN; 338 } 339 340 /* 341 * Choose a suitable clock divisor and work out the resulting 342 * sync transfer periods in 4ns units. 343 */ 344 if (dev->sc_clkfreq < 110) { 345 my_id |= SBIC_ID_FS_8_10; 346 div = 2; 347 } else if (dev->sc_clkfreq < 160) { 348 my_id |= SBIC_ID_FS_12_15; 349 div = 3; 350 } else if (dev->sc_clkfreq < 210) { 351 my_id |= SBIC_ID_FS_16_20; 352 div = 4; 353 } else 354 panic("wd33c93: invalid clock speed %d", dev->sc_clkfreq); 355 356 for (i = 0; i < 7; i++) 357 dev->sc_syncperiods[i] = 358 (i + 2) * div * 1250 / dev->sc_clkfreq; 359 dev->sc_minsyncperiod = dev->sc_syncperiods[0]; 360 SBIC_DEBUG(SYNC, ("available sync periods: %d %d %d %d %d %d %d\n", 361 dev->sc_syncperiods[0], dev->sc_syncperiods[1], 362 dev->sc_syncperiods[2], dev->sc_syncperiods[3], 363 dev->sc_syncperiods[4], dev->sc_syncperiods[5], 364 dev->sc_syncperiods[6])); 365 366 if (dev->sc_clkfreq >= 160 && dev->sc_chip == SBIC_CHIP_WD33C93B) { 367 for (i = 0; i < 3; i++) 368 dev->sc_fsyncperiods[i] = 369 (i + 2) * 2 * 1250 / dev->sc_clkfreq; 370 SBIC_DEBUG(SYNC, ("available fast sync periods: %d %d %d\n", 371 dev->sc_fsyncperiods[0], dev->sc_fsyncperiods[1], 372 dev->sc_fsyncperiods[2])); 373 dev->sc_minsyncperiod = dev->sc_fsyncperiods[0]; 374 } 375 376 /* 377 * don't allow Selection (SBIC_RID_ES) 378 * until we can handle target mode!! 379 */ 380 SET_SBIC_rselid(dev, SBIC_RID_ER); 381 382 /* Asynchronous for now */ 383 SET_SBIC_syn(dev, 0); 384 385 dev->sc_flags = 0; 386 dev->sc_state = SBIC_IDLE; 387 388 splx(s); 389 } 390 391 void 392 wd33c93_error(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 393 { 394 struct scsipi_xfer *xs = acb->xs; 395 396 KASSERT(xs); 397 398 if (xs->xs_control & XS_CTL_SILENT) 399 return; 400 401 scsipi_printaddr(xs->xs_periph); 402 printf("SCSI Error\n"); 403 } 404 405 /* 406 * Determine an appropriate value for the synchronous transfer register 407 * given the period and offset values in *ti. 408 */ 409 u_char 410 wd33c93_stp2syn(struct wd33c93_softc *dev, struct wd33c93_tinfo *ti) 411 { 412 unsigned i; 413 414 /* see if we can handle fast scsi (100-200ns) first */ 415 if (ti->period < 50 && dev->sc_minsyncperiod < 50) { 416 for (i = 0; i < 3; i++) 417 if (dev->sc_fsyncperiods[i] >= ti->period) 418 return (SBIC_SYN(ti->offset, i + 2, 1)); 419 } 420 421 for (i = 0; i < 7; i++) { 422 if (dev->sc_syncperiods[i] >= ti->period) { 423 if (i == 6) 424 return (SBIC_SYN(0, 0, 0)); 425 else 426 return (SBIC_SYN(ti->offset, i + 2, 0)); 427 } 428 } 429 430 /* XXX - can't handle it; do async */ 431 return (SBIC_SYN(0, 0, 0)); 432 } 433 434 /* 435 * Setup sync mode for given target 436 */ 437 void 438 wd33c93_setsync(struct wd33c93_softc *dev, struct wd33c93_tinfo *ti) 439 { 440 u_char syncreg; 441 442 if (ti->flags & T_SYNCMODE) 443 syncreg = wd33c93_stp2syn(dev, ti); 444 else 445 syncreg = SBIC_SYN(0, 0, 0); 446 447 SBIC_DEBUG(SYNC, ("wd33c93_setsync: sync reg = 0x%02x\n", syncreg)); 448 SET_SBIC_syn(dev, syncreg); 449 } 450 451 /* 452 * Check if current operation can be done using DMA 453 * 454 * returns 1 if DMA OK, 0 for polled I/O transfer 455 */ 456 int 457 wd33c93_dmaok(struct wd33c93_softc *dev, struct scsipi_xfer *xs) 458 { 459 if (wd33c93_nodma || (xs->xs_control & XS_CTL_POLL) || xs->datalen == 0) 460 return (0); 461 return(1); 462 } 463 464 /* 465 * Setup for DMA transfer 466 */ 467 void 468 wd33c93_dma_setup(struct wd33c93_softc *dev, int datain) 469 { 470 struct wd33c93_acb *acb = dev->sc_nexus; 471 int s; 472 473 dev->sc_daddr = acb->daddr; 474 dev->sc_dleft = acb->dleft; 475 476 s = splbio(); 477 /* Indicate that we're in DMA mode */ 478 if (dev->sc_dleft) { 479 dev->sc_dmasetup(dev, &dev->sc_daddr, &dev->sc_dleft, 480 datain, &dev->sc_dleft); 481 } 482 splx(s); 483 return; 484 } 485 486 487 /* 488 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 489 */ 490 void 491 wd33c93_dma_stop(struct wd33c93_softc *dev) 492 { 493 size_t count; 494 int asr; 495 496 /* Wait until WD chip is idle */ 497 do { 498 GET_SBIC_asr(dev, asr); /* XXX */ 499 if (asr & SBIC_ASR_DBR) { 500 printf("wd33c93_dma_stop: asr %02x canceled!\n", asr); 501 break; 502 } 503 } while (asr & (SBIC_ASR_BSY|SBIC_ASR_CIP)); 504 505 /* Only need to save pointers if DMA was active */ 506 if (dev->sc_flags & SBICF_INDMA) { 507 int s = splbio(); 508 509 /* Shut down DMA and flush FIFO's */ 510 dev->sc_dmastop(dev); 511 512 /* Fetch the residual count */ 513 SBIC_TC_GET(dev, count); 514 515 /* Work out how many bytes were actually transferred */ 516 count = dev->sc_tcnt - count; 517 518 if (dev->sc_dleft < count) 519 printf("xfer too large: dleft=%zu resid=%zu\n", 520 dev->sc_dleft, count); 521 522 /* Fixup partial xfers */ 523 dev->sc_daddr = (char*)dev->sc_daddr + count; 524 dev->sc_dleft -= count; 525 dev->sc_tcnt = 0; 526 dev->sc_flags &= ~SBICF_INDMA; 527 splx(s); 528 SBIC_DEBUG(DMA, ("dma_stop\n")); 529 } 530 /* 531 * Ensure the WD chip is back in polled I/O mode, with nothing to 532 * transfer. 533 */ 534 SBIC_TC_PUT(dev, 0); 535 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 536 } 537 538 539 /* 540 * Handle new request from scsipi layer 541 */ 542 void 543 wd33c93_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 544 { 545 struct wd33c93_softc *dev = (void *)chan->chan_adapter->adapt_dev; 546 struct scsipi_xfer *xs; 547 struct scsipi_periph *periph; 548 struct wd33c93_acb *acb; 549 int flags, s; 550 551 switch (req) { 552 case ADAPTER_REQ_RUN_XFER: 553 xs = arg; 554 periph = xs->xs_periph; 555 flags = xs->xs_control; 556 557 if (flags & XS_CTL_DATA_UIO) 558 panic("wd33c93: scsi data uio requested"); 559 560 if (dev->sc_nexus && (flags & XS_CTL_POLL)) 561 panic("wd33c93_scsicmd: busy"); 562 563 s = splbio(); 564 acb = (struct wd33c93_acb *)pool_get(&wd33c93_pool, PR_NOWAIT); 565 splx(s); 566 567 if (acb == NULL) { 568 scsipi_printaddr(periph); 569 printf("cannot allocate acb\n"); 570 xs->error = XS_RESOURCE_SHORTAGE; 571 scsipi_done(xs); 572 return; 573 } 574 575 acb->flags = ACB_ACTIVE; 576 acb->xs = xs; 577 acb->clen = xs->cmdlen; 578 acb->daddr = xs->data; 579 acb->dleft = xs->datalen; 580 acb->timeout = xs->timeout; 581 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 582 583 if (flags & XS_CTL_POLL) { 584 /* 585 * Complete currently active command(s) before 586 * issuing an immediate command 587 */ 588 while (dev->sc_nexus) 589 wd33c93_poll(dev, dev->sc_nexus); 590 } 591 592 s = splbio(); 593 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 594 acb->flags |= ACB_READY; 595 596 /* If nothing is active, try to start it now. */ 597 if (dev->sc_state == SBIC_IDLE) 598 wd33c93_sched(dev); 599 splx(s); 600 601 if ((flags & XS_CTL_POLL) == 0) 602 return; 603 604 if (wd33c93_poll(dev, acb)) { 605 wd33c93_timeout(acb); 606 if (wd33c93_poll(dev, acb)) /* 2nd retry for ABORT */ 607 wd33c93_timeout(acb); 608 } 609 return; 610 611 case ADAPTER_REQ_GROW_RESOURCES: 612 /* XXX Not supported. */ 613 return; 614 615 case ADAPTER_REQ_SET_XFER_MODE: 616 { 617 struct wd33c93_tinfo *ti; 618 struct scsipi_xfer_mode *xm = arg; 619 620 ti = &dev->sc_tinfo[xm->xm_target]; 621 ti->flags &= ~T_WANTSYNC; 622 623 if ((dev->sc_cfflags & (1<<(xm->xm_target+16))) == 0 && 624 (xm->xm_mode & PERIPH_CAP_TQING) && !wd33c93_notags) 625 ti->flags |= T_TAG; 626 else 627 ti->flags &= ~T_TAG; 628 629 SBIC_DEBUG(SYNC, ("wd33c93_scsi_request: " 630 "target %d: scsipi requested %s\n", xm->xm_target, 631 (xm->xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 632 633 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 634 (ti->flags & T_NOSYNC) == 0) 635 ti->flags |= T_WANTSYNC; 636 /* 637 * If we're not going to negotiate, send the notification 638 * now, since it won't happen later. 639 */ 640 if (!(ti->flags & T_WANTSYNC) == !(ti->flags & T_SYNCMODE)) 641 wd33c93_update_xfer_mode(dev, xm->xm_target); 642 else 643 ti->flags |= T_NEGOTIATE; 644 return; 645 } 646 647 } 648 } 649 650 /* 651 * attempt to start the next available command 652 */ 653 void 654 wd33c93_sched(struct wd33c93_softc *dev) 655 { 656 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 657 struct wd33c93_acb *acb; 658 struct wd33c93_tinfo *ti; 659 struct wd33c93_linfo *li; 660 int lun, tag, flags; 661 662 if (dev->sc_state != SBIC_IDLE) 663 return; 664 665 KASSERT(dev->sc_nexus == NULL); 666 667 /* Loop through the ready list looking for work to do... */ 668 TAILQ_FOREACH(acb, &dev->ready_list, chain) { 669 periph = acb->xs->xs_periph; 670 lun = periph->periph_lun; 671 ti = &dev->sc_tinfo[periph->periph_target]; 672 li = TINFO_LUN(ti, lun); 673 674 KASSERT(acb->flags & ACB_READY); 675 676 /* Select type of tag for this command */ 677 if ((ti->flags & T_NODISC) != 0) 678 tag = 0; 679 else if ((ti->flags & T_TAG) == 0) 680 tag = 0; 681 else if ((acb->flags & ACB_SENSE) != 0) 682 tag = 0; 683 else if (acb->xs->xs_control & XS_CTL_POLL) 684 tag = 0; /* No tags for polled commands */ 685 else 686 tag = acb->xs->xs_tag_type; 687 688 if (li == NULL) { 689 /* Initialize LUN info and add to list. */ 690 li = malloc(sizeof(*li), M_DEVBUF, M_NOWAIT); 691 if (li == NULL) 692 continue; 693 memset(li, 0, sizeof(*li)); 694 li->lun = lun; 695 if (lun < SBIC_NLUN) 696 ti->lun[lun] = li; 697 } 698 li->last_used = time_second; 699 700 /* 701 * We've found a potential command, but is the target/lun busy? 702 */ 703 704 if (tag == 0 && li->untagged == NULL) 705 li->untagged = acb; /* Issue untagged */ 706 707 if (li->untagged != NULL) { 708 tag = 0; 709 if ((li->state != L_STATE_BUSY) && li->used == 0) { 710 /* Issue this untagged command now */ 711 acb = li->untagged; 712 periph = acb->xs->xs_periph; 713 } else /* Not ready yet */ 714 continue; 715 } 716 717 acb->tag_type = tag; 718 if (tag != 0) { 719 if (li->queued[acb->xs->xs_tag_id]) 720 printf("queueing to active tag\n"); 721 li->queued[acb->xs->xs_tag_id] = acb; 722 acb->tag_id = acb->xs->xs_tag_id; 723 li->used++; 724 break; 725 } 726 if (li->untagged != NULL && (li->state != L_STATE_BUSY)) { 727 li->state = L_STATE_BUSY; 728 break; 729 } 730 if (li->untagged == NULL && tag != 0) { 731 break; 732 } else 733 printf("%d:%d busy\n", periph->periph_target, 734 periph->periph_lun); 735 } 736 737 if (acb == NULL) { 738 SBIC_DEBUG(ACBS, ("wd33c93sched: no work\n")); 739 return; /* did not find an available command */ 740 } 741 742 SBIC_DEBUG(ACBS, ("wd33c93_sched(%d,%d)\n", periph->periph_target, 743 periph->periph_lun)); 744 745 TAILQ_REMOVE(&dev->ready_list, acb, chain); 746 acb->flags &= ~ACB_READY; 747 748 flags = acb->xs->xs_control; 749 if (flags & XS_CTL_RESET) 750 wd33c93_reset(dev); 751 752 /* XXX - Implicitly call scsidone on select timeout */ 753 if (wd33c93_go(dev, acb) != 0 || acb->xs->error == XS_SELTIMEOUT) { 754 acb->dleft = dev->sc_dleft; 755 wd33c93_scsidone(dev, acb, dev->sc_status); 756 return; 757 } 758 759 return; 760 } 761 762 void 763 wd33c93_scsidone(struct wd33c93_softc *dev, struct wd33c93_acb *acb, int status) 764 { 765 struct scsipi_xfer *xs = acb->xs; 766 struct wd33c93_tinfo *ti; 767 struct wd33c93_linfo *li; 768 int s; 769 770 #ifdef DIAGNOSTIC 771 KASSERT(dev->target == xs->xs_periph->periph_target); 772 KASSERT(dev->lun == xs->xs_periph->periph_lun); 773 if (acb == NULL || xs == NULL) { 774 panic("wd33c93_scsidone -- (%d,%d) no scsipi_xfer", 775 dev->target, dev->lun); 776 } 777 KASSERT(acb->flags != ACB_FREE); 778 #endif 779 780 SBIC_DEBUG(ACBS, ("scsidone: (%d,%d)->(%d,%d)%02x\n", 781 xs->xs_periph->periph_target, xs->xs_periph->periph_lun, 782 dev->target, dev->lun, status)); 783 callout_stop(&xs->xs_callout); 784 785 xs->status = status & SCSI_STATUS_MASK; 786 xs->resid = acb->dleft; 787 788 if (xs->error == XS_NOERROR) { 789 switch (xs->status) { 790 case SCSI_CHECK: 791 case SCSI_TERMINATED: 792 /* XXX Need to read sense - return busy for now */ 793 /*FALLTHROUGH*/ 794 case SCSI_QUEUE_FULL: 795 case SCSI_BUSY: 796 xs->error = XS_BUSY; 797 break; 798 } 799 } 800 801 ti = &dev->sc_tinfo[dev->target]; 802 li = TINFO_LUN(ti, dev->lun); 803 ti->cmds++; 804 if (xs->error == XS_SELTIMEOUT) { 805 /* Selection timeout -- discard this LUN if empty */ 806 if (li->untagged == NULL && li->used == 0) { 807 if (dev->lun < SBIC_NLUN) 808 ti->lun[dev->lun] = NULL; 809 free(li, M_DEVBUF); 810 } 811 } 812 813 wd33c93_dequeue(dev, acb); 814 if (dev->sc_nexus == acb) { 815 dev->sc_state = SBIC_IDLE; 816 dev->sc_nexus = NULL; 817 dev->sc_flags = 0; 818 819 if (!TAILQ_EMPTY(&dev->ready_list)) 820 wd33c93_sched(dev); 821 } 822 823 /* place control block back on free list. */ 824 s = splbio(); 825 acb->flags = ACB_FREE; 826 pool_put(&wd33c93_pool, (void *)acb); 827 splx(s); 828 829 scsipi_done(xs); 830 } 831 832 void 833 wd33c93_dequeue(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 834 { 835 struct wd33c93_tinfo *ti = &dev->sc_tinfo[acb->xs->xs_periph->periph_target]; 836 struct wd33c93_linfo *li; 837 int lun = acb->xs->xs_periph->periph_lun; 838 839 li = TINFO_LUN(ti, lun); 840 #ifdef DIAGNOSTIC 841 if (li == NULL || li->lun != lun) 842 panic("wd33c93_dequeue: lun %d for ecb %p does not exist", 843 lun, acb); 844 #endif 845 if (li->untagged == acb) { 846 li->state = L_STATE_IDLE; 847 li->untagged = NULL; 848 } 849 if (acb->tag_type && li->queued[acb->tag_id] != NULL) { 850 #ifdef DIAGNOSTIC 851 if (li->queued[acb->tag_id] != NULL && 852 (li->queued[acb->tag_id] != acb)) 853 panic("wd33c93_dequeue: slot %d for lun %d has %p " 854 "instead of acb %p\n", acb->tag_id, 855 lun, li->queued[acb->tag_id], acb); 856 #endif 857 li->queued[acb->tag_id] = NULL; 858 li->used--; 859 } 860 } 861 862 863 int 864 wd33c93_wait(struct wd33c93_softc *dev, u_char until, int timeo, int line) 865 { 866 u_char val; 867 868 if (timeo == 0) 869 timeo = 1000000; /* some large value.. */ 870 GET_SBIC_asr(dev, val); 871 while ((val & until) == 0) { 872 if (timeo-- == 0) { 873 int csr; 874 GET_SBIC_csr(dev, csr); 875 printf("wd33c93_wait: TIMEO @%d with asr=x%x csr=x%x\n", 876 line, val, csr); 877 #if defined(DDB) && defined(DEBUG) 878 Debugger(); 879 #endif 880 return(val); /* Maybe I should abort */ 881 break; 882 } 883 DELAY(1); 884 GET_SBIC_asr(dev, val); 885 } 886 return(val); 887 } 888 889 int 890 wd33c93_abort(struct wd33c93_softc *dev, struct wd33c93_acb *acb, 891 const char *where) 892 { 893 u_char csr, asr; 894 895 GET_SBIC_asr(dev, asr); 896 GET_SBIC_csr(dev, csr); 897 898 scsipi_printaddr(acb->xs->xs_periph); 899 printf ("ABORT in %s: csr=0x%02x, asr=0x%02x\n", where, csr, asr); 900 901 acb->timeout = SBIC_ABORT_TIMEOUT; 902 acb->flags |= ACB_ABORT; 903 904 /* 905 * Clean up chip itself 906 */ 907 if (dev->sc_nexus == acb) { 908 /* Reschedule timeout. */ 909 callout_reset(&acb->xs->xs_callout, mstohz(acb->timeout), 910 wd33c93_timeout, acb); 911 912 while (asr & SBIC_ASR_DBR) { 913 /* 914 * wd33c93 is jammed w/data. need to clear it 915 * But we don't know what direction it needs to go 916 */ 917 GET_SBIC_data(dev, asr); 918 printf("abort %s: clearing data buffer 0x%02x\n", 919 where, asr); 920 GET_SBIC_asr(dev, asr); 921 if (asr & SBIC_ASR_DBR) /* Not the read direction */ 922 SET_SBIC_data(dev, asr); 923 GET_SBIC_asr(dev, asr); 924 } 925 926 scsipi_printaddr(acb->xs->xs_periph); 927 printf("sending ABORT command\n"); 928 929 WAIT_CIP(dev); 930 SET_SBIC_cmd(dev, SBIC_CMD_ABORT); 931 WAIT_CIP(dev); 932 933 GET_SBIC_asr(dev, asr); 934 935 scsipi_printaddr(acb->xs->xs_periph); 936 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 937 /* 938 * ok, get more drastic.. 939 */ 940 printf("Resetting bus\n"); 941 wd33c93_reset(dev); 942 } else { 943 printf("sending DISCONNECT to target\n"); 944 SET_SBIC_cmd(dev, SBIC_CMD_DISC); 945 WAIT_CIP(dev); 946 947 do { 948 SBIC_WAIT (dev, SBIC_ASR_INT, 0); 949 GET_SBIC_asr(dev, asr); 950 GET_SBIC_csr(dev, csr); 951 SBIC_DEBUG(MISC, ("csr: 0x%02x, asr: 0x%02x\n", 952 csr, asr)); 953 } while ((csr != SBIC_CSR_DISC) && 954 (csr != SBIC_CSR_DISC_1) && 955 (csr != SBIC_CSR_CMD_INVALID)); 956 } 957 dev->sc_state = SBIC_ERROR; 958 dev->sc_flags = 0; 959 } 960 return SBIC_STATE_ERROR; 961 } 962 963 964 /* 965 * select the bus, return when selected or error. 966 * 967 * Returns the current CSR following selection and optionally MSG out phase. 968 * i.e. the returned CSR *should* indicate CMD phase... 969 * If the return value is 0, some error happened. 970 */ 971 u_char 972 wd33c93_selectbus(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 973 { 974 struct scsipi_xfer *xs = acb->xs; 975 struct wd33c93_tinfo *ti; 976 u_char target, lun, asr, csr, id; 977 978 KASSERT(dev->sc_state == SBIC_IDLE); 979 980 target = xs->xs_periph->periph_target; 981 lun = xs->xs_periph->periph_lun; 982 ti = &dev->sc_tinfo[target]; 983 984 dev->sc_state = SBIC_SELECTING; 985 dev->target = target; 986 dev->lun = lun; 987 988 SBIC_DEBUG(PHASE, ("wd33c93_selectbus %d: ", target)); 989 990 if ((xs->xs_control & XS_CTL_POLL) == 0) 991 callout_reset(&xs->xs_callout, mstohz(acb->timeout), 992 wd33c93_timeout, acb); 993 994 /* 995 * issue select 996 */ 997 SBIC_TC_PUT(dev, 0); 998 SET_SBIC_selid(dev, target); 999 SET_SBIC_timeo(dev, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 1000 1001 GET_SBIC_asr(dev, asr); 1002 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) { 1003 /* This means we got ourselves reselected upon */ 1004 SBIC_DEBUG(PHASE, ("WD busy (reselect?) ASR=%02x\n", asr)); 1005 return 0; 1006 } 1007 1008 SET_SBIC_cmd(dev, SBIC_CMD_SEL_ATN); 1009 WAIT_CIP(dev); 1010 1011 /* 1012 * wait for select (merged from separate function may need 1013 * cleanup) 1014 */ 1015 do { 1016 asr = SBIC_WAIT(dev, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1017 if (asr & SBIC_ASR_LCI) { 1018 QPRINTF(("late LCI: asr %02x\n", asr)); 1019 return 0; 1020 } 1021 1022 /* Clear interrupt */ 1023 GET_SBIC_csr (dev, csr); 1024 1025 /* Reselected from under our feet? */ 1026 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1027 SBIC_DEBUG(PHASE, ("got reselected, asr %02x\n", asr)); 1028 /* 1029 * We need to handle this now so we don't lock up later 1030 */ 1031 wd33c93_nextstate(dev, acb, csr, asr); 1032 return 0; 1033 } 1034 1035 /* Whoops! */ 1036 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1037 panic("wd33c93_selectbus: target issued select!"); 1038 return 0; 1039 } 1040 1041 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1042 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1043 csr != SBIC_CSR_SEL_TIMEO); 1044 1045 /* Anyone at home? */ 1046 if (csr == SBIC_CSR_SEL_TIMEO) { 1047 xs->error = XS_SELTIMEOUT; 1048 SBIC_DEBUG(PHASE, ("-- Selection Timeout\n")); 1049 return 0; 1050 } 1051 1052 SBIC_DEBUG(PHASE, ("Selection Complete\n")); 1053 1054 /* Assume we're now selected */ 1055 GET_SBIC_selid(dev, id); 1056 if (id != target) { 1057 /* Something went wrong - wrong target was select */ 1058 printf("wd33c93_selectbus: wrong target selected;" 1059 " WANTED %d GOT %d", target, id); 1060 return 0; /* XXX: Need to call nexstate to handle? */ 1061 } 1062 1063 dev->sc_flags |= SBICF_SELECTED; 1064 dev->sc_state = SBIC_CONNECTED; 1065 1066 /* setup correct sync mode for this target */ 1067 wd33c93_setsync(dev, ti); 1068 1069 if (ti->flags & T_NODISC && dev->sc_disc == 0) 1070 SET_SBIC_rselid (dev, 0); /* Not expecting a reselect */ 1071 else 1072 SET_SBIC_rselid (dev, SBIC_RID_ER); 1073 1074 /* 1075 * We only really need to do anything when the target goes to MSG out 1076 * If the device ignored ATN, it's probably old and brain-dead, 1077 * but we'll try to support it anyhow. 1078 * If it doesn't support message out, it definately doesn't 1079 * support synchronous transfers, so no point in even asking... 1080 */ 1081 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 1082 if (ti->flags & T_NEGOTIATE) { 1083 /* Inititae a SDTR message */ 1084 SBIC_DEBUG(SYNC, ("Sending SDTR to target %d\n", id)); 1085 if (ti->flags & T_WANTSYNC) { 1086 ti->period = dev->sc_minsyncperiod; 1087 ti->offset = dev->sc_maxoffset; 1088 } else { 1089 ti->period = 0; 1090 ti->offset = 0; 1091 } 1092 /* Send Sync negotiation message */ 1093 dev->sc_omsg[0] = MSG_IDENTIFY(lun, 0); /* No Disc */ 1094 dev->sc_omsg[1] = MSG_EXTENDED; 1095 dev->sc_omsg[2] = MSG_EXT_SDTR_LEN; 1096 dev->sc_omsg[3] = MSG_EXT_SDTR; 1097 if (ti->flags & T_WANTSYNC) { 1098 dev->sc_omsg[4] = dev->sc_minsyncperiod; 1099 dev->sc_omsg[5] = dev->sc_maxoffset; 1100 } else { 1101 dev->sc_omsg[4] = 0; 1102 dev->sc_omsg[5] = 0; 1103 } 1104 wd33c93_xfout(dev, 6, dev->sc_omsg); 1105 dev->sc_msgout |= SEND_SDTR; /* may be rejected */ 1106 dev->sc_flags |= SBICF_SYNCNEGO; 1107 } else { 1108 if (dev->sc_nexus->tag_type != 0) { 1109 /* Use TAGS */ 1110 SBIC_DEBUG(TAGS, ("<select %d:%d TAG=%x>\n", 1111 dev->target, dev->lun, 1112 dev->sc_nexus->tag_id)); 1113 dev->sc_omsg[0] = MSG_IDENTIFY(lun, 1); 1114 dev->sc_omsg[1] = dev->sc_nexus->tag_type; 1115 dev->sc_omsg[2] = dev->sc_nexus->tag_id; 1116 wd33c93_xfout(dev, 3, dev->sc_omsg); 1117 dev->sc_msgout |= SEND_TAG; 1118 } else { 1119 int no_disc; 1120 1121 /* Setup LUN nexus and disconnect privilege */ 1122 no_disc = xs->xs_control & XS_CTL_POLL || 1123 ti->flags & T_NODISC; 1124 SEND_BYTE(dev, MSG_IDENTIFY(lun, !no_disc)); 1125 } 1126 } 1127 /* 1128 * There's one interrupt still to come: 1129 * the change to CMD phase... 1130 */ 1131 SBIC_WAIT(dev, SBIC_ASR_INT , 0); 1132 GET_SBIC_csr(dev, csr); 1133 } 1134 1135 return csr; 1136 } 1137 1138 /* 1139 * Information Transfer *to* a SCSI Target. 1140 * 1141 * Note: Don't expect there to be an interrupt immediately after all 1142 * the data is transferred out. The WD spec sheet says that the Transfer- 1143 * Info command for non-MSG_IN phases only completes when the target 1144 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1145 * 1146 * This can have a nasty effect on commands which take a relatively long 1147 * time to complete, for example a START/STOP unit command may remain in 1148 * CMD phase until the disk has spun up. Only then will the target change 1149 * to STATUS phase. This is really only a problem for immediate commands 1150 * since we don't allow disconnection for them (yet). 1151 */ 1152 int 1153 wd33c93_xfout(struct wd33c93_softc *dev, int len, void *bp) 1154 { 1155 int wait = wd33c93_data_wait; 1156 u_char asr, *buf = bp; 1157 1158 QPRINTF(("wd33c93_xfout {%d} %02x %02x %02x %02x %02x " 1159 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1160 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1161 1162 /* 1163 * sigh.. WD-PROTO strikes again.. sending the command in one go 1164 * causes the chip to lock up if talking to certain (misbehaving?) 1165 * targets. Anyway, this procedure should work for all targets, but 1166 * it's slightly slower due to the overhead 1167 */ 1168 1169 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1170 SBIC_TC_PUT (dev, (unsigned)len); 1171 1172 WAIT_CIP (dev); 1173 SET_SBIC_cmd (dev, SBIC_CMD_XFER_INFO); 1174 1175 /* 1176 * Loop for each byte transferred 1177 */ 1178 do { 1179 GET_SBIC_asr (dev, asr); 1180 1181 if (asr & SBIC_ASR_DBR) { 1182 if (len) { 1183 SET_SBIC_data (dev, *buf); 1184 buf++; 1185 len--; 1186 } else { 1187 SET_SBIC_data (dev, 0); 1188 } 1189 wait = wd33c93_data_wait; 1190 } 1191 } while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1192 1193 QPRINTF(("wd33c93_xfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1194 1195 /* 1196 * Normally, an interrupt will be pending when this routing returns. 1197 */ 1198 return(len); 1199 } 1200 1201 /* 1202 * Information Transfer *from* a Scsi Target 1203 * returns # bytes left to read 1204 */ 1205 int 1206 wd33c93_xfin(struct wd33c93_softc *dev, int len, void *bp) 1207 { 1208 int wait = wd33c93_data_wait; 1209 u_char *buf = bp; 1210 u_char asr; 1211 #ifdef DEBUG 1212 u_char *obp = bp; 1213 #endif 1214 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1215 SBIC_TC_PUT (dev, (unsigned)len); 1216 1217 WAIT_CIP (dev); 1218 SET_SBIC_cmd (dev, SBIC_CMD_XFER_INFO); 1219 1220 /* 1221 * Loop for each byte transferred 1222 */ 1223 do { 1224 GET_SBIC_asr (dev, asr); 1225 1226 if (asr & SBIC_ASR_DBR) { 1227 if (len) { 1228 GET_SBIC_data (dev, *buf); 1229 buf++; 1230 len--; 1231 } else { 1232 u_char foo; 1233 GET_SBIC_data (dev, foo); 1234 } 1235 wait = wd33c93_data_wait; 1236 } 1237 1238 } while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1239 1240 QPRINTF(("wd33c93_xfin {%d} %02x %02x %02x %02x %02x %02x " 1241 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1242 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1243 1244 SBIC_TC_PUT (dev, 0); 1245 1246 /* 1247 * this leaves with one csr to be read 1248 */ 1249 return len; 1250 } 1251 1252 1253 /* 1254 * Finish SCSI xfer command: After the completion interrupt from 1255 * a read/write operation, sequence through the final phases in 1256 * programmed i/o. 1257 */ 1258 void 1259 wd33c93_xferdone(struct wd33c93_softc *dev) 1260 { 1261 u_char phase, csr; 1262 int s; 1263 1264 QPRINTF(("{")); 1265 s = splbio(); 1266 1267 /* 1268 * have the wd33c93 complete on its own 1269 */ 1270 SBIC_TC_PUT(dev, 0); 1271 SET_SBIC_cmd_phase(dev, 0x46); 1272 SET_SBIC_cmd(dev, SBIC_CMD_SEL_ATN_XFER); 1273 1274 do { 1275 SBIC_WAIT (dev, SBIC_ASR_INT, 0); 1276 GET_SBIC_csr (dev, csr); 1277 QPRINTF(("%02x:", csr)); 1278 } while ((csr != SBIC_CSR_DISC) && 1279 (csr != SBIC_CSR_DISC_1) && 1280 (csr != SBIC_CSR_S_XFERRED)); 1281 1282 dev->sc_flags &= ~SBICF_SELECTED; 1283 dev->sc_state = SBIC_DISCONNECT; 1284 1285 GET_SBIC_cmd_phase (dev, phase); 1286 QPRINTF(("}%02x", phase)); 1287 1288 if (phase == 0x60) 1289 GET_SBIC_tlun(dev, dev->sc_status); 1290 else 1291 wd33c93_error(dev, dev->sc_nexus); 1292 1293 QPRINTF(("=STS:%02x=\n", dev->sc_status)); 1294 splx(s); 1295 } 1296 1297 1298 int 1299 wd33c93_go(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 1300 { 1301 struct scsipi_xfer *xs = acb->xs; 1302 int i, dmaok; 1303 u_char csr, asr; 1304 1305 SBIC_DEBUG(ACBS, ("wd33c93_go(%d:%d)\n", dev->target, dev->lun)); 1306 1307 dev->sc_nexus = acb; 1308 1309 dev->target = xs->xs_periph->periph_target; 1310 dev->lun = xs->xs_periph->periph_lun; 1311 1312 dev->sc_status = STATUS_UNKNOWN; 1313 dev->sc_daddr = acb->daddr; 1314 dev->sc_dleft = acb->dleft; 1315 1316 dev->sc_msgpriq = dev->sc_msgout = dev->sc_msgoutq = 0; 1317 dev->sc_flags = 0; 1318 1319 dmaok = wd33c93_dmaok(dev, xs); 1320 1321 if (dmaok == 0) 1322 dev->sc_flags |= SBICF_NODMA; 1323 1324 SBIC_DEBUG(DMA, ("wd33c93_go dmago:%d(tcnt=%zx) dmaok=%dx\n", 1325 dev->target, dev->sc_tcnt, dmaok)); 1326 1327 /* select the SCSI bus (it's an error if bus isn't free) */ 1328 if ((csr = wd33c93_selectbus(dev, acb)) == 0) 1329 return(0); /* Not done: needs to be rescheduled */ 1330 1331 /* 1332 * Lets cycle a while then let the interrupt handler take over. 1333 */ 1334 GET_SBIC_asr(dev, asr); 1335 do { 1336 QPRINTF(("go[0x%x] ", csr)); 1337 1338 /* Handle the new phase */ 1339 i = wd33c93_nextstate(dev, acb, csr, asr); 1340 WAIT_CIP(dev); /* XXX */ 1341 if (dev->sc_state == SBIC_CONNECTED) { 1342 1343 GET_SBIC_asr(dev, asr); 1344 1345 if (asr & SBIC_ASR_LCI) 1346 printf("wd33c93_go: LCI asr:%02x csr:%02x\n", asr, csr); 1347 1348 if (asr & SBIC_ASR_INT) 1349 GET_SBIC_csr(dev, csr); 1350 } 1351 1352 } while (dev->sc_state == SBIC_CONNECTED && 1353 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1354 1355 QPRINTF(("> done i=%d stat=%02x\n", i, dev->sc_status)); 1356 1357 if (i == SBIC_STATE_DONE) { 1358 if (dev->sc_status == STATUS_UNKNOWN) { 1359 printf("wd33c93_go: done & stat == UNKNOWN\n"); 1360 return 1; /* Did we really finish that fast? */ 1361 } 1362 } 1363 return 0; 1364 } 1365 1366 1367 int 1368 wd33c93_intr(struct wd33c93_softc *dev) 1369 { 1370 u_char asr, csr; 1371 int i; 1372 1373 /* 1374 * pending interrupt? 1375 */ 1376 GET_SBIC_asr (dev, asr); 1377 if ((asr & SBIC_ASR_INT) == 0) 1378 return(0); 1379 1380 GET_SBIC_csr(dev, csr); 1381 1382 do { 1383 SBIC_DEBUG(INTS, ("intr[csr=0x%x]", csr)); 1384 1385 i = wd33c93_nextstate(dev, dev->sc_nexus, csr, asr); 1386 WAIT_CIP(dev); /* XXX */ 1387 if (dev->sc_state == SBIC_CONNECTED) { 1388 GET_SBIC_asr(dev, asr); 1389 1390 if (asr & SBIC_ASR_LCI) 1391 printf("wd33c93_intr: LCI asr:%02x csr:%02x\n", 1392 asr, csr); 1393 1394 if (asr & SBIC_ASR_INT) 1395 GET_SBIC_csr(dev, csr); 1396 } 1397 } while (dev->sc_state == SBIC_CONNECTED && 1398 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1399 1400 SBIC_DEBUG(INTS, ("intr done. state=%d, asr=0x%02x\n", i, asr)); 1401 1402 return(1); 1403 } 1404 1405 /* 1406 * Complete current command using polled I/O. Used when interrupt driven 1407 * I/O is not allowed (ie. during boot and shutdown) 1408 * 1409 * Polled I/O is very processor intensive 1410 */ 1411 int 1412 wd33c93_poll(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 1413 { 1414 u_char asr, csr=0; 1415 int i, count; 1416 struct scsipi_xfer *xs = acb->xs; 1417 1418 SBIC_WAIT(dev, SBIC_ASR_INT, wd33c93_cmd_wait); 1419 for (count=acb->timeout; count;) { 1420 GET_SBIC_asr (dev, asr); 1421 if (asr & SBIC_ASR_LCI) 1422 printf("wd33c93_poll: LCI; asr:%02x csr:%02x\n", 1423 asr, csr); 1424 if (asr & SBIC_ASR_INT) { 1425 GET_SBIC_csr(dev, csr); 1426 dev->sc_flags |= SBICF_NODMA; 1427 i = wd33c93_nextstate(dev, dev->sc_nexus, csr, asr); 1428 WAIT_CIP(dev); /* XXX */ 1429 } else { 1430 DELAY(1000); 1431 count--; 1432 } 1433 1434 if ((xs->xs_status & XS_STS_DONE) != 0) 1435 return (0); 1436 1437 if (dev->sc_state == SBIC_IDLE) { 1438 SBIC_DEBUG(ACBS, ("[poll: rescheduling] ")); 1439 wd33c93_sched(dev); 1440 } 1441 } 1442 return (1); 1443 } 1444 1445 static inline int 1446 __verify_msg_format(u_char *p, int len) 1447 { 1448 1449 if (len == 1 && MSG_IS1BYTE(p[0])) 1450 return 1; 1451 if (len == 2 && MSG_IS2BYTE(p[0])) 1452 return 1; 1453 if (len >= 3 && MSG_ISEXTENDED(p[0]) && 1454 len == p[1] + 2) 1455 return 1; 1456 return 0; 1457 } 1458 1459 /* 1460 * Handle message_in phase 1461 */ 1462 int 1463 wd33c93_msgin_phase(struct wd33c93_softc *dev, int reselect) 1464 { 1465 int len; 1466 u_char asr, csr, *msg; 1467 1468 GET_SBIC_asr(dev, asr); 1469 1470 SBIC_DEBUG(MSGS, ("wd33c93msgin asr=%02x\n", asr)); 1471 1472 GET_SBIC_selid (dev, csr); 1473 SET_SBIC_selid (dev, csr | SBIC_SID_FROM_SCSI); 1474 1475 SBIC_TC_PUT(dev, 0); 1476 1477 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1478 1479 msg = dev->sc_imsg; 1480 len = 0; 1481 1482 do { 1483 /* Fetch the next byte of the message */ 1484 RECV_BYTE(dev, *msg++); 1485 len++; 1486 1487 /* 1488 * get the command completion interrupt, or we 1489 * can't send a new command (LCI) 1490 */ 1491 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1492 GET_SBIC_csr(dev, csr); 1493 1494 if (__verify_msg_format(dev->sc_imsg, len)) 1495 break; /* Complete message recieved */ 1496 1497 /* 1498 * Clear ACK, and wait for the interrupt 1499 * for the next byte or phase change 1500 */ 1501 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1502 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1503 1504 GET_SBIC_csr(dev, csr); 1505 } while (len < SBIC_MAX_MSGLEN); 1506 1507 if (__verify_msg_format(dev->sc_imsg, len)) 1508 wd33c93_msgin(dev, dev->sc_imsg, len); 1509 1510 /* 1511 * Clear ACK, and wait for the interrupt 1512 * for the phase change 1513 */ 1514 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1515 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1516 1517 /* Should still have one CSR to read */ 1518 return SBIC_STATE_RUNNING; 1519 } 1520 1521 1522 void wd33c93_msgin(struct wd33c93_softc *dev, u_char *msgaddr, int msglen) 1523 { 1524 struct wd33c93_acb *acb = dev->sc_nexus; 1525 struct wd33c93_tinfo *ti = &dev->sc_tinfo[dev->target]; 1526 struct wd33c93_linfo *li; 1527 u_char asr; 1528 1529 switch (dev->sc_state) { 1530 case SBIC_CONNECTED: 1531 switch (msgaddr[0]) { 1532 case MSG_MESSAGE_REJECT: 1533 SBIC_DEBUG(MSGS, ("msgin: MSG_REJECT, " 1534 "last msgout=%x\n", dev->sc_msgout)); 1535 switch (dev->sc_msgout) { 1536 case SEND_TAG: 1537 printf("%s: tagged queuing rejected: " 1538 "target %d\n", 1539 dev->sc_dev.dv_xname, dev->target); 1540 ti->flags &= ~T_TAG; 1541 li = TINFO_LUN(ti, dev->lun); 1542 if (acb->tag_type && 1543 li->queued[acb->tag_id] != NULL) { 1544 li->queued[acb->tag_id] = NULL; 1545 li->used--; 1546 } 1547 acb->tag_type = acb->tag_id = 0; 1548 li->untagged = acb; 1549 li->state = L_STATE_BUSY; 1550 break; 1551 1552 case SEND_SDTR: 1553 printf("%s: sync transfer rejected: target %d\n", 1554 dev->sc_dev.dv_xname, dev->target); 1555 1556 dev->sc_flags &= ~SBICF_SYNCNEGO; 1557 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1558 wd33c93_update_xfer_mode(dev, 1559 acb->xs->xs_periph->periph_target); 1560 wd33c93_setsync(dev, ti); 1561 1562 case SEND_INIT_DET_ERR: 1563 goto abort; 1564 1565 default: 1566 SBIC_DEBUG(MSGS, ("Unexpected MSG_REJECT\n")); 1567 break; 1568 } 1569 dev->sc_msgout = 0; 1570 break; 1571 1572 case MSG_HEAD_OF_Q_TAG: 1573 case MSG_ORDERED_Q_TAG: 1574 case MSG_SIMPLE_Q_TAG: 1575 printf("-- Out of phase TAG;" 1576 "Nexus=%d:%d Tag=%02x/%02x\n", 1577 dev->target, dev->lun, msgaddr[0], msgaddr[1]); 1578 break; 1579 1580 case MSG_DISCONNECT: 1581 SBIC_DEBUG(MSGS, ("msgin: DISCONNECT")); 1582 /* 1583 * Mark the fact that all bytes have moved. The 1584 * target may not bother to do a SAVE POINTERS 1585 * at this stage. This flag will set the residual 1586 * count to zero on MSG COMPLETE. 1587 */ 1588 if (dev->sc_dleft == 0) 1589 acb->flags |= ACB_COMPLETE; 1590 1591 if (acb->xs->xs_control & XS_CTL_POLL) 1592 /* Don't allow disconnect in immediate mode */ 1593 goto reject; 1594 else { /* Allow disconnect */ 1595 dev->sc_flags &= ~SBICF_SELECTED; 1596 dev->sc_state = SBIC_DISCONNECT; 1597 } 1598 if ((acb->xs->xs_periph->periph_quirks & 1599 PQUIRK_AUTOSAVE) == 0) 1600 break; 1601 /*FALLTHROUGH*/ 1602 1603 case MSG_SAVEDATAPOINTER: 1604 SBIC_DEBUG(MSGS, ("msgin: SAVEDATAPTR")); 1605 acb->daddr = dev->sc_daddr; 1606 acb->dleft = dev->sc_dleft; 1607 break; 1608 1609 case MSG_RESTOREPOINTERS: 1610 SBIC_DEBUG(MSGS, ("msgin: RESTOREPTR")); 1611 dev->sc_daddr = acb->daddr; 1612 dev->sc_dleft = acb->dleft; 1613 break; 1614 1615 case MSG_CMDCOMPLETE: 1616 /* 1617 * !! KLUDGE ALERT !! quite a few drives don't seem to 1618 * really like the current way of sending the 1619 * sync-handshake together with the ident-message, and 1620 * they react by sending command-complete and 1621 * disconnecting right after returning the valid sync 1622 * handshake. So, all I can do is reselect the drive, 1623 * and hope it won't disconnect again. I don't think 1624 * this is valid behavior, but I can't help fixing a 1625 * problem that apparently exists. 1626 * 1627 * Note: we should not get here on `normal' command 1628 * completion, as that condition is handled by the 1629 * high-level sel&xfer resume command used to walk 1630 * thru status/cc-phase. 1631 */ 1632 SBIC_DEBUG(MSGS, ("msgin: CMD_COMPLETE")); 1633 SBIC_DEBUG(SYNC, ("GOT MSG %d! target %d" 1634 " acting weird.." 1635 " waiting for disconnect...\n", 1636 msgaddr[0], dev->target)); 1637 1638 /* Check to see if wd33c93 is handling this */ 1639 GET_SBIC_asr(dev, asr); 1640 if (asr & SBIC_ASR_BSY) 1641 break; 1642 1643 /* XXX: Assume it works and set status to 00 */ 1644 dev->sc_status = 0; 1645 dev->sc_state = SBIC_CMDCOMPLETE; 1646 break; 1647 1648 case MSG_EXTENDED: 1649 switch(msgaddr[2]) { 1650 case MSG_EXT_SDTR: /* Sync negotiation */ 1651 SBIC_DEBUG(MSGS, ("msgin: EXT_SDTR; " 1652 "period %d, offset %d", 1653 msgaddr[3], msgaddr[4])); 1654 if (msgaddr[1] != 3) 1655 goto reject; 1656 1657 ti->period = 1658 MAX(msgaddr[3], dev->sc_minsyncperiod); 1659 ti->offset = MIN(msgaddr[4], dev->sc_maxoffset); 1660 if (!(ti->flags & T_WANTSYNC)) 1661 ti->period = ti->offset = 0; 1662 1663 ti->flags &= ~T_NEGOTIATE; 1664 1665 if (ti->offset == 0) 1666 ti->flags &= ~T_SYNCMODE; /* Async */ 1667 else 1668 ti->flags |= T_SYNCMODE; /* Sync */ 1669 1670 if ((dev->sc_flags&SBICF_SYNCNEGO) == 0) 1671 /* target initiated negotiation */ 1672 wd33c93_sched_msgout(dev, SEND_SDTR); 1673 dev->sc_flags &= ~SBICF_SYNCNEGO; 1674 1675 SBIC_DEBUG(SYNC, ("msgin(%d): SDTR(o=%d,p=%d)", 1676 dev->target, ti->offset, 1677 ti->period)); 1678 wd33c93_update_xfer_mode(dev, 1679 acb->xs->xs_periph->periph_target); 1680 wd33c93_setsync(dev, ti); 1681 break; 1682 1683 case MSG_EXT_WDTR: 1684 SBIC_DEBUG(MSGS, ("msgin: EXT_WDTR rejected")); 1685 goto reject; 1686 1687 default: 1688 scsipi_printaddr(acb->xs->xs_periph); 1689 printf("unrecognized MESSAGE EXTENDED;" 1690 " sending REJECT\n"); 1691 goto reject; 1692 } 1693 break; 1694 1695 default: 1696 scsipi_printaddr(acb->xs->xs_periph); 1697 printf("unrecognized MESSAGE; sending REJECT\n"); 1698 1699 reject: 1700 /* We don't support whatever this message is... */ 1701 wd33c93_sched_msgout(dev, SEND_REJECT); 1702 break; 1703 } 1704 break; 1705 1706 case SBIC_IDENTIFIED: 1707 /* 1708 * IDENTIFY message was received and queue tag is expected now 1709 */ 1710 if ((msgaddr[0]!=MSG_SIMPLE_Q_TAG) || (dev->sc_msgify==0)) { 1711 printf("%s: TAG reselect without IDENTIFY;" 1712 " MSG %x; sending DEVICE RESET\n", 1713 dev->sc_dev.dv_xname, msgaddr[0]); 1714 goto reset; 1715 } 1716 SBIC_DEBUG(TAGS, ("TAG %x/%x\n", msgaddr[0], msgaddr[1])); 1717 if (dev->sc_nexus) 1718 printf("*TAG Recv with active nexus!!\n"); 1719 wd33c93_reselect(dev, dev->target, dev->lun, 1720 msgaddr[0], msgaddr[1]); 1721 break; 1722 1723 case SBIC_RESELECTED: 1724 /* 1725 * IDENTIFY message with target 1726 */ 1727 if (MSG_ISIDENTIFY(msgaddr[0])) { 1728 SBIC_DEBUG(PHASE, ("IFFY[%x] ", msgaddr[0])); 1729 dev->sc_msgify = msgaddr[0]; 1730 } else { 1731 printf("%s: reselect without IDENTIFY;" 1732 " MSG %x;" 1733 " sending DEVICE RESET\n", 1734 dev->sc_dev.dv_xname, msgaddr[0]); 1735 goto reset; 1736 } 1737 break; 1738 1739 default: 1740 printf("Unexpected MESSAGE IN. State=%d - Sending RESET\n", 1741 dev->sc_state); 1742 reset: 1743 wd33c93_sched_msgout(dev, SEND_DEV_RESET); 1744 break; 1745 abort: 1746 wd33c93_sched_msgout(dev, SEND_ABORT); 1747 break; 1748 } 1749 } 1750 1751 void 1752 wd33c93_sched_msgout(struct wd33c93_softc *dev, u_short msg) 1753 { 1754 u_char asr; 1755 1756 SBIC_DEBUG(SYNC,("sched_msgout: %04x\n", msg)); 1757 dev->sc_msgpriq |= msg; 1758 1759 /* Schedule MSGOUT Phase to send message */ 1760 1761 WAIT_CIP(dev); 1762 SET_SBIC_cmd(dev, SBIC_CMD_SET_ATN); 1763 WAIT_CIP(dev); 1764 GET_SBIC_asr(dev, asr); 1765 if (asr & SBIC_ASR_LCI) { 1766 printf("MSGOUT Failed!\n"); 1767 } 1768 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1769 WAIT_CIP(dev); 1770 } 1771 1772 /* 1773 * Send the highest priority, scheduled message 1774 */ 1775 void 1776 wd33c93_msgout(struct wd33c93_softc *dev) 1777 { 1778 struct wd33c93_tinfo *ti; 1779 struct wd33c93_acb *acb = dev->sc_nexus; 1780 1781 if (acb == NULL) 1782 panic("MSGOUT with no nexus"); 1783 1784 if (dev->sc_omsglen == 0) { 1785 /* Pick up highest priority message */ 1786 dev->sc_msgout = dev->sc_msgpriq & -dev->sc_msgpriq; 1787 dev->sc_msgoutq |= dev->sc_msgout; 1788 dev->sc_msgpriq &= ~dev->sc_msgout; 1789 dev->sc_omsglen = 1; /* "Default" message len */ 1790 switch (dev->sc_msgout) { 1791 case SEND_SDTR: 1792 ti = &dev->sc_tinfo[acb->xs->xs_periph->periph_target]; 1793 dev->sc_omsg[0] = MSG_EXTENDED; 1794 dev->sc_omsg[1] = MSG_EXT_SDTR_LEN; 1795 dev->sc_omsg[2] = MSG_EXT_SDTR; 1796 if (ti->flags & T_WANTSYNC) { 1797 dev->sc_omsg[3] = ti->period; 1798 dev->sc_omsg[4] = ti->offset; 1799 } else { 1800 dev->sc_omsg[3] = 0; 1801 dev->sc_omsg[4] = 0; 1802 } 1803 dev->sc_omsglen = 5; 1804 if ((dev->sc_flags & SBICF_SYNCNEGO) == 0) { 1805 if (ti->flags & T_WANTSYNC) 1806 ti->flags |= T_SYNCMODE; 1807 else 1808 ti->flags &= ~T_SYNCMODE; 1809 wd33c93_setsync(dev, ti); 1810 } 1811 break; 1812 case SEND_IDENTIFY: 1813 if (dev->sc_state != SBIC_CONNECTED) { 1814 printf("%s at line %d: no nexus\n", 1815 dev->sc_dev.dv_xname, __LINE__); 1816 } 1817 dev->sc_omsg[0] = 1818 MSG_IDENTIFY(acb->xs->xs_periph->periph_lun, 0); 1819 break; 1820 case SEND_TAG: 1821 if (dev->sc_state != SBIC_CONNECTED) { 1822 printf("%s at line %d: no nexus\n", 1823 dev->sc_dev.dv_xname, __LINE__); 1824 } 1825 dev->sc_omsg[0] = acb->tag_type; 1826 dev->sc_omsg[1] = acb->tag_id; 1827 dev->sc_omsglen = 2; 1828 break; 1829 case SEND_DEV_RESET: 1830 dev->sc_omsg[0] = MSG_BUS_DEV_RESET; 1831 ti = &dev->sc_tinfo[dev->target]; 1832 ti->flags &= ~T_SYNCMODE; 1833 wd33c93_update_xfer_mode(dev, dev->target); 1834 if ((ti->flags & T_NOSYNC) == 0) 1835 /* We can re-start sync negotiation */ 1836 ti->flags |= T_NEGOTIATE; 1837 break; 1838 case SEND_PARITY_ERROR: 1839 dev->sc_omsg[0] = MSG_PARITY_ERROR; 1840 break; 1841 case SEND_ABORT: 1842 dev->sc_flags |= SBICF_ABORTING; 1843 dev->sc_omsg[0] = MSG_ABORT; 1844 break; 1845 case SEND_INIT_DET_ERR: 1846 dev->sc_omsg[0] = MSG_INITIATOR_DET_ERR; 1847 break; 1848 case SEND_REJECT: 1849 dev->sc_omsg[0] = MSG_MESSAGE_REJECT; 1850 break; 1851 default: 1852 /* Wasn't expecting MSGOUT Phase */ 1853 dev->sc_omsg[0] = MSG_NOOP; 1854 break; 1855 } 1856 } 1857 1858 wd33c93_xfout(dev, dev->sc_omsglen, dev->sc_omsg); 1859 } 1860 1861 1862 /* 1863 * wd33c93_nextstate() 1864 * return: 1865 * SBIC_STATE_DONE == done 1866 * SBIC_STATE_RUNNING == working 1867 * SBIC_STATE_DISCONNECT == disconnected 1868 * SBIC_STATE_ERROR == error 1869 */ 1870 int 1871 wd33c93_nextstate(struct wd33c93_softc *dev, struct wd33c93_acb *acb, u_char csr, u_char asr) 1872 { 1873 SBIC_DEBUG(PHASE, ("next[a=%02x,c=%02x]: ",asr,csr)); 1874 1875 switch (csr) { 1876 1877 case SBIC_CSR_XFERRED | CMD_PHASE: 1878 case SBIC_CSR_MIS | CMD_PHASE: 1879 case SBIC_CSR_MIS_1 | CMD_PHASE: 1880 case SBIC_CSR_MIS_2 | CMD_PHASE: 1881 1882 if (wd33c93_xfout(dev, acb->clen, &acb->cmd)) 1883 goto abort; 1884 break; 1885 1886 case SBIC_CSR_XFERRED | STATUS_PHASE: 1887 case SBIC_CSR_MIS | STATUS_PHASE: 1888 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1889 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1890 1891 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1892 1893 /* 1894 * this should be the normal i/o completion case. 1895 * get the status & cmd complete msg then let the 1896 * device driver look at what happened. 1897 */ 1898 wd33c93_xferdone(dev); 1899 1900 wd33c93_dma_stop(dev); 1901 1902 /* Fixup byte count to be passed to higher layer */ 1903 acb->dleft = (acb->flags & ACB_COMPLETE) ? 0 : 1904 dev->sc_dleft; 1905 1906 /* 1907 * Indicate to the upper layers that the command is done 1908 */ 1909 wd33c93_scsidone(dev, acb, dev->sc_status); 1910 1911 return SBIC_STATE_DONE; 1912 1913 1914 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 1915 case SBIC_CSR_MIS | DATA_IN_PHASE: 1916 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 1917 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 1918 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 1919 case SBIC_CSR_MIS | DATA_OUT_PHASE: 1920 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 1921 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 1922 /* 1923 * Verify that we expected to transfer data... 1924 */ 1925 if (acb->dleft <= 0) { 1926 printf("next: DATA phase with xfer count == %zd, asr:0x%02x csr:0x%02x\n", 1927 acb->dleft, asr, csr); 1928 goto abort; 1929 } 1930 1931 /* 1932 * Should we transfer using PIO or DMA ? 1933 */ 1934 if (acb->xs->xs_control & XS_CTL_POLL || 1935 dev->sc_flags & SBICF_NODMA) { 1936 /* Perfrom transfer using PIO */ 1937 int resid; 1938 1939 SBIC_DEBUG(DMA, ("PIO xfer: %d(%p:%zx)\n", dev->target, 1940 dev->sc_daddr, dev->sc_dleft)); 1941 1942 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 1943 /* data in */ 1944 resid = wd33c93_xfin(dev, dev->sc_dleft, 1945 dev->sc_daddr); 1946 else /* data out */ 1947 resid = wd33c93_xfout(dev, dev->sc_dleft, 1948 dev->sc_daddr); 1949 1950 dev->sc_daddr = (char*)dev->sc_daddr + 1951 (acb->dleft - resid); 1952 dev->sc_dleft = resid; 1953 } else { 1954 int datain = SBIC_PHASE(csr) == DATA_IN_PHASE; 1955 1956 /* Perform transfer using DMA */ 1957 wd33c93_dma_setup(dev, datain); 1958 1959 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI | 1960 dev->sc_dmamode); 1961 1962 SBIC_DEBUG(DMA, ("DMA xfer: %d(%p:%zx)\n", dev->target, 1963 dev->sc_daddr, dev->sc_dleft)); 1964 1965 /* Setup byte count for transfer */ 1966 SBIC_TC_PUT(dev, (unsigned)dev->sc_dleft); 1967 1968 /* Start the transfer */ 1969 SET_SBIC_cmd(dev, SBIC_CMD_XFER_INFO); 1970 1971 /* Start the DMA chip going */ 1972 dev->sc_tcnt = dev->sc_dmago(dev); 1973 1974 /* Indicate that we're in DMA mode */ 1975 dev->sc_flags |= SBICF_INDMA; 1976 } 1977 break; 1978 1979 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 1980 case SBIC_CSR_MIS | MESG_IN_PHASE: 1981 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 1982 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 1983 1984 wd33c93_dma_stop(dev); 1985 1986 /* Handle a single message in... */ 1987 return wd33c93_msgin_phase(dev, 0); 1988 1989 case SBIC_CSR_MSGIN_W_ACK: 1990 1991 /* 1992 * We should never see this since it's handled in 1993 * 'wd33c93_msgin_phase()' but just for the sake of paranoia... 1994 */ 1995 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1996 1997 printf("Acking unknown msgin CSR:%02x",csr); 1998 break; 1999 2000 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2001 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2002 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2003 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2004 2005 /* 2006 * Message out phase. ATN signal has been asserted 2007 */ 2008 wd33c93_dma_stop(dev); 2009 wd33c93_msgout(dev); 2010 return SBIC_STATE_RUNNING; 2011 2012 case SBIC_CSR_DISC: 2013 case SBIC_CSR_DISC_1: 2014 SBIC_DEBUG(RSEL, ("wd33c93next target %d disconnected\n", 2015 dev->target)); 2016 wd33c93_dma_stop(dev); 2017 2018 dev->sc_nexus = NULL; 2019 dev->sc_state = SBIC_IDLE; 2020 dev->sc_flags = 0; 2021 2022 ++dev->sc_tinfo[dev->target].dconns; 2023 ++dev->sc_disc; 2024 2025 if (acb->xs->xs_control & XS_CTL_POLL || wd33c93_nodisc) 2026 return SBIC_STATE_DISCONNECT; 2027 2028 /* Try to schedule another target */ 2029 wd33c93_sched(dev); 2030 2031 return SBIC_STATE_DISCONNECT; 2032 2033 case SBIC_CSR_RSLT_NI: 2034 case SBIC_CSR_RSLT_IFY: 2035 { 2036 /* 2037 * A reselection. 2038 * Note that since we don't enable Advanced Features (assuming 2039 * the WD chip is at least the 'A' revision), we're only ever 2040 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2041 * hell of it, we'll handle it anyway, for all the extra code 2042 * it needs... 2043 */ 2044 u_char newtarget, newlun; 2045 2046 if (dev->sc_flags & SBICF_INDMA) { 2047 printf("**** RESELECT WHILE DMA ACTIVE!!! ***\n"); 2048 wd33c93_dma_stop(dev); 2049 } 2050 2051 dev->sc_state = SBIC_RESELECTED; 2052 GET_SBIC_rselid(dev, newtarget); 2053 2054 /* check SBIC_RID_SIV? */ 2055 newtarget &= SBIC_RID_MASK; 2056 2057 if (csr == SBIC_CSR_RSLT_IFY) { 2058 /* Read Identify msg to avoid lockup */ 2059 GET_SBIC_data(dev, newlun); 2060 WAIT_CIP(dev); 2061 newlun &= SBIC_TLUN_MASK; 2062 dev->sc_msgify = MSG_IDENTIFY(newlun, 0); 2063 } else { 2064 /* 2065 * Need to read Identify message the hard way, assuming 2066 * the target even sends us one... 2067 */ 2068 for (newlun = 255; newlun; --newlun) { 2069 GET_SBIC_asr(dev, asr); 2070 if (asr & SBIC_ASR_INT) 2071 break; 2072 DELAY(10); 2073 } 2074 2075 /* If we didn't get an interrupt, somethink's up */ 2076 if ((asr & SBIC_ASR_INT) == 0) { 2077 printf("%s: Reselect without identify? asr %x\n", 2078 dev->sc_dev.dv_xname, asr); 2079 newlun = 0; /* XXXX */ 2080 } else { 2081 /* 2082 * We got an interrupt, verify that it's a 2083 * change to message in phase, and if so 2084 * read the message. 2085 */ 2086 GET_SBIC_csr(dev,csr); 2087 2088 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2089 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2090 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2091 /* 2092 * Yup, gone to message in. 2093 * Fetch the target LUN 2094 */ 2095 dev->sc_msgify = 0; 2096 wd33c93_msgin_phase(dev, 1); 2097 newlun = dev->sc_msgify & SBIC_TLUN_MASK; 2098 } else { 2099 /* 2100 * Whoops! Target didn't go to msg_in 2101 * phase!! 2102 */ 2103 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2104 newlun = 0; /* XXXSCW */ 2105 } 2106 } 2107 } 2108 2109 /* Ok, we have the identity of the reselecting target. */ 2110 SBIC_DEBUG(RSEL, ("wd33c93next: reselect from targ %d lun %d", 2111 newtarget, newlun)); 2112 wd33c93_reselect(dev, newtarget, newlun, 0, 0); 2113 dev->sc_disc--; 2114 2115 if (csr == SBIC_CSR_RSLT_IFY) 2116 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 2117 break; 2118 } 2119 2120 default: 2121 abort: 2122 /* Something unexpected happend -- deal with it. */ 2123 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2124 2125 #ifdef DDB 2126 Debugger(); 2127 #endif 2128 2129 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 2130 if (acb->xs) 2131 wd33c93_error(dev, acb); 2132 wd33c93_abort(dev, acb, "next"); 2133 2134 if (dev->sc_flags & SBICF_INDMA) { 2135 wd33c93_dma_stop(dev); 2136 wd33c93_scsidone(dev, acb, STATUS_UNKNOWN); 2137 } 2138 return SBIC_STATE_ERROR; 2139 } 2140 return SBIC_STATE_RUNNING; 2141 } 2142 2143 2144 void 2145 wd33c93_reselect(struct wd33c93_softc *dev, int target, int lun, int tag_type, int tag_id) 2146 { 2147 2148 struct wd33c93_tinfo *ti; 2149 struct wd33c93_linfo *li; 2150 struct wd33c93_acb *acb; 2151 2152 if (dev->sc_nexus) { 2153 /* 2154 * Whoops! We've been reselected with a 2155 * command in progress! 2156 * The best we can do is to put the current 2157 * command back on the ready list and hope 2158 * for the best. 2159 */ 2160 SBIC_DEBUG(RSEL, ("%s: reselect with active command\n", 2161 dev->sc_dev.dv_xname)); 2162 ti = &dev->sc_tinfo[dev->target]; 2163 li = TINFO_LUN(ti, dev->lun); 2164 li->state = L_STATE_IDLE; 2165 2166 wd33c93_dequeue(dev, dev->sc_nexus); 2167 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2168 dev->sc_nexus->flags |= ACB_READY; 2169 2170 dev->sc_nexus = NULL; 2171 } 2172 2173 /* Setup state for new nexus */ 2174 acb = NULL; 2175 dev->sc_flags = SBICF_SELECTED; 2176 dev->sc_msgpriq = dev->sc_msgout = dev->sc_msgoutq = 0; 2177 2178 ti = &dev->sc_tinfo[target]; 2179 li = TINFO_LUN(ti, lun); 2180 2181 if (li != NULL) { 2182 if (li->untagged != NULL && li->state) 2183 acb = li->untagged; 2184 else if (tag_type != MSG_SIMPLE_Q_TAG) { 2185 /* Wait for tag to come by during MESG_IN Phase */ 2186 dev->target = target; /* setup I_T_L nexus */ 2187 dev->lun = lun; 2188 dev->sc_state = SBIC_IDENTIFIED; 2189 return; 2190 } else if (tag_type) 2191 acb = li->queued[tag_id]; 2192 } 2193 2194 if (acb == NULL) { 2195 printf("%s: reselect from target %d lun %d tag %x:%x " 2196 "with no nexus; sending ABORT\n", 2197 dev->sc_dev.dv_xname, target, lun, tag_type, tag_id); 2198 goto abort; 2199 } 2200 2201 dev->target = target; 2202 dev->lun = lun; 2203 dev->sc_nexus = acb; 2204 dev->sc_state = SBIC_CONNECTED; 2205 2206 if (!wd33c93_dmaok(dev, acb->xs)) 2207 dev->sc_flags |= SBICF_NODMA; 2208 2209 /* Do an implicit RESTORE POINTERS. */ 2210 dev->sc_daddr = acb->daddr; 2211 dev->sc_dleft = acb->dleft; 2212 2213 /* Set sync modes for new target */ 2214 wd33c93_setsync(dev, ti); 2215 2216 if (acb->flags & ACB_RESET) 2217 wd33c93_sched_msgout(dev, SEND_DEV_RESET); 2218 else if (acb->flags & ACB_ABORT) 2219 wd33c93_sched_msgout(dev, SEND_ABORT); 2220 return; 2221 2222 abort: 2223 wd33c93_sched_msgout(dev, SEND_ABORT); 2224 return; 2225 2226 } 2227 2228 void 2229 wd33c93_update_xfer_mode(struct wd33c93_softc *sc, int target) 2230 { 2231 struct wd33c93_tinfo *ti = &sc->sc_tinfo[target]; 2232 struct scsipi_xfer_mode xm; 2233 2234 xm.xm_target = target; 2235 xm.xm_mode = 0; 2236 xm.xm_period = 0; 2237 xm.xm_offset = 0; 2238 2239 if (ti->flags & T_SYNCMODE) { 2240 xm.xm_mode |= PERIPH_CAP_SYNC; 2241 xm.xm_period = ti->period; 2242 xm.xm_offset = ti->offset; 2243 } 2244 2245 if ((ti->flags & (T_NODISC|T_TAG)) == T_TAG) 2246 xm.xm_mode |= PERIPH_CAP_TQING; 2247 2248 SBIC_DEBUG(SYNC, ("wd33c93_update_xfer_mode: reporting target %d %s\n", 2249 xm.xm_target, 2250 (xm.xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 2251 2252 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 2253 } 2254 2255 void 2256 wd33c93_timeout(void *arg) 2257 { 2258 struct wd33c93_acb *acb = arg; 2259 struct scsipi_xfer *xs = acb->xs; 2260 struct scsipi_periph *periph = xs->xs_periph; 2261 struct wd33c93_softc *dev = 2262 (void *)periph->periph_channel->chan_adapter->adapt_dev; 2263 int s, asr; 2264 2265 s = splbio(); 2266 2267 GET_SBIC_asr(dev, asr); 2268 2269 scsipi_printaddr(periph); 2270 printf("%s: timed out; asr=0x%02x [acb %p (flags 0x%x, dleft %zx)], " 2271 "<state %d, nexus %p, resid %lx, msg(q %x,o %x)>", 2272 dev->sc_dev.dv_xname, asr, acb, acb->flags, acb->dleft, 2273 dev->sc_state, dev->sc_nexus, (long)dev->sc_dleft, 2274 dev->sc_msgpriq, dev->sc_msgout); 2275 2276 if (asr & SBIC_ASR_INT) { 2277 /* We need to service a missed IRQ */ 2278 wd33c93_intr(dev); 2279 } else { 2280 (void) wd33c93_abort(dev, dev->sc_nexus, "timeout"); 2281 } 2282 splx(s); 2283 } 2284 2285 2286 void 2287 wd33c93_watchdog(void *arg) 2288 { 2289 struct wd33c93_softc *dev = arg; 2290 struct wd33c93_tinfo *ti; 2291 struct wd33c93_linfo *li; 2292 int t, s, l; 2293 /* scrub LUN's that have not been used in the last 10min. */ 2294 time_t old = time_second - (10 * 60); 2295 2296 for (t = 0; t < SBIC_NTARG; t++) { 2297 ti = &dev->sc_tinfo[t]; 2298 for (l = 0; l < SBIC_NLUN; l++) { 2299 s = splbio(); 2300 li = TINFO_LUN(ti, l); 2301 if (li && li->last_used < old && 2302 li->untagged == NULL && li->used == 0) { 2303 ti->lun[li->lun] = NULL; 2304 free(li, M_DEVBUF); 2305 } 2306 splx(s); 2307 } 2308 } 2309 callout_reset(&dev->sc_watchdog, 60 * hz, wd33c93_watchdog, dev); 2310 } 2311 2312 2313 #ifdef DEBUG 2314 void 2315 wd33c93_hexdump(u_char *buf, int len) 2316 { 2317 printf("{%d}:", len); 2318 while (len--) 2319 printf(" %02x", *buf++); 2320 printf("\n"); 2321 } 2322 2323 2324 void 2325 wd33c93_print_csr(u_char csr) 2326 { 2327 switch (SCSI_PHASE(csr)) { 2328 case CMD_PHASE: 2329 printf("CMD_PHASE\n"); 2330 break; 2331 2332 case STATUS_PHASE: 2333 printf("STATUS_PHASE\n"); 2334 break; 2335 2336 case DATA_IN_PHASE: 2337 printf("DATAIN_PHASE\n"); 2338 break; 2339 2340 case DATA_OUT_PHASE: 2341 printf("DATAOUT_PHASE\n"); 2342 break; 2343 2344 case MESG_IN_PHASE: 2345 printf("MESG_IN_PHASE\n"); 2346 break; 2347 2348 case MESG_OUT_PHASE: 2349 printf("MESG_OUT_PHASE\n"); 2350 break; 2351 2352 default: 2353 switch (csr) { 2354 case SBIC_CSR_DISC_1: 2355 printf("DISC_1\n"); 2356 break; 2357 2358 case SBIC_CSR_RSLT_NI: 2359 printf("RESELECT_NO_IFY\n"); 2360 break; 2361 2362 case SBIC_CSR_RSLT_IFY: 2363 printf("RESELECT_IFY\n"); 2364 break; 2365 2366 case SBIC_CSR_SLT: 2367 printf("SELECT\n"); 2368 break; 2369 2370 case SBIC_CSR_SLT_ATN: 2371 printf("SELECT, ATN\n"); 2372 break; 2373 2374 case SBIC_CSR_UNK_GROUP: 2375 printf("UNK_GROUP\n"); 2376 break; 2377 2378 default: 2379 printf("UNKNOWN csr=%02x\n", csr); 2380 } 2381 } 2382 } 2383 #endif 2384
Indexes created Thu Sep 25 16:09:42 GMT 2025