wd33c93.c revision 1.13
1 /* $NetBSD: wd33c93.c,v 1.13 2007/05/08 00:29:30 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37 /* 38 * Changes Copyright (c) 2001 Wayne Knowles 39 * Changes Copyright (c) 1996 Steve Woodford 40 * Original Copyright (c) 1994 Christian E. Hopps 41 * 42 * This code is derived from software contributed to Berkeley by 43 * Van Jacobson of Lawrence Berkeley Laboratory. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 74 */ 75 76 /* 77 * This version of the driver is pretty well generic, so should work with 78 * any flavour of WD33C93 chip. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.13 2007/05/08 00:29:30 rumble Exp $"); 83 84 #include "opt_ddb.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> /* For hz */ 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsiconf.h> 96 #include <dev/scsipi/scsi_message.h> 97 98 #include <uvm/uvm_extern.h> 99 100 #include <machine/bus.h> 101 102 #include <dev/ic/wd33c93reg.h> 103 #include <dev/ic/wd33c93var.h> 104 105 /* 106 * SCSI delays 107 * In u-seconds, primarily for state changes on the SPC. 108 */ 109 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 110 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 111 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 112 113 #define STATUS_UNKNOWN 0xff /* uninitialized status */ 114 115 /* 116 * Convenience macro for waiting for a particular wd33c93 event 117 */ 118 #define SBIC_WAIT(regs, until, timeo) wd33c93_wait(regs, until, timeo, __LINE__) 119 120 void wd33c93_init (struct wd33c93_softc *); 121 void wd33c93_reset (struct wd33c93_softc *); 122 int wd33c93_go (struct wd33c93_softc *, struct wd33c93_acb *); 123 int wd33c93_dmaok (struct wd33c93_softc *, struct scsipi_xfer *); 124 int wd33c93_wait (struct wd33c93_softc *, u_char, int , int); 125 u_char wd33c93_selectbus (struct wd33c93_softc *, struct wd33c93_acb *); 126 int wd33c93_xfout (struct wd33c93_softc *, int, void *); 127 int wd33c93_xfin (struct wd33c93_softc *, int, void *); 128 int wd33c93_poll (struct wd33c93_softc *, struct wd33c93_acb *); 129 int wd33c93_nextstate (struct wd33c93_softc *, struct wd33c93_acb *, 130 u_char, u_char); 131 int wd33c93_abort (struct wd33c93_softc *, struct wd33c93_acb *, 132 const char *); 133 void wd33c93_xferdone (struct wd33c93_softc *); 134 void wd33c93_error (struct wd33c93_softc *, struct wd33c93_acb *); 135 void wd33c93_scsidone (struct wd33c93_softc *, struct wd33c93_acb *, int); 136 void wd33c93_sched (struct wd33c93_softc *); 137 void wd33c93_dequeue (struct wd33c93_softc *, struct wd33c93_acb *); 138 void wd33c93_dma_stop (struct wd33c93_softc *); 139 void wd33c93_dma_setup (struct wd33c93_softc *, int); 140 int wd33c93_msgin_phase (struct wd33c93_softc *, int); 141 void wd33c93_msgin (struct wd33c93_softc *, u_char *, int); 142 void wd33c93_reselect (struct wd33c93_softc *, int, int, int, int); 143 void wd33c93_sched_msgout (struct wd33c93_softc *, u_short); 144 void wd33c93_msgout (struct wd33c93_softc *); 145 void wd33c93_timeout (void *arg); 146 void wd33c93_watchdog (void *arg); 147 u_char wd33c93_stp2syn (struct wd33c93_softc *, struct wd33c93_tinfo *); 148 void wd33c93_setsync (struct wd33c93_softc *, struct wd33c93_tinfo *); 149 void wd33c93_update_xfer_mode (struct wd33c93_softc *, int); 150 151 static struct pool wd33c93_pool; /* Adapter Control Blocks */ 152 static int wd33c93_pool_initialized = 0; 153 154 /* 155 * Timeouts 156 */ 157 int wd33c93_cmd_wait = SBIC_CMD_WAIT; 158 int wd33c93_data_wait = SBIC_DATA_WAIT; 159 int wd33c93_init_wait = SBIC_INIT_WAIT; 160 161 int wd33c93_nodma = 0; /* Use polled IO transfers */ 162 int wd33c93_nodisc = 0; /* Allow command queues */ 163 int wd33c93_notags = 0; /* No Tags */ 164 165 /* 166 * Some useful stuff for debugging purposes 167 */ 168 #ifdef DEBUG 169 170 #define QPRINTF(a) SBIC_DEBUG(MISC, a) 171 172 int wd33c93_debug = 0; /* Debug flags */ 173 174 void wd33c93_print_csr (u_char); 175 void wd33c93_hexdump (u_char *, int); 176 177 #else 178 #define QPRINTF(a) /* */ 179 #endif 180 181 static const char *wd33c93_chip_names[] = SBIC_CHIP_LIST; 182 183 /* 184 * Attach instance of driver and probe for sub devices 185 */ 186 void 187 wd33c93_attach(struct wd33c93_softc *dev) 188 { 189 struct scsipi_adapter *adapt = &dev->sc_adapter; 190 struct scsipi_channel *chan = &dev->sc_channel; 191 192 adapt->adapt_dev = &dev->sc_dev; 193 adapt->adapt_nchannels = 1; 194 adapt->adapt_openings = 256; 195 adapt->adapt_max_periph = 256; /* Max tags per device */ 196 adapt->adapt_ioctl = NULL; 197 /* adapt_request initialized by MD interface */ 198 /* adapt_minphys initialized by MD interface */ 199 200 memset(chan, 0, sizeof(*chan)); 201 chan->chan_adapter = &dev->sc_adapter; 202 chan->chan_bustype = &scsi_bustype; 203 chan->chan_channel = 0; 204 chan->chan_ntargets = SBIC_NTARG; 205 chan->chan_nluns = SBIC_NLUN; 206 chan->chan_id = dev->sc_id; 207 208 callout_init(&dev->sc_watchdog); 209 210 /* 211 * Add reference to adapter so that we drop the reference after 212 * config_found() to make sure the adatper is disabled. 213 */ 214 if (scsipi_adapter_addref(&dev->sc_adapter) != 0) { 215 printf("%s: unable to enable controller\n", 216 dev->sc_dev.dv_xname); 217 return; 218 } 219 220 dev->sc_cfflags = device_cfdata(&dev->sc_dev)->cf_flags; 221 wd33c93_init(dev); 222 223 printf(": %s (%d.%d MHz clock, SCSI ID %d)\n", 224 wd33c93_chip_names[dev->sc_chip], 225 dev->sc_clkfreq / 10, dev->sc_clkfreq % 10, 226 dev->sc_channel.chan_id); 227 if (dev->sc_chip == SBIC_CHIP_WD33C93B) { 228 printf("%s: microcode revision 0x%02x", 229 dev->sc_dev.dv_xname, dev->sc_rev); 230 if (dev->sc_minsyncperiod < 50) 231 printf(", Fast SCSI"); 232 printf("\n"); 233 } 234 235 dev->sc_child = config_found(&dev->sc_dev, &dev->sc_channel, 236 scsiprint); 237 scsipi_adapter_delref(&dev->sc_adapter); 238 } 239 240 /* 241 * Initialize driver-private structures 242 */ 243 void 244 wd33c93_init(struct wd33c93_softc *dev) 245 { 246 u_int i; 247 248 if (!wd33c93_pool_initialized) { 249 /* All instances share the same pool */ 250 pool_init(&wd33c93_pool, sizeof(struct wd33c93_acb), 0, 0, 0, 251 "wd33c93_acb", NULL, IPL_BIO); 252 ++wd33c93_pool_initialized; 253 } 254 255 if (dev->sc_state == 0) { 256 TAILQ_INIT(&dev->ready_list); 257 258 dev->sc_nexus = NULL; 259 dev->sc_disc = 0; 260 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 261 262 callout_reset(&dev->sc_watchdog, 60 * hz, wd33c93_watchdog, dev); 263 } else 264 panic("wd33c93: reinitializing driver!"); 265 266 dev->sc_flags = 0; 267 dev->sc_state = SBIC_IDLE; 268 wd33c93_reset(dev); 269 270 for (i = 0; i < 8; i++) { 271 struct wd33c93_tinfo *ti = &dev->sc_tinfo[i]; 272 /* 273 * sc_flags = 0xTTRRSS 274 * 275 * TT = Bitmask to disable Tagged Queues 276 * RR = Bitmask to disable disconnect/reselect 277 * SS = Bitmask to diable Sync negotiation 278 */ 279 ti->flags = T_NEED_RESET; 280 if (dev->sc_cfflags & (1<<(i+8))) 281 ti->flags |= T_NOSYNC; 282 if (dev->sc_cfflags & (1<<i) || wd33c93_nodisc) 283 ti->flags |= T_NODISC; 284 ti->period = dev->sc_minsyncperiod; 285 ti->offset = 0; 286 } 287 } 288 289 void 290 wd33c93_reset(struct wd33c93_softc *dev) 291 { 292 u_int my_id, s, div, i; 293 u_char csr, reg; 294 295 SET_SBIC_cmd(dev, SBIC_CMD_ABORT); 296 WAIT_CIP(dev); 297 298 s = splbio(); 299 300 if (dev->sc_reset != NULL) 301 (*dev->sc_reset)(dev); 302 303 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 304 305 /* Enable advanced features and really(!) advanced features */ 306 #if 1 307 my_id |= (SBIC_ID_EAF | SBIC_ID_RAF); /* XXX - MD Layer */ 308 #endif 309 310 SET_SBIC_myid(dev, my_id); 311 312 /* Reset the chip */ 313 SET_SBIC_cmd(dev, SBIC_CMD_RESET); 314 DELAY(25); 315 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 316 317 /* Set up various chip parameters */ 318 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 319 320 GET_SBIC_csr(dev, csr); /* clears interrupt also */ 321 GET_SBIC_cdb1(dev, dev->sc_rev); /* valid with RAF on wd33c93b */ 322 323 switch (csr) { 324 case SBIC_CSR_RESET: 325 dev->sc_chip = SBIC_CHIP_WD33C93; 326 break; 327 case SBIC_CSR_RESET_AM: 328 SET_SBIC_queue_tag(dev, 0x55); 329 GET_SBIC_queue_tag(dev, reg); 330 dev->sc_chip = (reg == 0x55) ? 331 SBIC_CHIP_WD33C93B : SBIC_CHIP_WD33C93A; 332 SET_SBIC_queue_tag(dev, 0x0); 333 break; 334 default: 335 dev->sc_chip = SBIC_CHIP_UNKNOWN; 336 } 337 338 /* 339 * Choose a suitable clock divisor and work out the resulting 340 * sync transfer periods in 4ns units. 341 */ 342 if (dev->sc_clkfreq < 110) { 343 my_id |= SBIC_ID_FS_8_10; 344 div = 2; 345 } else if (dev->sc_clkfreq < 160) { 346 my_id |= SBIC_ID_FS_12_15; 347 div = 3; 348 } else if (dev->sc_clkfreq < 210) { 349 my_id |= SBIC_ID_FS_16_20; 350 div = 4; 351 } else 352 panic("wd33c93: invalid clock speed %d", dev->sc_clkfreq); 353 354 for (i = 0; i < 7; i++) 355 dev->sc_syncperiods[i] = 356 (i + 2) * div * 1250 / dev->sc_clkfreq; 357 dev->sc_minsyncperiod = dev->sc_syncperiods[0]; 358 SBIC_DEBUG(SYNC, ("available sync periods: %d %d %d %d %d %d %d\n", 359 dev->sc_syncperiods[0], dev->sc_syncperiods[1], 360 dev->sc_syncperiods[2], dev->sc_syncperiods[3], 361 dev->sc_syncperiods[4], dev->sc_syncperiods[5], 362 dev->sc_syncperiods[6])); 363 364 if (dev->sc_clkfreq >= 160 && dev->sc_chip == SBIC_CHIP_WD33C93B) { 365 for (i = 0; i < 3; i++) 366 dev->sc_fsyncperiods[i] = 367 (i + 2) * 2 * 1250 / dev->sc_clkfreq; 368 SBIC_DEBUG(SYNC, ("available fast sync periods: %d %d %d\n", 369 dev->sc_fsyncperiods[0], dev->sc_fsyncperiods[1], 370 dev->sc_fsyncperiods[2])); 371 dev->sc_minsyncperiod = dev->sc_fsyncperiods[0]; 372 } 373 374 /* Max Sync Offset */ 375 if (dev->sc_chip == SBIC_CHIP_WD33C93A || 376 dev->sc_chip == SBIC_CHIP_WD33C93B) 377 dev->sc_maxoffset = SBIC_SYN_93AB_MAX_OFFSET; 378 else 379 dev->sc_maxoffset = SBIC_SYN_93_MAX_OFFSET; 380 381 /* 382 * don't allow Selection (SBIC_RID_ES) 383 * until we can handle target mode!! 384 */ 385 SET_SBIC_rselid(dev, SBIC_RID_ER); 386 387 /* Asynchronous for now */ 388 SET_SBIC_syn(dev, 0); 389 390 dev->sc_flags = 0; 391 dev->sc_state = SBIC_IDLE; 392 393 splx(s); 394 } 395 396 void 397 wd33c93_error(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 398 { 399 struct scsipi_xfer *xs = acb->xs; 400 401 KASSERT(xs); 402 403 if (xs->xs_control & XS_CTL_SILENT) 404 return; 405 406 scsipi_printaddr(xs->xs_periph); 407 printf("SCSI Error\n"); 408 } 409 410 /* 411 * Determine an appropriate value for the synchronous transfer register 412 * given the period and offset values in *ti. 413 */ 414 u_char 415 wd33c93_stp2syn(struct wd33c93_softc *dev, struct wd33c93_tinfo *ti) 416 { 417 unsigned i; 418 419 /* see if we can handle fast scsi (100-200ns) first */ 420 if (ti->period < 50 && dev->sc_minsyncperiod < 50) { 421 for (i = 0; i < 3; i++) 422 if (dev->sc_fsyncperiods[i] >= ti->period) 423 return (SBIC_SYN(ti->offset, i + 2, 1)); 424 } 425 426 for (i = 0; i < 7; i++) { 427 if (dev->sc_syncperiods[i] >= ti->period) { 428 if (i == 6) 429 return (SBIC_SYN(0, 0, 0)); 430 else 431 return (SBIC_SYN(ti->offset, i + 2, 0)); 432 } 433 } 434 435 /* XXX - can't handle it; do async */ 436 return (SBIC_SYN(0, 0, 0)); 437 } 438 439 /* 440 * Setup sync mode for given target 441 */ 442 void 443 wd33c93_setsync(struct wd33c93_softc *dev, struct wd33c93_tinfo *ti) 444 { 445 u_char syncreg; 446 447 if (ti->flags & T_SYNCMODE) 448 syncreg = wd33c93_stp2syn(dev, ti); 449 else 450 syncreg = SBIC_SYN(0, 0, 0); 451 452 SBIC_DEBUG(SYNC, ("wd33c93_setsync: sync reg = 0x%02x\n", syncreg)); 453 SET_SBIC_syn(dev, syncreg); 454 } 455 456 /* 457 * Check if current operation can be done using DMA 458 * 459 * returns 1 if DMA OK, 0 for polled I/O transfer 460 */ 461 int 462 wd33c93_dmaok(struct wd33c93_softc *dev, struct scsipi_xfer *xs) 463 { 464 if (wd33c93_nodma || (xs->xs_control & XS_CTL_POLL) || xs->datalen == 0) 465 return (0); 466 return(1); 467 } 468 469 /* 470 * Setup for DMA transfer 471 */ 472 void 473 wd33c93_dma_setup(struct wd33c93_softc *dev, int datain) 474 { 475 struct wd33c93_acb *acb = dev->sc_nexus; 476 int s; 477 478 dev->sc_daddr = acb->daddr; 479 dev->sc_dleft = acb->dleft; 480 481 s = splbio(); 482 /* Indicate that we're in DMA mode */ 483 if (dev->sc_dleft) { 484 dev->sc_dmasetup(dev, &dev->sc_daddr, &dev->sc_dleft, 485 datain, &dev->sc_dleft); 486 } 487 splx(s); 488 return; 489 } 490 491 492 /* 493 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 494 */ 495 void 496 wd33c93_dma_stop(struct wd33c93_softc *dev) 497 { 498 size_t count; 499 int asr; 500 501 /* Wait until WD chip is idle */ 502 do { 503 GET_SBIC_asr(dev, asr); /* XXX */ 504 if (asr & SBIC_ASR_DBR) { 505 printf("wd33c93_dma_stop: asr %02x canceled!\n", asr); 506 break; 507 } 508 } while (asr & (SBIC_ASR_BSY|SBIC_ASR_CIP)); 509 510 /* Only need to save pointers if DMA was active */ 511 if (dev->sc_flags & SBICF_INDMA) { 512 int s = splbio(); 513 514 /* Shut down DMA and flush FIFO's */ 515 dev->sc_dmastop(dev); 516 517 /* Fetch the residual count */ 518 SBIC_TC_GET(dev, count); 519 520 /* Work out how many bytes were actually transferred */ 521 count = dev->sc_tcnt - count; 522 523 if (dev->sc_dleft < count) 524 printf("xfer too large: dleft=%zu resid=%zu\n", 525 dev->sc_dleft, count); 526 527 /* Fixup partial xfers */ 528 dev->sc_daddr = (char*)dev->sc_daddr + count; 529 dev->sc_dleft -= count; 530 dev->sc_tcnt = 0; 531 dev->sc_flags &= ~SBICF_INDMA; 532 splx(s); 533 SBIC_DEBUG(DMA, ("dma_stop\n")); 534 } 535 /* 536 * Ensure the WD chip is back in polled I/O mode, with nothing to 537 * transfer. 538 */ 539 SBIC_TC_PUT(dev, 0); 540 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 541 } 542 543 544 /* 545 * Handle new request from scsipi layer 546 */ 547 void 548 wd33c93_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 549 { 550 struct wd33c93_softc *dev = (void *)chan->chan_adapter->adapt_dev; 551 struct scsipi_xfer *xs; 552 struct scsipi_periph *periph; 553 struct wd33c93_acb *acb; 554 int flags, s; 555 556 switch (req) { 557 case ADAPTER_REQ_RUN_XFER: 558 xs = arg; 559 periph = xs->xs_periph; 560 flags = xs->xs_control; 561 562 if (flags & XS_CTL_DATA_UIO) 563 panic("wd33c93: scsi data uio requested"); 564 565 if (dev->sc_nexus && (flags & XS_CTL_POLL)) 566 panic("wd33c93_scsicmd: busy"); 567 568 s = splbio(); 569 acb = (struct wd33c93_acb *)pool_get(&wd33c93_pool, PR_NOWAIT); 570 splx(s); 571 572 if (acb == NULL) { 573 scsipi_printaddr(periph); 574 printf("cannot allocate acb\n"); 575 xs->error = XS_RESOURCE_SHORTAGE; 576 scsipi_done(xs); 577 return; 578 } 579 580 acb->flags = ACB_ACTIVE; 581 acb->xs = xs; 582 acb->clen = xs->cmdlen; 583 acb->daddr = xs->data; 584 acb->dleft = xs->datalen; 585 acb->timeout = xs->timeout; 586 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 587 588 if (flags & XS_CTL_POLL) { 589 /* 590 * Complete currently active command(s) before 591 * issuing an immediate command 592 */ 593 while (dev->sc_nexus) 594 wd33c93_poll(dev, dev->sc_nexus); 595 } 596 597 s = splbio(); 598 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 599 acb->flags |= ACB_READY; 600 601 /* If nothing is active, try to start it now. */ 602 if (dev->sc_state == SBIC_IDLE) 603 wd33c93_sched(dev); 604 splx(s); 605 606 if ((flags & XS_CTL_POLL) == 0) 607 return; 608 609 if (wd33c93_poll(dev, acb)) { 610 wd33c93_timeout(acb); 611 if (wd33c93_poll(dev, acb)) /* 2nd retry for ABORT */ 612 wd33c93_timeout(acb); 613 } 614 return; 615 616 case ADAPTER_REQ_GROW_RESOURCES: 617 /* XXX Not supported. */ 618 return; 619 620 case ADAPTER_REQ_SET_XFER_MODE: 621 { 622 struct wd33c93_tinfo *ti; 623 struct scsipi_xfer_mode *xm = arg; 624 625 ti = &dev->sc_tinfo[xm->xm_target]; 626 ti->flags &= ~T_WANTSYNC; 627 628 if ((dev->sc_cfflags & (1<<(xm->xm_target+16))) == 0 && 629 (xm->xm_mode & PERIPH_CAP_TQING) && !wd33c93_notags) 630 ti->flags |= T_TAG; 631 else 632 ti->flags &= ~T_TAG; 633 634 SBIC_DEBUG(SYNC, ("wd33c93_scsi_request: " 635 "target %d: scsipi requested %s\n", xm->xm_target, 636 (xm->xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 637 638 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 639 (ti->flags & T_NOSYNC) == 0) 640 ti->flags |= T_WANTSYNC; 641 /* 642 * If we're not going to negotiate, send the notification 643 * now, since it won't happen later. 644 */ 645 if (!(ti->flags & T_WANTSYNC) == !(ti->flags & T_SYNCMODE)) 646 wd33c93_update_xfer_mode(dev, xm->xm_target); 647 else 648 ti->flags |= T_NEGOTIATE; 649 return; 650 } 651 652 } 653 } 654 655 /* 656 * attempt to start the next available command 657 */ 658 void 659 wd33c93_sched(struct wd33c93_softc *dev) 660 { 661 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 662 struct wd33c93_acb *acb; 663 struct wd33c93_tinfo *ti; 664 struct wd33c93_linfo *li; 665 int lun, tag, flags; 666 667 if (dev->sc_state != SBIC_IDLE) 668 return; 669 670 KASSERT(dev->sc_nexus == NULL); 671 672 /* Loop through the ready list looking for work to do... */ 673 TAILQ_FOREACH(acb, &dev->ready_list, chain) { 674 periph = acb->xs->xs_periph; 675 lun = periph->periph_lun; 676 ti = &dev->sc_tinfo[periph->periph_target]; 677 li = TINFO_LUN(ti, lun); 678 679 KASSERT(acb->flags & ACB_READY); 680 681 /* Select type of tag for this command */ 682 if ((ti->flags & T_NODISC) != 0) 683 tag = 0; 684 else if ((ti->flags & T_TAG) == 0) 685 tag = 0; 686 else if ((acb->flags & ACB_SENSE) != 0) 687 tag = 0; 688 else if (acb->xs->xs_control & XS_CTL_POLL) 689 tag = 0; /* No tags for polled commands */ 690 else 691 tag = acb->xs->xs_tag_type; 692 693 if (li == NULL) { 694 /* Initialize LUN info and add to list. */ 695 li = malloc(sizeof(*li), M_DEVBUF, M_NOWAIT); 696 if (li == NULL) 697 continue; 698 memset(li, 0, sizeof(*li)); 699 li->lun = lun; 700 if (lun < SBIC_NLUN) 701 ti->lun[lun] = li; 702 } 703 li->last_used = time_second; 704 705 /* 706 * We've found a potential command, but is the target/lun busy? 707 */ 708 709 if (tag == 0 && li->untagged == NULL) 710 li->untagged = acb; /* Issue untagged */ 711 712 if (li->untagged != NULL) { 713 tag = 0; 714 if ((li->state != L_STATE_BUSY) && li->used == 0) { 715 /* Issue this untagged command now */ 716 acb = li->untagged; 717 periph = acb->xs->xs_periph; 718 } else /* Not ready yet */ 719 continue; 720 } 721 722 acb->tag_type = tag; 723 if (tag != 0) { 724 if (li->queued[acb->xs->xs_tag_id]) 725 printf("queueing to active tag\n"); 726 li->queued[acb->xs->xs_tag_id] = acb; 727 acb->tag_id = acb->xs->xs_tag_id; 728 li->used++; 729 break; 730 } 731 if (li->untagged != NULL && (li->state != L_STATE_BUSY)) { 732 li->state = L_STATE_BUSY; 733 break; 734 } 735 if (li->untagged == NULL && tag != 0) { 736 break; 737 } else 738 printf("%d:%d busy\n", periph->periph_target, 739 periph->periph_lun); 740 } 741 742 if (acb == NULL) { 743 SBIC_DEBUG(ACBS, ("wd33c93sched: no work\n")); 744 return; /* did not find an available command */ 745 } 746 747 SBIC_DEBUG(ACBS, ("wd33c93_sched(%d,%d)\n", periph->periph_target, 748 periph->periph_lun)); 749 750 TAILQ_REMOVE(&dev->ready_list, acb, chain); 751 acb->flags &= ~ACB_READY; 752 753 flags = acb->xs->xs_control; 754 if (flags & XS_CTL_RESET) 755 wd33c93_reset(dev); 756 757 /* XXX - Implicitly call scsidone on select timeout */ 758 if (wd33c93_go(dev, acb) != 0 || acb->xs->error == XS_SELTIMEOUT) { 759 acb->dleft = dev->sc_dleft; 760 wd33c93_scsidone(dev, acb, dev->sc_status); 761 return; 762 } 763 764 return; 765 } 766 767 void 768 wd33c93_scsidone(struct wd33c93_softc *dev, struct wd33c93_acb *acb, int status) 769 { 770 struct scsipi_xfer *xs = acb->xs; 771 struct wd33c93_tinfo *ti; 772 struct wd33c93_linfo *li; 773 int s; 774 775 #ifdef DIAGNOSTIC 776 KASSERT(dev->target == xs->xs_periph->periph_target); 777 KASSERT(dev->lun == xs->xs_periph->periph_lun); 778 if (acb == NULL || xs == NULL) { 779 panic("wd33c93_scsidone -- (%d,%d) no scsipi_xfer", 780 dev->target, dev->lun); 781 } 782 KASSERT(acb->flags != ACB_FREE); 783 #endif 784 785 SBIC_DEBUG(ACBS, ("scsidone: (%d,%d)->(%d,%d)%02x\n", 786 xs->xs_periph->periph_target, xs->xs_periph->periph_lun, 787 dev->target, dev->lun, status)); 788 callout_stop(&xs->xs_callout); 789 790 xs->status = status & SCSI_STATUS_MASK; 791 xs->resid = acb->dleft; 792 793 if (xs->error == XS_NOERROR) { 794 switch (xs->status) { 795 case SCSI_CHECK: 796 case SCSI_TERMINATED: 797 /* XXX Need to read sense - return busy for now */ 798 /*FALLTHROUGH*/ 799 case SCSI_QUEUE_FULL: 800 case SCSI_BUSY: 801 xs->error = XS_BUSY; 802 break; 803 } 804 } 805 806 ti = &dev->sc_tinfo[dev->target]; 807 li = TINFO_LUN(ti, dev->lun); 808 ti->cmds++; 809 if (xs->error == XS_SELTIMEOUT) { 810 /* Selection timeout -- discard this LUN if empty */ 811 if (li->untagged == NULL && li->used == 0) { 812 if (dev->lun < SBIC_NLUN) 813 ti->lun[dev->lun] = NULL; 814 free(li, M_DEVBUF); 815 } 816 } 817 818 wd33c93_dequeue(dev, acb); 819 if (dev->sc_nexus == acb) { 820 dev->sc_state = SBIC_IDLE; 821 dev->sc_nexus = NULL; 822 dev->sc_flags = 0; 823 824 if (!TAILQ_EMPTY(&dev->ready_list)) 825 wd33c93_sched(dev); 826 } 827 828 /* place control block back on free list. */ 829 s = splbio(); 830 acb->flags = ACB_FREE; 831 pool_put(&wd33c93_pool, (void *)acb); 832 splx(s); 833 834 scsipi_done(xs); 835 } 836 837 void 838 wd33c93_dequeue(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 839 { 840 struct wd33c93_tinfo *ti = &dev->sc_tinfo[acb->xs->xs_periph->periph_target]; 841 struct wd33c93_linfo *li; 842 int lun = acb->xs->xs_periph->periph_lun; 843 844 li = TINFO_LUN(ti, lun); 845 #ifdef DIAGNOSTIC 846 if (li == NULL || li->lun != lun) 847 panic("wd33c93_dequeue: lun %d for ecb %p does not exist", 848 lun, acb); 849 #endif 850 if (li->untagged == acb) { 851 li->state = L_STATE_IDLE; 852 li->untagged = NULL; 853 } 854 if (acb->tag_type && li->queued[acb->tag_id] != NULL) { 855 #ifdef DIAGNOSTIC 856 if (li->queued[acb->tag_id] != NULL && 857 (li->queued[acb->tag_id] != acb)) 858 panic("wd33c93_dequeue: slot %d for lun %d has %p " 859 "instead of acb %p\n", acb->tag_id, 860 lun, li->queued[acb->tag_id], acb); 861 #endif 862 li->queued[acb->tag_id] = NULL; 863 li->used--; 864 } 865 } 866 867 868 int 869 wd33c93_wait(struct wd33c93_softc *dev, u_char until, int timeo, int line) 870 { 871 u_char val; 872 873 if (timeo == 0) 874 timeo = 1000000; /* some large value.. */ 875 GET_SBIC_asr(dev, val); 876 while ((val & until) == 0) { 877 if (timeo-- == 0) { 878 int csr; 879 GET_SBIC_csr(dev, csr); 880 printf("wd33c93_wait: TIMEO @%d with asr=x%x csr=x%x\n", 881 line, val, csr); 882 #if defined(DDB) && defined(DEBUG) 883 Debugger(); 884 #endif 885 return(val); /* Maybe I should abort */ 886 break; 887 } 888 DELAY(1); 889 GET_SBIC_asr(dev, val); 890 } 891 return(val); 892 } 893 894 int 895 wd33c93_abort(struct wd33c93_softc *dev, struct wd33c93_acb *acb, 896 const char *where) 897 { 898 u_char csr, asr; 899 900 GET_SBIC_asr(dev, asr); 901 GET_SBIC_csr(dev, csr); 902 903 scsipi_printaddr(acb->xs->xs_periph); 904 printf ("ABORT in %s: csr=0x%02x, asr=0x%02x\n", where, csr, asr); 905 906 acb->timeout = SBIC_ABORT_TIMEOUT; 907 acb->flags |= ACB_ABORT; 908 909 /* 910 * Clean up chip itself 911 */ 912 if (dev->sc_nexus == acb) { 913 /* Reschedule timeout. */ 914 callout_reset(&acb->xs->xs_callout, mstohz(acb->timeout), 915 wd33c93_timeout, acb); 916 917 while (asr & SBIC_ASR_DBR) { 918 /* 919 * wd33c93 is jammed w/data. need to clear it 920 * But we don't know what direction it needs to go 921 */ 922 GET_SBIC_data(dev, asr); 923 printf("abort %s: clearing data buffer 0x%02x\n", 924 where, asr); 925 GET_SBIC_asr(dev, asr); 926 if (asr & SBIC_ASR_DBR) /* Not the read direction */ 927 SET_SBIC_data(dev, asr); 928 GET_SBIC_asr(dev, asr); 929 } 930 931 scsipi_printaddr(acb->xs->xs_periph); 932 printf("sending ABORT command\n"); 933 934 WAIT_CIP(dev); 935 SET_SBIC_cmd(dev, SBIC_CMD_ABORT); 936 WAIT_CIP(dev); 937 938 GET_SBIC_asr(dev, asr); 939 940 scsipi_printaddr(acb->xs->xs_periph); 941 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 942 /* 943 * ok, get more drastic.. 944 */ 945 printf("Resetting bus\n"); 946 wd33c93_reset(dev); 947 } else { 948 printf("sending DISCONNECT to target\n"); 949 SET_SBIC_cmd(dev, SBIC_CMD_DISC); 950 WAIT_CIP(dev); 951 952 do { 953 SBIC_WAIT (dev, SBIC_ASR_INT, 0); 954 GET_SBIC_asr(dev, asr); 955 GET_SBIC_csr(dev, csr); 956 SBIC_DEBUG(MISC, ("csr: 0x%02x, asr: 0x%02x\n", 957 csr, asr)); 958 } while ((csr != SBIC_CSR_DISC) && 959 (csr != SBIC_CSR_DISC_1) && 960 (csr != SBIC_CSR_CMD_INVALID)); 961 } 962 dev->sc_state = SBIC_ERROR; 963 dev->sc_flags = 0; 964 } 965 return SBIC_STATE_ERROR; 966 } 967 968 969 /* 970 * select the bus, return when selected or error. 971 * 972 * Returns the current CSR following selection and optionally MSG out phase. 973 * i.e. the returned CSR *should* indicate CMD phase... 974 * If the return value is 0, some error happened. 975 */ 976 u_char 977 wd33c93_selectbus(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 978 { 979 struct scsipi_xfer *xs = acb->xs; 980 struct wd33c93_tinfo *ti; 981 u_char target, lun, asr, csr, id; 982 983 KASSERT(dev->sc_state == SBIC_IDLE); 984 985 target = xs->xs_periph->periph_target; 986 lun = xs->xs_periph->periph_lun; 987 ti = &dev->sc_tinfo[target]; 988 989 dev->sc_state = SBIC_SELECTING; 990 dev->target = target; 991 dev->lun = lun; 992 993 SBIC_DEBUG(PHASE, ("wd33c93_selectbus %d: ", target)); 994 995 if ((xs->xs_control & XS_CTL_POLL) == 0) 996 callout_reset(&xs->xs_callout, mstohz(acb->timeout), 997 wd33c93_timeout, acb); 998 999 /* 1000 * issue select 1001 */ 1002 SBIC_TC_PUT(dev, 0); 1003 SET_SBIC_selid(dev, target); 1004 SET_SBIC_timeo(dev, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 1005 1006 GET_SBIC_asr(dev, asr); 1007 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) { 1008 /* This means we got ourselves reselected upon */ 1009 SBIC_DEBUG(PHASE, ("WD busy (reselect?) ASR=%02x\n", asr)); 1010 return 0; 1011 } 1012 1013 SET_SBIC_cmd(dev, SBIC_CMD_SEL_ATN); 1014 WAIT_CIP(dev); 1015 1016 /* 1017 * wait for select (merged from separate function may need 1018 * cleanup) 1019 */ 1020 do { 1021 asr = SBIC_WAIT(dev, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1022 if (asr & SBIC_ASR_LCI) { 1023 QPRINTF(("late LCI: asr %02x\n", asr)); 1024 return 0; 1025 } 1026 1027 /* Clear interrupt */ 1028 GET_SBIC_csr (dev, csr); 1029 1030 /* Reselected from under our feet? */ 1031 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1032 SBIC_DEBUG(PHASE, ("got reselected, asr %02x\n", asr)); 1033 /* 1034 * We need to handle this now so we don't lock up later 1035 */ 1036 wd33c93_nextstate(dev, acb, csr, asr); 1037 return 0; 1038 } 1039 1040 /* Whoops! */ 1041 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1042 panic("wd33c93_selectbus: target issued select!"); 1043 return 0; 1044 } 1045 1046 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1047 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1048 csr != SBIC_CSR_SEL_TIMEO); 1049 1050 /* Anyone at home? */ 1051 if (csr == SBIC_CSR_SEL_TIMEO) { 1052 xs->error = XS_SELTIMEOUT; 1053 SBIC_DEBUG(PHASE, ("-- Selection Timeout\n")); 1054 return 0; 1055 } 1056 1057 SBIC_DEBUG(PHASE, ("Selection Complete\n")); 1058 1059 /* Assume we're now selected */ 1060 GET_SBIC_selid(dev, id); 1061 if (id != target) { 1062 /* Something went wrong - wrong target was select */ 1063 printf("wd33c93_selectbus: wrong target selected;" 1064 " WANTED %d GOT %d", target, id); 1065 return 0; /* XXX: Need to call nexstate to handle? */ 1066 } 1067 1068 dev->sc_flags |= SBICF_SELECTED; 1069 dev->sc_state = SBIC_CONNECTED; 1070 1071 /* setup correct sync mode for this target */ 1072 wd33c93_setsync(dev, ti); 1073 1074 if (ti->flags & T_NODISC && dev->sc_disc == 0) 1075 SET_SBIC_rselid (dev, 0); /* Not expecting a reselect */ 1076 else 1077 SET_SBIC_rselid (dev, SBIC_RID_ER); 1078 1079 /* 1080 * We only really need to do anything when the target goes to MSG out 1081 * If the device ignored ATN, it's probably old and brain-dead, 1082 * but we'll try to support it anyhow. 1083 * If it doesn't support message out, it definately doesn't 1084 * support synchronous transfers, so no point in even asking... 1085 */ 1086 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 1087 if (ti->flags & T_NEGOTIATE) { 1088 /* Inititae a SDTR message */ 1089 SBIC_DEBUG(SYNC, ("Sending SDTR to target %d\n", id)); 1090 if (ti->flags & T_WANTSYNC) { 1091 ti->period = dev->sc_minsyncperiod; 1092 ti->offset = dev->sc_maxoffset; 1093 } else { 1094 ti->period = 0; 1095 ti->offset = 0; 1096 } 1097 /* Send Sync negotiation message */ 1098 dev->sc_omsg[0] = MSG_IDENTIFY(lun, 0); /* No Disc */ 1099 dev->sc_omsg[1] = MSG_EXTENDED; 1100 dev->sc_omsg[2] = MSG_EXT_SDTR_LEN; 1101 dev->sc_omsg[3] = MSG_EXT_SDTR; 1102 if (ti->flags & T_WANTSYNC) { 1103 dev->sc_omsg[4] = dev->sc_minsyncperiod; 1104 dev->sc_omsg[5] = dev->sc_maxoffset; 1105 } else { 1106 dev->sc_omsg[4] = 0; 1107 dev->sc_omsg[5] = 0; 1108 } 1109 wd33c93_xfout(dev, 6, dev->sc_omsg); 1110 dev->sc_msgout |= SEND_SDTR; /* may be rejected */ 1111 dev->sc_flags |= SBICF_SYNCNEGO; 1112 } else { 1113 if (dev->sc_nexus->tag_type != 0) { 1114 /* Use TAGS */ 1115 SBIC_DEBUG(TAGS, ("<select %d:%d TAG=%x>\n", 1116 dev->target, dev->lun, 1117 dev->sc_nexus->tag_id)); 1118 dev->sc_omsg[0] = MSG_IDENTIFY(lun, 1); 1119 dev->sc_omsg[1] = dev->sc_nexus->tag_type; 1120 dev->sc_omsg[2] = dev->sc_nexus->tag_id; 1121 wd33c93_xfout(dev, 3, dev->sc_omsg); 1122 dev->sc_msgout |= SEND_TAG; 1123 } else { 1124 int no_disc; 1125 1126 /* Setup LUN nexus and disconnect privilege */ 1127 no_disc = xs->xs_control & XS_CTL_POLL || 1128 ti->flags & T_NODISC; 1129 SEND_BYTE(dev, MSG_IDENTIFY(lun, !no_disc)); 1130 } 1131 } 1132 /* 1133 * There's one interrupt still to come: 1134 * the change to CMD phase... 1135 */ 1136 SBIC_WAIT(dev, SBIC_ASR_INT , 0); 1137 GET_SBIC_csr(dev, csr); 1138 } 1139 1140 return csr; 1141 } 1142 1143 /* 1144 * Information Transfer *to* a SCSI Target. 1145 * 1146 * Note: Don't expect there to be an interrupt immediately after all 1147 * the data is transferred out. The WD spec sheet says that the Transfer- 1148 * Info command for non-MSG_IN phases only completes when the target 1149 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1150 * 1151 * This can have a nasty effect on commands which take a relatively long 1152 * time to complete, for example a START/STOP unit command may remain in 1153 * CMD phase until the disk has spun up. Only then will the target change 1154 * to STATUS phase. This is really only a problem for immediate commands 1155 * since we don't allow disconnection for them (yet). 1156 */ 1157 int 1158 wd33c93_xfout(struct wd33c93_softc *dev, int len, void *bp) 1159 { 1160 int wait = wd33c93_data_wait; 1161 u_char asr, *buf = bp; 1162 1163 QPRINTF(("wd33c93_xfout {%d} %02x %02x %02x %02x %02x " 1164 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1165 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1166 1167 /* 1168 * sigh.. WD-PROTO strikes again.. sending the command in one go 1169 * causes the chip to lock up if talking to certain (misbehaving?) 1170 * targets. Anyway, this procedure should work for all targets, but 1171 * it's slightly slower due to the overhead 1172 */ 1173 1174 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1175 SBIC_TC_PUT (dev, (unsigned)len); 1176 1177 WAIT_CIP (dev); 1178 SET_SBIC_cmd (dev, SBIC_CMD_XFER_INFO); 1179 1180 /* 1181 * Loop for each byte transferred 1182 */ 1183 do { 1184 GET_SBIC_asr (dev, asr); 1185 1186 if (asr & SBIC_ASR_DBR) { 1187 if (len) { 1188 SET_SBIC_data (dev, *buf); 1189 buf++; 1190 len--; 1191 } else { 1192 SET_SBIC_data (dev, 0); 1193 } 1194 wait = wd33c93_data_wait; 1195 } 1196 } while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1197 1198 QPRINTF(("wd33c93_xfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1199 1200 /* 1201 * Normally, an interrupt will be pending when this routing returns. 1202 */ 1203 return(len); 1204 } 1205 1206 /* 1207 * Information Transfer *from* a Scsi Target 1208 * returns # bytes left to read 1209 */ 1210 int 1211 wd33c93_xfin(struct wd33c93_softc *dev, int len, void *bp) 1212 { 1213 int wait = wd33c93_data_wait; 1214 u_char *buf = bp; 1215 u_char asr; 1216 #ifdef DEBUG 1217 u_char *obp = bp; 1218 #endif 1219 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1220 SBIC_TC_PUT (dev, (unsigned)len); 1221 1222 WAIT_CIP (dev); 1223 SET_SBIC_cmd (dev, SBIC_CMD_XFER_INFO); 1224 1225 /* 1226 * Loop for each byte transferred 1227 */ 1228 do { 1229 GET_SBIC_asr (dev, asr); 1230 1231 if (asr & SBIC_ASR_DBR) { 1232 if (len) { 1233 GET_SBIC_data (dev, *buf); 1234 buf++; 1235 len--; 1236 } else { 1237 u_char foo; 1238 GET_SBIC_data (dev, foo); 1239 } 1240 wait = wd33c93_data_wait; 1241 } 1242 1243 } while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1244 1245 QPRINTF(("wd33c93_xfin {%d} %02x %02x %02x %02x %02x %02x " 1246 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1247 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1248 1249 SBIC_TC_PUT (dev, 0); 1250 1251 /* 1252 * this leaves with one csr to be read 1253 */ 1254 return len; 1255 } 1256 1257 1258 /* 1259 * Finish SCSI xfer command: After the completion interrupt from 1260 * a read/write operation, sequence through the final phases in 1261 * programmed i/o. 1262 */ 1263 void 1264 wd33c93_xferdone(struct wd33c93_softc *dev) 1265 { 1266 u_char phase, csr; 1267 int s; 1268 1269 QPRINTF(("{")); 1270 s = splbio(); 1271 1272 /* 1273 * have the wd33c93 complete on its own 1274 */ 1275 SBIC_TC_PUT(dev, 0); 1276 SET_SBIC_cmd_phase(dev, 0x46); 1277 SET_SBIC_cmd(dev, SBIC_CMD_SEL_ATN_XFER); 1278 1279 do { 1280 SBIC_WAIT (dev, SBIC_ASR_INT, 0); 1281 GET_SBIC_csr (dev, csr); 1282 QPRINTF(("%02x:", csr)); 1283 } while ((csr != SBIC_CSR_DISC) && 1284 (csr != SBIC_CSR_DISC_1) && 1285 (csr != SBIC_CSR_S_XFERRED)); 1286 1287 dev->sc_flags &= ~SBICF_SELECTED; 1288 dev->sc_state = SBIC_DISCONNECT; 1289 1290 GET_SBIC_cmd_phase (dev, phase); 1291 QPRINTF(("}%02x", phase)); 1292 1293 if (phase == 0x60) 1294 GET_SBIC_tlun(dev, dev->sc_status); 1295 else 1296 wd33c93_error(dev, dev->sc_nexus); 1297 1298 QPRINTF(("=STS:%02x=\n", dev->sc_status)); 1299 splx(s); 1300 } 1301 1302 1303 int 1304 wd33c93_go(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 1305 { 1306 struct scsipi_xfer *xs = acb->xs; 1307 int i, dmaok; 1308 u_char csr, asr; 1309 1310 SBIC_DEBUG(ACBS, ("wd33c93_go(%d:%d)\n", dev->target, dev->lun)); 1311 1312 dev->sc_nexus = acb; 1313 1314 dev->target = xs->xs_periph->periph_target; 1315 dev->lun = xs->xs_periph->periph_lun; 1316 1317 dev->sc_status = STATUS_UNKNOWN; 1318 dev->sc_daddr = acb->daddr; 1319 dev->sc_dleft = acb->dleft; 1320 1321 dev->sc_msgpriq = dev->sc_msgout = dev->sc_msgoutq = 0; 1322 dev->sc_flags = 0; 1323 1324 dmaok = wd33c93_dmaok(dev, xs); 1325 1326 if (dmaok == 0) 1327 dev->sc_flags |= SBICF_NODMA; 1328 1329 SBIC_DEBUG(DMA, ("wd33c93_go dmago:%d(tcnt=%zx) dmaok=%dx\n", 1330 dev->target, dev->sc_tcnt, dmaok)); 1331 1332 /* select the SCSI bus (it's an error if bus isn't free) */ 1333 if ((csr = wd33c93_selectbus(dev, acb)) == 0) 1334 return(0); /* Not done: needs to be rescheduled */ 1335 1336 /* 1337 * Lets cycle a while then let the interrupt handler take over. 1338 */ 1339 GET_SBIC_asr(dev, asr); 1340 do { 1341 QPRINTF(("go[0x%x] ", csr)); 1342 1343 /* Handle the new phase */ 1344 i = wd33c93_nextstate(dev, acb, csr, asr); 1345 WAIT_CIP(dev); /* XXX */ 1346 if (dev->sc_state == SBIC_CONNECTED) { 1347 1348 GET_SBIC_asr(dev, asr); 1349 1350 if (asr & SBIC_ASR_LCI) 1351 printf("wd33c93_go: LCI asr:%02x csr:%02x\n", asr, csr); 1352 1353 if (asr & SBIC_ASR_INT) 1354 GET_SBIC_csr(dev, csr); 1355 } 1356 1357 } while (dev->sc_state == SBIC_CONNECTED && 1358 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1359 1360 QPRINTF(("> done i=%d stat=%02x\n", i, dev->sc_status)); 1361 1362 if (i == SBIC_STATE_DONE) { 1363 if (dev->sc_status == STATUS_UNKNOWN) { 1364 printf("wd33c93_go: done & stat == UNKNOWN\n"); 1365 return 1; /* Did we really finish that fast? */ 1366 } 1367 } 1368 return 0; 1369 } 1370 1371 1372 int 1373 wd33c93_intr(struct wd33c93_softc *dev) 1374 { 1375 u_char asr, csr; 1376 int i; 1377 1378 /* 1379 * pending interrupt? 1380 */ 1381 GET_SBIC_asr (dev, asr); 1382 if ((asr & SBIC_ASR_INT) == 0) 1383 return(0); 1384 1385 GET_SBIC_csr(dev, csr); 1386 1387 do { 1388 SBIC_DEBUG(INTS, ("intr[csr=0x%x]", csr)); 1389 1390 i = wd33c93_nextstate(dev, dev->sc_nexus, csr, asr); 1391 WAIT_CIP(dev); /* XXX */ 1392 if (dev->sc_state == SBIC_CONNECTED) { 1393 GET_SBIC_asr(dev, asr); 1394 1395 if (asr & SBIC_ASR_LCI) 1396 printf("wd33c93_intr: LCI asr:%02x csr:%02x\n", 1397 asr, csr); 1398 1399 if (asr & SBIC_ASR_INT) 1400 GET_SBIC_csr(dev, csr); 1401 } 1402 } while (dev->sc_state == SBIC_CONNECTED && 1403 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1404 1405 SBIC_DEBUG(INTS, ("intr done. state=%d, asr=0x%02x\n", i, asr)); 1406 1407 return(1); 1408 } 1409 1410 /* 1411 * Complete current command using polled I/O. Used when interrupt driven 1412 * I/O is not allowed (ie. during boot and shutdown) 1413 * 1414 * Polled I/O is very processor intensive 1415 */ 1416 int 1417 wd33c93_poll(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 1418 { 1419 u_char asr, csr=0; 1420 int i, count; 1421 struct scsipi_xfer *xs = acb->xs; 1422 1423 SBIC_WAIT(dev, SBIC_ASR_INT, wd33c93_cmd_wait); 1424 for (count=acb->timeout; count;) { 1425 GET_SBIC_asr (dev, asr); 1426 if (asr & SBIC_ASR_LCI) 1427 printf("wd33c93_poll: LCI; asr:%02x csr:%02x\n", 1428 asr, csr); 1429 if (asr & SBIC_ASR_INT) { 1430 GET_SBIC_csr(dev, csr); 1431 dev->sc_flags |= SBICF_NODMA; 1432 i = wd33c93_nextstate(dev, dev->sc_nexus, csr, asr); 1433 WAIT_CIP(dev); /* XXX */ 1434 } else { 1435 DELAY(1000); 1436 count--; 1437 } 1438 1439 if ((xs->xs_status & XS_STS_DONE) != 0) 1440 return (0); 1441 1442 if (dev->sc_state == SBIC_IDLE) { 1443 SBIC_DEBUG(ACBS, ("[poll: rescheduling] ")); 1444 wd33c93_sched(dev); 1445 } 1446 } 1447 return (1); 1448 } 1449 1450 static inline int 1451 __verify_msg_format(u_char *p, int len) 1452 { 1453 1454 if (len == 1 && MSG_IS1BYTE(p[0])) 1455 return 1; 1456 if (len == 2 && MSG_IS2BYTE(p[0])) 1457 return 1; 1458 if (len >= 3 && MSG_ISEXTENDED(p[0]) && 1459 len == p[1] + 2) 1460 return 1; 1461 return 0; 1462 } 1463 1464 /* 1465 * Handle message_in phase 1466 */ 1467 int 1468 wd33c93_msgin_phase(struct wd33c93_softc *dev, int reselect) 1469 { 1470 int len; 1471 u_char asr, csr, *msg; 1472 1473 GET_SBIC_asr(dev, asr); 1474 1475 SBIC_DEBUG(MSGS, ("wd33c93msgin asr=%02x\n", asr)); 1476 1477 GET_SBIC_selid (dev, csr); 1478 SET_SBIC_selid (dev, csr | SBIC_SID_FROM_SCSI); 1479 1480 SBIC_TC_PUT(dev, 0); 1481 1482 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1483 1484 msg = dev->sc_imsg; 1485 len = 0; 1486 1487 do { 1488 /* Fetch the next byte of the message */ 1489 RECV_BYTE(dev, *msg++); 1490 len++; 1491 1492 /* 1493 * get the command completion interrupt, or we 1494 * can't send a new command (LCI) 1495 */ 1496 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1497 GET_SBIC_csr(dev, csr); 1498 1499 if (__verify_msg_format(dev->sc_imsg, len)) 1500 break; /* Complete message recieved */ 1501 1502 /* 1503 * Clear ACK, and wait for the interrupt 1504 * for the next byte or phase change 1505 */ 1506 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1507 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1508 1509 GET_SBIC_csr(dev, csr); 1510 } while (len < SBIC_MAX_MSGLEN); 1511 1512 if (__verify_msg_format(dev->sc_imsg, len)) 1513 wd33c93_msgin(dev, dev->sc_imsg, len); 1514 1515 /* 1516 * Clear ACK, and wait for the interrupt 1517 * for the phase change 1518 */ 1519 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1520 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1521 1522 /* Should still have one CSR to read */ 1523 return SBIC_STATE_RUNNING; 1524 } 1525 1526 1527 void wd33c93_msgin(struct wd33c93_softc *dev, u_char *msgaddr, int msglen) 1528 { 1529 struct wd33c93_acb *acb = dev->sc_nexus; 1530 struct wd33c93_tinfo *ti = &dev->sc_tinfo[dev->target]; 1531 struct wd33c93_linfo *li; 1532 u_char asr; 1533 1534 switch (dev->sc_state) { 1535 case SBIC_CONNECTED: 1536 switch (msgaddr[0]) { 1537 case MSG_MESSAGE_REJECT: 1538 SBIC_DEBUG(MSGS, ("msgin: MSG_REJECT, " 1539 "last msgout=%x\n", dev->sc_msgout)); 1540 switch (dev->sc_msgout) { 1541 case SEND_TAG: 1542 printf("%s: tagged queuing rejected: " 1543 "target %d\n", 1544 dev->sc_dev.dv_xname, dev->target); 1545 ti->flags &= ~T_TAG; 1546 li = TINFO_LUN(ti, dev->lun); 1547 if (acb->tag_type && 1548 li->queued[acb->tag_id] != NULL) { 1549 li->queued[acb->tag_id] = NULL; 1550 li->used--; 1551 } 1552 acb->tag_type = acb->tag_id = 0; 1553 li->untagged = acb; 1554 li->state = L_STATE_BUSY; 1555 break; 1556 1557 case SEND_SDTR: 1558 printf("%s: sync transfer rejected: target %d\n", 1559 dev->sc_dev.dv_xname, dev->target); 1560 1561 dev->sc_flags &= ~SBICF_SYNCNEGO; 1562 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1563 wd33c93_update_xfer_mode(dev, 1564 acb->xs->xs_periph->periph_target); 1565 wd33c93_setsync(dev, ti); 1566 1567 case SEND_INIT_DET_ERR: 1568 goto abort; 1569 1570 default: 1571 SBIC_DEBUG(MSGS, ("Unexpected MSG_REJECT\n")); 1572 break; 1573 } 1574 dev->sc_msgout = 0; 1575 break; 1576 1577 case MSG_HEAD_OF_Q_TAG: 1578 case MSG_ORDERED_Q_TAG: 1579 case MSG_SIMPLE_Q_TAG: 1580 printf("-- Out of phase TAG;" 1581 "Nexus=%d:%d Tag=%02x/%02x\n", 1582 dev->target, dev->lun, msgaddr[0], msgaddr[1]); 1583 break; 1584 1585 case MSG_DISCONNECT: 1586 SBIC_DEBUG(MSGS, ("msgin: DISCONNECT")); 1587 /* 1588 * Mark the fact that all bytes have moved. The 1589 * target may not bother to do a SAVE POINTERS 1590 * at this stage. This flag will set the residual 1591 * count to zero on MSG COMPLETE. 1592 */ 1593 if (dev->sc_dleft == 0) 1594 acb->flags |= ACB_COMPLETE; 1595 1596 if (acb->xs->xs_control & XS_CTL_POLL) 1597 /* Don't allow disconnect in immediate mode */ 1598 goto reject; 1599 else { /* Allow disconnect */ 1600 dev->sc_flags &= ~SBICF_SELECTED; 1601 dev->sc_state = SBIC_DISCONNECT; 1602 } 1603 if ((acb->xs->xs_periph->periph_quirks & 1604 PQUIRK_AUTOSAVE) == 0) 1605 break; 1606 /*FALLTHROUGH*/ 1607 1608 case MSG_SAVEDATAPOINTER: 1609 SBIC_DEBUG(MSGS, ("msgin: SAVEDATAPTR")); 1610 acb->daddr = dev->sc_daddr; 1611 acb->dleft = dev->sc_dleft; 1612 break; 1613 1614 case MSG_RESTOREPOINTERS: 1615 SBIC_DEBUG(MSGS, ("msgin: RESTOREPTR")); 1616 dev->sc_daddr = acb->daddr; 1617 dev->sc_dleft = acb->dleft; 1618 break; 1619 1620 case MSG_CMDCOMPLETE: 1621 /* 1622 * !! KLUDGE ALERT !! quite a few drives don't seem to 1623 * really like the current way of sending the 1624 * sync-handshake together with the ident-message, and 1625 * they react by sending command-complete and 1626 * disconnecting right after returning the valid sync 1627 * handshake. So, all I can do is reselect the drive, 1628 * and hope it won't disconnect again. I don't think 1629 * this is valid behavior, but I can't help fixing a 1630 * problem that apparently exists. 1631 * 1632 * Note: we should not get here on `normal' command 1633 * completion, as that condition is handled by the 1634 * high-level sel&xfer resume command used to walk 1635 * thru status/cc-phase. 1636 */ 1637 SBIC_DEBUG(MSGS, ("msgin: CMD_COMPLETE")); 1638 SBIC_DEBUG(SYNC, ("GOT MSG %d! target %d" 1639 " acting weird.." 1640 " waiting for disconnect...\n", 1641 msgaddr[0], dev->target)); 1642 1643 /* Check to see if wd33c93 is handling this */ 1644 GET_SBIC_asr(dev, asr); 1645 if (asr & SBIC_ASR_BSY) 1646 break; 1647 1648 /* XXX: Assume it works and set status to 00 */ 1649 dev->sc_status = 0; 1650 dev->sc_state = SBIC_CMDCOMPLETE; 1651 break; 1652 1653 case MSG_EXTENDED: 1654 switch(msgaddr[2]) { 1655 case MSG_EXT_SDTR: /* Sync negotiation */ 1656 SBIC_DEBUG(MSGS, ("msgin: EXT_SDTR; " 1657 "period %d, offset %d", 1658 msgaddr[3], msgaddr[4])); 1659 if (msgaddr[1] != 3) 1660 goto reject; 1661 1662 ti->period = 1663 MAX(msgaddr[3], dev->sc_minsyncperiod); 1664 ti->offset = MIN(msgaddr[4], dev->sc_maxoffset); 1665 if (!(ti->flags & T_WANTSYNC)) 1666 ti->period = ti->offset = 0; 1667 1668 ti->flags &= ~T_NEGOTIATE; 1669 1670 if (ti->offset == 0) 1671 ti->flags &= ~T_SYNCMODE; /* Async */ 1672 else 1673 ti->flags |= T_SYNCMODE; /* Sync */ 1674 1675 if ((dev->sc_flags&SBICF_SYNCNEGO) == 0) 1676 /* target initiated negotiation */ 1677 wd33c93_sched_msgout(dev, SEND_SDTR); 1678 dev->sc_flags &= ~SBICF_SYNCNEGO; 1679 1680 SBIC_DEBUG(SYNC, ("msgin(%d): SDTR(o=%d,p=%d)", 1681 dev->target, ti->offset, 1682 ti->period)); 1683 wd33c93_update_xfer_mode(dev, 1684 acb->xs->xs_periph->periph_target); 1685 wd33c93_setsync(dev, ti); 1686 break; 1687 1688 case MSG_EXT_WDTR: 1689 SBIC_DEBUG(MSGS, ("msgin: EXT_WDTR rejected")); 1690 goto reject; 1691 1692 default: 1693 scsipi_printaddr(acb->xs->xs_periph); 1694 printf("unrecognized MESSAGE EXTENDED;" 1695 " sending REJECT\n"); 1696 goto reject; 1697 } 1698 break; 1699 1700 default: 1701 scsipi_printaddr(acb->xs->xs_periph); 1702 printf("unrecognized MESSAGE; sending REJECT\n"); 1703 1704 reject: 1705 /* We don't support whatever this message is... */ 1706 wd33c93_sched_msgout(dev, SEND_REJECT); 1707 break; 1708 } 1709 break; 1710 1711 case SBIC_IDENTIFIED: 1712 /* 1713 * IDENTIFY message was received and queue tag is expected now 1714 */ 1715 if ((msgaddr[0]!=MSG_SIMPLE_Q_TAG) || (dev->sc_msgify==0)) { 1716 printf("%s: TAG reselect without IDENTIFY;" 1717 " MSG %x; sending DEVICE RESET\n", 1718 dev->sc_dev.dv_xname, msgaddr[0]); 1719 goto reset; 1720 } 1721 SBIC_DEBUG(TAGS, ("TAG %x/%x\n", msgaddr[0], msgaddr[1])); 1722 if (dev->sc_nexus) 1723 printf("*TAG Recv with active nexus!!\n"); 1724 wd33c93_reselect(dev, dev->target, dev->lun, 1725 msgaddr[0], msgaddr[1]); 1726 break; 1727 1728 case SBIC_RESELECTED: 1729 /* 1730 * IDENTIFY message with target 1731 */ 1732 if (MSG_ISIDENTIFY(msgaddr[0])) { 1733 SBIC_DEBUG(PHASE, ("IFFY[%x] ", msgaddr[0])); 1734 dev->sc_msgify = msgaddr[0]; 1735 } else { 1736 printf("%s: reselect without IDENTIFY;" 1737 " MSG %x;" 1738 " sending DEVICE RESET\n", 1739 dev->sc_dev.dv_xname, msgaddr[0]); 1740 goto reset; 1741 } 1742 break; 1743 1744 default: 1745 printf("Unexpected MESSAGE IN. State=%d - Sending RESET\n", 1746 dev->sc_state); 1747 reset: 1748 wd33c93_sched_msgout(dev, SEND_DEV_RESET); 1749 break; 1750 abort: 1751 wd33c93_sched_msgout(dev, SEND_ABORT); 1752 break; 1753 } 1754 } 1755 1756 void 1757 wd33c93_sched_msgout(struct wd33c93_softc *dev, u_short msg) 1758 { 1759 u_char asr; 1760 1761 SBIC_DEBUG(SYNC,("sched_msgout: %04x\n", msg)); 1762 dev->sc_msgpriq |= msg; 1763 1764 /* Schedule MSGOUT Phase to send message */ 1765 1766 WAIT_CIP(dev); 1767 SET_SBIC_cmd(dev, SBIC_CMD_SET_ATN); 1768 WAIT_CIP(dev); 1769 GET_SBIC_asr(dev, asr); 1770 if (asr & SBIC_ASR_LCI) { 1771 printf("MSGOUT Failed!\n"); 1772 } 1773 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1774 WAIT_CIP(dev); 1775 } 1776 1777 /* 1778 * Send the highest priority, scheduled message 1779 */ 1780 void 1781 wd33c93_msgout(struct wd33c93_softc *dev) 1782 { 1783 struct wd33c93_tinfo *ti; 1784 struct wd33c93_acb *acb = dev->sc_nexus; 1785 1786 if (acb == NULL) 1787 panic("MSGOUT with no nexus"); 1788 1789 if (dev->sc_omsglen == 0) { 1790 /* Pick up highest priority message */ 1791 dev->sc_msgout = dev->sc_msgpriq & -dev->sc_msgpriq; 1792 dev->sc_msgoutq |= dev->sc_msgout; 1793 dev->sc_msgpriq &= ~dev->sc_msgout; 1794 dev->sc_omsglen = 1; /* "Default" message len */ 1795 switch (dev->sc_msgout) { 1796 case SEND_SDTR: 1797 ti = &dev->sc_tinfo[acb->xs->xs_periph->periph_target]; 1798 dev->sc_omsg[0] = MSG_EXTENDED; 1799 dev->sc_omsg[1] = MSG_EXT_SDTR_LEN; 1800 dev->sc_omsg[2] = MSG_EXT_SDTR; 1801 if (ti->flags & T_WANTSYNC) { 1802 dev->sc_omsg[3] = ti->period; 1803 dev->sc_omsg[4] = ti->offset; 1804 } else { 1805 dev->sc_omsg[3] = 0; 1806 dev->sc_omsg[4] = 0; 1807 } 1808 dev->sc_omsglen = 5; 1809 if ((dev->sc_flags & SBICF_SYNCNEGO) == 0) { 1810 if (ti->flags & T_WANTSYNC) 1811 ti->flags |= T_SYNCMODE; 1812 else 1813 ti->flags &= ~T_SYNCMODE; 1814 wd33c93_setsync(dev, ti); 1815 } 1816 break; 1817 case SEND_IDENTIFY: 1818 if (dev->sc_state != SBIC_CONNECTED) { 1819 printf("%s at line %d: no nexus\n", 1820 dev->sc_dev.dv_xname, __LINE__); 1821 } 1822 dev->sc_omsg[0] = 1823 MSG_IDENTIFY(acb->xs->xs_periph->periph_lun, 0); 1824 break; 1825 case SEND_TAG: 1826 if (dev->sc_state != SBIC_CONNECTED) { 1827 printf("%s at line %d: no nexus\n", 1828 dev->sc_dev.dv_xname, __LINE__); 1829 } 1830 dev->sc_omsg[0] = acb->tag_type; 1831 dev->sc_omsg[1] = acb->tag_id; 1832 dev->sc_omsglen = 2; 1833 break; 1834 case SEND_DEV_RESET: 1835 dev->sc_omsg[0] = MSG_BUS_DEV_RESET; 1836 ti = &dev->sc_tinfo[dev->target]; 1837 ti->flags &= ~T_SYNCMODE; 1838 wd33c93_update_xfer_mode(dev, dev->target); 1839 if ((ti->flags & T_NOSYNC) == 0) 1840 /* We can re-start sync negotiation */ 1841 ti->flags |= T_NEGOTIATE; 1842 break; 1843 case SEND_PARITY_ERROR: 1844 dev->sc_omsg[0] = MSG_PARITY_ERROR; 1845 break; 1846 case SEND_ABORT: 1847 dev->sc_flags |= SBICF_ABORTING; 1848 dev->sc_omsg[0] = MSG_ABORT; 1849 break; 1850 case SEND_INIT_DET_ERR: 1851 dev->sc_omsg[0] = MSG_INITIATOR_DET_ERR; 1852 break; 1853 case SEND_REJECT: 1854 dev->sc_omsg[0] = MSG_MESSAGE_REJECT; 1855 break; 1856 default: 1857 /* Wasn't expecting MSGOUT Phase */ 1858 dev->sc_omsg[0] = MSG_NOOP; 1859 break; 1860 } 1861 } 1862 1863 wd33c93_xfout(dev, dev->sc_omsglen, dev->sc_omsg); 1864 } 1865 1866 1867 /* 1868 * wd33c93_nextstate() 1869 * return: 1870 * SBIC_STATE_DONE == done 1871 * SBIC_STATE_RUNNING == working 1872 * SBIC_STATE_DISCONNECT == disconnected 1873 * SBIC_STATE_ERROR == error 1874 */ 1875 int 1876 wd33c93_nextstate(struct wd33c93_softc *dev, struct wd33c93_acb *acb, u_char csr, u_char asr) 1877 { 1878 SBIC_DEBUG(PHASE, ("next[a=%02x,c=%02x]: ",asr,csr)); 1879 1880 switch (csr) { 1881 1882 case SBIC_CSR_XFERRED | CMD_PHASE: 1883 case SBIC_CSR_MIS | CMD_PHASE: 1884 case SBIC_CSR_MIS_1 | CMD_PHASE: 1885 case SBIC_CSR_MIS_2 | CMD_PHASE: 1886 1887 if (wd33c93_xfout(dev, acb->clen, &acb->cmd)) 1888 goto abort; 1889 break; 1890 1891 case SBIC_CSR_XFERRED | STATUS_PHASE: 1892 case SBIC_CSR_MIS | STATUS_PHASE: 1893 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1894 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1895 1896 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1897 1898 /* 1899 * this should be the normal i/o completion case. 1900 * get the status & cmd complete msg then let the 1901 * device driver look at what happened. 1902 */ 1903 wd33c93_xferdone(dev); 1904 1905 wd33c93_dma_stop(dev); 1906 1907 /* Fixup byte count to be passed to higher layer */ 1908 acb->dleft = (acb->flags & ACB_COMPLETE) ? 0 : 1909 dev->sc_dleft; 1910 1911 /* 1912 * Indicate to the upper layers that the command is done 1913 */ 1914 wd33c93_scsidone(dev, acb, dev->sc_status); 1915 1916 return SBIC_STATE_DONE; 1917 1918 1919 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 1920 case SBIC_CSR_MIS | DATA_IN_PHASE: 1921 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 1922 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 1923 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 1924 case SBIC_CSR_MIS | DATA_OUT_PHASE: 1925 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 1926 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 1927 /* 1928 * Verify that we expected to transfer data... 1929 */ 1930 if (acb->dleft <= 0) { 1931 printf("next: DATA phase with xfer count == %zd, asr:0x%02x csr:0x%02x\n", 1932 acb->dleft, asr, csr); 1933 goto abort; 1934 } 1935 1936 /* 1937 * Should we transfer using PIO or DMA ? 1938 */ 1939 if (acb->xs->xs_control & XS_CTL_POLL || 1940 dev->sc_flags & SBICF_NODMA) { 1941 /* Perfrom transfer using PIO */ 1942 int resid; 1943 1944 SBIC_DEBUG(DMA, ("PIO xfer: %d(%p:%zx)\n", dev->target, 1945 dev->sc_daddr, dev->sc_dleft)); 1946 1947 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 1948 /* data in */ 1949 resid = wd33c93_xfin(dev, dev->sc_dleft, 1950 dev->sc_daddr); 1951 else /* data out */ 1952 resid = wd33c93_xfout(dev, dev->sc_dleft, 1953 dev->sc_daddr); 1954 1955 dev->sc_daddr = (char*)dev->sc_daddr + 1956 (acb->dleft - resid); 1957 dev->sc_dleft = resid; 1958 } else { 1959 int datain = SBIC_PHASE(csr) == DATA_IN_PHASE; 1960 1961 /* Perform transfer using DMA */ 1962 wd33c93_dma_setup(dev, datain); 1963 1964 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI | 1965 dev->sc_dmamode); 1966 1967 SBIC_DEBUG(DMA, ("DMA xfer: %d(%p:%zx)\n", dev->target, 1968 dev->sc_daddr, dev->sc_dleft)); 1969 1970 /* Setup byte count for transfer */ 1971 SBIC_TC_PUT(dev, (unsigned)dev->sc_dleft); 1972 1973 /* Start the transfer */ 1974 SET_SBIC_cmd(dev, SBIC_CMD_XFER_INFO); 1975 1976 /* Start the DMA chip going */ 1977 dev->sc_tcnt = dev->sc_dmago(dev); 1978 1979 /* Indicate that we're in DMA mode */ 1980 dev->sc_flags |= SBICF_INDMA; 1981 } 1982 break; 1983 1984 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 1985 case SBIC_CSR_MIS | MESG_IN_PHASE: 1986 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 1987 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 1988 1989 wd33c93_dma_stop(dev); 1990 1991 /* Handle a single message in... */ 1992 return wd33c93_msgin_phase(dev, 0); 1993 1994 case SBIC_CSR_MSGIN_W_ACK: 1995 1996 /* 1997 * We should never see this since it's handled in 1998 * 'wd33c93_msgin_phase()' but just for the sake of paranoia... 1999 */ 2000 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 2001 2002 printf("Acking unknown msgin CSR:%02x",csr); 2003 break; 2004 2005 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2006 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2007 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2008 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2009 2010 /* 2011 * Message out phase. ATN signal has been asserted 2012 */ 2013 wd33c93_dma_stop(dev); 2014 wd33c93_msgout(dev); 2015 return SBIC_STATE_RUNNING; 2016 2017 case SBIC_CSR_DISC: 2018 case SBIC_CSR_DISC_1: 2019 SBIC_DEBUG(RSEL, ("wd33c93next target %d disconnected\n", 2020 dev->target)); 2021 wd33c93_dma_stop(dev); 2022 2023 dev->sc_nexus = NULL; 2024 dev->sc_state = SBIC_IDLE; 2025 dev->sc_flags = 0; 2026 2027 ++dev->sc_tinfo[dev->target].dconns; 2028 ++dev->sc_disc; 2029 2030 if (acb->xs->xs_control & XS_CTL_POLL || wd33c93_nodisc) 2031 return SBIC_STATE_DISCONNECT; 2032 2033 /* Try to schedule another target */ 2034 wd33c93_sched(dev); 2035 2036 return SBIC_STATE_DISCONNECT; 2037 2038 case SBIC_CSR_RSLT_NI: 2039 case SBIC_CSR_RSLT_IFY: 2040 { 2041 /* 2042 * A reselection. 2043 * Note that since we don't enable Advanced Features (assuming 2044 * the WD chip is at least the 'A' revision), we're only ever 2045 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2046 * hell of it, we'll handle it anyway, for all the extra code 2047 * it needs... 2048 */ 2049 u_char newtarget, newlun; 2050 2051 if (dev->sc_flags & SBICF_INDMA) { 2052 printf("**** RESELECT WHILE DMA ACTIVE!!! ***\n"); 2053 wd33c93_dma_stop(dev); 2054 } 2055 2056 dev->sc_state = SBIC_RESELECTED; 2057 GET_SBIC_rselid(dev, newtarget); 2058 2059 /* check SBIC_RID_SIV? */ 2060 newtarget &= SBIC_RID_MASK; 2061 2062 if (csr == SBIC_CSR_RSLT_IFY) { 2063 /* Read Identify msg to avoid lockup */ 2064 GET_SBIC_data(dev, newlun); 2065 WAIT_CIP(dev); 2066 newlun &= SBIC_TLUN_MASK; 2067 dev->sc_msgify = MSG_IDENTIFY(newlun, 0); 2068 } else { 2069 /* 2070 * Need to read Identify message the hard way, assuming 2071 * the target even sends us one... 2072 */ 2073 for (newlun = 255; newlun; --newlun) { 2074 GET_SBIC_asr(dev, asr); 2075 if (asr & SBIC_ASR_INT) 2076 break; 2077 DELAY(10); 2078 } 2079 2080 /* If we didn't get an interrupt, somethink's up */ 2081 if ((asr & SBIC_ASR_INT) == 0) { 2082 printf("%s: Reselect without identify? asr %x\n", 2083 dev->sc_dev.dv_xname, asr); 2084 newlun = 0; /* XXXX */ 2085 } else { 2086 /* 2087 * We got an interrupt, verify that it's a 2088 * change to message in phase, and if so 2089 * read the message. 2090 */ 2091 GET_SBIC_csr(dev,csr); 2092 2093 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2094 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2095 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2096 /* 2097 * Yup, gone to message in. 2098 * Fetch the target LUN 2099 */ 2100 dev->sc_msgify = 0; 2101 wd33c93_msgin_phase(dev, 1); 2102 newlun = dev->sc_msgify & SBIC_TLUN_MASK; 2103 } else { 2104 /* 2105 * Whoops! Target didn't go to msg_in 2106 * phase!! 2107 */ 2108 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2109 newlun = 0; /* XXXSCW */ 2110 } 2111 } 2112 } 2113 2114 /* Ok, we have the identity of the reselecting target. */ 2115 SBIC_DEBUG(RSEL, ("wd33c93next: reselect from targ %d lun %d", 2116 newtarget, newlun)); 2117 wd33c93_reselect(dev, newtarget, newlun, 0, 0); 2118 dev->sc_disc--; 2119 2120 if (csr == SBIC_CSR_RSLT_IFY) 2121 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 2122 break; 2123 } 2124 2125 default: 2126 abort: 2127 /* Something unexpected happend -- deal with it. */ 2128 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2129 2130 #ifdef DDB 2131 Debugger(); 2132 #endif 2133 2134 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 2135 if (acb->xs) 2136 wd33c93_error(dev, acb); 2137 wd33c93_abort(dev, acb, "next"); 2138 2139 if (dev->sc_flags & SBICF_INDMA) { 2140 wd33c93_dma_stop(dev); 2141 wd33c93_scsidone(dev, acb, STATUS_UNKNOWN); 2142 } 2143 return SBIC_STATE_ERROR; 2144 } 2145 return SBIC_STATE_RUNNING; 2146 } 2147 2148 2149 void 2150 wd33c93_reselect(struct wd33c93_softc *dev, int target, int lun, int tag_type, int tag_id) 2151 { 2152 2153 struct wd33c93_tinfo *ti; 2154 struct wd33c93_linfo *li; 2155 struct wd33c93_acb *acb; 2156 2157 if (dev->sc_nexus) { 2158 /* 2159 * Whoops! We've been reselected with a 2160 * command in progress! 2161 * The best we can do is to put the current 2162 * command back on the ready list and hope 2163 * for the best. 2164 */ 2165 SBIC_DEBUG(RSEL, ("%s: reselect with active command\n", 2166 dev->sc_dev.dv_xname)); 2167 ti = &dev->sc_tinfo[dev->target]; 2168 li = TINFO_LUN(ti, dev->lun); 2169 li->state = L_STATE_IDLE; 2170 2171 wd33c93_dequeue(dev, dev->sc_nexus); 2172 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2173 dev->sc_nexus->flags |= ACB_READY; 2174 2175 dev->sc_nexus = NULL; 2176 } 2177 2178 /* Setup state for new nexus */ 2179 acb = NULL; 2180 dev->sc_flags = SBICF_SELECTED; 2181 dev->sc_msgpriq = dev->sc_msgout = dev->sc_msgoutq = 0; 2182 2183 ti = &dev->sc_tinfo[target]; 2184 li = TINFO_LUN(ti, lun); 2185 2186 if (li != NULL) { 2187 if (li->untagged != NULL && li->state) 2188 acb = li->untagged; 2189 else if (tag_type != MSG_SIMPLE_Q_TAG) { 2190 /* Wait for tag to come by during MESG_IN Phase */ 2191 dev->target = target; /* setup I_T_L nexus */ 2192 dev->lun = lun; 2193 dev->sc_state = SBIC_IDENTIFIED; 2194 return; 2195 } else if (tag_type) 2196 acb = li->queued[tag_id]; 2197 } 2198 2199 if (acb == NULL) { 2200 printf("%s: reselect from target %d lun %d tag %x:%x " 2201 "with no nexus; sending ABORT\n", 2202 dev->sc_dev.dv_xname, target, lun, tag_type, tag_id); 2203 goto abort; 2204 } 2205 2206 dev->target = target; 2207 dev->lun = lun; 2208 dev->sc_nexus = acb; 2209 dev->sc_state = SBIC_CONNECTED; 2210 2211 if (!wd33c93_dmaok(dev, acb->xs)) 2212 dev->sc_flags |= SBICF_NODMA; 2213 2214 /* Do an implicit RESTORE POINTERS. */ 2215 dev->sc_daddr = acb->daddr; 2216 dev->sc_dleft = acb->dleft; 2217 2218 /* Set sync modes for new target */ 2219 wd33c93_setsync(dev, ti); 2220 2221 if (acb->flags & ACB_RESET) 2222 wd33c93_sched_msgout(dev, SEND_DEV_RESET); 2223 else if (acb->flags & ACB_ABORT) 2224 wd33c93_sched_msgout(dev, SEND_ABORT); 2225 return; 2226 2227 abort: 2228 wd33c93_sched_msgout(dev, SEND_ABORT); 2229 return; 2230 2231 } 2232 2233 void 2234 wd33c93_update_xfer_mode(struct wd33c93_softc *sc, int target) 2235 { 2236 struct wd33c93_tinfo *ti = &sc->sc_tinfo[target]; 2237 struct scsipi_xfer_mode xm; 2238 2239 xm.xm_target = target; 2240 xm.xm_mode = 0; 2241 xm.xm_period = 0; 2242 xm.xm_offset = 0; 2243 2244 if (ti->flags & T_SYNCMODE) { 2245 xm.xm_mode |= PERIPH_CAP_SYNC; 2246 xm.xm_period = ti->period; 2247 xm.xm_offset = ti->offset; 2248 } 2249 2250 if ((ti->flags & (T_NODISC|T_TAG)) == T_TAG) 2251 xm.xm_mode |= PERIPH_CAP_TQING; 2252 2253 SBIC_DEBUG(SYNC, ("wd33c93_update_xfer_mode: reporting target %d %s\n", 2254 xm.xm_target, 2255 (xm.xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 2256 2257 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 2258 } 2259 2260 void 2261 wd33c93_timeout(void *arg) 2262 { 2263 struct wd33c93_acb *acb = arg; 2264 struct scsipi_xfer *xs = acb->xs; 2265 struct scsipi_periph *periph = xs->xs_periph; 2266 struct wd33c93_softc *dev = 2267 (void *)periph->periph_channel->chan_adapter->adapt_dev; 2268 int s, asr; 2269 2270 s = splbio(); 2271 2272 GET_SBIC_asr(dev, asr); 2273 2274 scsipi_printaddr(periph); 2275 printf("%s: timed out; asr=0x%02x [acb %p (flags 0x%x, dleft %zx)], " 2276 "<state %d, nexus %p, resid %lx, msg(q %x,o %x)>", 2277 dev->sc_dev.dv_xname, asr, acb, acb->flags, acb->dleft, 2278 dev->sc_state, dev->sc_nexus, (long)dev->sc_dleft, 2279 dev->sc_msgpriq, dev->sc_msgout); 2280 2281 if (asr & SBIC_ASR_INT) { 2282 /* We need to service a missed IRQ */ 2283 wd33c93_intr(dev); 2284 } else { 2285 (void) wd33c93_abort(dev, dev->sc_nexus, "timeout"); 2286 } 2287 splx(s); 2288 } 2289 2290 2291 void 2292 wd33c93_watchdog(void *arg) 2293 { 2294 struct wd33c93_softc *dev = arg; 2295 struct wd33c93_tinfo *ti; 2296 struct wd33c93_linfo *li; 2297 int t, s, l; 2298 /* scrub LUN's that have not been used in the last 10min. */ 2299 time_t old = time_second - (10 * 60); 2300 2301 for (t = 0; t < SBIC_NTARG; t++) { 2302 ti = &dev->sc_tinfo[t]; 2303 for (l = 0; l < SBIC_NLUN; l++) { 2304 s = splbio(); 2305 li = TINFO_LUN(ti, l); 2306 if (li && li->last_used < old && 2307 li->untagged == NULL && li->used == 0) { 2308 ti->lun[li->lun] = NULL; 2309 free(li, M_DEVBUF); 2310 } 2311 splx(s); 2312 } 2313 } 2314 callout_reset(&dev->sc_watchdog, 60 * hz, wd33c93_watchdog, dev); 2315 } 2316 2317 2318 #ifdef DEBUG 2319 void 2320 wd33c93_hexdump(u_char *buf, int len) 2321 { 2322 printf("{%d}:", len); 2323 while (len--) 2324 printf(" %02x", *buf++); 2325 printf("\n"); 2326 } 2327 2328 2329 void 2330 wd33c93_print_csr(u_char csr) 2331 { 2332 switch (SCSI_PHASE(csr)) { 2333 case CMD_PHASE: 2334 printf("CMD_PHASE\n"); 2335 break; 2336 2337 case STATUS_PHASE: 2338 printf("STATUS_PHASE\n"); 2339 break; 2340 2341 case DATA_IN_PHASE: 2342 printf("DATAIN_PHASE\n"); 2343 break; 2344 2345 case DATA_OUT_PHASE: 2346 printf("DATAOUT_PHASE\n"); 2347 break; 2348 2349 case MESG_IN_PHASE: 2350 printf("MESG_IN_PHASE\n"); 2351 break; 2352 2353 case MESG_OUT_PHASE: 2354 printf("MESG_OUT_PHASE\n"); 2355 break; 2356 2357 default: 2358 switch (csr) { 2359 case SBIC_CSR_DISC_1: 2360 printf("DISC_1\n"); 2361 break; 2362 2363 case SBIC_CSR_RSLT_NI: 2364 printf("RESELECT_NO_IFY\n"); 2365 break; 2366 2367 case SBIC_CSR_RSLT_IFY: 2368 printf("RESELECT_IFY\n"); 2369 break; 2370 2371 case SBIC_CSR_SLT: 2372 printf("SELECT\n"); 2373 break; 2374 2375 case SBIC_CSR_SLT_ATN: 2376 printf("SELECT, ATN\n"); 2377 break; 2378 2379 case SBIC_CSR_UNK_GROUP: 2380 printf("UNK_GROUP\n"); 2381 break; 2382 2383 default: 2384 printf("UNKNOWN csr=%02x\n", csr); 2385 } 2386 } 2387 } 2388 #endif 2389
Indexes created Wed Sep 24 05:09:52 GMT 2025