wd33c93.c revision 1.14
1 /* $NetBSD: wd33c93.c,v 1.14 2007/05/08 02:08:17 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37 /* 38 * Changes Copyright (c) 2001 Wayne Knowles 39 * Changes Copyright (c) 1996 Steve Woodford 40 * Original Copyright (c) 1994 Christian E. Hopps 41 * 42 * This code is derived from software contributed to Berkeley by 43 * Van Jacobson of Lawrence Berkeley Laboratory. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 74 */ 75 76 /* 77 * This version of the driver is pretty well generic, so should work with 78 * any flavour of WD33C93 chip. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.14 2007/05/08 02:08:17 rumble Exp $"); 83 84 #include "opt_ddb.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> /* For hz */ 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsiconf.h> 96 #include <dev/scsipi/scsi_message.h> 97 98 #include <uvm/uvm_extern.h> 99 100 #include <machine/bus.h> 101 102 #include <dev/ic/wd33c93reg.h> 103 #include <dev/ic/wd33c93var.h> 104 105 /* 106 * SCSI delays 107 * In u-seconds, primarily for state changes on the SPC. 108 */ 109 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 110 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 111 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 112 113 #define STATUS_UNKNOWN 0xff /* uninitialized status */ 114 115 /* 116 * Convenience macro for waiting for a particular wd33c93 event 117 */ 118 #define SBIC_WAIT(regs, until, timeo) wd33c93_wait(regs, until, timeo, __LINE__) 119 120 void wd33c93_init (struct wd33c93_softc *); 121 void wd33c93_reset (struct wd33c93_softc *); 122 int wd33c93_go (struct wd33c93_softc *, struct wd33c93_acb *); 123 int wd33c93_dmaok (struct wd33c93_softc *, struct scsipi_xfer *); 124 int wd33c93_wait (struct wd33c93_softc *, u_char, int , int); 125 u_char wd33c93_selectbus (struct wd33c93_softc *, struct wd33c93_acb *); 126 int wd33c93_xfout (struct wd33c93_softc *, int, void *); 127 int wd33c93_xfin (struct wd33c93_softc *, int, void *); 128 int wd33c93_poll (struct wd33c93_softc *, struct wd33c93_acb *); 129 int wd33c93_nextstate (struct wd33c93_softc *, struct wd33c93_acb *, 130 u_char, u_char); 131 int wd33c93_abort (struct wd33c93_softc *, struct wd33c93_acb *, 132 const char *); 133 void wd33c93_xferdone (struct wd33c93_softc *); 134 void wd33c93_error (struct wd33c93_softc *, struct wd33c93_acb *); 135 void wd33c93_scsidone (struct wd33c93_softc *, struct wd33c93_acb *, int); 136 void wd33c93_sched (struct wd33c93_softc *); 137 void wd33c93_dequeue (struct wd33c93_softc *, struct wd33c93_acb *); 138 void wd33c93_dma_stop (struct wd33c93_softc *); 139 void wd33c93_dma_setup (struct wd33c93_softc *, int); 140 int wd33c93_msgin_phase (struct wd33c93_softc *, int); 141 void wd33c93_msgin (struct wd33c93_softc *, u_char *, int); 142 void wd33c93_reselect (struct wd33c93_softc *, int, int, int, int); 143 void wd33c93_sched_msgout (struct wd33c93_softc *, u_short); 144 void wd33c93_msgout (struct wd33c93_softc *); 145 void wd33c93_timeout (void *arg); 146 void wd33c93_watchdog (void *arg); 147 u_char wd33c93_stp2syn (struct wd33c93_softc *, struct wd33c93_tinfo *); 148 void wd33c93_setsync (struct wd33c93_softc *, struct wd33c93_tinfo *); 149 void wd33c93_update_xfer_mode (struct wd33c93_softc *, int); 150 151 static struct pool wd33c93_pool; /* Adapter Control Blocks */ 152 static int wd33c93_pool_initialized = 0; 153 154 /* 155 * Timeouts 156 */ 157 int wd33c93_cmd_wait = SBIC_CMD_WAIT; 158 int wd33c93_data_wait = SBIC_DATA_WAIT; 159 int wd33c93_init_wait = SBIC_INIT_WAIT; 160 161 int wd33c93_nodma = 0; /* Use polled IO transfers */ 162 int wd33c93_nodisc = 0; /* Allow command queues */ 163 int wd33c93_notags = 0; /* No Tags */ 164 165 /* 166 * Some useful stuff for debugging purposes 167 */ 168 #ifdef DEBUG 169 170 #define QPRINTF(a) SBIC_DEBUG(MISC, a) 171 172 int wd33c93_debug = 0; /* Debug flags */ 173 174 void wd33c93_print_csr (u_char); 175 void wd33c93_hexdump (u_char *, int); 176 177 #else 178 #define QPRINTF(a) /* */ 179 #endif 180 181 static const char *wd33c93_chip_names[] = SBIC_CHIP_LIST; 182 183 /* 184 * Attach instance of driver and probe for sub devices 185 */ 186 void 187 wd33c93_attach(struct wd33c93_softc *dev) 188 { 189 struct scsipi_adapter *adapt = &dev->sc_adapter; 190 struct scsipi_channel *chan = &dev->sc_channel; 191 192 adapt->adapt_dev = &dev->sc_dev; 193 adapt->adapt_nchannels = 1; 194 adapt->adapt_openings = 256; 195 adapt->adapt_max_periph = 256; /* Max tags per device */ 196 adapt->adapt_ioctl = NULL; 197 /* adapt_request initialized by MD interface */ 198 /* adapt_minphys initialized by MD interface */ 199 200 memset(chan, 0, sizeof(*chan)); 201 chan->chan_adapter = &dev->sc_adapter; 202 chan->chan_bustype = &scsi_bustype; 203 chan->chan_channel = 0; 204 chan->chan_ntargets = SBIC_NTARG; 205 chan->chan_nluns = SBIC_NLUN; 206 chan->chan_id = dev->sc_id; 207 208 callout_init(&dev->sc_watchdog); 209 210 /* 211 * Add reference to adapter so that we drop the reference after 212 * config_found() to make sure the adatper is disabled. 213 */ 214 if (scsipi_adapter_addref(&dev->sc_adapter) != 0) { 215 printf("%s: unable to enable controller\n", 216 dev->sc_dev.dv_xname); 217 return; 218 } 219 220 dev->sc_cfflags = device_cfdata(&dev->sc_dev)->cf_flags; 221 wd33c93_init(dev); 222 223 printf(": %s (%d.%d MHz clock, %s, SCSI ID %d)\n", 224 wd33c93_chip_names[dev->sc_chip], 225 dev->sc_clkfreq / 10, dev->sc_clkfreq % 10, 226 (dev->sc_dmamode == SBIC_CTL_DMA) ? "DMA" : 227 (dev->sc_dmamode == SBIC_CTL_DBA_DMA) ? "DBA" : 228 (dev->sc_dmamode == SBIC_CTL_BURST_DMA) ? "BURST DMA" : "PIO", 229 dev->sc_channel.chan_id); 230 if (dev->sc_chip == SBIC_CHIP_WD33C93B) { 231 printf("%s: microcode revision 0x%02x", 232 dev->sc_dev.dv_xname, dev->sc_rev); 233 if (dev->sc_minsyncperiod < 50) 234 printf(", Fast SCSI"); 235 printf("\n"); 236 } 237 238 dev->sc_child = config_found(&dev->sc_dev, &dev->sc_channel, 239 scsiprint); 240 scsipi_adapter_delref(&dev->sc_adapter); 241 } 242 243 /* 244 * Initialize driver-private structures 245 */ 246 void 247 wd33c93_init(struct wd33c93_softc *dev) 248 { 249 u_int i; 250 251 if (!wd33c93_pool_initialized) { 252 /* All instances share the same pool */ 253 pool_init(&wd33c93_pool, sizeof(struct wd33c93_acb), 0, 0, 0, 254 "wd33c93_acb", NULL, IPL_BIO); 255 ++wd33c93_pool_initialized; 256 } 257 258 if (dev->sc_state == 0) { 259 TAILQ_INIT(&dev->ready_list); 260 261 dev->sc_nexus = NULL; 262 dev->sc_disc = 0; 263 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 264 265 callout_reset(&dev->sc_watchdog, 60 * hz, wd33c93_watchdog, dev); 266 } else 267 panic("wd33c93: reinitializing driver!"); 268 269 dev->sc_flags = 0; 270 dev->sc_state = SBIC_IDLE; 271 wd33c93_reset(dev); 272 273 for (i = 0; i < 8; i++) { 274 struct wd33c93_tinfo *ti = &dev->sc_tinfo[i]; 275 /* 276 * sc_flags = 0xTTRRSS 277 * 278 * TT = Bitmask to disable Tagged Queues 279 * RR = Bitmask to disable disconnect/reselect 280 * SS = Bitmask to diable Sync negotiation 281 */ 282 ti->flags = T_NEED_RESET; 283 if (dev->sc_cfflags & (1<<(i+8))) 284 ti->flags |= T_NOSYNC; 285 if (dev->sc_cfflags & (1<<i) || wd33c93_nodisc) 286 ti->flags |= T_NODISC; 287 ti->period = dev->sc_minsyncperiod; 288 ti->offset = 0; 289 } 290 } 291 292 void 293 wd33c93_reset(struct wd33c93_softc *dev) 294 { 295 u_int my_id, s, div, i; 296 u_char csr, reg; 297 298 SET_SBIC_cmd(dev, SBIC_CMD_ABORT); 299 WAIT_CIP(dev); 300 301 s = splbio(); 302 303 if (dev->sc_reset != NULL) 304 (*dev->sc_reset)(dev); 305 306 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 307 308 /* Enable advanced features and really(!) advanced features */ 309 #if 1 310 my_id |= (SBIC_ID_EAF | SBIC_ID_RAF); /* XXX - MD Layer */ 311 #endif 312 313 SET_SBIC_myid(dev, my_id); 314 315 /* Reset the chip */ 316 SET_SBIC_cmd(dev, SBIC_CMD_RESET); 317 DELAY(25); 318 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 319 320 /* Set up various chip parameters */ 321 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 322 323 GET_SBIC_csr(dev, csr); /* clears interrupt also */ 324 GET_SBIC_cdb1(dev, dev->sc_rev); /* valid with RAF on wd33c93b */ 325 326 switch (csr) { 327 case SBIC_CSR_RESET: 328 dev->sc_chip = SBIC_CHIP_WD33C93; 329 break; 330 case SBIC_CSR_RESET_AM: 331 SET_SBIC_queue_tag(dev, 0x55); 332 GET_SBIC_queue_tag(dev, reg); 333 dev->sc_chip = (reg == 0x55) ? 334 SBIC_CHIP_WD33C93B : SBIC_CHIP_WD33C93A; 335 SET_SBIC_queue_tag(dev, 0x0); 336 break; 337 default: 338 dev->sc_chip = SBIC_CHIP_UNKNOWN; 339 } 340 341 /* 342 * Choose a suitable clock divisor and work out the resulting 343 * sync transfer periods in 4ns units. 344 */ 345 if (dev->sc_clkfreq < 110) { 346 my_id |= SBIC_ID_FS_8_10; 347 div = 2; 348 } else if (dev->sc_clkfreq < 160) { 349 my_id |= SBIC_ID_FS_12_15; 350 div = 3; 351 } else if (dev->sc_clkfreq < 210) { 352 my_id |= SBIC_ID_FS_16_20; 353 div = 4; 354 } else 355 panic("wd33c93: invalid clock speed %d", dev->sc_clkfreq); 356 357 for (i = 0; i < 7; i++) 358 dev->sc_syncperiods[i] = 359 (i + 2) * div * 1250 / dev->sc_clkfreq; 360 dev->sc_minsyncperiod = dev->sc_syncperiods[0]; 361 SBIC_DEBUG(SYNC, ("available sync periods: %d %d %d %d %d %d %d\n", 362 dev->sc_syncperiods[0], dev->sc_syncperiods[1], 363 dev->sc_syncperiods[2], dev->sc_syncperiods[3], 364 dev->sc_syncperiods[4], dev->sc_syncperiods[5], 365 dev->sc_syncperiods[6])); 366 367 if (dev->sc_clkfreq >= 160 && dev->sc_chip == SBIC_CHIP_WD33C93B) { 368 for (i = 0; i < 3; i++) 369 dev->sc_fsyncperiods[i] = 370 (i + 2) * 2 * 1250 / dev->sc_clkfreq; 371 SBIC_DEBUG(SYNC, ("available fast sync periods: %d %d %d\n", 372 dev->sc_fsyncperiods[0], dev->sc_fsyncperiods[1], 373 dev->sc_fsyncperiods[2])); 374 dev->sc_minsyncperiod = dev->sc_fsyncperiods[0]; 375 } 376 377 /* Max Sync Offset */ 378 if (dev->sc_chip == SBIC_CHIP_WD33C93A || 379 dev->sc_chip == SBIC_CHIP_WD33C93B) 380 dev->sc_maxoffset = SBIC_SYN_93AB_MAX_OFFSET; 381 else 382 dev->sc_maxoffset = SBIC_SYN_93_MAX_OFFSET; 383 384 /* 385 * don't allow Selection (SBIC_RID_ES) 386 * until we can handle target mode!! 387 */ 388 SET_SBIC_rselid(dev, SBIC_RID_ER); 389 390 /* Asynchronous for now */ 391 SET_SBIC_syn(dev, 0); 392 393 dev->sc_flags = 0; 394 dev->sc_state = SBIC_IDLE; 395 396 splx(s); 397 } 398 399 void 400 wd33c93_error(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 401 { 402 struct scsipi_xfer *xs = acb->xs; 403 404 KASSERT(xs); 405 406 if (xs->xs_control & XS_CTL_SILENT) 407 return; 408 409 scsipi_printaddr(xs->xs_periph); 410 printf("SCSI Error\n"); 411 } 412 413 /* 414 * Determine an appropriate value for the synchronous transfer register 415 * given the period and offset values in *ti. 416 */ 417 u_char 418 wd33c93_stp2syn(struct wd33c93_softc *dev, struct wd33c93_tinfo *ti) 419 { 420 unsigned i; 421 422 /* see if we can handle fast scsi (100-200ns) first */ 423 if (ti->period < 50 && dev->sc_minsyncperiod < 50) { 424 for (i = 0; i < 3; i++) 425 if (dev->sc_fsyncperiods[i] >= ti->period) 426 return (SBIC_SYN(ti->offset, i + 2, 1)); 427 } 428 429 for (i = 0; i < 7; i++) { 430 if (dev->sc_syncperiods[i] >= ti->period) { 431 if (i == 6) 432 return (SBIC_SYN(0, 0, 0)); 433 else 434 return (SBIC_SYN(ti->offset, i + 2, 0)); 435 } 436 } 437 438 /* XXX - can't handle it; do async */ 439 return (SBIC_SYN(0, 0, 0)); 440 } 441 442 /* 443 * Setup sync mode for given target 444 */ 445 void 446 wd33c93_setsync(struct wd33c93_softc *dev, struct wd33c93_tinfo *ti) 447 { 448 u_char syncreg; 449 450 if (ti->flags & T_SYNCMODE) 451 syncreg = wd33c93_stp2syn(dev, ti); 452 else 453 syncreg = SBIC_SYN(0, 0, 0); 454 455 SBIC_DEBUG(SYNC, ("wd33c93_setsync: sync reg = 0x%02x\n", syncreg)); 456 SET_SBIC_syn(dev, syncreg); 457 } 458 459 /* 460 * Check if current operation can be done using DMA 461 * 462 * returns 1 if DMA OK, 0 for polled I/O transfer 463 */ 464 int 465 wd33c93_dmaok(struct wd33c93_softc *dev, struct scsipi_xfer *xs) 466 { 467 if (wd33c93_nodma || (xs->xs_control & XS_CTL_POLL) || xs->datalen == 0) 468 return (0); 469 return(1); 470 } 471 472 /* 473 * Setup for DMA transfer 474 */ 475 void 476 wd33c93_dma_setup(struct wd33c93_softc *dev, int datain) 477 { 478 struct wd33c93_acb *acb = dev->sc_nexus; 479 int s; 480 481 dev->sc_daddr = acb->daddr; 482 dev->sc_dleft = acb->dleft; 483 484 s = splbio(); 485 /* Indicate that we're in DMA mode */ 486 if (dev->sc_dleft) { 487 dev->sc_dmasetup(dev, &dev->sc_daddr, &dev->sc_dleft, 488 datain, &dev->sc_dleft); 489 } 490 splx(s); 491 return; 492 } 493 494 495 /* 496 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 497 */ 498 void 499 wd33c93_dma_stop(struct wd33c93_softc *dev) 500 { 501 size_t count; 502 int asr; 503 504 /* Wait until WD chip is idle */ 505 do { 506 GET_SBIC_asr(dev, asr); /* XXX */ 507 if (asr & SBIC_ASR_DBR) { 508 printf("wd33c93_dma_stop: asr %02x canceled!\n", asr); 509 break; 510 } 511 } while (asr & (SBIC_ASR_BSY|SBIC_ASR_CIP)); 512 513 /* Only need to save pointers if DMA was active */ 514 if (dev->sc_flags & SBICF_INDMA) { 515 int s = splbio(); 516 517 /* Shut down DMA and flush FIFO's */ 518 dev->sc_dmastop(dev); 519 520 /* Fetch the residual count */ 521 SBIC_TC_GET(dev, count); 522 523 /* Work out how many bytes were actually transferred */ 524 count = dev->sc_tcnt - count; 525 526 if (dev->sc_dleft < count) 527 printf("xfer too large: dleft=%zu resid=%zu\n", 528 dev->sc_dleft, count); 529 530 /* Fixup partial xfers */ 531 dev->sc_daddr = (char*)dev->sc_daddr + count; 532 dev->sc_dleft -= count; 533 dev->sc_tcnt = 0; 534 dev->sc_flags &= ~SBICF_INDMA; 535 splx(s); 536 SBIC_DEBUG(DMA, ("dma_stop\n")); 537 } 538 /* 539 * Ensure the WD chip is back in polled I/O mode, with nothing to 540 * transfer. 541 */ 542 SBIC_TC_PUT(dev, 0); 543 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 544 } 545 546 547 /* 548 * Handle new request from scsipi layer 549 */ 550 void 551 wd33c93_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 552 { 553 struct wd33c93_softc *dev = (void *)chan->chan_adapter->adapt_dev; 554 struct scsipi_xfer *xs; 555 struct scsipi_periph *periph; 556 struct wd33c93_acb *acb; 557 int flags, s; 558 559 switch (req) { 560 case ADAPTER_REQ_RUN_XFER: 561 xs = arg; 562 periph = xs->xs_periph; 563 flags = xs->xs_control; 564 565 if (flags & XS_CTL_DATA_UIO) 566 panic("wd33c93: scsi data uio requested"); 567 568 if (dev->sc_nexus && (flags & XS_CTL_POLL)) 569 panic("wd33c93_scsicmd: busy"); 570 571 s = splbio(); 572 acb = (struct wd33c93_acb *)pool_get(&wd33c93_pool, PR_NOWAIT); 573 splx(s); 574 575 if (acb == NULL) { 576 scsipi_printaddr(periph); 577 printf("cannot allocate acb\n"); 578 xs->error = XS_RESOURCE_SHORTAGE; 579 scsipi_done(xs); 580 return; 581 } 582 583 acb->flags = ACB_ACTIVE; 584 acb->xs = xs; 585 acb->clen = xs->cmdlen; 586 acb->daddr = xs->data; 587 acb->dleft = xs->datalen; 588 acb->timeout = xs->timeout; 589 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 590 591 if (flags & XS_CTL_POLL) { 592 /* 593 * Complete currently active command(s) before 594 * issuing an immediate command 595 */ 596 while (dev->sc_nexus) 597 wd33c93_poll(dev, dev->sc_nexus); 598 } 599 600 s = splbio(); 601 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 602 acb->flags |= ACB_READY; 603 604 /* If nothing is active, try to start it now. */ 605 if (dev->sc_state == SBIC_IDLE) 606 wd33c93_sched(dev); 607 splx(s); 608 609 if ((flags & XS_CTL_POLL) == 0) 610 return; 611 612 if (wd33c93_poll(dev, acb)) { 613 wd33c93_timeout(acb); 614 if (wd33c93_poll(dev, acb)) /* 2nd retry for ABORT */ 615 wd33c93_timeout(acb); 616 } 617 return; 618 619 case ADAPTER_REQ_GROW_RESOURCES: 620 /* XXX Not supported. */ 621 return; 622 623 case ADAPTER_REQ_SET_XFER_MODE: 624 { 625 struct wd33c93_tinfo *ti; 626 struct scsipi_xfer_mode *xm = arg; 627 628 ti = &dev->sc_tinfo[xm->xm_target]; 629 ti->flags &= ~T_WANTSYNC; 630 631 if ((dev->sc_cfflags & (1<<(xm->xm_target+16))) == 0 && 632 (xm->xm_mode & PERIPH_CAP_TQING) && !wd33c93_notags) 633 ti->flags |= T_TAG; 634 else 635 ti->flags &= ~T_TAG; 636 637 SBIC_DEBUG(SYNC, ("wd33c93_scsi_request: " 638 "target %d: scsipi requested %s\n", xm->xm_target, 639 (xm->xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 640 641 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 642 (ti->flags & T_NOSYNC) == 0) 643 ti->flags |= T_WANTSYNC; 644 /* 645 * If we're not going to negotiate, send the notification 646 * now, since it won't happen later. 647 */ 648 if (!(ti->flags & T_WANTSYNC) == !(ti->flags & T_SYNCMODE)) 649 wd33c93_update_xfer_mode(dev, xm->xm_target); 650 else 651 ti->flags |= T_NEGOTIATE; 652 return; 653 } 654 655 } 656 } 657 658 /* 659 * attempt to start the next available command 660 */ 661 void 662 wd33c93_sched(struct wd33c93_softc *dev) 663 { 664 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 665 struct wd33c93_acb *acb; 666 struct wd33c93_tinfo *ti; 667 struct wd33c93_linfo *li; 668 int lun, tag, flags; 669 670 if (dev->sc_state != SBIC_IDLE) 671 return; 672 673 KASSERT(dev->sc_nexus == NULL); 674 675 /* Loop through the ready list looking for work to do... */ 676 TAILQ_FOREACH(acb, &dev->ready_list, chain) { 677 periph = acb->xs->xs_periph; 678 lun = periph->periph_lun; 679 ti = &dev->sc_tinfo[periph->periph_target]; 680 li = TINFO_LUN(ti, lun); 681 682 KASSERT(acb->flags & ACB_READY); 683 684 /* Select type of tag for this command */ 685 if ((ti->flags & T_NODISC) != 0) 686 tag = 0; 687 else if ((ti->flags & T_TAG) == 0) 688 tag = 0; 689 else if ((acb->flags & ACB_SENSE) != 0) 690 tag = 0; 691 else if (acb->xs->xs_control & XS_CTL_POLL) 692 tag = 0; /* No tags for polled commands */ 693 else 694 tag = acb->xs->xs_tag_type; 695 696 if (li == NULL) { 697 /* Initialize LUN info and add to list. */ 698 li = malloc(sizeof(*li), M_DEVBUF, M_NOWAIT); 699 if (li == NULL) 700 continue; 701 memset(li, 0, sizeof(*li)); 702 li->lun = lun; 703 if (lun < SBIC_NLUN) 704 ti->lun[lun] = li; 705 } 706 li->last_used = time_second; 707 708 /* 709 * We've found a potential command, but is the target/lun busy? 710 */ 711 712 if (tag == 0 && li->untagged == NULL) 713 li->untagged = acb; /* Issue untagged */ 714 715 if (li->untagged != NULL) { 716 tag = 0; 717 if ((li->state != L_STATE_BUSY) && li->used == 0) { 718 /* Issue this untagged command now */ 719 acb = li->untagged; 720 periph = acb->xs->xs_periph; 721 } else /* Not ready yet */ 722 continue; 723 } 724 725 acb->tag_type = tag; 726 if (tag != 0) { 727 if (li->queued[acb->xs->xs_tag_id]) 728 printf("queueing to active tag\n"); 729 li->queued[acb->xs->xs_tag_id] = acb; 730 acb->tag_id = acb->xs->xs_tag_id; 731 li->used++; 732 break; 733 } 734 if (li->untagged != NULL && (li->state != L_STATE_BUSY)) { 735 li->state = L_STATE_BUSY; 736 break; 737 } 738 if (li->untagged == NULL && tag != 0) { 739 break; 740 } else 741 printf("%d:%d busy\n", periph->periph_target, 742 periph->periph_lun); 743 } 744 745 if (acb == NULL) { 746 SBIC_DEBUG(ACBS, ("wd33c93sched: no work\n")); 747 return; /* did not find an available command */ 748 } 749 750 SBIC_DEBUG(ACBS, ("wd33c93_sched(%d,%d)\n", periph->periph_target, 751 periph->periph_lun)); 752 753 TAILQ_REMOVE(&dev->ready_list, acb, chain); 754 acb->flags &= ~ACB_READY; 755 756 flags = acb->xs->xs_control; 757 if (flags & XS_CTL_RESET) 758 wd33c93_reset(dev); 759 760 /* XXX - Implicitly call scsidone on select timeout */ 761 if (wd33c93_go(dev, acb) != 0 || acb->xs->error == XS_SELTIMEOUT) { 762 acb->dleft = dev->sc_dleft; 763 wd33c93_scsidone(dev, acb, dev->sc_status); 764 return; 765 } 766 767 return; 768 } 769 770 void 771 wd33c93_scsidone(struct wd33c93_softc *dev, struct wd33c93_acb *acb, int status) 772 { 773 struct scsipi_xfer *xs = acb->xs; 774 struct wd33c93_tinfo *ti; 775 struct wd33c93_linfo *li; 776 int s; 777 778 #ifdef DIAGNOSTIC 779 KASSERT(dev->target == xs->xs_periph->periph_target); 780 KASSERT(dev->lun == xs->xs_periph->periph_lun); 781 if (acb == NULL || xs == NULL) { 782 panic("wd33c93_scsidone -- (%d,%d) no scsipi_xfer", 783 dev->target, dev->lun); 784 } 785 KASSERT(acb->flags != ACB_FREE); 786 #endif 787 788 SBIC_DEBUG(ACBS, ("scsidone: (%d,%d)->(%d,%d)%02x\n", 789 xs->xs_periph->periph_target, xs->xs_periph->periph_lun, 790 dev->target, dev->lun, status)); 791 callout_stop(&xs->xs_callout); 792 793 xs->status = status & SCSI_STATUS_MASK; 794 xs->resid = acb->dleft; 795 796 if (xs->error == XS_NOERROR) { 797 switch (xs->status) { 798 case SCSI_CHECK: 799 case SCSI_TERMINATED: 800 /* XXX Need to read sense - return busy for now */ 801 /*FALLTHROUGH*/ 802 case SCSI_QUEUE_FULL: 803 case SCSI_BUSY: 804 xs->error = XS_BUSY; 805 break; 806 } 807 } 808 809 ti = &dev->sc_tinfo[dev->target]; 810 li = TINFO_LUN(ti, dev->lun); 811 ti->cmds++; 812 if (xs->error == XS_SELTIMEOUT) { 813 /* Selection timeout -- discard this LUN if empty */ 814 if (li->untagged == NULL && li->used == 0) { 815 if (dev->lun < SBIC_NLUN) 816 ti->lun[dev->lun] = NULL; 817 free(li, M_DEVBUF); 818 } 819 } 820 821 wd33c93_dequeue(dev, acb); 822 if (dev->sc_nexus == acb) { 823 dev->sc_state = SBIC_IDLE; 824 dev->sc_nexus = NULL; 825 dev->sc_flags = 0; 826 827 if (!TAILQ_EMPTY(&dev->ready_list)) 828 wd33c93_sched(dev); 829 } 830 831 /* place control block back on free list. */ 832 s = splbio(); 833 acb->flags = ACB_FREE; 834 pool_put(&wd33c93_pool, (void *)acb); 835 splx(s); 836 837 scsipi_done(xs); 838 } 839 840 void 841 wd33c93_dequeue(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 842 { 843 struct wd33c93_tinfo *ti = &dev->sc_tinfo[acb->xs->xs_periph->periph_target]; 844 struct wd33c93_linfo *li; 845 int lun = acb->xs->xs_periph->periph_lun; 846 847 li = TINFO_LUN(ti, lun); 848 #ifdef DIAGNOSTIC 849 if (li == NULL || li->lun != lun) 850 panic("wd33c93_dequeue: lun %d for ecb %p does not exist", 851 lun, acb); 852 #endif 853 if (li->untagged == acb) { 854 li->state = L_STATE_IDLE; 855 li->untagged = NULL; 856 } 857 if (acb->tag_type && li->queued[acb->tag_id] != NULL) { 858 #ifdef DIAGNOSTIC 859 if (li->queued[acb->tag_id] != NULL && 860 (li->queued[acb->tag_id] != acb)) 861 panic("wd33c93_dequeue: slot %d for lun %d has %p " 862 "instead of acb %p\n", acb->tag_id, 863 lun, li->queued[acb->tag_id], acb); 864 #endif 865 li->queued[acb->tag_id] = NULL; 866 li->used--; 867 } 868 } 869 870 871 int 872 wd33c93_wait(struct wd33c93_softc *dev, u_char until, int timeo, int line) 873 { 874 u_char val; 875 876 if (timeo == 0) 877 timeo = 1000000; /* some large value.. */ 878 GET_SBIC_asr(dev, val); 879 while ((val & until) == 0) { 880 if (timeo-- == 0) { 881 int csr; 882 GET_SBIC_csr(dev, csr); 883 printf("wd33c93_wait: TIMEO @%d with asr=x%x csr=x%x\n", 884 line, val, csr); 885 #if defined(DDB) && defined(DEBUG) 886 Debugger(); 887 #endif 888 return(val); /* Maybe I should abort */ 889 break; 890 } 891 DELAY(1); 892 GET_SBIC_asr(dev, val); 893 } 894 return(val); 895 } 896 897 int 898 wd33c93_abort(struct wd33c93_softc *dev, struct wd33c93_acb *acb, 899 const char *where) 900 { 901 u_char csr, asr; 902 903 GET_SBIC_asr(dev, asr); 904 GET_SBIC_csr(dev, csr); 905 906 scsipi_printaddr(acb->xs->xs_periph); 907 printf ("ABORT in %s: csr=0x%02x, asr=0x%02x\n", where, csr, asr); 908 909 acb->timeout = SBIC_ABORT_TIMEOUT; 910 acb->flags |= ACB_ABORT; 911 912 /* 913 * Clean up chip itself 914 */ 915 if (dev->sc_nexus == acb) { 916 /* Reschedule timeout. */ 917 callout_reset(&acb->xs->xs_callout, mstohz(acb->timeout), 918 wd33c93_timeout, acb); 919 920 while (asr & SBIC_ASR_DBR) { 921 /* 922 * wd33c93 is jammed w/data. need to clear it 923 * But we don't know what direction it needs to go 924 */ 925 GET_SBIC_data(dev, asr); 926 printf("abort %s: clearing data buffer 0x%02x\n", 927 where, asr); 928 GET_SBIC_asr(dev, asr); 929 if (asr & SBIC_ASR_DBR) /* Not the read direction */ 930 SET_SBIC_data(dev, asr); 931 GET_SBIC_asr(dev, asr); 932 } 933 934 scsipi_printaddr(acb->xs->xs_periph); 935 printf("sending ABORT command\n"); 936 937 WAIT_CIP(dev); 938 SET_SBIC_cmd(dev, SBIC_CMD_ABORT); 939 WAIT_CIP(dev); 940 941 GET_SBIC_asr(dev, asr); 942 943 scsipi_printaddr(acb->xs->xs_periph); 944 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 945 /* 946 * ok, get more drastic.. 947 */ 948 printf("Resetting bus\n"); 949 wd33c93_reset(dev); 950 } else { 951 printf("sending DISCONNECT to target\n"); 952 SET_SBIC_cmd(dev, SBIC_CMD_DISC); 953 WAIT_CIP(dev); 954 955 do { 956 SBIC_WAIT (dev, SBIC_ASR_INT, 0); 957 GET_SBIC_asr(dev, asr); 958 GET_SBIC_csr(dev, csr); 959 SBIC_DEBUG(MISC, ("csr: 0x%02x, asr: 0x%02x\n", 960 csr, asr)); 961 } while ((csr != SBIC_CSR_DISC) && 962 (csr != SBIC_CSR_DISC_1) && 963 (csr != SBIC_CSR_CMD_INVALID)); 964 } 965 dev->sc_state = SBIC_ERROR; 966 dev->sc_flags = 0; 967 } 968 return SBIC_STATE_ERROR; 969 } 970 971 972 /* 973 * select the bus, return when selected or error. 974 * 975 * Returns the current CSR following selection and optionally MSG out phase. 976 * i.e. the returned CSR *should* indicate CMD phase... 977 * If the return value is 0, some error happened. 978 */ 979 u_char 980 wd33c93_selectbus(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 981 { 982 struct scsipi_xfer *xs = acb->xs; 983 struct wd33c93_tinfo *ti; 984 u_char target, lun, asr, csr, id; 985 986 KASSERT(dev->sc_state == SBIC_IDLE); 987 988 target = xs->xs_periph->periph_target; 989 lun = xs->xs_periph->periph_lun; 990 ti = &dev->sc_tinfo[target]; 991 992 dev->sc_state = SBIC_SELECTING; 993 dev->target = target; 994 dev->lun = lun; 995 996 SBIC_DEBUG(PHASE, ("wd33c93_selectbus %d: ", target)); 997 998 if ((xs->xs_control & XS_CTL_POLL) == 0) 999 callout_reset(&xs->xs_callout, mstohz(acb->timeout), 1000 wd33c93_timeout, acb); 1001 1002 /* 1003 * issue select 1004 */ 1005 SBIC_TC_PUT(dev, 0); 1006 SET_SBIC_selid(dev, target); 1007 SET_SBIC_timeo(dev, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 1008 1009 GET_SBIC_asr(dev, asr); 1010 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) { 1011 /* This means we got ourselves reselected upon */ 1012 SBIC_DEBUG(PHASE, ("WD busy (reselect?) ASR=%02x\n", asr)); 1013 return 0; 1014 } 1015 1016 SET_SBIC_cmd(dev, SBIC_CMD_SEL_ATN); 1017 WAIT_CIP(dev); 1018 1019 /* 1020 * wait for select (merged from separate function may need 1021 * cleanup) 1022 */ 1023 do { 1024 asr = SBIC_WAIT(dev, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1025 if (asr & SBIC_ASR_LCI) { 1026 QPRINTF(("late LCI: asr %02x\n", asr)); 1027 return 0; 1028 } 1029 1030 /* Clear interrupt */ 1031 GET_SBIC_csr (dev, csr); 1032 1033 /* Reselected from under our feet? */ 1034 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1035 SBIC_DEBUG(PHASE, ("got reselected, asr %02x\n", asr)); 1036 /* 1037 * We need to handle this now so we don't lock up later 1038 */ 1039 wd33c93_nextstate(dev, acb, csr, asr); 1040 return 0; 1041 } 1042 1043 /* Whoops! */ 1044 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1045 panic("wd33c93_selectbus: target issued select!"); 1046 return 0; 1047 } 1048 1049 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1050 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1051 csr != SBIC_CSR_SEL_TIMEO); 1052 1053 /* Anyone at home? */ 1054 if (csr == SBIC_CSR_SEL_TIMEO) { 1055 xs->error = XS_SELTIMEOUT; 1056 SBIC_DEBUG(PHASE, ("-- Selection Timeout\n")); 1057 return 0; 1058 } 1059 1060 SBIC_DEBUG(PHASE, ("Selection Complete\n")); 1061 1062 /* Assume we're now selected */ 1063 GET_SBIC_selid(dev, id); 1064 if (id != target) { 1065 /* Something went wrong - wrong target was select */ 1066 printf("wd33c93_selectbus: wrong target selected;" 1067 " WANTED %d GOT %d", target, id); 1068 return 0; /* XXX: Need to call nexstate to handle? */ 1069 } 1070 1071 dev->sc_flags |= SBICF_SELECTED; 1072 dev->sc_state = SBIC_CONNECTED; 1073 1074 /* setup correct sync mode for this target */ 1075 wd33c93_setsync(dev, ti); 1076 1077 if (ti->flags & T_NODISC && dev->sc_disc == 0) 1078 SET_SBIC_rselid (dev, 0); /* Not expecting a reselect */ 1079 else 1080 SET_SBIC_rselid (dev, SBIC_RID_ER); 1081 1082 /* 1083 * We only really need to do anything when the target goes to MSG out 1084 * If the device ignored ATN, it's probably old and brain-dead, 1085 * but we'll try to support it anyhow. 1086 * If it doesn't support message out, it definately doesn't 1087 * support synchronous transfers, so no point in even asking... 1088 */ 1089 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 1090 if (ti->flags & T_NEGOTIATE) { 1091 /* Inititae a SDTR message */ 1092 SBIC_DEBUG(SYNC, ("Sending SDTR to target %d\n", id)); 1093 if (ti->flags & T_WANTSYNC) { 1094 ti->period = dev->sc_minsyncperiod; 1095 ti->offset = dev->sc_maxoffset; 1096 } else { 1097 ti->period = 0; 1098 ti->offset = 0; 1099 } 1100 /* Send Sync negotiation message */ 1101 dev->sc_omsg[0] = MSG_IDENTIFY(lun, 0); /* No Disc */ 1102 dev->sc_omsg[1] = MSG_EXTENDED; 1103 dev->sc_omsg[2] = MSG_EXT_SDTR_LEN; 1104 dev->sc_omsg[3] = MSG_EXT_SDTR; 1105 if (ti->flags & T_WANTSYNC) { 1106 dev->sc_omsg[4] = dev->sc_minsyncperiod; 1107 dev->sc_omsg[5] = dev->sc_maxoffset; 1108 } else { 1109 dev->sc_omsg[4] = 0; 1110 dev->sc_omsg[5] = 0; 1111 } 1112 wd33c93_xfout(dev, 6, dev->sc_omsg); 1113 dev->sc_msgout |= SEND_SDTR; /* may be rejected */ 1114 dev->sc_flags |= SBICF_SYNCNEGO; 1115 } else { 1116 if (dev->sc_nexus->tag_type != 0) { 1117 /* Use TAGS */ 1118 SBIC_DEBUG(TAGS, ("<select %d:%d TAG=%x>\n", 1119 dev->target, dev->lun, 1120 dev->sc_nexus->tag_id)); 1121 dev->sc_omsg[0] = MSG_IDENTIFY(lun, 1); 1122 dev->sc_omsg[1] = dev->sc_nexus->tag_type; 1123 dev->sc_omsg[2] = dev->sc_nexus->tag_id; 1124 wd33c93_xfout(dev, 3, dev->sc_omsg); 1125 dev->sc_msgout |= SEND_TAG; 1126 } else { 1127 int no_disc; 1128 1129 /* Setup LUN nexus and disconnect privilege */ 1130 no_disc = xs->xs_control & XS_CTL_POLL || 1131 ti->flags & T_NODISC; 1132 SEND_BYTE(dev, MSG_IDENTIFY(lun, !no_disc)); 1133 } 1134 } 1135 /* 1136 * There's one interrupt still to come: 1137 * the change to CMD phase... 1138 */ 1139 SBIC_WAIT(dev, SBIC_ASR_INT , 0); 1140 GET_SBIC_csr(dev, csr); 1141 } 1142 1143 return csr; 1144 } 1145 1146 /* 1147 * Information Transfer *to* a SCSI Target. 1148 * 1149 * Note: Don't expect there to be an interrupt immediately after all 1150 * the data is transferred out. The WD spec sheet says that the Transfer- 1151 * Info command for non-MSG_IN phases only completes when the target 1152 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1153 * 1154 * This can have a nasty effect on commands which take a relatively long 1155 * time to complete, for example a START/STOP unit command may remain in 1156 * CMD phase until the disk has spun up. Only then will the target change 1157 * to STATUS phase. This is really only a problem for immediate commands 1158 * since we don't allow disconnection for them (yet). 1159 */ 1160 int 1161 wd33c93_xfout(struct wd33c93_softc *dev, int len, void *bp) 1162 { 1163 int wait = wd33c93_data_wait; 1164 u_char asr, *buf = bp; 1165 1166 QPRINTF(("wd33c93_xfout {%d} %02x %02x %02x %02x %02x " 1167 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1168 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1169 1170 /* 1171 * sigh.. WD-PROTO strikes again.. sending the command in one go 1172 * causes the chip to lock up if talking to certain (misbehaving?) 1173 * targets. Anyway, this procedure should work for all targets, but 1174 * it's slightly slower due to the overhead 1175 */ 1176 1177 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1178 SBIC_TC_PUT (dev, (unsigned)len); 1179 1180 WAIT_CIP (dev); 1181 SET_SBIC_cmd (dev, SBIC_CMD_XFER_INFO); 1182 1183 /* 1184 * Loop for each byte transferred 1185 */ 1186 do { 1187 GET_SBIC_asr (dev, asr); 1188 1189 if (asr & SBIC_ASR_DBR) { 1190 if (len) { 1191 SET_SBIC_data (dev, *buf); 1192 buf++; 1193 len--; 1194 } else { 1195 SET_SBIC_data (dev, 0); 1196 } 1197 wait = wd33c93_data_wait; 1198 } 1199 } while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1200 1201 QPRINTF(("wd33c93_xfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1202 1203 /* 1204 * Normally, an interrupt will be pending when this routing returns. 1205 */ 1206 return(len); 1207 } 1208 1209 /* 1210 * Information Transfer *from* a Scsi Target 1211 * returns # bytes left to read 1212 */ 1213 int 1214 wd33c93_xfin(struct wd33c93_softc *dev, int len, void *bp) 1215 { 1216 int wait = wd33c93_data_wait; 1217 u_char *buf = bp; 1218 u_char asr; 1219 #ifdef DEBUG 1220 u_char *obp = bp; 1221 #endif 1222 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1223 SBIC_TC_PUT (dev, (unsigned)len); 1224 1225 WAIT_CIP (dev); 1226 SET_SBIC_cmd (dev, SBIC_CMD_XFER_INFO); 1227 1228 /* 1229 * Loop for each byte transferred 1230 */ 1231 do { 1232 GET_SBIC_asr (dev, asr); 1233 1234 if (asr & SBIC_ASR_DBR) { 1235 if (len) { 1236 GET_SBIC_data (dev, *buf); 1237 buf++; 1238 len--; 1239 } else { 1240 u_char foo; 1241 GET_SBIC_data (dev, foo); 1242 } 1243 wait = wd33c93_data_wait; 1244 } 1245 1246 } while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1247 1248 QPRINTF(("wd33c93_xfin {%d} %02x %02x %02x %02x %02x %02x " 1249 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1250 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1251 1252 SBIC_TC_PUT (dev, 0); 1253 1254 /* 1255 * this leaves with one csr to be read 1256 */ 1257 return len; 1258 } 1259 1260 1261 /* 1262 * Finish SCSI xfer command: After the completion interrupt from 1263 * a read/write operation, sequence through the final phases in 1264 * programmed i/o. 1265 */ 1266 void 1267 wd33c93_xferdone(struct wd33c93_softc *dev) 1268 { 1269 u_char phase, csr; 1270 int s; 1271 1272 QPRINTF(("{")); 1273 s = splbio(); 1274 1275 /* 1276 * have the wd33c93 complete on its own 1277 */ 1278 SBIC_TC_PUT(dev, 0); 1279 SET_SBIC_cmd_phase(dev, 0x46); 1280 SET_SBIC_cmd(dev, SBIC_CMD_SEL_ATN_XFER); 1281 1282 do { 1283 SBIC_WAIT (dev, SBIC_ASR_INT, 0); 1284 GET_SBIC_csr (dev, csr); 1285 QPRINTF(("%02x:", csr)); 1286 } while ((csr != SBIC_CSR_DISC) && 1287 (csr != SBIC_CSR_DISC_1) && 1288 (csr != SBIC_CSR_S_XFERRED)); 1289 1290 dev->sc_flags &= ~SBICF_SELECTED; 1291 dev->sc_state = SBIC_DISCONNECT; 1292 1293 GET_SBIC_cmd_phase (dev, phase); 1294 QPRINTF(("}%02x", phase)); 1295 1296 if (phase == 0x60) 1297 GET_SBIC_tlun(dev, dev->sc_status); 1298 else 1299 wd33c93_error(dev, dev->sc_nexus); 1300 1301 QPRINTF(("=STS:%02x=\n", dev->sc_status)); 1302 splx(s); 1303 } 1304 1305 1306 int 1307 wd33c93_go(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 1308 { 1309 struct scsipi_xfer *xs = acb->xs; 1310 int i, dmaok; 1311 u_char csr, asr; 1312 1313 SBIC_DEBUG(ACBS, ("wd33c93_go(%d:%d)\n", dev->target, dev->lun)); 1314 1315 dev->sc_nexus = acb; 1316 1317 dev->target = xs->xs_periph->periph_target; 1318 dev->lun = xs->xs_periph->periph_lun; 1319 1320 dev->sc_status = STATUS_UNKNOWN; 1321 dev->sc_daddr = acb->daddr; 1322 dev->sc_dleft = acb->dleft; 1323 1324 dev->sc_msgpriq = dev->sc_msgout = dev->sc_msgoutq = 0; 1325 dev->sc_flags = 0; 1326 1327 dmaok = wd33c93_dmaok(dev, xs); 1328 1329 if (dmaok == 0) 1330 dev->sc_flags |= SBICF_NODMA; 1331 1332 SBIC_DEBUG(DMA, ("wd33c93_go dmago:%d(tcnt=%zx) dmaok=%dx\n", 1333 dev->target, dev->sc_tcnt, dmaok)); 1334 1335 /* select the SCSI bus (it's an error if bus isn't free) */ 1336 if ((csr = wd33c93_selectbus(dev, acb)) == 0) 1337 return(0); /* Not done: needs to be rescheduled */ 1338 1339 /* 1340 * Lets cycle a while then let the interrupt handler take over. 1341 */ 1342 GET_SBIC_asr(dev, asr); 1343 do { 1344 QPRINTF(("go[0x%x] ", csr)); 1345 1346 /* Handle the new phase */ 1347 i = wd33c93_nextstate(dev, acb, csr, asr); 1348 WAIT_CIP(dev); /* XXX */ 1349 if (dev->sc_state == SBIC_CONNECTED) { 1350 1351 GET_SBIC_asr(dev, asr); 1352 1353 if (asr & SBIC_ASR_LCI) 1354 printf("wd33c93_go: LCI asr:%02x csr:%02x\n", asr, csr); 1355 1356 if (asr & SBIC_ASR_INT) 1357 GET_SBIC_csr(dev, csr); 1358 } 1359 1360 } while (dev->sc_state == SBIC_CONNECTED && 1361 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1362 1363 QPRINTF(("> done i=%d stat=%02x\n", i, dev->sc_status)); 1364 1365 if (i == SBIC_STATE_DONE) { 1366 if (dev->sc_status == STATUS_UNKNOWN) { 1367 printf("wd33c93_go: done & stat == UNKNOWN\n"); 1368 return 1; /* Did we really finish that fast? */ 1369 } 1370 } 1371 return 0; 1372 } 1373 1374 1375 int 1376 wd33c93_intr(struct wd33c93_softc *dev) 1377 { 1378 u_char asr, csr; 1379 int i; 1380 1381 /* 1382 * pending interrupt? 1383 */ 1384 GET_SBIC_asr (dev, asr); 1385 if ((asr & SBIC_ASR_INT) == 0) 1386 return(0); 1387 1388 GET_SBIC_csr(dev, csr); 1389 1390 do { 1391 SBIC_DEBUG(INTS, ("intr[csr=0x%x]", csr)); 1392 1393 i = wd33c93_nextstate(dev, dev->sc_nexus, csr, asr); 1394 WAIT_CIP(dev); /* XXX */ 1395 if (dev->sc_state == SBIC_CONNECTED) { 1396 GET_SBIC_asr(dev, asr); 1397 1398 if (asr & SBIC_ASR_LCI) 1399 printf("wd33c93_intr: LCI asr:%02x csr:%02x\n", 1400 asr, csr); 1401 1402 if (asr & SBIC_ASR_INT) 1403 GET_SBIC_csr(dev, csr); 1404 } 1405 } while (dev->sc_state == SBIC_CONNECTED && 1406 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1407 1408 SBIC_DEBUG(INTS, ("intr done. state=%d, asr=0x%02x\n", i, asr)); 1409 1410 return(1); 1411 } 1412 1413 /* 1414 * Complete current command using polled I/O. Used when interrupt driven 1415 * I/O is not allowed (ie. during boot and shutdown) 1416 * 1417 * Polled I/O is very processor intensive 1418 */ 1419 int 1420 wd33c93_poll(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 1421 { 1422 u_char asr, csr=0; 1423 int i, count; 1424 struct scsipi_xfer *xs = acb->xs; 1425 1426 SBIC_WAIT(dev, SBIC_ASR_INT, wd33c93_cmd_wait); 1427 for (count=acb->timeout; count;) { 1428 GET_SBIC_asr (dev, asr); 1429 if (asr & SBIC_ASR_LCI) 1430 printf("wd33c93_poll: LCI; asr:%02x csr:%02x\n", 1431 asr, csr); 1432 if (asr & SBIC_ASR_INT) { 1433 GET_SBIC_csr(dev, csr); 1434 dev->sc_flags |= SBICF_NODMA; 1435 i = wd33c93_nextstate(dev, dev->sc_nexus, csr, asr); 1436 WAIT_CIP(dev); /* XXX */ 1437 } else { 1438 DELAY(1000); 1439 count--; 1440 } 1441 1442 if ((xs->xs_status & XS_STS_DONE) != 0) 1443 return (0); 1444 1445 if (dev->sc_state == SBIC_IDLE) { 1446 SBIC_DEBUG(ACBS, ("[poll: rescheduling] ")); 1447 wd33c93_sched(dev); 1448 } 1449 } 1450 return (1); 1451 } 1452 1453 static inline int 1454 __verify_msg_format(u_char *p, int len) 1455 { 1456 1457 if (len == 1 && MSG_IS1BYTE(p[0])) 1458 return 1; 1459 if (len == 2 && MSG_IS2BYTE(p[0])) 1460 return 1; 1461 if (len >= 3 && MSG_ISEXTENDED(p[0]) && 1462 len == p[1] + 2) 1463 return 1; 1464 return 0; 1465 } 1466 1467 /* 1468 * Handle message_in phase 1469 */ 1470 int 1471 wd33c93_msgin_phase(struct wd33c93_softc *dev, int reselect) 1472 { 1473 int len; 1474 u_char asr, csr, *msg; 1475 1476 GET_SBIC_asr(dev, asr); 1477 1478 SBIC_DEBUG(MSGS, ("wd33c93msgin asr=%02x\n", asr)); 1479 1480 GET_SBIC_selid (dev, csr); 1481 SET_SBIC_selid (dev, csr | SBIC_SID_FROM_SCSI); 1482 1483 SBIC_TC_PUT(dev, 0); 1484 1485 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1486 1487 msg = dev->sc_imsg; 1488 len = 0; 1489 1490 do { 1491 /* Fetch the next byte of the message */ 1492 RECV_BYTE(dev, *msg++); 1493 len++; 1494 1495 /* 1496 * get the command completion interrupt, or we 1497 * can't send a new command (LCI) 1498 */ 1499 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1500 GET_SBIC_csr(dev, csr); 1501 1502 if (__verify_msg_format(dev->sc_imsg, len)) 1503 break; /* Complete message recieved */ 1504 1505 /* 1506 * Clear ACK, and wait for the interrupt 1507 * for the next byte or phase change 1508 */ 1509 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1510 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1511 1512 GET_SBIC_csr(dev, csr); 1513 } while (len < SBIC_MAX_MSGLEN); 1514 1515 if (__verify_msg_format(dev->sc_imsg, len)) 1516 wd33c93_msgin(dev, dev->sc_imsg, len); 1517 1518 /* 1519 * Clear ACK, and wait for the interrupt 1520 * for the phase change 1521 */ 1522 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1523 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1524 1525 /* Should still have one CSR to read */ 1526 return SBIC_STATE_RUNNING; 1527 } 1528 1529 1530 void wd33c93_msgin(struct wd33c93_softc *dev, u_char *msgaddr, int msglen) 1531 { 1532 struct wd33c93_acb *acb = dev->sc_nexus; 1533 struct wd33c93_tinfo *ti = &dev->sc_tinfo[dev->target]; 1534 struct wd33c93_linfo *li; 1535 u_char asr; 1536 1537 switch (dev->sc_state) { 1538 case SBIC_CONNECTED: 1539 switch (msgaddr[0]) { 1540 case MSG_MESSAGE_REJECT: 1541 SBIC_DEBUG(MSGS, ("msgin: MSG_REJECT, " 1542 "last msgout=%x\n", dev->sc_msgout)); 1543 switch (dev->sc_msgout) { 1544 case SEND_TAG: 1545 printf("%s: tagged queuing rejected: " 1546 "target %d\n", 1547 dev->sc_dev.dv_xname, dev->target); 1548 ti->flags &= ~T_TAG; 1549 li = TINFO_LUN(ti, dev->lun); 1550 if (acb->tag_type && 1551 li->queued[acb->tag_id] != NULL) { 1552 li->queued[acb->tag_id] = NULL; 1553 li->used--; 1554 } 1555 acb->tag_type = acb->tag_id = 0; 1556 li->untagged = acb; 1557 li->state = L_STATE_BUSY; 1558 break; 1559 1560 case SEND_SDTR: 1561 printf("%s: sync transfer rejected: target %d\n", 1562 dev->sc_dev.dv_xname, dev->target); 1563 1564 dev->sc_flags &= ~SBICF_SYNCNEGO; 1565 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1566 wd33c93_update_xfer_mode(dev, 1567 acb->xs->xs_periph->periph_target); 1568 wd33c93_setsync(dev, ti); 1569 1570 case SEND_INIT_DET_ERR: 1571 goto abort; 1572 1573 default: 1574 SBIC_DEBUG(MSGS, ("Unexpected MSG_REJECT\n")); 1575 break; 1576 } 1577 dev->sc_msgout = 0; 1578 break; 1579 1580 case MSG_HEAD_OF_Q_TAG: 1581 case MSG_ORDERED_Q_TAG: 1582 case MSG_SIMPLE_Q_TAG: 1583 printf("-- Out of phase TAG;" 1584 "Nexus=%d:%d Tag=%02x/%02x\n", 1585 dev->target, dev->lun, msgaddr[0], msgaddr[1]); 1586 break; 1587 1588 case MSG_DISCONNECT: 1589 SBIC_DEBUG(MSGS, ("msgin: DISCONNECT")); 1590 /* 1591 * Mark the fact that all bytes have moved. The 1592 * target may not bother to do a SAVE POINTERS 1593 * at this stage. This flag will set the residual 1594 * count to zero on MSG COMPLETE. 1595 */ 1596 if (dev->sc_dleft == 0) 1597 acb->flags |= ACB_COMPLETE; 1598 1599 if (acb->xs->xs_control & XS_CTL_POLL) 1600 /* Don't allow disconnect in immediate mode */ 1601 goto reject; 1602 else { /* Allow disconnect */ 1603 dev->sc_flags &= ~SBICF_SELECTED; 1604 dev->sc_state = SBIC_DISCONNECT; 1605 } 1606 if ((acb->xs->xs_periph->periph_quirks & 1607 PQUIRK_AUTOSAVE) == 0) 1608 break; 1609 /*FALLTHROUGH*/ 1610 1611 case MSG_SAVEDATAPOINTER: 1612 SBIC_DEBUG(MSGS, ("msgin: SAVEDATAPTR")); 1613 acb->daddr = dev->sc_daddr; 1614 acb->dleft = dev->sc_dleft; 1615 break; 1616 1617 case MSG_RESTOREPOINTERS: 1618 SBIC_DEBUG(MSGS, ("msgin: RESTOREPTR")); 1619 dev->sc_daddr = acb->daddr; 1620 dev->sc_dleft = acb->dleft; 1621 break; 1622 1623 case MSG_CMDCOMPLETE: 1624 /* 1625 * !! KLUDGE ALERT !! quite a few drives don't seem to 1626 * really like the current way of sending the 1627 * sync-handshake together with the ident-message, and 1628 * they react by sending command-complete and 1629 * disconnecting right after returning the valid sync 1630 * handshake. So, all I can do is reselect the drive, 1631 * and hope it won't disconnect again. I don't think 1632 * this is valid behavior, but I can't help fixing a 1633 * problem that apparently exists. 1634 * 1635 * Note: we should not get here on `normal' command 1636 * completion, as that condition is handled by the 1637 * high-level sel&xfer resume command used to walk 1638 * thru status/cc-phase. 1639 */ 1640 SBIC_DEBUG(MSGS, ("msgin: CMD_COMPLETE")); 1641 SBIC_DEBUG(SYNC, ("GOT MSG %d! target %d" 1642 " acting weird.." 1643 " waiting for disconnect...\n", 1644 msgaddr[0], dev->target)); 1645 1646 /* Check to see if wd33c93 is handling this */ 1647 GET_SBIC_asr(dev, asr); 1648 if (asr & SBIC_ASR_BSY) 1649 break; 1650 1651 /* XXX: Assume it works and set status to 00 */ 1652 dev->sc_status = 0; 1653 dev->sc_state = SBIC_CMDCOMPLETE; 1654 break; 1655 1656 case MSG_EXTENDED: 1657 switch(msgaddr[2]) { 1658 case MSG_EXT_SDTR: /* Sync negotiation */ 1659 SBIC_DEBUG(MSGS, ("msgin: EXT_SDTR; " 1660 "period %d, offset %d", 1661 msgaddr[3], msgaddr[4])); 1662 if (msgaddr[1] != 3) 1663 goto reject; 1664 1665 ti->period = 1666 MAX(msgaddr[3], dev->sc_minsyncperiod); 1667 ti->offset = MIN(msgaddr[4], dev->sc_maxoffset); 1668 if (!(ti->flags & T_WANTSYNC)) 1669 ti->period = ti->offset = 0; 1670 1671 ti->flags &= ~T_NEGOTIATE; 1672 1673 if (ti->offset == 0) 1674 ti->flags &= ~T_SYNCMODE; /* Async */ 1675 else 1676 ti->flags |= T_SYNCMODE; /* Sync */ 1677 1678 if ((dev->sc_flags&SBICF_SYNCNEGO) == 0) 1679 /* target initiated negotiation */ 1680 wd33c93_sched_msgout(dev, SEND_SDTR); 1681 dev->sc_flags &= ~SBICF_SYNCNEGO; 1682 1683 SBIC_DEBUG(SYNC, ("msgin(%d): SDTR(o=%d,p=%d)", 1684 dev->target, ti->offset, 1685 ti->period)); 1686 wd33c93_update_xfer_mode(dev, 1687 acb->xs->xs_periph->periph_target); 1688 wd33c93_setsync(dev, ti); 1689 break; 1690 1691 case MSG_EXT_WDTR: 1692 SBIC_DEBUG(MSGS, ("msgin: EXT_WDTR rejected")); 1693 goto reject; 1694 1695 default: 1696 scsipi_printaddr(acb->xs->xs_periph); 1697 printf("unrecognized MESSAGE EXTENDED;" 1698 " sending REJECT\n"); 1699 goto reject; 1700 } 1701 break; 1702 1703 default: 1704 scsipi_printaddr(acb->xs->xs_periph); 1705 printf("unrecognized MESSAGE; sending REJECT\n"); 1706 1707 reject: 1708 /* We don't support whatever this message is... */ 1709 wd33c93_sched_msgout(dev, SEND_REJECT); 1710 break; 1711 } 1712 break; 1713 1714 case SBIC_IDENTIFIED: 1715 /* 1716 * IDENTIFY message was received and queue tag is expected now 1717 */ 1718 if ((msgaddr[0]!=MSG_SIMPLE_Q_TAG) || (dev->sc_msgify==0)) { 1719 printf("%s: TAG reselect without IDENTIFY;" 1720 " MSG %x; sending DEVICE RESET\n", 1721 dev->sc_dev.dv_xname, msgaddr[0]); 1722 goto reset; 1723 } 1724 SBIC_DEBUG(TAGS, ("TAG %x/%x\n", msgaddr[0], msgaddr[1])); 1725 if (dev->sc_nexus) 1726 printf("*TAG Recv with active nexus!!\n"); 1727 wd33c93_reselect(dev, dev->target, dev->lun, 1728 msgaddr[0], msgaddr[1]); 1729 break; 1730 1731 case SBIC_RESELECTED: 1732 /* 1733 * IDENTIFY message with target 1734 */ 1735 if (MSG_ISIDENTIFY(msgaddr[0])) { 1736 SBIC_DEBUG(PHASE, ("IFFY[%x] ", msgaddr[0])); 1737 dev->sc_msgify = msgaddr[0]; 1738 } else { 1739 printf("%s: reselect without IDENTIFY;" 1740 " MSG %x;" 1741 " sending DEVICE RESET\n", 1742 dev->sc_dev.dv_xname, msgaddr[0]); 1743 goto reset; 1744 } 1745 break; 1746 1747 default: 1748 printf("Unexpected MESSAGE IN. State=%d - Sending RESET\n", 1749 dev->sc_state); 1750 reset: 1751 wd33c93_sched_msgout(dev, SEND_DEV_RESET); 1752 break; 1753 abort: 1754 wd33c93_sched_msgout(dev, SEND_ABORT); 1755 break; 1756 } 1757 } 1758 1759 void 1760 wd33c93_sched_msgout(struct wd33c93_softc *dev, u_short msg) 1761 { 1762 u_char asr; 1763 1764 SBIC_DEBUG(SYNC,("sched_msgout: %04x\n", msg)); 1765 dev->sc_msgpriq |= msg; 1766 1767 /* Schedule MSGOUT Phase to send message */ 1768 1769 WAIT_CIP(dev); 1770 SET_SBIC_cmd(dev, SBIC_CMD_SET_ATN); 1771 WAIT_CIP(dev); 1772 GET_SBIC_asr(dev, asr); 1773 if (asr & SBIC_ASR_LCI) { 1774 printf("MSGOUT Failed!\n"); 1775 } 1776 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1777 WAIT_CIP(dev); 1778 } 1779 1780 /* 1781 * Send the highest priority, scheduled message 1782 */ 1783 void 1784 wd33c93_msgout(struct wd33c93_softc *dev) 1785 { 1786 struct wd33c93_tinfo *ti; 1787 struct wd33c93_acb *acb = dev->sc_nexus; 1788 1789 if (acb == NULL) 1790 panic("MSGOUT with no nexus"); 1791 1792 if (dev->sc_omsglen == 0) { 1793 /* Pick up highest priority message */ 1794 dev->sc_msgout = dev->sc_msgpriq & -dev->sc_msgpriq; 1795 dev->sc_msgoutq |= dev->sc_msgout; 1796 dev->sc_msgpriq &= ~dev->sc_msgout; 1797 dev->sc_omsglen = 1; /* "Default" message len */ 1798 switch (dev->sc_msgout) { 1799 case SEND_SDTR: 1800 ti = &dev->sc_tinfo[acb->xs->xs_periph->periph_target]; 1801 dev->sc_omsg[0] = MSG_EXTENDED; 1802 dev->sc_omsg[1] = MSG_EXT_SDTR_LEN; 1803 dev->sc_omsg[2] = MSG_EXT_SDTR; 1804 if (ti->flags & T_WANTSYNC) { 1805 dev->sc_omsg[3] = ti->period; 1806 dev->sc_omsg[4] = ti->offset; 1807 } else { 1808 dev->sc_omsg[3] = 0; 1809 dev->sc_omsg[4] = 0; 1810 } 1811 dev->sc_omsglen = 5; 1812 if ((dev->sc_flags & SBICF_SYNCNEGO) == 0) { 1813 if (ti->flags & T_WANTSYNC) 1814 ti->flags |= T_SYNCMODE; 1815 else 1816 ti->flags &= ~T_SYNCMODE; 1817 wd33c93_setsync(dev, ti); 1818 } 1819 break; 1820 case SEND_IDENTIFY: 1821 if (dev->sc_state != SBIC_CONNECTED) { 1822 printf("%s at line %d: no nexus\n", 1823 dev->sc_dev.dv_xname, __LINE__); 1824 } 1825 dev->sc_omsg[0] = 1826 MSG_IDENTIFY(acb->xs->xs_periph->periph_lun, 0); 1827 break; 1828 case SEND_TAG: 1829 if (dev->sc_state != SBIC_CONNECTED) { 1830 printf("%s at line %d: no nexus\n", 1831 dev->sc_dev.dv_xname, __LINE__); 1832 } 1833 dev->sc_omsg[0] = acb->tag_type; 1834 dev->sc_omsg[1] = acb->tag_id; 1835 dev->sc_omsglen = 2; 1836 break; 1837 case SEND_DEV_RESET: 1838 dev->sc_omsg[0] = MSG_BUS_DEV_RESET; 1839 ti = &dev->sc_tinfo[dev->target]; 1840 ti->flags &= ~T_SYNCMODE; 1841 wd33c93_update_xfer_mode(dev, dev->target); 1842 if ((ti->flags & T_NOSYNC) == 0) 1843 /* We can re-start sync negotiation */ 1844 ti->flags |= T_NEGOTIATE; 1845 break; 1846 case SEND_PARITY_ERROR: 1847 dev->sc_omsg[0] = MSG_PARITY_ERROR; 1848 break; 1849 case SEND_ABORT: 1850 dev->sc_flags |= SBICF_ABORTING; 1851 dev->sc_omsg[0] = MSG_ABORT; 1852 break; 1853 case SEND_INIT_DET_ERR: 1854 dev->sc_omsg[0] = MSG_INITIATOR_DET_ERR; 1855 break; 1856 case SEND_REJECT: 1857 dev->sc_omsg[0] = MSG_MESSAGE_REJECT; 1858 break; 1859 default: 1860 /* Wasn't expecting MSGOUT Phase */ 1861 dev->sc_omsg[0] = MSG_NOOP; 1862 break; 1863 } 1864 } 1865 1866 wd33c93_xfout(dev, dev->sc_omsglen, dev->sc_omsg); 1867 } 1868 1869 1870 /* 1871 * wd33c93_nextstate() 1872 * return: 1873 * SBIC_STATE_DONE == done 1874 * SBIC_STATE_RUNNING == working 1875 * SBIC_STATE_DISCONNECT == disconnected 1876 * SBIC_STATE_ERROR == error 1877 */ 1878 int 1879 wd33c93_nextstate(struct wd33c93_softc *dev, struct wd33c93_acb *acb, u_char csr, u_char asr) 1880 { 1881 SBIC_DEBUG(PHASE, ("next[a=%02x,c=%02x]: ",asr,csr)); 1882 1883 switch (csr) { 1884 1885 case SBIC_CSR_XFERRED | CMD_PHASE: 1886 case SBIC_CSR_MIS | CMD_PHASE: 1887 case SBIC_CSR_MIS_1 | CMD_PHASE: 1888 case SBIC_CSR_MIS_2 | CMD_PHASE: 1889 1890 if (wd33c93_xfout(dev, acb->clen, &acb->cmd)) 1891 goto abort; 1892 break; 1893 1894 case SBIC_CSR_XFERRED | STATUS_PHASE: 1895 case SBIC_CSR_MIS | STATUS_PHASE: 1896 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1897 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1898 1899 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1900 1901 /* 1902 * this should be the normal i/o completion case. 1903 * get the status & cmd complete msg then let the 1904 * device driver look at what happened. 1905 */ 1906 wd33c93_xferdone(dev); 1907 1908 wd33c93_dma_stop(dev); 1909 1910 /* Fixup byte count to be passed to higher layer */ 1911 acb->dleft = (acb->flags & ACB_COMPLETE) ? 0 : 1912 dev->sc_dleft; 1913 1914 /* 1915 * Indicate to the upper layers that the command is done 1916 */ 1917 wd33c93_scsidone(dev, acb, dev->sc_status); 1918 1919 return SBIC_STATE_DONE; 1920 1921 1922 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 1923 case SBIC_CSR_MIS | DATA_IN_PHASE: 1924 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 1925 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 1926 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 1927 case SBIC_CSR_MIS | DATA_OUT_PHASE: 1928 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 1929 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 1930 /* 1931 * Verify that we expected to transfer data... 1932 */ 1933 if (acb->dleft <= 0) { 1934 printf("next: DATA phase with xfer count == %zd, asr:0x%02x csr:0x%02x\n", 1935 acb->dleft, asr, csr); 1936 goto abort; 1937 } 1938 1939 /* 1940 * Should we transfer using PIO or DMA ? 1941 */ 1942 if (acb->xs->xs_control & XS_CTL_POLL || 1943 dev->sc_flags & SBICF_NODMA) { 1944 /* Perfrom transfer using PIO */ 1945 int resid; 1946 1947 SBIC_DEBUG(DMA, ("PIO xfer: %d(%p:%zx)\n", dev->target, 1948 dev->sc_daddr, dev->sc_dleft)); 1949 1950 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 1951 /* data in */ 1952 resid = wd33c93_xfin(dev, dev->sc_dleft, 1953 dev->sc_daddr); 1954 else /* data out */ 1955 resid = wd33c93_xfout(dev, dev->sc_dleft, 1956 dev->sc_daddr); 1957 1958 dev->sc_daddr = (char*)dev->sc_daddr + 1959 (acb->dleft - resid); 1960 dev->sc_dleft = resid; 1961 } else { 1962 int datain = SBIC_PHASE(csr) == DATA_IN_PHASE; 1963 1964 /* Perform transfer using DMA */ 1965 wd33c93_dma_setup(dev, datain); 1966 1967 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI | 1968 dev->sc_dmamode); 1969 1970 SBIC_DEBUG(DMA, ("DMA xfer: %d(%p:%zx)\n", dev->target, 1971 dev->sc_daddr, dev->sc_dleft)); 1972 1973 /* Setup byte count for transfer */ 1974 SBIC_TC_PUT(dev, (unsigned)dev->sc_dleft); 1975 1976 /* Start the transfer */ 1977 SET_SBIC_cmd(dev, SBIC_CMD_XFER_INFO); 1978 1979 /* Start the DMA chip going */ 1980 dev->sc_tcnt = dev->sc_dmago(dev); 1981 1982 /* Indicate that we're in DMA mode */ 1983 dev->sc_flags |= SBICF_INDMA; 1984 } 1985 break; 1986 1987 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 1988 case SBIC_CSR_MIS | MESG_IN_PHASE: 1989 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 1990 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 1991 1992 wd33c93_dma_stop(dev); 1993 1994 /* Handle a single message in... */ 1995 return wd33c93_msgin_phase(dev, 0); 1996 1997 case SBIC_CSR_MSGIN_W_ACK: 1998 1999 /* 2000 * We should never see this since it's handled in 2001 * 'wd33c93_msgin_phase()' but just for the sake of paranoia... 2002 */ 2003 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 2004 2005 printf("Acking unknown msgin CSR:%02x",csr); 2006 break; 2007 2008 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2009 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2010 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2011 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2012 2013 /* 2014 * Message out phase. ATN signal has been asserted 2015 */ 2016 wd33c93_dma_stop(dev); 2017 wd33c93_msgout(dev); 2018 return SBIC_STATE_RUNNING; 2019 2020 case SBIC_CSR_DISC: 2021 case SBIC_CSR_DISC_1: 2022 SBIC_DEBUG(RSEL, ("wd33c93next target %d disconnected\n", 2023 dev->target)); 2024 wd33c93_dma_stop(dev); 2025 2026 dev->sc_nexus = NULL; 2027 dev->sc_state = SBIC_IDLE; 2028 dev->sc_flags = 0; 2029 2030 ++dev->sc_tinfo[dev->target].dconns; 2031 ++dev->sc_disc; 2032 2033 if (acb->xs->xs_control & XS_CTL_POLL || wd33c93_nodisc) 2034 return SBIC_STATE_DISCONNECT; 2035 2036 /* Try to schedule another target */ 2037 wd33c93_sched(dev); 2038 2039 return SBIC_STATE_DISCONNECT; 2040 2041 case SBIC_CSR_RSLT_NI: 2042 case SBIC_CSR_RSLT_IFY: 2043 { 2044 /* 2045 * A reselection. 2046 * Note that since we don't enable Advanced Features (assuming 2047 * the WD chip is at least the 'A' revision), we're only ever 2048 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2049 * hell of it, we'll handle it anyway, for all the extra code 2050 * it needs... 2051 */ 2052 u_char newtarget, newlun; 2053 2054 if (dev->sc_flags & SBICF_INDMA) { 2055 printf("**** RESELECT WHILE DMA ACTIVE!!! ***\n"); 2056 wd33c93_dma_stop(dev); 2057 } 2058 2059 dev->sc_state = SBIC_RESELECTED; 2060 GET_SBIC_rselid(dev, newtarget); 2061 2062 /* check SBIC_RID_SIV? */ 2063 newtarget &= SBIC_RID_MASK; 2064 2065 if (csr == SBIC_CSR_RSLT_IFY) { 2066 /* Read Identify msg to avoid lockup */ 2067 GET_SBIC_data(dev, newlun); 2068 WAIT_CIP(dev); 2069 newlun &= SBIC_TLUN_MASK; 2070 dev->sc_msgify = MSG_IDENTIFY(newlun, 0); 2071 } else { 2072 /* 2073 * Need to read Identify message the hard way, assuming 2074 * the target even sends us one... 2075 */ 2076 for (newlun = 255; newlun; --newlun) { 2077 GET_SBIC_asr(dev, asr); 2078 if (asr & SBIC_ASR_INT) 2079 break; 2080 DELAY(10); 2081 } 2082 2083 /* If we didn't get an interrupt, somethink's up */ 2084 if ((asr & SBIC_ASR_INT) == 0) { 2085 printf("%s: Reselect without identify? asr %x\n", 2086 dev->sc_dev.dv_xname, asr); 2087 newlun = 0; /* XXXX */ 2088 } else { 2089 /* 2090 * We got an interrupt, verify that it's a 2091 * change to message in phase, and if so 2092 * read the message. 2093 */ 2094 GET_SBIC_csr(dev,csr); 2095 2096 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2097 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2098 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2099 /* 2100 * Yup, gone to message in. 2101 * Fetch the target LUN 2102 */ 2103 dev->sc_msgify = 0; 2104 wd33c93_msgin_phase(dev, 1); 2105 newlun = dev->sc_msgify & SBIC_TLUN_MASK; 2106 } else { 2107 /* 2108 * Whoops! Target didn't go to msg_in 2109 * phase!! 2110 */ 2111 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2112 newlun = 0; /* XXXSCW */ 2113 } 2114 } 2115 } 2116 2117 /* Ok, we have the identity of the reselecting target. */ 2118 SBIC_DEBUG(RSEL, ("wd33c93next: reselect from targ %d lun %d", 2119 newtarget, newlun)); 2120 wd33c93_reselect(dev, newtarget, newlun, 0, 0); 2121 dev->sc_disc--; 2122 2123 if (csr == SBIC_CSR_RSLT_IFY) 2124 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 2125 break; 2126 } 2127 2128 default: 2129 abort: 2130 /* Something unexpected happend -- deal with it. */ 2131 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2132 2133 #ifdef DDB 2134 Debugger(); 2135 #endif 2136 2137 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 2138 if (acb->xs) 2139 wd33c93_error(dev, acb); 2140 wd33c93_abort(dev, acb, "next"); 2141 2142 if (dev->sc_flags & SBICF_INDMA) { 2143 wd33c93_dma_stop(dev); 2144 wd33c93_scsidone(dev, acb, STATUS_UNKNOWN); 2145 } 2146 return SBIC_STATE_ERROR; 2147 } 2148 return SBIC_STATE_RUNNING; 2149 } 2150 2151 2152 void 2153 wd33c93_reselect(struct wd33c93_softc *dev, int target, int lun, int tag_type, int tag_id) 2154 { 2155 2156 struct wd33c93_tinfo *ti; 2157 struct wd33c93_linfo *li; 2158 struct wd33c93_acb *acb; 2159 2160 if (dev->sc_nexus) { 2161 /* 2162 * Whoops! We've been reselected with a 2163 * command in progress! 2164 * The best we can do is to put the current 2165 * command back on the ready list and hope 2166 * for the best. 2167 */ 2168 SBIC_DEBUG(RSEL, ("%s: reselect with active command\n", 2169 dev->sc_dev.dv_xname)); 2170 ti = &dev->sc_tinfo[dev->target]; 2171 li = TINFO_LUN(ti, dev->lun); 2172 li->state = L_STATE_IDLE; 2173 2174 wd33c93_dequeue(dev, dev->sc_nexus); 2175 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2176 dev->sc_nexus->flags |= ACB_READY; 2177 2178 dev->sc_nexus = NULL; 2179 } 2180 2181 /* Setup state for new nexus */ 2182 acb = NULL; 2183 dev->sc_flags = SBICF_SELECTED; 2184 dev->sc_msgpriq = dev->sc_msgout = dev->sc_msgoutq = 0; 2185 2186 ti = &dev->sc_tinfo[target]; 2187 li = TINFO_LUN(ti, lun); 2188 2189 if (li != NULL) { 2190 if (li->untagged != NULL && li->state) 2191 acb = li->untagged; 2192 else if (tag_type != MSG_SIMPLE_Q_TAG) { 2193 /* Wait for tag to come by during MESG_IN Phase */ 2194 dev->target = target; /* setup I_T_L nexus */ 2195 dev->lun = lun; 2196 dev->sc_state = SBIC_IDENTIFIED; 2197 return; 2198 } else if (tag_type) 2199 acb = li->queued[tag_id]; 2200 } 2201 2202 if (acb == NULL) { 2203 printf("%s: reselect from target %d lun %d tag %x:%x " 2204 "with no nexus; sending ABORT\n", 2205 dev->sc_dev.dv_xname, target, lun, tag_type, tag_id); 2206 goto abort; 2207 } 2208 2209 dev->target = target; 2210 dev->lun = lun; 2211 dev->sc_nexus = acb; 2212 dev->sc_state = SBIC_CONNECTED; 2213 2214 if (!wd33c93_dmaok(dev, acb->xs)) 2215 dev->sc_flags |= SBICF_NODMA; 2216 2217 /* Do an implicit RESTORE POINTERS. */ 2218 dev->sc_daddr = acb->daddr; 2219 dev->sc_dleft = acb->dleft; 2220 2221 /* Set sync modes for new target */ 2222 wd33c93_setsync(dev, ti); 2223 2224 if (acb->flags & ACB_RESET) 2225 wd33c93_sched_msgout(dev, SEND_DEV_RESET); 2226 else if (acb->flags & ACB_ABORT) 2227 wd33c93_sched_msgout(dev, SEND_ABORT); 2228 return; 2229 2230 abort: 2231 wd33c93_sched_msgout(dev, SEND_ABORT); 2232 return; 2233 2234 } 2235 2236 void 2237 wd33c93_update_xfer_mode(struct wd33c93_softc *sc, int target) 2238 { 2239 struct wd33c93_tinfo *ti = &sc->sc_tinfo[target]; 2240 struct scsipi_xfer_mode xm; 2241 2242 xm.xm_target = target; 2243 xm.xm_mode = 0; 2244 xm.xm_period = 0; 2245 xm.xm_offset = 0; 2246 2247 if (ti->flags & T_SYNCMODE) { 2248 xm.xm_mode |= PERIPH_CAP_SYNC; 2249 xm.xm_period = ti->period; 2250 xm.xm_offset = ti->offset; 2251 } 2252 2253 if ((ti->flags & (T_NODISC|T_TAG)) == T_TAG) 2254 xm.xm_mode |= PERIPH_CAP_TQING; 2255 2256 SBIC_DEBUG(SYNC, ("wd33c93_update_xfer_mode: reporting target %d %s\n", 2257 xm.xm_target, 2258 (xm.xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 2259 2260 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 2261 } 2262 2263 void 2264 wd33c93_timeout(void *arg) 2265 { 2266 struct wd33c93_acb *acb = arg; 2267 struct scsipi_xfer *xs = acb->xs; 2268 struct scsipi_periph *periph = xs->xs_periph; 2269 struct wd33c93_softc *dev = 2270 (void *)periph->periph_channel->chan_adapter->adapt_dev; 2271 int s, asr; 2272 2273 s = splbio(); 2274 2275 GET_SBIC_asr(dev, asr); 2276 2277 scsipi_printaddr(periph); 2278 printf("%s: timed out; asr=0x%02x [acb %p (flags 0x%x, dleft %zx)], " 2279 "<state %d, nexus %p, resid %lx, msg(q %x,o %x)>", 2280 dev->sc_dev.dv_xname, asr, acb, acb->flags, acb->dleft, 2281 dev->sc_state, dev->sc_nexus, (long)dev->sc_dleft, 2282 dev->sc_msgpriq, dev->sc_msgout); 2283 2284 if (asr & SBIC_ASR_INT) { 2285 /* We need to service a missed IRQ */ 2286 wd33c93_intr(dev); 2287 } else { 2288 (void) wd33c93_abort(dev, dev->sc_nexus, "timeout"); 2289 } 2290 splx(s); 2291 } 2292 2293 2294 void 2295 wd33c93_watchdog(void *arg) 2296 { 2297 struct wd33c93_softc *dev = arg; 2298 struct wd33c93_tinfo *ti; 2299 struct wd33c93_linfo *li; 2300 int t, s, l; 2301 /* scrub LUN's that have not been used in the last 10min. */ 2302 time_t old = time_second - (10 * 60); 2303 2304 for (t = 0; t < SBIC_NTARG; t++) { 2305 ti = &dev->sc_tinfo[t]; 2306 for (l = 0; l < SBIC_NLUN; l++) { 2307 s = splbio(); 2308 li = TINFO_LUN(ti, l); 2309 if (li && li->last_used < old && 2310 li->untagged == NULL && li->used == 0) { 2311 ti->lun[li->lun] = NULL; 2312 free(li, M_DEVBUF); 2313 } 2314 splx(s); 2315 } 2316 } 2317 callout_reset(&dev->sc_watchdog, 60 * hz, wd33c93_watchdog, dev); 2318 } 2319 2320 2321 #ifdef DEBUG 2322 void 2323 wd33c93_hexdump(u_char *buf, int len) 2324 { 2325 printf("{%d}:", len); 2326 while (len--) 2327 printf(" %02x", *buf++); 2328 printf("\n"); 2329 } 2330 2331 2332 void 2333 wd33c93_print_csr(u_char csr) 2334 { 2335 switch (SCSI_PHASE(csr)) { 2336 case CMD_PHASE: 2337 printf("CMD_PHASE\n"); 2338 break; 2339 2340 case STATUS_PHASE: 2341 printf("STATUS_PHASE\n"); 2342 break; 2343 2344 case DATA_IN_PHASE: 2345 printf("DATAIN_PHASE\n"); 2346 break; 2347 2348 case DATA_OUT_PHASE: 2349 printf("DATAOUT_PHASE\n"); 2350 break; 2351 2352 case MESG_IN_PHASE: 2353 printf("MESG_IN_PHASE\n"); 2354 break; 2355 2356 case MESG_OUT_PHASE: 2357 printf("MESG_OUT_PHASE\n"); 2358 break; 2359 2360 default: 2361 switch (csr) { 2362 case SBIC_CSR_DISC_1: 2363 printf("DISC_1\n"); 2364 break; 2365 2366 case SBIC_CSR_RSLT_NI: 2367 printf("RESELECT_NO_IFY\n"); 2368 break; 2369 2370 case SBIC_CSR_RSLT_IFY: 2371 printf("RESELECT_IFY\n"); 2372 break; 2373 2374 case SBIC_CSR_SLT: 2375 printf("SELECT\n"); 2376 break; 2377 2378 case SBIC_CSR_SLT_ATN: 2379 printf("SELECT, ATN\n"); 2380 break; 2381 2382 case SBIC_CSR_UNK_GROUP: 2383 printf("UNK_GROUP\n"); 2384 break; 2385 2386 default: 2387 printf("UNKNOWN csr=%02x\n", csr); 2388 } 2389 } 2390 } 2391 #endif 2392
Indexes created Fri Sep 26 20:09:58 GMT 2025